JP5200276B2 - Inline lithography and etching system - Google Patents

Description

  The present invention relates to wafer processing and, more particularly, to site-dependent (S-D) processing and improved wafer processing using subsystems.

  Current manufacturing methods and factory designs used for integrated circuits require a lot of equipment. Many of these devices are either provided as stand-alone platforms or are grouped in their entire area—typically spaced apart by more than 2000 feet. Therefore, the equipment that operates these devices must be widely distributed throughout the factory. Typical functions required for these platforms are substrate coating (adhesion, BARC, TARC, resist, top coating), baking (post-application baking and post-exposure baking), drawing (exposure), metrology (overlay, limit) Dimensions, defects, and film thickness), pre-exposure and post-exposure cleaning using an immersion process, etching (defining a pattern in the underlying thin film), and post-etch cleaning (removing polymers and other by-products) It is. The technology aiming at a gate length of less than 32 nm requires repeating these operations until one active layer of a semiconductor device is completed, that is, double BARC, double or triple patterning, or triple drawing.

US Patent Application Publication No. 20080243297 US Pat. No. 7,756,423 US Patent Application Publication No. 20080243295 US Patent Application Publication No. 20080241970 US Patent Application Publication No. 20080241971 US Pat. No. 6,913,900 International Publication No. 2005/003911 Pamphlet US Patent No. 7092110 US Pat. No. 7,588,949 U.S. Patent No. 7388677 U.S. Pat. No. 6,785,638

Simon Haykin, "Neural Networks", Prentice Hall, 1999

The gate level defect density required for 15nm gate technology is expected to be about 0.01 / cm ² at 10nm in the ITRS2005 roadmap. The critical dimension control requires about 0.6 nm (3σ) for the gate element after etching. There are no lithography and etch processing equipment with these capabilities.

  These advanced technologies require real-time process adjustments between wafers to maintain acceptable device results. Due to the requirements for defects, it is required to reduce movement between devices in a factory. Because these movements cause defects and factory clean room costs.

  The platform used today functions as an “island” for manufacturing. For this reason, there is no allowance for the best CoO development or optimal process control is not possible. Today's 300mm track designs cannot meet the 300-sheet / hour throughput, as claimed by some lithography tool manufacturers.

  The present invention provides a real-time wafer processing method using S-D processing and / or S-D evaluation processing. In some embodiments, one or more subsystems and / or one or more controllers in the system may be used to perform SD processing and / or S-D evaluation processing using real-time S-D parameters. In addition, S-D processing and / or S-D measurement processing may operate using history data.

  In some other embodiments, the present invention provides a method and apparatus for verifying S-D. In one process, a first set of SD wafers may be received by one or more SD processing units in one or more processing subsystems, and the one or more SD processing units may be one or more SD transport sub-units. May be combined with the system. Each wafer may have data associated with that wafer. The wafer data may include historical data and / or real time data. In other processes, a first set of unverified SD wafers may be generated by performing a first SD generation process using one or more SD processing devices, and one or more unverified evaluation sites are present. It may be generated at the first number of evaluation sites on each unverified SD wafer. S-D wafer status data may be generated for each unverified S-D wafer. The S-D wafer state data may include a necessary number of generation sites and a required number of evaluation sites for each unverified S-D wafer. A first set of evaluation wafers including the first number of unverified S-D wafers may be fabricated. The first set of evaluation wafers may be evaluated using the first SD evaluation process. Subsequently, a first operating state may be created for a plurality of S-D evaluation devices in one or more subsystems coupled to one or more S-D transport subsystems. The first number of available evaluation devices may be determined using the first operating state for one or more S-D evaluation devices. The first SD transport sequence may be created using wafer data, S-D wafer data, a first number of S-D evaluation wafers, a first number of available evaluation devices, or a combination thereof. When the number of SD evaluation wafers is less than or equal to the first number of available evaluation devices, the first set of SD evaluation wafers may include one or more evaluation sub-systems by using the first SD transport sequence. It can be transported to the first number of available evaluation devices in the system. When the number of S-D evaluation wafers is greater than a first number that is the number of available evaluation devices, a first correction operation is performed. In addition, the present invention provides a system for verifying S-D wafers. The system includes: one or more processing units in one or more processing subsystems configured to receive a first set of wafers; and one or more transfer subsystems coupled to the one or more processing units You may have. One or more S-D processing apparatuses may be provided to generate a first set of unverified S-D wafers by performing a first S-D generation process. One or more unverified evaluation sites may be generated at the first number of evaluation sites on each unverified SD wafer. The system may also include one or more control devices coupled to one or more SD processing devices and one or more SD transport subsystems in one or more processing subsystems. One or more control devices may be provided to create S-D wafer status data for each unverified S-D wafer. The S-D wafer status data has a number of required generation sites and a number of required evaluation sites for each unverified S-D wafer. This is coupled to one or more SD transport subsystems to produce a first set of evaluation wafers having a first number of unverified SD wafers that are evaluated using a first S-D evaluation process. A first number of available evaluations by using the first operating state for the one or more SD evaluators to create a first operating state for a plurality of SD evaluators in one or more subsystems Create first SD transport sequence using wafer data, SD wafer status data, first number of SD evaluation wafers, first number of available evaluation devices, or a combination thereof to determine equipment Therefore, the first correction operation is applied when the number of SD evaluation wafers is equal to or less than the first number that is the number of available evaluation apparatuses.

  In some additional embodiments, the present invention provides a method and apparatus for verifying SD processing. The verified S-D generation process may generate one or more verified evaluation parts at one or more points on the wafer to be processed. As risk factors decrease, the number of sites required to validate the process also decreases, which can improve throughput. In addition, when the confidence value rises, the number of sites required for processing verification is also reduced, which can improve throughput. For products of sufficient quality, verification decisions can be made using fewer wafers and fewer sites. In one process, one or more site-dependent (SD) wafers may be received by one or more SD transport subsystems that can be combined with one or more SD processing equipment in one or more processing subsystems. . Each wafer may have associated wafer data. The wafer data may include history and / or real time data. In various processes, SD wafer status data may be determined for each wafer, a first set of verification wafers may be created using the SD wafer status data and wafer data, and the first set of verification wafers. May have multiple SD wafers. For each verification wafer, the number of verification sites required, the number of verification sites accessed, and the number of other verification sites may be determined from the S-D wafer state data. Next, for the first verification wafer in the first set of verification wafers, the first processing verification sequence is the wafer data, the SD wafer status data, the number of required verification sites, and the sites accessed for verification. Or a number of other verification sites, or a combination thereof. For the first verification wafer, the first S-D verification process may be determined by using the process verification sequence, and the first S-D verification process may include one or more processes. When the first S-D processing device is available, the first verification wafer uses the SD transport subsystem coupled to the first processing subsystem, thereby allowing the first S-D processing device in the first processing subsystem to be used. Can be transported to When the first S-D processing apparatus is not available, the first evaluation wafer is delayed for the first period by using the S-D transfer subsystem.

  In yet another embodiment, the present invention provides a method for generating a library for SD evaluation. The method includes the steps of generating an SD reference structure in one or more layers on the wafer using an SD processing sequence, and obtaining SD evaluation data for the SD reference structure by using an evaluation subsystem. A step of comparing the SD evaluation data with the predicted library-related data, a step of creating reliability data and risk evaluation data for the evaluation data, and the reference structure when the risk evaluation limit is satisfied. A step of authorizing as a verified structure, and a step of storing data relating to the verified reference structure in an SD evaluation library. The data in the SD evaluation library is an SD set consisting of multiple types of wavelengths, and when a matching condition is found, the SD evaluation library data regarding the matching condition is used to certify the SD reference structure or find a matching condition. Characterized by applying the first corrective action when it is not possible. In addition, the present invention provides a system for generating an S-D evaluation library. The system includes an SD processing subsystem that generates an SD reference structure in one or more layers on a wafer, an SD evaluation subsystem that provides evaluation data, and a comparison of the evaluation data with predicted data; and A control device may be provided for storing data related to the verified reference structure in the SD evaluation library.

  In additional embodiments, the present invention provides a system and method for performing dual damascene processing by using a site dependent (S-D) processor, an S-D evaluator, an S-D generator, or an S-D evaluator, or a combination thereof.

  In another additional embodiment, the present invention provides a method for performing a double patterning process sequence using multiple SD processes. The method may include receiving a first set of wafers by a first SD transport subsystem in the processing system. The processing system includes one or more lithography subsystems, one or more scanner subsystems, one or more etching subsystems, one or more thermal subsystems, one or more evaluation subsystems, one or more inspections Subsystems, one or more rework subsystems, or one or more deposition subsystems, or combinations thereof may be included.

  Other aspects of the invention will become apparent from the following detailed description and accompanying drawings.

1 is an exemplary block diagram of a processing system according to an embodiment of the present invention. 2 shows an exemplary flow diagram of a wafer processing method using SD processing according to an embodiment of the present invention. FIG. 4 shows a simplified diagram of a wafer map according to an embodiment of the present invention. FIG. 4 shows a simplified block diagram of an exemplary subsystem according to an embodiment of the present invention. FIG. 4 depicts an exemplary flow diagram of a method for verifying an S-D site, an S-D wafer, and / or an S-D process according to an embodiment of the present invention. 2 represents an exemplary flow diagram of a method for generating an S-D evaluation library according to an embodiment of the present invention. A typical flow diagram of a method for generating a dual damascene structure using S-D processing is shown. Fig. 4 represents another typical flow diagram of a method for generating an S-D evaluation library. 1 is a block diagram of an embodiment of the present invention illustrating a system of modules. FIG. Here, each module includes all the equipment necessary to process the wafer.

  The invention will now be described by way of example with reference to the accompanying schematic drawings. Corresponding reference numbers in the figures represent corresponding parts.

  The present invention provides an apparatus and method for processing a wafer having a number of semiconductor devices thereon by using site-dependent (S-D) processing, sequences, and / or subsystems. When a wafer is received, the wafer may be identified as a site-dependent (S-D) wafer or a non-site-dependent (N-S-D) wafer. In various embodiments, an SD processing sequence that can include executing an SD transfer sequence, processing an SD wafer, generating an SD evaluation library, one or more SD generation processes, and / or one or more SD evaluation processes. An apparatus and a method for executing and executing SD verification processing are provided.

  The processing system may include an S-D processing device, an S-D evaluation device, and one or more SD transport subsystems coupled to the S-D processing device and the S-D evaluation device. Alternatively, other configurations may be used.

  One or more sites may be served at various points on the S-D wafer. The site may be relevant to the process. One or more of the sites may be used in the S-D evaluation and / or verification process. The SD evaluation and / or verification process evaluates and / or verifies an SD transfer sequence, SD wafer, SD process, SD evaluation library, SD process sequence, or a specific site used in a process, or a combination thereof. May be used for

  S-D wafers may have associated wafer data. The wafer data may include real time and historical data. The wafer data may be S-D and / or N-S-D data. In addition, the wafer data may include reliability data and / or risk data about the wafer. The S-D wafer may have associated site data. The site data may include the number of sites required, the number of sites visited, reliability data and / or risk data for one or more sites, site ranking data, transport sequence data, process related data, evaluation / verification related data, or You may have these bonds. The wafer data may include one or more transfer sequence variables that can be used to set SD transfer sequence characteristics. In order to optimize throughput, maximize use of processing equipment, maximize use of evaluation equipment, and reprocess wafers with defects as quickly as possible, the S-D transfer sequence may change in real time. The wafer data may have one or more process sequence variables that can be used to set the S-D process sequence characteristics. Optimize throughput, maximize use of processing equipment, maximize use of evaluation equipment, rework defective wafers as quickly as possible, avoid offline and / or defective equipment, one or more The SD transfer sequence may change in real time to transfer the wafer when the site is evaluated and / or verified.

  For each S-D wafer, an S-D transfer sequence and / or an S-D processing sequence may also be set by using the wafer data. The S-D processing sequence may be set based on various conditions detailed in this specification. The SD transport sequence may be set based on various conditions detailed in this specification.

  The S-D transfer sequence may be set based on the number of sites required for each wafer, the number of wafers that require processing, the number of available S-D processing apparatuses, and the carry-in data for the S-D transfer subsystem.

  The SD transfer sequence also obtains reliability data for the first site of the required sites on the first wafer within the minimum time, and one or more of the required sites on the first wafer within the minimum time. Acquire reliability data for the site, acquire reliability data for all of the required sites on the first wafer within the minimum time, and acquire required data on one or more additional wafers within the minimum time To obtain reliability data for the first site, and obtain reliability data for one or more of the required sites on one or more additional wafers within the minimum time and within the minimum time Obtain reliability data for all of the required sites on one or more additional wafers, and acquire reliability data for the first required sites on all wafers belonging to Group 1 within the minimum time. And the minimum time Obtain reliability data for one or more required sites on all wafers belonging to the first group and / or trust for all required sites on all wafers belonging to the first group within a minimum time May be configured to obtain sex data.

  In other embodiments, the SD transfer sequence obtains risk data on the first wafer within a minimum time, obtains risk data on one or more additional wafers within a minimum time, and / or minimizes It may be set to acquire risk data on all wafers belonging to the first group within a time period. In addition, the transfer sequence acquires new wafer data on the first wafer within a minimum time, acquires new wafer data on one or more additional wafers within a minimum time, and / or It may be set to acquire new wafer data on all the wafers belonging to the first group within the minimum time. For example, S-D and / or N-S-D wafers may be used, S-D and / or N-S-D reliability data may be acquired, and S-D and / or N-S-D risk data may be acquired.

  In yet another embodiment, the SD transport sequence acquires risk data for the first process within a minimum time, acquires risk data for one or more additional processes within the minimum time, and / or the minimum time The risk data for all the processes belonging to the first group may be acquired from the first library.

  In additional embodiments, the SD transport sequence acquires the first library related data within a minimum time, acquires the additional library related data within a minimum time, and / or the first subset of the first library within a minimum time. It may be set to acquire all the library related data to which it belongs. For example, S-D and / or N-S-D library related data may be obtained.

  In addition, the SD transfer sequence can transfer the wafer to one or more designated processing equipment and / or evaluation equipment, one or more available processing equipment and / or evaluation equipment, and one or more “high” Set to be transported to one or more low-risk processing devices and / or evaluation devices, to one or more high-reliability processing devices and / or evaluation devices. May be good. For example, S-D and / or N-S-D wafers may be used, S-D and / or N-S-D processing equipment may be used, and S-D and / or N-S-D evaluation equipment may be used.

  In additional embodiments, when one or more processing devices and / or evaluation devices are not available, the SD transport sequence may be set to use the SD transport subsystem, or one or more processing devices and / or When the evaluation device is not available, the SD transfer sequence may be set to “grace” and / or “save” the wafer for a predetermined period of time using the SD transfer subsystem, or one or more processing devices and When the evaluation device is not available, the SD transfer sequence may be set to transfer wafers to other subsystems within a minimum time using the SD transfer subsystem.

  The SD transfer sequence also transfers wafers that have been “graced” and / or “stored” within a minimum amount of time to one or more processing and / or evaluation equipment, and one or more newly available processes. Transport to a device and / or evaluation device, transport to one or more processing devices and / or evaluation devices available after a period of time, transport to one or more low risk processing devices and / or evaluation devices, Alternatively, it may be set so as to be conveyed to one or more high-reliability processing devices and / or evaluation devices.

  In another additional embodiment, the SD transfer sequence transfers wafers that have been “graced” and / or “stored” within a minimum time to one or more processing and / or evaluation devices, and one or more new Transport to available processing equipment and / or evaluation equipment, transport to one or more processing equipment and / or evaluation equipment available after a period of time, and one or more low risk processing equipment and / or It may be set to be transported to an evaluation device or to one or more high-reliability processing devices and / or evaluation devices.

  The SD transfer sequence may be set to transfer a wafer to one or more subsystems for pre-processing and / or post-processing. For example, S-D wafer data—eg, wafer profile data, wafer thickness data, wafer temperature data, or optical data, or a combination thereof—may be acquired during pre-processing and / or post-processing. When an error occurs, the SD transfer sequence may be set to transfer the wafer to one or more rework subsystems within a minimum time.

  The SD transport sequence maximizes yield, allows operator intervention, and allows host system intervention by allowing processing to continue with at least one verified device on top. And / or may be set to minimize delay caused by the scanner subsystem. Current factory systems do not have an SD transfer subsystem for transferring wafers and / or an SD processing subsystem for processing wafers. In addition, current factory systems do not have S-D processing for processing wafers and / or for transferring S-D wafer data from one subsystem to another after processing the wafers. The S-D variation caused by wafer processing is not uniform across the wafer, and the S-D variation may include chamber-to-chamber variation, processing time, processing chemicals, and long-term chamber drift.

  By reducing the size of the site to less than 65 nm node, accurate processing and / or measurement data becomes more important and difficult to acquire. S-D processing may be used to more accurately process and / or measure these minimal sites. S-D data can be compared to warning and / or control limits. When the operation rule is violated, an alarm is generated to indicate that a problem has occurred in the processing.

  FIG. 1 shows an exemplary block diagram of a processing system according to an embodiment of the present invention. In the illustrated embodiment, the processing system 100 includes a system controller 195, a first lithography subsystem 110, a scanner subsystem 115, a second lithography subsystem 120, a third lithography subsystem 125, a thermal processing subsystem 130, an inspection subsystem. It has a system 135, an etching subsystem 140, a deposition subsystem 145, an evaluation subsystem 150, and a rework subsystem 155. Although a single subsystem (110, 115, 120, 125, 130, 135, 140, 145, 150, and 155) is shown in the illustrated embodiment, multiple subsystems may be used. good. For example, in some embodiments, multiple subsystems (110, 115, 120, 125, 130, 135, 140, 145, 150, and 155) may be used in the processing system 100. In addition, one or more subsystems (110, 115, 120, 125, 130, 135, 140, 145, 150, and 155) can be used to handle one or more processes. You may have the above processing apparatus.

  The system controller 195 uses the data transfer subsystem 106 to provide a first lithography subsystem 110, a scanner subsystem 115, a second lithography subsystem 120, a third lithography subsystem 125, a thermal processing subsystem 130, an inspection subsystem. 135, etching subsystem 140, deposition subsystem 145, evaluation subsystem 150, and rework subsystem 155 may be combined. For example, the second lithography subsystem 120 may have a cleaning subsystem (not shown) (after immersion).

  The first lithography subsystem 110 may be coupled at the first SD transport subsystem 101 and 111a and may be coupled at the second SD transport subsystem 102 and 111b. The scanner subsystem 115 may be coupled at the first SD transport subsystem 101 and 116a and may be coupled at the second SD transport subsystem 102 and 116b. The second lithography subsystem 120 may be coupled at the first SD transport subsystem 101 and 121a and may be coupled at the second SD transport subsystem 102 and 121b. The third lithography subsystem 125 may be coupled at the first SD transport subsystem 101 and 126a and may be coupled at the second SD transport subsystem 102 and 126b. The heat treatment subsystem 130 may be coupled by the first SD transport subsystems 101 and 131a and may be coupled by the second SD transport subsystems 102 and 131b. The inspection subsystem 135 may be coupled at the first SD transport subsystem 101 and 136a and may be coupled at the second SD transport subsystem 102 and 136b. Etch subsystem 140 may be coupled at first SD transport subsystems 101 and 141a and coupled at second SD transport subsystems 102 and 141b. The deposition subsystem 145 may be coupled at the first SD transport subsystems 101 and 146a and may be coupled at the second SD transport subsystems 102 and 146b. The evaluation subsystem 150 may be coupled by the first SD transport subsystems 101 and 151a and may be coupled by the second SD transport subsystems 102 and 151b. The rework subsystem 155 may be coupled at the first SD transport subsystem 101 and 156a and may be coupled at the second SD transport subsystem 102 and 156b. Alternatively, other coupling arrangements may be used.

  In addition, the third transport subsystem 103 may be coupled to the first SD transport subsystem 101 and may be coupled to the second SD transport subsystem 102. The third transport subsystem 103 may be coupled with other transport subsystems and / or processing systems (not shown). For example, the transfer system (101, 102, and 103) uses a transfer device 104 coupled to a supply device 105 to receive a wafer, transfer the wafer, align the wafer, store the wafer, and / or Wafer transfer may be delayed. Alternatively, other transport means may be used.

  A manufacturing execution system (MES) 180 may be coupled to the system controller 195 by using the data transfer subsystem 106. Alternatively, factory level and / or host system may be used, and other coupling techniques may be used. In alternative embodiments, one or more additional subsystems may be required. For example, the system controller 195 may be coupled to other processing systems and / or subsystems (not shown). Alternatively, other configurations may be used and other combining techniques may be used.

  The first lithography subsystem 110 may include one or more processing devices 112. The one or more processing devices 112 may be coupled with the internal transport device 113 and / or coupled with the first SD transport subsystems 101 and 111a. The scanner subsystem 115 may include one or more processing devices 117. The one or more processing devices 117 may be coupled with the internal transport device 118 and / or coupled with the first SD transport subsystems 101 and 116a. The second lithography subsystem 120 may include one or more processing devices 122. The one or more processing devices 122 may be coupled with the internal transport device 123 and / or may be coupled with the first SD transport subsystems 101 and 121a. The third lithography subsystem 125 may include one or more processing devices 127. The one or more processing devices 127 may be coupled with the internal transport device 128 and / or coupled with the first SD transport subsystems 101 and 126a. The thermal processing subsystem 130 may include one or more processing devices 132. The one or more processing devices 132 may be coupled with the internal transport device 133 and / or may be coupled with the first SD transport subsystems 101 and 131a. The inspection subsystem 135 can include one or more processing devices 137. The one or more processing devices 137 may be coupled with the internal transport device 138 and / or may be coupled with the first SD transport subsystems 101 and 136a. Etching subsystem 140 may include one or more processing devices 142. The one or more processing devices 142 may be coupled with the internal transport device 143 and / or coupled with the first SD transport subsystems 101 and 141a. The deposition subsystem 145 can include one or more processing devices 147. The one or more processing devices 147 may be coupled with the internal transport device 148 and / or may be coupled with the first SD transport subsystems 101 and 146a. Evaluation subsystem 150 may include one or more processing devices 152. The one or more processing devices 152 may be coupled with the internal transport device 153 and / or may be coupled with the first SD transport subsystems 101 and 151a. The rework subsystem 155 can include one or more processing devices 157. The one or more processing devices 157 may be coupled with the internal transport device 158 and / or coupled with the first SD transport subsystems 101 and 156a. Various numbers of processing devices can be used within a subsystem. The processing device may be coupled in series and / or in parallel and may have one or more input ports and / or one or more output ports. For example, the processing apparatus may include tools, modules, chambers, sensors, and / or other devices.

  In some embodiments, the subsystem may have additional transport devices. The first lithography subsystem 110 may include one or more internal transport devices 113 that can be coupled by the second SD transport subsystems 102 and 111b. The scanner subsystem 115 may include one or more internal transport devices 118 that can be coupled to the second SD transport subsystem 102 and 116b. The second lithography subsystem 120 may include one or more internal transport devices 123 that can be coupled by the second SD transport subsystems 102 and 121b. The third lithography subsystem 125 may include one or more internal transport devices 128 that can be coupled by the second SD transport subsystems 102 and 126b. The heat treatment subsystem 130 may include one or more internal transfer devices 133 that can be coupled by the second SD transfer subsystems 102 and 131b. The inspection subsystem 135 may include one or more internal transport devices 138 that can be coupled by the second SD transport subsystems 102 and 136b. Etching subsystem 140 may include one or more internal transport devices 143 that can be coupled by second SD transport subsystems 102 and 141b. The deposition subsystem 145 may include one or more internal transport devices 148 that can be coupled by the second SD transport subsystems 102 and 146b. The evaluation subsystem 150 may include one or more internal transport devices 153 that can be coupled by the second SD transport subsystems 102 and 151b. The rework subsystem 155 may include one or more internal transport devices 158 that can be coupled by the second SD transport subsystems 102 and 156b. In other embodiments, any number of transport devices and / or transport subsystems may be used in a system. The transport device and / or transport subsystem may be coupled in series and / or in parallel and may have one or more input ports and / or one or more output ports.

  The first lithography subsystem 110 may include one or more controllers 114 that can be combined with the system controller 195 and / or other controllers by using the data transfer subsystem 106. The scanner subsystem 115 may include one or more controllers 119 that can be coupled with the system controller 195 and / or other controllers by using the data transfer subsystem 106. The second lithography subsystem 120 may include one or more controllers 124 that can be combined with the system controller 195 and / or other controllers by using the data transfer subsystem 106. The third lithography subsystem 125 may include one or more controllers 129 that can be coupled to the system controller 195 and / or other controllers by using the data transfer subsystem 106. The thermal processing subsystem 130 may include one or more controllers 134 that can be coupled to the system controller 195 and / or other controllers by using the data transfer subsystem 106. The inspection subsystem 135 may include one or more controllers 139 that can be coupled with the system controller 195 and / or other controllers by using the data transfer subsystem 106. Etch subsystem 140 may include one or more controllers 144 that may be coupled to system controller 195 and / or other controllers by using data transfer subsystem 106. The deposition subsystem 145 may include one or more controllers 149 that can be coupled to the system controller 195 and / or other controllers by using the data transfer subsystem 106. The evaluation subsystem 150 may include one or more controllers 154 that can be coupled to the system controller 195 and / or other controllers by using the data transfer subsystem 106. The rework subsystem 155 may include one or more controllers 159 that can be coupled to the system controller 195 and / or other controllers by using the data transfer subsystem 106. Alternatively, other coupling arrangements may be used. In other embodiments, any number of controllers may be used in a system. The controller may be coupled in series and / or in parallel and may have one or more input ports and / or one or more output ports. For example, the controller may have an 8-bit, 16-bit, 32-bit, and / or 64-bit processor.

  In addition, subsystems (110, 115, 120, 125, 130, 135, 140, 145, 150, and 155) can be coupled together by using intranet, internet, and wired and / or wireless connections, It may be combined with other devices. Control devices (114, 119, 124, 129, 134, 139, 144, 149, 154, 159, and 195) may be coupled together as required.

  When performing real-time S-D processing, one or more controllers (114, 119, 124, 129, 134, 139, 144, 149, 154, 159, and 195) may be used. The controller may receive real-time data and update subsystems, processing devices, processes, recipes, profiles, and / or model data. One or more controllers (114, 119, 124, 129, 134, 139, 144, 149, 154, 159, and 195) perform real-time SD processing by using real-time data, and are described herein. Real-time SD data may be provided as described. In some embodiments, one or more controllers may exchange one or more SECS messages with MES 180, read and / or remove SD information, feed forward and / or feedback SD information, and / or SECS. It may be used for transmission of SD information. One or more controllers (114, 119, 124, 129, 134, 139, 144, 149, 154, 159, and 195) perform SD processing by using real-time data and provide real-time SD data Good. For example, the controller can be used to receive, process, and / or transmit messages that include real-time data.

  In addition, the control devices (114, 119, 124, 129, 134, 139, 144, 149, 154, 159, and 195) may have a memory (not shown) as required. For example, memory (not shown) may be used to store instructions executed by information and control devices (114, 119, 124, 129, 134, 139, 144, 149, 154, and 159), and It may be used to store temporary variables or other intermediate information during execution of instructions by various computers / processors in processing system 100. One or more controllers (114, 119, 124, 129, 134, 139, 144, 149, 154, and 159) or other system components are means for reading data and / or instructions from a computer readable medium And means for writing data and / or instructions to a computer readable medium.

  The processing system 100 is responsive to a computer / processor in the processing system executing one or more sequences of one or more instructions contained in memory and / or received in a message. Some or all of the processing steps may be performed. Such instructions may be received from another computer, a computer readable medium, or a network connection.

  Stored in any one or any combination of computer readable media, the present invention provides control of a processing system, driving a device or apparatus that implements the present invention, and a human user. Software for realizing interaction with the processing system 100 is included. Such software may include, but is not limited to, device drivers, operating systems, development tools, and application software. The computer-readable medium further includes a computer program product according to the present invention that executes part or all of the processing executed when the present invention is implemented (when processing is distributed).

  As used herein, “computer readable medium” refers to any medium that participates in providing instructions to a processor for execution. The computer readable medium may take any form. Any form thereof includes, but is not limited to, non-volatile media, volatile media, and transmission media.

  The subsystems (110, 115, 120, 125, 130, 135, 140, 145, 150, and 155) may have processing equipment (not shown). In some embodiments, an integrated system may be provided that uses system components from Tokyo Electron Limited (TEL). In other embodiments, external subsystems and / or devices may be included. The processing apparatus may include one or more etching apparatus, deposition apparatus, ALD apparatus, measurement apparatus, ionization apparatus, polishing apparatus, coating apparatus, developing apparatus, exposure apparatus, and heat treatment apparatus. In addition, for example, a CD scanning electron microscope (CDSEM) device, a transmission electron microscope (TEM) device, a focused ion beam (FIB) device, an ODP device, an atomic force microscope (AFM) device, or other optical measurement device. Including a measuring device may be provided. Each subsystem and / or processing device may have different interface requirements. Controllers may be provided to meet these different interface requirements.

  One or more subsystems (110, 115, 120, 125, 130, 135, 140, 145, 150, and 155) have control components, GUI components, and / or database components (not shown). good. For example, a GUI component (not shown) provides an easy-to-operate interface. Its easy-to-operate interface allows users to monitor conditions, site-dependent (SD) and / or non-SD processing, strategies, plans, errors, faults, databases, rules, recipes, modeling applications, simulations, and / or Allows creation / monitoring / editing of spreadsheet applications, email messages, and diagnostic screens. As will be apparent to those skilled in the art, the GUI component does not need to provide an interface for all functions, and may provide an interface for a subset of these functions or other functions not listed herein.

  One or more controllers (114, 119, 124, 129, 134, 139, 144, 149, 154, and 159) and / or the system controller 195 may include a data transfer system 190 that exchanges information with the MES 180 and May be combined with other subsystems. Data transfer system 190 may include wired and wireless components.

  Subsystems (110, 115, 120, 125, 130, 135, 140, 145, 150, and 155) and / or controllers (114, 119, 124, 129, 134, 139, 144, 149, 154, and 159) ) May include an advanced process control (APC) application, an equipment anomaly detection and classification (FDC) application, and / or a run-to-run (R2R) application. In some embodiments, an APC application that is S-D, an FDC application that is S-D, and / or an R2R application that is S-D may be executed.

  In some embodiments, one or more of the controllers (114, 119, 124, 129, 134, 139, 144, 149, 154, 159, and 195) is an SD process optimization process, an SD model optimization process Alternatively, an SD library optimization process or an optimization process combining these may be executed. In the S-D optimization process, the process may be updated and / or optimized using wafer data, a model, a recipe, and profile data. For example, the S-D optimization process may operate in real time. By using real-time S-D optimization, more accurate process results can be achieved. Similar geometric techniques below the 65nm node require more accurate results.

  Materials and / or process results that may affect process recipes, profiles, models, and / or process results may vary from site to site within a wafer, wafer to wafer, and lot to lot. These variations are believed to be caused by changes and / or problems in one or more subsystems (110, 115, 120, 125, 130, 135, 140, 145, 150, and 155). Non-uniform films and / or non-uniform processes can cause problems. In addition, device-to-device variation, chamber-to-chamber variation, and chamber drift become a problem over time. Due to the nature of the control of the bottom CD using endpoints and sacrificial layers, during the etching process, thickness and / or uniformity can vary from site to site within a single wafer, from wafer to wafer, and from lot to lot. It is thought that will change. In addition, thickness variations can cause changes in optical properties and other physical properties. The S-D process may be used to solve or mitigate the problems caused by “overetch”.

  The output data and / or messages from the S-D process may be used in subsequent processes to optimize process accuracy and precision. Data may be passed to the S-D calculation process in real time as a real time variable. This overrides the default values of the current model and narrows the search space to achieve accurate results. Information may be used in a library-based system, or a real-time recursive process, or a combination thereof, to optimize processing.

  For example, an evaluation subsystem such as 150 may have an integrated optical digital profilometry (iODP) device (not shown). Alternatively, other measurement systems may be used. iODP equipment is available from Timbre Technologies (Tokyo Electron Limited). For example, ODP technology may be used to obtain critical dimension (CD) data, structural profile data, or via profile data. The wavelength range for iODP data can be less than about 200 nm to greater than about 900 nm. A typical iODP device may include an ODP profiler library, a profiler application server (PAS), and ODP profiler software. The ODP profiler library may include an application specific database for optical spectra, and corresponding semiconductor profiles, CDs, and film thicknesses. The PAS may have at least one computer connected to optical hardware and a computer network. The PAS may be provided to provide data communication, ODP library manipulation, measurement processing, result generation, result analysis, and result output. The ODP profiler software may include software installed on the PAS. The software manages measurement recipes, ODP profiler library, ODP profiler data, ODP profiler search / match results, ODP profiler calculation / analysis results, data communication, and interfaces to various measurement elements and computer networks.

  Evaluation subsystems such as 150 can be used for polarization reflectometry, spectroscopic ellipsometry, reflectometry, or other optical profiles that measure device profile, accurate critical dimension (CD), and thickness of multiple layers on a wafer. Measurement techniques may be used. An integrated metrology process (iODP) may be performed inline. As a result, the integrated process eliminates the need to break the wafer or perform long periods of data from external systems for analysis. ODP technology can be used in conjunction with existing thin film metrology systems that measure inline profiles and CDs and can be integrated with TEL processing systems for real-time process monitoring and control. A typical optical measurement system is described in Patent Document 6.

  Another process for generating an S-D library of simulated diffraction signals may include the use of a machine learning system (MLS). Prior to generating a library of simulated diffraction signals, the MLS is trained by using known input and output data. In one exemplary embodiment, simulated diffraction signals are generated using a machine learning system (MLS) that uses machine learning algorithms such as inverse error propagation, radial basis function, support vectors, kernel regression analysis, etc. Good. See Non-Patent Document 1 and Patent Document 7 for a more detailed description of machine learning systems and algorithms.

  See Patent Literature 8, Patent Literature 9, and Patent Literature 10 for a detailed explanation of the optimization of the measurement model.

  When a process based on regression analysis is used, the measured diffraction signal measured off the patterned structure may be compared with the simulated diffraction signal. The simulated diffraction signal is repeatedly generated based on the set of profile parameters, so that a convergence value can be obtained for the set of profile parameters that generate the simulated diffraction signal that most closely matches the measured diffraction signal. . See Patent Document 11 for a more detailed explanation of the approach based on regression analysis.

  When a library-based process is used, an optical metrology data library may be generated and / or improved by using SD and / or optimized recipes and / or models. The optical metrology data data library may include simulated diffraction signal pairs and corresponding sets of profile parameters. A detailed description of the generation of optical measurement data—for example, a library of diffraction signals by simulation and a corresponding set of profile parameters—is described in US Pat. A process based on regression analysis and / or library may have S-D and / or non-S-D steps.

  One or more controllers (114, 119, 124, 129, 134, 139, 144, 149, 154, 159, and 195) may perform APC, R2R, FDC, and / or S-D processing. APC, R2R, FDC, and / or S-D processing can operate as a control strategy, control plan, control model, and / or recipe manager that provides real-time S-D processing. S-D control and / or analysis strategies / plans cover multiple processing steps within a wafer processing sequence and can be used to analyze real-time and / or collected data and set error conditions. The S-D analysis process may be executed when the conditions match. During the execution of the S-D analysis process, one or more analysis plans may be executed. An SD plan may generate an error when a data failure, execution problem, or control problem occurs. The S-D data collection plan and / or analysis may reject data at one or more evaluation sites for a wafer or reject data due to failure of the S-D process. For example, the matching of dynamic S-D conditions allows a special configuration at each site.

  In one embodiment, the failure of the S-D process may not interrupt the S-D process. For example, S-D processing may include failure when a limit is exceeded. For example, a successful SD process can generate a warning message when it is approaching its limit. Pre-specified failure actions for S-D processing errors are stored in a database and may be obtained from the database when an error occurs.

  In some embodiments, one or more subsystems (110, 115, 120, 125, 130, 135, 140, 145, 150, and 155) receive SD data received via the data transfer system 190. Can be used to perform SD processing.

  When a lot of 25 wafers (hereinafter referred to as a 25 wafer lot) is being processed in the processing system, the throughput of the processing can be improved by providing 25 parallel processing paths. But this is not realistic. However, the SD processing system 100 can be used to efficiently and cost effectively process one or more 25 wafer lots. In addition, the S-D processing system 100 may be used to efficiently and cost-effectively process lots having a different number of wafers than the 25 wafer lot.

  The transport subsystem (101, 102, and 103) and transport device (113, 118, 123, 128, 133, 138, 143, 148, 153, and 158) can use the SD transport sequence and / or processing to One or more wafers in one or more wafer lots may be efficiently and cost-effectively transferred, aligned, delayed, and / or stored. Some S-D processes may be wafer dependent processes, lot dependent processes, and / or product dependent processes.

  The first lithography subsystem 110 may include one or more processing devices 112. The processing device 112 may process, measure, inspect, align, and / or store one or more wafers by using S-D processing and / or non-S-D processing. The transport device 113, the first SD transport subsystem 101, and / or the second SD transport subsystem 102 can transport, measure, and inspect one or more wafers by using SD processing and / or non-SD processing. , Alignment and / or storage. In some embodiments, the first lithography subsystem 110 may include one or more processing devices 112. The processing apparatus 112 may perform coating processing, heat treatment, inspection processing, alignment processing, and / or storage processing on one or more wafers by using S-D processing and / or non-S-D processing. For example, one or more processing units 112 may be used to deposit one or more mask layers having a photoresist material and / or an anti-reflective coating (ARC) material, and the one or more processing units 112 may be It may be used for heat-treating (baking) one or more mask layers. In addition, one or more processing devices 112 may be used to measure and / or inspect one or more mask layers. S-D processing and / or non-S-D processing may be used to measure and / or inspect one or more wafers. One or more control devices 113 may perform S-D processing to determine whether the wafer has been processed correctly or whether rework processing is necessary. The internal transfer device 113, the first SD transport subsystem 101, and / or the second SD transport subsystem 102 may transport a defective wafer to the rework subsystem.

  In other embodiments, the first lithography subsystem 110 may include one or more processing units 112 that perform processes that can cause contamination. One or more processing devices 112 may be isolated from other subsystems. This can reduce defects and minimize the risk of contamination. One or more processing devices 112 may include suspended particulate particle counters that monitor peripheral defect levels that can be set within the wafer path and / or critical processing areas. A detection level for the warning condition may be set. For example, these processes may have “dirty” baking processes, and this allows these “dirty” processes to be isolated from other systems. In addition, one or more rework processes may be performed by a processing device that is isolated from other subsystems.

  The scanner subsystem 115 may include one or more processing devices 117. The processing apparatus 117 may process, measure, inspect, align, and / or store one or more wafers by using S-D processing and / or non-S-D processing. The internal transfer device 118, the first SD transport subsystem 101, and / or the second SD transport subsystem 102 can transfer, measure, or transfer one or more wafers by using SD processing and / or non-SD processing. It may be inspected, aligned and / or stored. In some embodiments, scanner subsystem 115 may include one or more processing devices 117. The processing apparatus 117 performs exposure processing, heat treatment, drying processing, measurement processing, inspection processing, alignment processing, and / or storage processing on one or more wafers by using SD processing and / or non-SD processing. You can do it. In addition, the scanner subsystem 115 may be used to perform wet exposure processing and / or dry exposure processing. The wet exposure process and / or the dry exposure process may be S-D. In other processing sequences, the scanner subsystem 115 may be used to perform an extreme ultraviolet (EUV) exposure process. The extreme ultraviolet (EUV) exposure process may be S-D. For example, one or more processing units 117 may be used to expose one or more mask layers that include a photoresist material and / or an anti-reflective coating (ARC) material, and the one or more processing units 117 are It may be used for patterning one or more mask layers. In addition, one or more processing devices 117 may be used to measure and / or inspect one or more patterned layers. S-D processing and / or non-S-D processing may be used to measure and / or inspect one or more wafers. One or more control devices 113 may perform S-D processing to determine whether the wafer has been processed correctly or whether rework processing is necessary. The internal transport device 118, the first SD transport subsystem 101, and / or the second SD transport subsystem 102 may transport the defective wafer to the rework subsystem.

  The second lithography subsystem 120 may include one or more processing devices 112. The processing device 112 may process, measure, inspect, align, and / or store one or more wafers by using S-D processing and / or non-S-D processing. The internal transfer device 123, the first SD transport subsystem 101, and / or the second SD transport subsystem 102 can transfer, measure, and transfer one or more wafers by using SD processing and / or non-SD processing. It may be inspected, aligned and / or stored. In some embodiments, the second lithography subsystem 120 may include one or more processing devices 122. The processing apparatus 122 performs cleaning processing, heat treatment, measurement processing, inspection processing, alignment processing, and / or storage processing on one or more wafers by using SD processing and / or non-SD processing. good. For example, one or more processing units 122 may be used to perform a cleaning process after immersion, and one or more processing units 122 are used to heat treat (dry) one or more mask layers. It ’s good. In addition, one or more processing devices 122 may be used to measure and / or inspect one or more cleaned and / or dried wafers. S-D processing and / or non-S-D processing may be used to measure and / or inspect one or more wafers. One or more controllers 124 may perform S-D processing and / or non-S-D processing to determine whether the wafer has been accurately cleaned or whether rework processing is necessary. For example, wafer spots and / or other anomalies may be detected. The internal transfer device 123, the first SD transfer subsystem 101, and / or the second SD transfer subsystem 102 may transfer a defective wafer to the rework subsystem.

  The third lithography subsystem 125 may include one or more processing devices 127. The processing device 127 may process, measure, inspect, align, and / or store one or more wafers by using S-D processing and / or non-S-D processing. The internal transfer device 128, the first SD transfer subsystem 101, and / or the second SD transfer subsystem 102 can transfer, measure, or transfer one or more wafers by using SD processing and / or non-SD processing. It may be inspected, aligned and / or stored. In some embodiments, the third lithography subsystem 125 may include one or more processing devices 127. The processing device 127 performs development processing, heat treatment, measurement processing, inspection processing, alignment processing, and / or storage processing on one or more wafers by using SD processing and / or non-SD processing. good. For example, one or more processing devices 127 may be used to develop one or more patterned mask layers--which may include a photoresist material and / or an anti-reflective coating material--and one or more. The processing device 127 may be used for heat treatment (baking) of one or more patterned mask layers. In addition, one or more processing devices 127 may be used to measure and / or inspect one or more cleaned and / or dried wafers. S-D processing and / or non-S-D processing may be used to measure and / or inspect one or more wafers. One or more control devices 129 may perform S-D processing and / or non-S-D processing to determine whether the wafer has been processed correctly or whether rework processing is necessary. For example, wafer spots and / or other anomalies may be detected. The internal transport device 128, the first SD transport subsystem 101, and / or the second SD transport subsystem 102 may transport the defective wafer to the rework subsystem.

  In other embodiments, the third lithography subsystem 125 may include one or more processing units 127 that perform processes that can cause contamination. One or more processing units 127 may be isolated from other subsystems. This can reduce defects and minimize the risk of contamination. One or more processing devices 127 may include a suspended particulate counter that monitors peripheral defect levels that can be set within the wafer path and / or critical processing areas. A detection level for the warning condition may be set. For example, these processes may have “dirty” baking processes, and this allows these “dirty” processes to be isolated from other systems. In addition, one or more rework processes may be performed by a processing device that is isolated from other subsystems.

  In other embodiments, the first lithography subsystem 110 may include one or more processing units 112 that perform processes that can cause contamination. One or more processing devices 112 may be isolated from other subsystems. This can reduce defects and minimize the risk of contamination. One or more processing units 112 may include atmospheric particle counters that monitor atmospheric defect levels that can be set within the wafer path and / or critical processing areas. A detection level for the warning condition may be set. For example, these processes may have “dirty” baking processes, and this allows these “dirty” processes to be isolated from other systems. In addition, one or more rework processes may be performed by a processing device that is isolated from other subsystems.

  The thermal processing subsystem 130 may include one or more processing devices 132. The processing device 132 may process, measure, inspect, align, and / or store one or more wafers by using S-D processing and / or non-S-D processing. The internal transfer device 133, the first S-D transfer subsystem 101, and / or the second S-D transfer subsystem 102 can transfer and measure one or more wafers by using SD processing and / or non-SD processing. It may be inspected, aligned and / or stored. In some embodiments, the thermal processing subsystem 130 may include one or more processing devices 132. The processing device 132 uses one or more of SD processing and / or non-SD processing to perform one or more of baking processing, annealing processing, spike annealing processing, heat treatment, measurement processing, inspection processing, alignment processing, and / or storage processing. May be performed on a single wafer. For example, one or more processing units 132 may be used to increase and / or control the temperature of one or more wafers, and the one or more processing units 132 may be used to increase the temperature of one or more wafers. Can be used to cool and / or control the temperature. In addition, one or more processing devices 132 may be used to measure and / or inspect one or more wafers. S-D processing and / or non-S-D processing may be used to measure and / or inspect one or more wafers. One or more controllers 134 may perform S-D processing and / or non-S-D processing to determine whether the wafer has been processed correctly or whether rework processing is necessary. The internal transfer device 133, the first SD transport subsystem 101, and / or the second SD transport subsystem 102 may transport a defective wafer to the rework subsystem.

  The inspection subsystem 135 can include one or more processing devices 137. The processing device 137 may evaluate, process, measure, inspect, align, and / or store one or more wafers by using S-D processing and / or non-S-D processing. The internal transfer device 138, the first SD transport subsystem 101, and / or the second SD transport subsystem 102 can transfer, measure, and / or transfer one or more wafers by using SD processing and / or non-SD processing. It may be inspected, aligned and / or stored. In some embodiments, the inspection subsystem 135 may include one or more processing devices 137. The processing device 137 can perform evaluation processing, inspection processing, particle detection processing, measurement processing, alignment processing, verification processing, and / or storage processing using one or more wafers by using SD processing and / or non-SD processing. Good to run on. For example, one or more SD evaluation devices 137 may be used to perform optical inspection, and one or more SD evaluation processing devices 137 may be used for inspection at one or more wafers at short wavelengths. good. In addition, one or more S-D evaluation devices 137 may be used to detect particles on one or more wafers. S-D processing and / or non-S-D processing may be used to measure and / or inspect one or more surfaces of one or more wafers. One or more controllers 139 may perform S-D processing and / or non-S-D processing to determine whether the wafer has been processed correctly or whether rework processing is necessary. The internal transfer device 138, the first SD transport subsystem 101, and / or the second SD transport subsystem 102 may transport the defective wafer to the rework subsystem.

  The inspection subsystem 135 can include one or more processing devices 137. The processing device 137 may evaluate, process, measure, inspect, align, and / or store one or more wafers by using S-D processing and / or non-S-D processing. The internal transfer device 138, the first SD transport subsystem 101, and / or the second SD transport subsystem 102 can transfer, measure, and / or transfer one or more wafers by using SD processing and / or non-SD processing. It may be inspected, aligned and / or stored. In some embodiments, the inspection subsystem 135 may include one or more processing devices 137. The processing device 137 can perform evaluation processing, inspection processing, particle detection processing, measurement processing, alignment processing, verification processing, and / or storage processing using one or more wafers by using SD processing and / or non-SD processing. Good to run on. For example, one or more SD evaluation devices 137 may be used to perform optical inspection, and one or more SD evaluation processing devices 137 may be used for inspection at one or more wafers at short wavelengths. good. In addition, one or more S-D evaluation devices 137 may be used to detect particles on one or more wafers. S-D processing and / or non-S-D processing may be used to measure and / or inspect one or more surfaces of one or more wafers. One or more controllers 139 may perform S-D processing and / or non-S-D processing to determine whether the wafer has been processed correctly or whether rework processing is necessary. The internal transfer device 138, the first SD transport subsystem 101, and / or the second SD transport subsystem 102 may transport the defective wafer to the rework subsystem.

  Etching subsystem 140 may include one or more processing devices 142. The processing apparatus 142 may process, measure, inspect, align, and / or store one or more wafers by using S-D processing and / or non-S-D processing. The internal transfer device 143, the first SD transport subsystem 101, and / or the second SD transport subsystem 102 can transfer, measure, and / or transfer one or more wafers by using SD processing and / or non-SD processing. It may be inspected, aligned and / or stored. In some embodiments, the etching subsystem 140 may include one or more processing devices 142. The processing device 142 uses an SD process and / or a non-SD process to perform an etching process, a chemical oxide removal (COR) process, an ashing process, an inspection process, a rework process, a measurement process, an alignment process, and a verification process. Processing and / or storage processing may be performed on one or more wafers. For example, one or more processing units 142 may be used to create and / or modify a patterned wafer by using one or more SD and / or non-SD plasma etching processes, and one or more processes The apparatus 142 may be used to create and / or modify a patterned wafer by using one or more SD and / or non-SD non-plasma etch processes. In addition, one or more processing units 142 may be used to remove layer material and / or process residue from one or more wafers. S-D processing and / or non-S-D processing may be used to measure and / or inspect one or more surfaces of one or more wafers. One or more controllers 144 may perform S-D processing and / or non-S-D processing to determine whether the wafer has been processed correctly or whether rework processing is necessary. The internal transfer device 143, the first SD transfer subsystem 101, and / or the second SD transfer subsystem 102 may transfer a defective wafer to the rework subsystem.

  The deposition subsystem 145 can include one or more processing devices 147. The processing apparatus 147 may process, measure, inspect, align, and / or store one or more wafers by using S-D processing and / or non-S-D processing. The internal transfer device 148, the first SD transfer subsystem 101, and / or the second SD transfer subsystem 102 can transfer, measure, or transfer one or more wafers by using SD processing and / or non-SD processing. It may be inspected, aligned and / or stored. In some embodiments, the deposition subsystem 145 may include one or more processing devices 147. The processing device 147 may perform deposition processing, inspection processing, measurement processing, alignment processing, and / or storage processing on one or more wafers by using S-D processing and / or non-S-D processing. For example, one or more processing devices 147 may include physical vapor deposition (PVD) processing, chemical vapor deposition (CVD) processing, ionized physical vapor deposition (iPVD) processing, atomic layer deposition (ALD) processing, plasma atomic layer It can be used to perform a deposition (PEALD) process and / or a plasma enhanced chemical vapor deposition (PECVD) process. S-D processing and / or non-S-D processing may be used to measure and / or inspect one or more surfaces of one or more wafers. One or more control devices 149 may perform S-D processing and / or non-S-D processing to determine whether the wafer has been processed correctly or whether rework processing is necessary. The internal transport device 148, the first SD transport subsystem 101, and / or the second SD transport subsystem 102 may transport a defective wafer to the rework subsystem.

  Evaluation subsystem 150 may include one or more processing devices 152. The processing apparatus 152 may evaluate, measure, inspect, align, verify, and / or store one or more wafers by using S-D processing and / or non-S-D processing. The internal transfer device 153, the first SD transfer subsystem 101, and / or the second SD transfer subsystem 102 can transfer, measure, and transfer one or more wafers by using SD processing and / or non-SD processing. It may be inspected, aligned and / or stored. In some embodiments, the evaluation subsystem 150 may include one or more processing units 152. The processing device 152 uses one or more wafers to perform evaluation processing, inspection processing, temperature control processing, measurement processing, alignment processing, verification processing, and / or storage processing by using SD processing and / or non-SD processing. Good to run on. For example, one or more processing units 152 may be used to perform optical measurements that can be used to measure sites and / or structures on the wafer, and one or more processing units 152 may perform measurements on the wafer surface. Can be used to execute. In addition, the S-D evaluation apparatus may be used to determine the wafer curvature of one or more surfaces of one or more wafers, or to measure and / or inspect one or more surfaces of one or more wafers. The S-D evaluation device 152 may perform S-D processing and / or non-S-D processing. One or more controllers 154 may perform S-D processing and / or non-S-D processing to determine whether the wafer has been processed correctly or whether rework processing is necessary. The internal transfer device 153, the first SD transport subsystem 101, and / or the second SD transport subsystem 102 may transport a defective wafer to the rework subsystem.

  The rework subsystem 155 can include one or more processing devices 157. The processing device 157 may process, measure, inspect, align, and / or store one or more wafers by using S-D processing and / or non-S-D processing. The internal transfer device 158, the first SD transfer subsystem 101, and / or the second SD transfer subsystem 102 can transfer, measure, and transfer one or more wafers by using SD processing and / or non-SD processing. It may be inspected, aligned and / or stored. In some embodiments, the rework subsystem 155 may include one or more processing devices 157. The processing device 157 uses an SD process and / or a non-SD process to perform a cleaning process, an etching process, a layer removal process, an ashing process, an inspection process, a residue removal process, a measurement process, an alignment process, and a verification process. And / or storage processing may be performed on one or more wafers. For example, one or more processing units 157 may be used to remove a patterned wafer by using one or more SD and / or non-SD plasma etching processes, and one or more processing units 157 are one. It can be used to remove patterned wafers by using the above SD and / or non-SD non-plasma etching processes. In addition, one or more processing devices 157 may be used to remove damaged material from one or more wafers. S-D processing and / or non-S-D processing may be used to measure and / or inspect one or more surfaces of one or more wafers. One or more control devices 159 may perform S-D processing and / or non-S-D processing to determine whether the wafer has been processed correctly or whether rework processing is necessary. The internal transport device 158, the first SD transport subsystem 101, and / or the second SD transport subsystem 102 may transport a defective wafer to the rework subsystem.

  Each subsystem can process one or more wafers in parallel. One or more S-D processes and / or non-S-D processes may be performed.

  One or more formulated messages may be exchanged between subsystems. The controller may process the message and retrieve new data. When new data is available, the controller uses the new data to update the recipe, profile, and / or mode currently used for the wafer lot, or the recipe, profile, And / or update the mode. When the controller updates the recipe data, profile data, and / or modeling data for the currently processed wafer lot with the new data, the controller will update the recipe before the current wafer is processed, It can be determined whether the profile and / or model is updatable. When the recipe, profile, and / or model is updatable before the current wafer is processed, the current wafer may be processed by using the updated recipe, profile, and / or model. When the recipe, profile, and / or model cannot be updated before the current wafer is processed, the current wafer may be processed by using an unupdated recipe, profile, and / or model. For example, when a new 3D etch recipe, profile, and / or model is available, when will the etch subsystem and / or etch controller use the new SD etch recipe, profile, and / or model? Can be determined.

  One or more evaluation processes may provide S-D damage evaluation data and / or non-S-D damage evaluation data. S-D damage assessment data and / or non-S-D damage assessment data may include damaged layer, site, and / or structure data for each different site, wafer, and / or lot. One or more processing subsystems may use the damage assessment data to update and / or optimize processing recipe data, processing profile data, and / or modeling data. For example, the etch subsystem 140 may use the damage assessment data to update and / or optimize the etch chemistry and / or etch time. In addition, the deposition subsystem 145 and / or the lithography subsystem (110, 120, and 125) uses the damage assessment data to update and / or optimize recipe data, profile data, and / or modeling data. good.

  The S-D process may be used to create, modify, and / or evaluate isolated and / or nested structures at various times and / or sites. For example, wafer thickness data may be different near isolated and / or nested structures, and wafer thickness data may be different near the open area and / or the trench array area. The processing subsystem may update and / or optimize the S-D processing recipe and / or processing time using the new S-D data for isolated and / or nested structures. S-D processing may improve calculation accuracy using end point detection (EPD) data and processing time. While wafers and / or lots are being processed, SD data is generated and this data is fed back and / or feedforward in real time by the processing system so that the current wafer is processed, Alternatively, processing, measurement, and / or simulation recipes may be updated before additional wafers in the wafer lot are processed. Alternatively, non-S-D data may be used instead. When EPD data is used to stop S-D processing, the EPD time data and processing speed data may be used for calculation and / or estimation of S-D film thickness. During processing, monitoring and / or verification wafers are used periodically, and SD measurement processing is used to verify SD film thickness before and after SD processing-eg etching, deposition, lithography, cleaning, and polishing. good.

  The data of the evaluation subsystem 150 may comprise measurement and / or simulation signals related to S-D patterned or non-patterned structures. The S-D signal may be stored using process state data and wafer, lot, recipe, site, or wafer position data. The measurement data may include variables associated with the patterned structural profile, the type of metrology device and its associated variables, ranges used for variables that vary in modeling, and values of variables that are constant in modeling. Library profile data and SD data have fixed and / or variable profile data (eg CD, sidewall angle, N & K parameters) and / or instrument parameters (eg wavelength, incident angle, and / or azimuth) good.

  In some embodiments, the S-D process may optimize the optical metrology data recipe, structure, and / or model by using measured, predicted, and / or simulated data. SD processing may use condition / identification information, such as site ID, wafer ID, slot ID, lot ID, recipe, state, and patterned structure ID as a means of organizing and indexing data. . In some examples, the library data may include verified data related to products, devices, wafers, processes, lots, recipes, sites, locations, patterned and / or non-patterned structures. The S-D data may include data on the base film. The data of the underlying film may be used in the S-D process, and real-time updating and / or correction may be performed. During processing, some measurement sites cannot be measured due to interference from the underlying film and / or structure. A map based on S-D interference may be generated and used to determine site locations that can be used for measurement. In addition, S-D interference profiles and / or models that can be generated can be used to solve these problems.

  In addition, the S-D process may generate, update, and / or optimize a library of sets of S-D signals and corresponding S-D profile parameters. S-D processing may generate, update, and / or optimize data sets from a trained machine learning system (MLS). MLS can be trained with a subset of library data. The changed and / or updated values can be stored and / or used to improve performance. S-D and / or non-S-D libraries and databases may be used.

  Intervention and / or decision rules may be defined within an SD strategy, plan, model, subsystem, device, or process. Intervention and / or decision rules may be implemented whenever a matching condition is encountered. Intervention and / or decision rules may be for various processes and may be maintained in a database.

  In some examples, MES 180 may be equipped to monitor some system processes, and factory-level interventions and / or decision rules determine which processes are monitored and which data can be used. Can be used to In addition, factory level intervention and / or decision rules may be used to determine how data is managed when a process is changed, interrupted, and / or stopped. In addition, the MES 180 may provide S-D setting information and S-D update information. Data may be exchanged using the GEM SECS communication protocol.

  In general, the rules allow the S-D process to be changed based on the dynamic state of the semiconductor processing system and / or the processing state of the product. Some configuration information may be determined by the processing system and / or subsystem when the processing system and / or subsystem is first configured. In addition, rules can be used to set up a control hierarchy for SD processing. Rules can be used to determine when a process can be interrupted and / or stopped and / or what can be done when the process is interrupted and / or stopped. In addition, the processing rules may be used to determine what corrective action should be taken. Rules regarding the processing sequence and transfer sequence may also be used to determine which wafers should be processed and / or transferred. A typical method for processing a wafer may include a procedure for receiving one or more wafers and associated wafer data, and a procedure for setting a processing sequence and / or status data for each wafer.

The wafer state data may include ordered state variables (SQ _{n, m} ) that can be determined from the processing sequence. In some embodiments, the processing sequence may be obtained from MES 180 and cannot be modified. In other embodiments, a pseudo (modifiable) process sequence may be established and the ordered state and / or process start time may be changed by the subsystem computer and / or operator. For example, the additional sequence state in which the start time is changed can be set as an additional processing step, holding a wafer while executing the processing step, holding a wafer while executing a calculation, and various devices when the device is in an offline state. It may be used for wafer transfer to and / or correction and / or analysis of failure conditions. In addition, additional sequence steps and / or delayed start times are used to hold and / or transport wafers at the same time that SD data and / or messages are generated, processed, transmitted, and / or received. Good.

  In some examples, the SD transport subsystem may use the mounting data to determine where to transport the wafer. In another example, the SD transport subsystem may use process sequence data to determine where to transport the wafer. In yet another example, the SD transport subsystem may use the reliability data to determine where to transport the wafer. Alternatively, other processing may be used.

  The reliability data may include an evaluation of each process performed on the wafer. When the processing data from the S-D process is close to the expected value, the confidence value for the S-D process is considered high. When the processing data from the S-D process is not close to the expected value, the confidence value for the S-D process is considered low. For example, the confidence value may range from 0 to 9. Here, 0 represents a failure condition, and 9 represents normal operation.

  Wafer status data includes wafer count (WN) data, processing sequence (PS) data, step counter (SC) data, processing type (PT) data, processing status (PS) data, site dependency (SD) data, status (ST) data and grace time (DT) data may be included. Wafer number (WN) data may be used to identify the wafer. Wafer number (WN) data may be used to identify the wafer. Processing sequence (PS) data may be used to identify the processing sequence. Step counter (SC) data may be used to identify the number of processing steps for a wafer. The processing type (PT) data may be used to verify the type of processing performed in each processing step. Site dependency (SD) data is the number of site dependencies and may be used to verify one or more sites used to verify the type of S-D processing performed at each processing step. The state (ST) data may be used to determine whether the processing step has been performed and whether the processing step has been successful. The grace time (DT) data may include timing data. The grace time data may be used to grace wafer sequencing, calculations, processing, and / or measurements.

  In some embodiments, the wafer data may include variable data. For example, when the feed forward data is a first value, the data and / or message may be feed forward, and when the feed forward data is a second value, the data and / or message is feed forward. Not. When the S-D variable is the first value, the S-D process may be executed, and when the S-D variable is the second value, the non-S-D process may be executed.

  In some embodiments, the input / output message is a failure message, response message, error message, SD message, feedback message, non-SD message, internal message, external message, optimization message, status message, timing message, processing result message. And / or other messages. In addition, the message may have real-time instructions, settings, calculations, and / or overwrite information. Data may be used in real time as SD process variables / parameters, may be used to overwrite current recipe data, profiles, and / or model failure values, may be used to overwrite current transfer sequence data, It can be used to override the current start time and can be used to narrow the search space for determining recipes, profiles, and / or models, and associated accuracy limits.

  In various embodiments, one or more input messages are received and / or processed by one or more controllers (114, 119, 124, 129, 134, 139, 144, 149, 154, and 159). In addition, one or more output messages may be generated and / or transmitted by one or more controllers (114, 119, 124, 129, 134, 139, 144, 149, 154, and 159). In some examples, the input message may be a formulated message having S-D data and non-S-D data. The controller may process the formulated message and generate an S-D message and / or a separate non-S-D message for the subsystem. The S-D message may include S-D wafer data. The S-D wafer data can be used to reduce search time in libraries and databases, reduce calculation errors, and improve accuracy. For example, if the profile space in the library space is reduced, identification using S-D data is possible. In addition, S-D thickness and / or temperature data may be used, and the S-D process may use this data to determine a profile from the pre-file library in real time. Thereby, the measurement time is reduced and the throughput is increased. The controller reviews the input message in real time to determine when the input message contains an SD message that the controller can use and / or how the controller reads the SD message. You may judge whether to take out in real time. The message may use XML format and / or SML format. The system provides and operates exception handling with S-D messages that are sent, distributed, and / or parsed for multiple subsystems.

  For example, some devices / products may require 20-30 nm gate structures, and every wafer manufactured will have these structures on the order of 1 million. S-D processing may be used to minimize the number of tests that must be performed to ensure that the structure is correct.

  The processing sequence may also depend on the throughput of other subsystems, including the scanner subsystem. An SD transport system can be provided to maximize overall throughput. For example, the SD transport sequence may be set up and used to minimize throughput problems caused by slow subsystems, such as scanner subsystems. In some embodiments, the SD transfer subsystem may grace the transfer of low confidence and / or high risk wafers. In other embodiments, when the rework sequence is set up and executed in a relatively short time, the SD transfer subsystem may immediately send a low confidence and / or high risk wafer to the rework sequence. .

  S-D processing may produce specific results at specific locations on the wafer. When processing is sufficient, the confidence value is high, the number of wafers required for evaluation is minimized, and one site on one wafer represents a group of wafers and / or multiple wafers. May be used for When processing is sufficient, the processing results from all sites on one wafer are the same (within uniformity limits). When a product is developed, assessment sites / characteristics / structures at multiple sites can be used to establish a low risk treatment.

  The processing system 100 may be used to verify one or more SD processes.

  In some embodiments, one or more wafers are received by one or more SD transfer subsystems (101, 102), and the SD transfer subsystems (101, 102) are one or more in processing system 100. The subsystems (110, 115, 120, 125, 130, 135, 140, 145, 150, and 155) may be combined. Each wafer may have one or more layers above it and may have associated wafer data. The wafer data may include historical data and / or real time data. The SD transport subsystem may use business rules that determine when to send a wafer to a rework subsystem or storage point. These business rules may differ with the processing of the wafer (by providing additional layers).

  For example, a “golden wafer” may be manufactured using a “high performance” S-D processing sequence. At some positions on the wafer, a measurement structure may be fabricated near one or more gate structures. At these locations, CDSEM data is processed by using the first wafer, and the first reliability data can be obtained during the comparison. The reliability data can be compared to a confidence limit. If the first confidence limit is not accompanied by the first delta, the processing (measurement) sequence for the wafer may be changed and measurement data may be obtained from one or more additional sites on the wafer. If the reliability data is bad, the wafer can be reworked. If reliability data at two or more sites is poor, the wafer can be reworked. If the reliability data for two or more wafers is poor, the entire group may be reworked.

  An SD transport system can be provided to maximize the overall throughput. For example, the S-D transport sequence may be set and used to minimize throughput problems caused by slow subsystems, such as the scanner subsystem. In some embodiments, the SD transfer subsystem may grace the transfer of low confidence and / or high risk wafers. In other embodiments, when the rework sequence is set up and executed in a relatively short time, the SD transfer subsystem may immediately send a low confidence and / or high risk wafer to the rework sequence. .

  S-D processing may produce specific results at specific locations on the wafer. When processing is sufficient, the confidence value is high, the number of wafers required for evaluation is minimized, and one site on one wafer represents a group of wafers and / or multiple wafers. May be used for When processing is sufficient, the processing results from all sites on one wafer are the same (within uniformity limits). When a product is developed, assessment sites / characteristics / structures at multiple sites can be used to establish a low risk treatment.

  When a product is developed, assessment sites / characteristics / structures at multiple sites can be used to establish a low risk treatment.

  The processing system 100 may be used to verify one or more SD processes.

  In some embodiments, one or more wafers are received by one or more SD transfer subsystems (101, 102), and the SD transfer subsystem (101, 102) is one or more in processing system 100 It may be combined with subsystems (110, 115, 120, 125, 130, 135, 140, 145, 150, and 155). Each wafer may have one or more layers above it, may have associated wafer data, and may have historical data and / or real-time data. The SD transport subsystem may use business rules that determine when to send a wafer to a rework subsystem or storage point. These business rules may differ with the processing of the wafer (by providing additional layers).

  One or more controllers (114, 119, 124, 129, 134, 139, 144, 149, 154, 159, and 195) may use the wafer data and / or wafer state data to determine wafer state data, A first unverified SD process decision may be made. The first unverified S-D process is performed using one or more subsystems (110, 115, 120, 125, 130, 135, 140, 145, 150, and 155).

  One or more control devices (114, 119, 124, 129, 134, 139, 144, 149, 154, 159, and 195) are used for the first number of SD wafers to be processed using the first unverified SD process. Setting, setting of wafer data and the required number of verification sites for each SD wafer using the first unverified SD processing, determining operating state data for one or more SD processing devices in the first processing subsystem, 1 Determination of incoming data, wafer data, wafer status data, operational status data, incoming data, or number of verification sites required for one or more SD transfer devices 104 in one or more SD transfer subsystems (101, 102); Or the setting of the first transfer sequence for the first S-D wafer included in the first number of SD wafers using these combinations, and the first processing subsystem when the first S-D processing sequence is not available. 1st period using SD transport subsystem to combine Or provided so as to convey grace of the 1S-D wafer.

  One or more SD transfer subsystems (101, 102) can transfer the first S-D wafer to one or more subsystems (110, 115, 120, 125, 130, 135, 140, 145, 150, and 155). It may be provided to transport to one of the SD processing devices (112, 117, 122, 127, 132, 137, 142, 147, and 157). In addition, the one or more SD transfer subsystems (101, 102) can only transfer the first S-D wafer for a first period by using the transfer device 104 in the one or more SD transfer subsystems (101, 102). And the transfer device 104 may include two or more wafers. After the first period, the deferred first SD wafer may be processed in one or more subsystems (110, 115, 120, 125, 130, 135, 140, 145, 150, and 155).

  After the transfer of the first S-D wafer, a first unverified SD process may be performed using the first S-D wafer, and the first set of SD verification sites is the first target during the first unverified SD process. It may be generated on a processed SD wafer. The first set of S-D verification sites may include a first verification site at a first site on the first processed S-D wafer.

  When the first unverified S-D process is performed on the first wafer, a first processed S-D wafer may be generated. When the first S-D evaluation device (137, 152) is available, the first processed SD wafer is one or more SD transfer subsystems (101, 102) coupled with the inspection subsystem 135 and the evaluation subsystem 150. ) May be transported to the first S-D evaluation device 137 in the inspection subsystem 135 or the first S-D evaluation device 152 in the first evaluation subsystem 150. When the first S-D evaluation apparatus is not available, the first S-D wafer may be deferred for a second period using one or more S-D transfer subsystems (101, 102). In addition, one or more SD transfer subsystems (101, 102) transfer the first processed SD wafer only for the second period by using the transfer device 104 in the SD transfer subsystem (101, 102). A grace period may be provided and the transfer device 104 may support more than one wafer. After the second period, the first processed SD wafer may be evaluated in the inspection subsystem 135 and / or the evaluation subsystem 150.

  When the evaluation process is executed, the first site may be used. In some examples, the evaluation decision may be made by using data from the first site. One or more controllers (114, 119, 124, 129, 134, 139, 144, 149, 154, 159, and 195) are: a) first unverified from the number of required sites on the first wafer to be processed Select the first site with the first unverified site generated by the SD process, b) the first unverified data from the first site with unverified measurement and / or inspection data present on the first S-D wafer C) setting first verification data having verified measurement and / or inspection data for the first site on the first S-D wafer; and d) first unverified data and first verification data; E) set the first confidence value by using the first difference between, e) the first confidence value, the first difference, or the wafer data, or a combination thereof, by using the first confidence value, the first difference for the first unverified SD process. 1) Set risk factors, and f) Set the first total risk factor for the first unverified SD treatment using the first risk factor or a combination of these. G) when the first risk factor is below the new threshold, certify the first unverified SD process as the first verified process with the associated first risk factor and determine the number of sites required Decrease by 1 and increase the number of accessed sites by 1; h) When the first risk factor is greater than or equal to a new threshold, the first unverified SD as the first unverified process with the associated second risk factor You may be prepared to certify the process and increase the number of sites required by one and reduce the number of sites accessed by one. Here, the first unverified SD process has associated reliability data, risk data, and / or verification data.

  In some examples, additional sites may be used on the first S-D wafer when the evaluation process is performed. For example, the evaluation decision may be made by using data from the first site and data from one or more additional sites on the first S-D wafer. One or more controllers (114, 119, 124, 129, 134, 139, 144, 149, 154, 159, and 195) are: a) the first verification SD from the required number of sites on the first S-D wafer. Select a new site with a new unverified site generated using the process, b) New unverified from a new site with unverified measurement and / or inspection data present on the first S-D wafer New data on the first S-D wafer by acquiring data, c) setting new verification data for the new site, and d) using the new difference between the new unverified data and the new verification data New confidence values for new sites, and e) new first risk factors for first unverified SD processing by using new confidence values, new differences, or wafer data, or a combination of these. F) wafer data, or new first risk factor, or a combination of these Set a new first total risk factor for the first unverified SD process used, and g) if the new first total risk factor is less than or equal to the new threshold, the associated new first total risk factor Certify the first unverified SD process as a new verified process that has a reduced number of required sites and increase the number of accessed sites by one, and h) the first risk factor is above the new threshold , Certify the first unverified SD process as a new unverified process with the associated second risk factor, increase the required number of sites by one and reduce the number of accessed sites by one, i) It may be provided to repeat steps a) to h) when the required number of sites is greater than 0, and to stop verification of the first wafer when j) the required number of sites is equal to zero.

  In another example, a site on an additional SD wafer may be used when the evaluation process is performed. For example, the evaluation decision may be made by using data from sites on one or more SD wafers. One or more controllers (114, 119, 124, 129, 134, 139, 144, 149, 154, 159, and 195) have access to wafer data, process status data, number of required verification sites, and verification Set the additional process verification sequence for the additional SD wafers in the first set of SD wafers and determine the first unverified SD process for the additional SD wafers using the number of sites or a combination thereof You may be prepared as well. Here, the first unverified SD process is determined using an additional process verification sequence and includes one or more processes.

  One or more SD transfer subsystems (101, 102) can store additional SD wafers in one or more subsystems (110, 115, 120, 125, 130, 135, 140, 145, 150, and 155). It may be provided for transport to one of the SD processing devices (112, 117, 122, 127, 132, 137, 142, 147, and 157). In addition, the one or more SD transfer subsystems (101, 102) can transfer the first S-D wafer for a second period by using the transfer device 104 in the one or more SD transfer subsystems (101, 102). And the transfer device 104 may include two or more wafers. After the second period, the deferred first SD wafer may be processed in one or more subsystems (110, 115, 120, 125, 130, 135, 140, 145, 150, and 155).

  After the additional SD wafer is transferred, the first unverified SD process may be performed using the additional SD wafer, and during the first unverified SD process, the first set of SD verification sites is on the additional SD wafer to be processed. May be generated. The first set of S-D verification sites may include a first verification site at a first site on an additional processed S-D wafer.

  When the first unverified S-D process is performed on an additional wafer, an additional processed S-D wafer may be generated. When the first S-D evaluation device (137, 152) is available, the additional processed SD wafer is one or more SD transfer subsystems (101, 102) coupled with the inspection subsystem 135 and the evaluation subsystem 150. ) May be transported to the first S-D evaluation device 137 in the inspection subsystem 135 or the first S-D evaluation device 152 in the first evaluation subsystem 150. When the first S-D evaluation apparatus is not available, additional processed S-D wafers may be deferred for a third period using one or more S-D transfer subsystems (101, 102). In addition, one or more SD transfer subsystems (101, 102) can transfer additional processed SD wafers for a third period by using the transfer device 104 in the SD transfer subsystem (101, 102). A grace period may be provided and the transfer device 104 may support more than one wafer. After the third period, the first processed SD wafer may be evaluated in the inspection subsystem 135 and / or the evaluation subsystem 150.

  When a first site on an additional processed SD wafer is used, one or more controllers (114, 119, 124, 129, 134, 139, 144, 149, 154, 159, and 195) perform the following steps May be provided to perform. The following steps are: a1) a step of selecting a first site having an associated first verification site from the required number of sites on the additional SD wafer to be processed; b1) existing on the additional SD wafer to be processed Obtaining additional unverified data from a first site having unverified measurement and / or inspection data to be performed; c1) additional verification for additional processed SD wafers by using the first site on the additional SD wafer Setting data, wherein the additional verification data comprises verified measurement and / or inspection data; d1) using an additional difference between additional unverified data and additional verification data E1) an additional confidence value, an additional difference, a first confidence value, a first difference, or wafer data, or these data By using a bond F1) Additional risk factors, additional confidence values, additional differences, first risk factors, first confidence values, first differences, or wafer data Setting additional total risk factors for the first unverified SD process using g1, and when all additional risk factors are less than or equal to the additional threshold, verified processes with all associated additional risk factors Certifying the first unverified SD process and reducing the required number of sites by one and increasing the number of accessed sites by one, h1) relevant when all additional risk factors are above the new threshold Approve the first unverified SD process as an additional unverified process with an additional second risk factor, increase the required number of sites by 1 and reduce the number of accessed sites by 1, i1) the required number of sites If greater than 0, repeat a1) -h2) And j1) stopping the verification of the first wafer when the required number of sites is equal to zero.

  When additional required sites on additional processed SD wafers are used, one or more controllers (114, 119, 124, 129, 134, 139, 144, 149, 154, 159, and 195) are: It may be provided to perform the process. The following steps are: a2) a step of selecting a new site having a first verification site generated by the first unverified SD process from the necessary number of sites on the additional SD wafer to be processed; b2) additional Obtaining additional new unverified data from a new site having unverified measurement and / or inspection data existing on the processed SD wafer, and c2) creating a new site on the additional processed SD wafer. A step of setting new additional verification data for an additional SD wafer to be processed, wherein the new additional verification data includes verified measurement and / or inspection data; d2) Setting a new additional confidence value using a new site on an additional processed SD wafer by using a new additional difference between the verification data and the new additional verification data, e2) a new Additional confidence values, New additional risk factors for the first unverified SD process by using new additional differences, additional confidence values, additional differences, first confidence values, first differences, or wafer data, or combinations thereof F2) new additional risk factors, new additional confidence values, new additional differences, additional risk factors, additional confidence values, additional differences, first risk factor, first confidence value, Setting a new additional all risk factor for the first difference or first unverified SD process using wafer data, g2) relevant if all new risk factors are below the new additional threshold limit Certifying the first unverified SD process as a verified process with all the additional risk factors to be added, reducing the number of required sites by one and increasing the number of accessed sites by one, h2) additional The first risk factor is above the new threshold Certifying the first unverified SD process as an additional unverified SD process with an associated additional second risk factor, increasing the required number of sites by one and reducing the number of accessed sites by one, i2 A) repeating steps a2) to h2) when the required number of sites is greater than 0, and j2) stopping the verification of the first wafer when the required number of sites is equal to zero.

  When additional required sites on the deferred processed SD wafer are used, one or more controllers (114, 119, 124, 129, 134, 139, 144, 149, 154, 159, and 195) are: It may be provided to execute the process. The following steps are: a3) a step of selecting a site having a first verification site from the number of remaining sites on the post-processed SD wafer; b3) unverified existing on the post-processed SD wafer. Obtaining unverified data that has been suspended from a site that has measurement and / or inspection data; c3) deferred verification for a deferred SD wafer by using a site on the deferred SD wafer. Setting the data, wherein the graced verification data comprises validated measurement and / or inspection data; d3) a grace period between the graced unverified data and the graced validation data. Setting a graced confidence value for a site on a processed SD wafer that is graced by using a difference, e3) a graced confidence value, a graced difference, an additional confidence value, an additional difference, 1 letter Setting a deferred additional risk factor for the first unverified SD process by using the confidence value, first difference, or wafer data, or a combination thereof; f3) a deferred risk factor, a deferred confidence. Setting the value, graced difference, first risk factor, first confidence value, first difference, or wafer data, or all graced risk factors for the first unverified SD process using a combination thereof , G3) Qualify the first unverified SD treatment as a validated treatment with all relevant graced risk factors when all graced risk factors are below the grace threshold threshold, and the number of sites required H3) when all postponed risk factors are greater than or equal to an additional threshold, the first as an additional unverified process with an associated second risk factor Approve the verification SD process, increase the required number of sites by 1 and decrease the number of accessed sites by 1, i3) repeat the steps a3) -h3) when the required number of sites is greater than 0, and j3 ) The step of stopping the verification of the first wafer when the required number of sites is equal to zero.

  In various embodiments, the one or more processing devices are one or more SD lithography related processing devices, one or more SD scanner related processing devices, one or more SD inspection related processing devices, one or more SD measurements. Related processing equipment, one or more SD evaluation related processing equipment, one or more SD etching related processing equipment, one or more SD deposition related processing equipment, one or more SD heat treatment related processing equipment, one or more SD coatings Related processing equipment, one or more SD alignment related processing equipment, one or more SD polishing related processing equipment, one or more SD storage related processing equipment, one or more SD transport related processing equipment, one or more SD Cleaning related processing equipment, one or more SD rework related processing equipment, one or more SD oxidation related processing equipment, one or more SD nitriding related processing equipment, or one or more S-external processing equipment, or these May have a bond.

  In addition, the first unverified SD process can be executed in real time, and one or more SD lithography related processing devices, one or more SD scanner related processing devices, and one or more SD inspection related processings. Equipment, one or more SD measurement related processing equipment, one or more SD evaluation related processing equipment, one or more SD etching related processing equipment, one or more SD deposition related processing equipment, one or more SD heat treatment related processing Equipment, one or more SD coating related processing equipment, one or more SD alignment related processing equipment, one or more SD polishing related processing equipment, one or more SD storage related processing equipment, one or more SD transport related Processing equipment, one or more SD cleaning related processing equipment, one or more SD rework related processing equipment, one or more SD oxidation related processing equipment, one or more SD nitriding related processing equipment, or one or more S -It may have an external processor or a combination of these.

  In some embodiments, the unverified data includes SD intensity data, SD transmission data, SD absorption data, SD reflectance data, SD diffraction data, SD optical property data, SD image data, or a combination thereof. You can do it. Verification data includes historical data, library data, optical measurement data, imaging data, particle data, CD-scanning electron microscope (CD-SEM) data, transmission electron microscope (TEM) data, and / or focused ion beam (FIB) May have data. The threshold limit may include S-D data. The S-D data includes goodness-of-fit data, CD data, accuracy data, wavelength data, sidewall data, particle data, process data, history data, or a combination thereof.

  In one example, a first set of SD verification sites is generated on the first SD processed wafer by developing the exposed mask. In another example, a first set of S-D verification sites is generated on a first S-D processed wafer by etching one or more layers. In another example, a first set of S-D verification sites is generated on a first S-D processed wafer by exposing a deposited mask layer.

  In various embodiments disclosed herein, a wafer may have one or more layers. The one or more layers include a semiconductor material, a carbon material, a dielectric material, a glass material, a ceramic material, a metal material, an oxide material, a mask material, or a planarizing material, or a combination thereof.

  In some examples, the lithography-related processing device may perform SD and / or SD mask layer deposition processing, mask layer exposure processing, and / or development processing, and the evaluation device may be SD and / or SD. It may also be used for verification of mask layer deposition processing, which is SD, mask layer exposure processing, and / or development processing.

  The SD transport sequence may be used to determine the SD transport subsystem used, the number of transport devices used, the number of transports, and / or the transport speed.

  The S-D wafer status data may depend on the number of sites required, the number of sites accessed (evaluated / completed), or the number of remaining sites, or a combination thereof. The S-D process status data may depend on the number of required processes, the number of completed processes, or the number of remaining processes, or a combination thereof. In some cases, when excellent results are obtained at an already measured site, the actual number of evaluations performed may be less than the original number.

  Throughput time may be used to determine the number of processing devices required to process one or more wafers.

  When the S-D process is verified, the S-D process and the data associated with the S-D process may be stored in a library and / or database.

  As the product is developed, one or more S-D libraries may be generated, refined, updated, and / or used. The S-D evaluation library may include site-dependent S-D sites, properties, structures, processes, images, and / or optical data.

  The processing system 100 may generate S-D data for one or more S-D evaluation libraries using an S-D generation process and / or an S-D evaluation process.

  In some embodiments, one or more wafers are coupled to one or more processing equipment (112, 117, 122, 127, 132, 137, 142, 147, and 157) and its SD transport subsystem (101, 102) is one or more subsystems (110, 115, 120, 125, 130, 135, 140, 145, 150, and 155) in the processing system 100 ). Each wafer may have one or more layers above it and may have associated wafer data. The wafer data may include historical data and / or real time data.

  One or more controllers (114, 119, 124, 129, 134, 139, 144, 149, 154, 159, and 195) may be provided to receive wafer data for the first set of SD wafers. .

  One or more processing devices (112, 117, 122, 127, 132, 137, 142, 147, and 157) may perform one or more first S-D generation processes. Here, a first set of processed S-D wafers having one or more library-related reference sites at the first number of evaluation sites are generated.

  One or more controllers (114, 119, 124, 129, 134, 139, 144, 149, 154, 159, and 195) have a number of required production sites and a number of required for each processed SD wafer. Set up SD wafer status data with an evaluation site, set up a first set of evaluation wafers with a first number of SD wafers to be processed that should be evaluated using the first S-D evaluation process, and 1 First by setting operating states for a plurality of SD evaluation devices in one or more subsystems coupled to one or more SD transport subsystems and using a first operating state for one or more SD evaluation devices First S-D by determining the number of available evaluation devices and using wafer data, SD wafer data, the first number of SD evaluation wafers, or the first number of available evaluation devices, or a combination thereof Set the transfer sequence and use the number of wafers for SD evaluation When more than the first number is the number of the evaluation device may be adapted for applying a first corrective actions.

  When the number of SD evaluation wafers is less than or equal to the first number, which is the number of available evaluation wafers, the first set of SD evaluation wafers can be more than one by using the first SD transport sequence. It may be conveyed to the first number of available evaluation devices (137, 152) in the evaluation subsystem (135, 150). One or more SD transport subsystems (101, 102) may be coupled to the inspection subsystem 135 and the evaluation subsystem 150.

  In addition, one or more controllers (114, 119, 124, 129, 134, 139, 144, 149, 154, 159, and 195) a) wafer data, data from the first S-D generation process The number of evaluation sites required for each SD evaluation wafer is determined by using the SD wafer status data, the SD evaluation library generation rule, or a combination thereof, and b) from the required number of sites on the first wafer to be processed. Selecting a first site having a reference site related to the first library generated using the first SD generation process, and c) measurement related to the first library existing on the first S-D evaluation wafer and / or Obtain evaluation data related to the first library from the first site having inspection data, and d) first prediction data having predicted measurement and / or inspection data for the first site on the first S-D evaluation wafer. E) Evaluation data related to the first library and the first schedule Set the first confidence value for the first site on the first S-D evaluation wafer by using the difference related to the first library calculated using the data, f) First confidence value, first library related The first risk factor for the first site on the first SD evaluation wafer by using the difference or wafer data, or a combination thereof, and g) the first risk factor, the first confidence value, the first Set the first total risk factor for the first site on the first S-D evaluation wafer using the library-related differences, or wafer data, or a combination of these, and h) the first total risk factor is the first library If it is below the relevant generation criteria, the first site on the first S-D evaluation wafer process is certified as the first verification site with the first relevant all risk factors, and the number of required sites is reduced by one. Increase the number of sites visited by one, Storing data associated with the first site as validated data in the SD assessment library, and h) when the first validated site has validated library-related data, the associated second risk factor The first site may be certified as the first unverified site with the number of sites required increased by one and the number of sites accessed may be reduced by one. Here, the first verified site has verified library-related data.

  When the SD evaluation library is generated, a new site on the first S-D evaluation wafer is used and one or more controllers (114, 119, 124, 129, 134, 139, 144, 149, 154 159 and 195) may be provided to perform the following steps. The following steps are: a) a new site having a new library-related reference site generated using the first S-D generation process from the number of necessary sites on the first S-D evaluation wafer. Selecting step, b) obtaining new library-related evaluation data from a new site having library-related measurement and / or inspection data existing on the first S-D evaluation wafer, c) first S-D evaluation Setting new prediction data for a new site on the wafer for processing, wherein the new prediction data includes newly predicted measurement and / or inspection data; d) new library related data and new Setting a new confidence value for a new site on the first S-D evaluation wafer by using a new library-related difference calculated by using a new prediction data, e) a new confidence value, new Setting new risk factors for new sites on the first SD evaluation wafer by using library related differences, first confidence values, first library related differences, or wafer data, or a combination thereof F) a new risk factor, a new confidence value, a new library related difference, a first risk factor, a first confidence value, a first library related difference, or wafer data, or a first S using these combinations -D, setting all new risk factors for new sites on the evaluation wafer, g) if all new risk factors are below the new library-related generation criteria limit, all related new risk factors Qualify new sites on the 1st SD evaluation wafer as new verified sites with reduced number of sites required and increased number of accessed sites by 1 And storing the data associated with the new site as verified data in the assessment library, h) if all new risk factors are greater than or equal to the new library-related generation criteria limit, Certifying a new site on the first SD evaluation wafer as a new unverified site with the second risk factor, increasing the required number of sites by one and reducing the number of accessed sites by one, i) A) repeating steps a) to h) when the required number of sites is greater than 0, and j) stopping the verification of the first wafer when the required number of sites is equal to zero.

  When the SD evaluation library is generated, additional sites on the first S-D evaluation wafer are used and one or more controllers (114, 119, 124, 129, 134, 139, 144, 149, 154 159 and 195) may be provided to perform the following steps. The following steps are: a1) a step of selecting an additional SD evaluation wafer, b1) a step of determining the first required site for the additional SD evaluation wafer, c1) on the additional SD evaluation wafer Selecting an additional site from the first required number of sites, wherein the additional site includes an additional library-related reference (evaluation) site generated using the first S-D generation process, d1 A) obtaining additional library-related evaluation data from an additional site on an additional SD evaluation wafer, wherein the additional site has additional library-related measurement and / or inspection data; e1) additional SD Setting additional prediction data for additional sites on the evaluation wafer; f1) by using additional library-related differences calculated by using additional library-related evaluation data and additional prediction data. G1) additional confidence values, additional library-related differences, new confidence values, new library-related differences, first Setting additional risk factors for additional sites on additional SD evaluation wafers by using confidence values, first library related differences, or wafer data, or combinations thereof, h1) additional risk factors, Additional confidence values, additional library-related differences, new risk factors, new confidence values, new library-related differences, first risk factors, first confidence values, first library-related differences, or wafer data, Or the process of setting all additional risk factors for additional sites on additional SD evaluation wafers using these combinations, i1) additional all risk factors are associated with additional libraries When below the production criteria limit, additional sites on additional SD evaluation wafers are qualified as additional verified sites with all associated additional risk factors and are accessed with one fewer site requirement. Storing the data related to the additional sites as verified data in the evaluation library, j1) When all the additional risk factors are above the additional library-related generation criteria limit Qualify additional sites on additional SD evaluation wafers as additional unverified sites with additional second risk factors associated with them, increasing the number of required sites by one and reducing the number of accessed sites by one Steps k1) Repeat steps a1) to j1) when the required number of sites is greater than 0, and l1) Stop verification of the first wafer when the required number of sites is equal to 0.

  In some examples, when the first corrective action is performed, one or more control devices (114, 119, 124, 129, 134, 139, 144, 149, 154, 159, and 195) are One or more SD transport subsystems may be provided to determine the first number of deferred SD wafers by using the difference between the number of SD processing wafers and the first number of available processing equipment. One or more transfer devices 104 in (101, 102) may be provided to store and / or suspend a first number of graced wafers during a first time period.

  In another example, when the first corrective action is performed, one or more control devices (114, 119, 124, 129, 134, 139, 144, 149, 154, 159, and 195) are the first number. The difference between the first SD evaluation wafer and the first available evaluation device is used to determine the first number of deferred SD wafers and an updated SD wafer for the first deferred SD evaluation wafer Determine status data, determine updated operational status data for one or more SD processing devices in the first processing subsystem, and first updated for the first deferred SD evaluation wafer By determining the transfer sequence and using the updated operating state data, one or more newly available SD processing devices are identified and used by the first newly available SD evaluation device It may be provided to apply a second corrective action when not possible. In addition, one or more transport devices 104 in one or more SD transport subsystems (101, 102) can be used when one or more newly available SD processing devices are available. By using the first updated transfer sequence, it may be provided to transfer one or more deferred wafers.

  In an additional example, the corrective action includes the steps of suspending the process, suspending the process, reevaluating one or more SD evaluation wafers, re-measuring one or more SD evaluation wafers, 1 Re-inspecting one or more SD evaluation wafers, reworking one or more SD evaluation wafers, storing one or more SD evaluation wafers, cleaning one or more SD evaluation wafers A step of delaying the conveyance of one or more SD evaluation wafers, a step of removing one or more SD evaluation wafers, or a step of combining them.

  One set of additional processing steps is a step of calculating an SD reliability map for the SD wafer to be processed, and the first SD reliability map of the SD reliability maps is calculated on each SD wafer to be processed. A first set of evaluations by using a reliability map for the process and SD wafer to be processed, having reliability data for one or more library-related reference sites generated at the first number of evaluation sites There may be a step of setting a wafer.

  The second set of additional processing steps is a step of calculating an SD reliability map for the SD wafer to be processed, and the first SD reliability map of the SD reliability maps is calculated on each SD wafer to be processed. Process, with reliability data for one or more library-related reference sites generated at the first number of evaluation sites, at least one value in the first S-D reliability map is the first reliability If not within the limits, reduce the number of required evaluation sites by one or more, and if one or more values in the first S-D reliability map are within the first reliability limits, A step of increasing the number by one or more.

  The third set of additional processing steps is a step of calculating an SD risk evaluation map for the SD wafer to be processed, and the first risk evaluation in the SD reliability map is the first risk evaluation on each SD wafer to be processed. A risk assessment for one or more library-related reference sites generated at a number of assessment sites, when one or more values in the first S-D risk assessment are not within the first confidence limits, The process of reducing the number of required evaluation sites by one or more, and when one or more values in the first S-D risk evaluation are within the first reliability limit, increase the number of required evaluation sites by one or more A process.

  In an alternative embodiment, a first set of non-SD wafers is determined, these wafers are processed using a first non-SD process sequence, and the first non-SD process sequence has one or more non-SD processes. Good. The first set of non-SD wafers may be transferred to one or more first non-SD processing equipment in one or more first subsystems by using the SD transfer subsystem and the first non-SD processing. The sequence may be used to determine one or more first non-SD processing devices in one or more first subsystems.

  In some examples, the SD evaluation library data includes fitness data, production rule data, SD measurement data, SD inspection data, SD verification data, SD map data, SD reliability data, SD accuracy data, SD process data, Or SD uniformity data, or a combination thereof.

  FIG. 2 shows an exemplary flow diagram of a wafer processing method using SD processing according to an embodiment of the present invention. The wafer may have one or more layers. The one or more layers include a semiconductor material, a carbon material, a dielectric material, a glass material, a ceramic material, a metal material, an oxide material, a doping material, a mask material, a planarizing material, or a combination thereof. In some cases, the S-D process may be used throughout the manufacturing cycle. Also, in some cases, when more important processing steps are performed, the S-D process may be used early in the manufacturing cycle. In some cases, the SD process creates a mobility difference between the nMOS and pMOS structures, locates the test structure, and provides linewidth roughness and / or line end roughness. And can be used to improve overlay problems.

  In some examples, the wafer data is real-time data, historical data, SD reliability data, non-SD reliability data, SD risk data, non-SD risk data, SD limit data, or non-SD limit data, or a combination thereof. You may have.

  At 205, one or more wafers may be received by one or more subsystems (110, 115, 120, 125, 130, 135, 140, 145, 150, and 155) in the processing system 100. In some embodiments, one or more transports in which one or more wafers are combined with one or more subsystems (110, 115, 120, 125, 130, 135, 140, 145, 150, and 155) Can be received by the subsystem (101, 102). Alternatively, one or more wafers may be received by different subsystems. In addition, the system controller 195 can be used to receive wafer data for one or more wafers. Alternatively, some wafer data may be received by different controllers. Wafer data may include historical data and / or real-time data. For example, the wafer data may include S-D data and / or non-S-D data. The SD data and / or non-SD data includes a wafer-related map, a process-related map, a damage evaluation map, a reference map, a measurement map, a prediction map, a risk map, an inspection map, and a verification map for one or more wafers. An evaluation map, particle map, and / or reliability map (s) may be included. In some cases, MES 180 may exchange data with system controller 195 and one or more subsystems (110, 115, 120, 125, 130, 135, 140, 145, 150, and 155), In addition, the data may be used to determine and / or control the processing sequence and / or transport sequence. The exchanged data may be used to determine which SD and / or non-S-D processing is used for each wafer. The data may include system data, subsystem data, chamber data, product data, sensor data, and history data.

  The wafer may comprise an S-D wafer and / or a non-S-D wafer. S-D wafer state data may be set for each S-D wafer, and non-S-D wafer state data may be set for each non-S-D wafer.

  At 210, an S-D process and / or transfer sequence for the S-D wafer may be set by using wafer data and S-D wafer state data. Non-S-D processing and / or transfer sequences for non-S-D wafers may be set by using wafer data and non-S-D wafer state data. Alternatively, other sequences and additional data may be used instead.

  Verification related sequences may be set up to verify sites used in S-D processing, S-D wafers, and / or S-D libraries. The verification related sequence may include an S-D generation process, an S-D transport process, an S-D verification process, an S-D evaluation process, an S-D measurement process, an S-D inspection process, or a combination thereof. Alternatively, non-S-D processing may be included. One or more S-D wafers may be processed using one or more process related processes and verified using a process verification process sequence.

  Sites in SD processing include gate structure in transistor, drain structure in transistor, source structure in transistor, capacitor structure, via structure, trench structure, 2D memory structure, 3D memory structure, sidewall angle, bottom critical dimension ( CD), top CD, intermediate CD, array, periodic structure, alignment site, doping site, strain site, damage structure, or reference structure, or a combination thereof.

  An SD processing sequence and / or a non-SD processing sequence may include one or more mask generation processes, one or more deposition processes, one or more coating processes, one or more etching processes, one or more heat treatments, one or more. Implantation treatment, one or more doping treatments, one or more exposure treatments, one or more oxidation treatments, one or more nitriding treatments, one or more ionization treatments, one or more development treatments, one or more development treatments Lithographic processing, one or more scanner related processing, one or more measurement processing, one or more inspection processing, one or more evaluation processing, one or more simulation processing, one or more prediction processing, one or more prediction processing There may be a rework process, one or more storage processes, one or more transport processes, one or more load lock processes, or one or more cleaning processes, or a combination thereof.

  In some examples, the S-D processing sequence may include pre-processing and / or post-processing that can be performed using a smaller number of wafers. The pre-processing and / or post-processing is S-D and may include processing, evaluation, measurement, inspection, verification, and / or damage evaluation processing. During the life of the product, the processing sequence may change many times until the product is of sufficient quality. The degree of pre-processing and / or post-processing may be different for each wafer and / or number of times. Some wafers may be qualified as verification, inspection, evaluation, damage assessment, test, and / or Send-Ahead wafers, and pre-processing and / or post-processing may be It may be performed on a part of the wafer. When a product is fully developed and / or verified, process results may vary and additional processing may be performed on a larger number of wafers. For example, when additional SD processing is required, pre-processing and / or post-processing may be performed using a predetermined number of sites on the wafer.

  In 215, the required number of generation processes for each S-D wafer may be determined by using one or more S-D verification related sequences, wafer data, S-D wafer status data, and other data as required. In addition, the required number of generations for each non-SD wafer is determined by using one or more non-SD verification related sequences, wafer data, non-SD wafer status data, and other data as required. Good. Alternatively, additional data may be used instead.

  In some cases, the wafer status data may include the number of process related sites required, the number of process related sites accessed, or the number of remaining process related sites, or a combination thereof. An S-D generation process may be determined for each “to be processed” S-D wafer. The S-D generation process may include one or more process related processes. The S-D generation process may be used to identify an S-D processing device within the S-D processing subsystem and / or the processing subsystem used.

  At 220, the required number of evaluation processes for each S-D wafer may be determined by using one or more S-D processing sequences, wafer data, and S-D wafer data. In addition, the required number of evaluation processes for each non-S-D wafer may be determined by using one or more non-S-D process sequences, wafer data, and non-S-D wafer data. Alternatively, additional data may be used instead.

  In some cases, the wafer status data may include the required number of evaluation related sites, the number of accessed evaluation related sites, or the remaining number of evaluation related sites, or a combination thereof. An S-D evaluation process may be determined for a “to be evaluated” site, wafer, process, and / or library. The S-D evaluation process may include one or more verification, evaluation, measurement, inspection, and / or test processes. In addition, an S-D evaluation process may be determined for a “to be verified” site, wafer, process, and / or library. The S-D evaluation subsystem and / or the S-D evaluation device used may be used to identify the S-D evaluation process within the verification subsystem used. The wafer state data may include the number of verification related sites required, the number of verification related sites accessed, or the number of remaining verification related sites, or a combination thereof.

  In other cases, the wafer status data may include the number of verification sites required, the number of verification related sites accessed, or the number of remaining verification related sites, or a combination thereof. An SD verification process may be determined for a site, wafer, process, and / or library that is to be verified. The S-D verification process may include one or more verification, evaluation, measurement, inspection, and / or test processes. The S-D verification process may be used to identify the S-D verification subsystem in the S-D verification subsystem and / or the verification subsystem used.

  In 225, one or more SD transfer sequences for each SD wafer are SD sequence data, import data, availability data, operational status data, processing data, system data, subsystem data, wafer data, or SD wafer status. It may be set by using data or a combination of these. In addition, one or more non-S-D transfer sequences may be set for each non-S-D wafer. Alternatively, different data may be used instead.

  In some examples, a first SD transport sequence may be determined and the first SD transport sequence may be used to transport a first wafer or a first group of wafers. Data from the first wafer or the first group of wafers may be used to make decisions regarding other related wafers. One or more “high quality” wafers and / or “high performance” chambers may be used during processing. In addition, the transfer and / or processing sequence can be used to remove and / or mitigate the “first wafer effect”. The SD transport sequence may be used to determine the SD transport subsystem used, the number of transport devices used, the order of loading, the number of transports, and / or the transport speed.

  When a lithography related sequence is performed, by using a lithography related generation process, one or more lithography related evaluation sites may be generated at one or more locations on one or more SD wafers, and lithography related By using an evaluation process, one or more lithography-related evaluation sites may be evaluated.

  In some examples, the MES 180 may include one or more verification related sequences, one or more processing related sequences, one or more generation processes, one or more SD evaluation processes, or one or more transport run sequences, or These bonds may be provided. In other examples, the MES 180 may include one or more verification-related sequences, one or more processing-related sequences, one or more generation processes, one or more SD evaluation processes, or one or more transport sequences. Information that can be used to set the combination of the above may be provided.

  An internal transport system coupled to the internal SD supply element in the subsystem, a transport apparatus coupled to the SD supply element in the SD transport subsystem, an exchange between the transport apparatuses, an exchange between the transport apparatus and the processing apparatus, and An SD transfer sequence may be set for the exchange between the transfer device and the SD subsystem.

  At 230, a first set of S-D “processed” wafers may be transferred to one or more available S-D processing equipment in one or more processing subsystems. Operating state data may be determined for one or more S-D processing devices in one or more processing subsystems. The operational state data may be used to determine one or more available S-D processing devices. In other cases, the process may be performed using a non-S-D processor and the transport sequence may be set to allow this process.

  For example, operational state data for a processing device may include availability data, conformance data for a processing device, expected processing time for some processing steps and / or sites, reliability data and / or risk for a processing device. Data, reliability data and / or risk data for one or more processing related sites may be included.

  In some examples, real-time operational states may be set for one or more S-D processing devices in one or more processing subsystems. When the first number of first SD processing devices are available, the first number of SD processing wafers are transferred to the first number of SD processing devices by using the SD transfer subsystem. good. When the S-D processing apparatus is not available for the other S-D wafers in the set of S-D processing wafers, the other S-D wafers in the set of S-D processing wafers may be deferred for the first period. When the wafer is carried into and out of the S-D processing apparatus, the operating state may change. A real-time transfer sequence may be set and used to load and unload a wafer to and from the first SD processing apparatus in the lithography related subsystem. The updated operating state can be obtained by making an inquiry to one or more processing devices and / or one or more subsystems in real time. The updated carry-in data can be obtained by making an inquiry to one or more transport devices and / or one or more transport subsystems in real time.

  A graced wafer may be processed and / or transported by using a “graced” processing sequence and / or a “graced” transport sequence. A “graced” processing sequence and / or a “graced” transport sequence can have a graced process and provide graced data. For example, when a “newly available” SD evaluation device is identified, a deferred SD evaluation wafer can be identified by using a “deferred” transfer sequence in one or more evaluation subsystems. It can be transported to an SD evaluation device that is newly available.

  In 235, generation processing may be performed. The verified SD generation process may be used to generate a verified wafer having one or more verified sites at one or more sites. The unverified generation process may be used to generate an unverified wafer having one or more unverified sites at one or more sites. Wafer data, processing equipment, and / or processing subsystem data may be acquired and / or stored before, during, and / or after S-D and / or non-S-D generation processing.

  During some generation processes, output data may be obtained from one or more process-dependent sites during one or more processing steps of the SD process, and one set for SD output data and process-dependent sites. By comparing the above SD product requirements, SD reliability data for one or more wafers may be set.

  At 240, a query can be used to determine when additional generation processing is required for the current wafer. Process 200 may return to branch 240 when another generation process is required for the current wafer. Process 200 may proceed to branch 250 when no other generation process is required for the current wafer.

  In 245, a first set of S-D evaluation wafers may be set, and the first set of S-D evaluation wafers may include a first number of S-D wafers.

  At 250, one or more of the first set of S-D evaluation wafers may be transferred to one or more available S-D evaluation devices in one or more evaluation subsystems. Operational state data may be set for one or more S-D evaluation devices in one or more evaluation subsystems. The operational state data may be used to determine one or more available S-D evaluation devices. In some other cases, the evaluation may be performed by using a non-S-D evaluation device, and the transport sequence may be set so that this evaluation can be performed. In addition, one or more of the first set of S-D evaluation wafers may be transferred to one or more available S-D evaluation devices in one or more inspection subsystems. Operational state data may be set for one or more S-D evaluation devices within one or more inspection subsystems. The operational state data may be used to determine one or more available S-D evaluation devices. In some other cases, the inspection may be performed by using a non-S-D evaluation device, and the transport sequence may be set to allow this evaluation.

  For example, operational status data for an evaluation device may include conformance data for the evaluation device, expected processing time for some evaluation processes and / or sites, reliability data and / or risk data for the evaluation device, one or more You may have reliability data and / or risk data for your assessment site.

  In some examples, when the first number, which is the number of SD evaluation wafers, is equal to or less than the first number, which is the number of available evaluation apparatuses, the transfer sequence includes the first number of SD evaluation wafers as the first number. It can be used to determine when and how to transport to a number of available evaluation devices. One or more correction actions may be applied when the first number, which is the number of first set of S-D wafers, is greater than the first number, which is the number of available evaluation devices. Here, the first number of available evaluation devices is determined by using the first operating state.

  At 255, an evaluation wafer may be selected. The evaluation wafer may include a first wafer, an additional wafer, and / or a deferred wafer. The remaining evaluation wafers may be inspected. Selection may include SD wafer status data, processing sequence, number of remaining wafers, number of required evaluation and / or verification sites, number of accessed evaluation and / or verification sites, number of remaining evaluation and / or verification sites, or It can be determined based on the combination.

  At 260, the current site on the wafer may be selected. In some examples, the first site may be selected from the required number of sites on the first S-D evaluation wafer, and the first site is the first unverified generated using the first S-D generation process. It may have a site for evaluation. One or more additional sites may be selected from the required number of sites on the first S-D evaluation wafer, and the additional sites are additional unverified evaluation sites generated using the first S-D generation process. May have. The first wafer may be one of the most important wafers, and the determination of the group of wafers may be based on results obtained from the first wafer. In other examples, the determination may be based on data from additional wafers and / or graced wafers.

  At 265, the evaluation process may be performed by using the selected site. Evaluation data about a site may be acquired by using an S-D evaluation process performed using an S-D evaluation apparatus. For example, the measurement process may provide measurement data and / or the inspection process may provide inspection data.

  In some examples, the first site may be selected from the number of remaining sites on the evaluation and / or verification wafer, and the first site may have an associated first unverified site. The first unverified data may be obtained from the first site. The first unverified data for the first site may comprise first unverified measurement and / or inspection data. First verification data may be set for the first site. The first verification site may have verified measurement and / or inspection data. The first reliability data for the first site may be set by using a first difference between the first unverified data and the first verified data. First risk data for the first site, wafer, and / or process may be set by using the first reliability data. When the first reliability data is greater than or equal to the first threshold limit, the first site may be qualified as the first verified site having the first confidence level, the remaining number of sites is reduced by one, and The number of sites visited increases by one. When the first reliability data is below the first threshold limit, the first site may be certified as the first unverified site with the second trust level, the remaining number of sites is reduced by 1 and accessed. Increased number of sites.

  In some embodiments, unverified data includes a gate structure in a transistor, a drain structure in a transistor, a source structure in a transistor, a capacitor structure, a via structure, a trench structure, a two-dimensional memory structure, a three-dimensional memory structure, and a sidewall. Evaluation data may be included for corners, critical dimensions (CD), arrays, periodic structures, alignment sites, doping sites, strain sites, damage structures, or reference structures, or combinations thereof. In other embodiments, the unverified data includes evaluation data, measurement data, inspection data, alignment data, verification data, processing data, wafer data, library data, historical data, real time data, optical data, layer data, thermal data, Data, or time data, or a combination thereof may be included. Alternatively, other data may be used instead.

  In some embodiments, the verified data includes a gate structure in a transistor, a drain structure in a transistor, a source structure in a transistor, a capacitor structure, a via structure, a trench structure, a two-dimensional memory structure, a three-dimensional memory structure, Verified, predicted, simulated for sidewall angle, critical dimension (CD), array, periodic structure, alignment site, doping site, strain site, damage structure, or reference structure, or combinations thereof, and And / or library data. In another embodiment, the verified data includes evaluation data, measurement data, inspection data, alignment data, verification data, processing data, wafer data, library data, historical data, real-time data, optical data, layer data, Thermal data, or time data, or a combination thereof may be included. Alternatively, other data may be used instead.

  In other examples, when one or more reliability and / or risk limits are met, one or more evaluation wafers are qualified as evaluated and / or verified wafers, or one or more limits Corrective action may be applied when is not satisfied.

  The historical verification data may include the first S-D verification data in the SD verification library, and the first S-D verification data in the SD verification library includes the first verified structural data and the associated first verification evaluation data. And the first verification signal may be characterized by a first S-D set of wavelengths.

  Real-time verification data may include verification data acquired in real time. For example, real-time verification data may be set using data obtained from one or more wafers similar to the wafer, parts of the same wafer lot, similarly processed wafers, or a combination thereof. The history verification data may include stored data.

  When one or more limits are met, the S-D evaluation site, structure, data, wafer, process, and / or image may be verified. When multiple sites and / or wafers are evaluated, reliability and / or risk data for individual wafers and / or groups of wafers may be established. Alternatively, other data may be used instead. For example, the reliability data value may range from 0 to 9. Where 0 represents a failure condition and 9 represents the most accurate performance. In addition, risk data values may range from 0 to 9. Where 0 represents a failure or high risk condition and 9 represents the lowest risk condition. Alternatively, other ranges may be used instead. Ranges may be set for limits for providing reliability data and / or risk data that take multiple values.

  When the first (most accurate) threshold limit is met, the object being evaluated may be identified as having the highest confidence and / or lowest risk factor. When other (least accurate) threshold limits are met, the object being evaluated may be identified as having low confidence and / or high risk factors. When one or more (accuracy varying) threshold limits are not met, the object being evaluated may be identified as an unverified object with the highest confidence and / or lowest risk factor.

  At 275, a query may be performed to determine if additional sites are needed. When additional sites are needed, process 200 may return to step 260. If no additional sites are needed, process 200 may proceed to step 280.

  At 280, a query can be performed to determine whether additional evaluation wafers are needed. When additional evaluation wafers are needed, process 200 may return to step 255. If no additional sites are needed, process 200 may proceed to step 285.

  At 285, a query may be performed to determine if the current sequence is complete. When the current sequence is complete, the process 200 may proceed to step 290. If the current sequence is not complete, process 200 may return to step 215.

  At 290, a query may be performed to determine if additional sequences are needed. When additional sequences are needed, process 200 may return to step 210. If no additional sequence is required, the process 200 may proceed to step 295. The process ends at 195.

  In some embodiments, a first double patterning sequence may be performed followed by a second double patterning sequence. The first set of wafers may be received by one or more subsystems (110, 115, 120, 125, 130, 135, 140, 145, 150, and 155) in the processing system 100. By using the first S-D DP processing sequence, one or more first patterning layers may be generated on one or more of the first set of patterned wafers. The first S-D processing sequence may be performed by using one or more subsystems (110, 115, 120, 125, 130, 135, 140, 145, 150, and 155) in the processing system 100. Subsequently, reliability data and / or first risk data for the first set of patterned wafers may be set using the first S-D evaluation process, and the first set of high reliability wafers. However, it may be created by using data from the first S-D evaluation process. Subsequently, one or more second patterning layers may be generated on the second set of patterned wafers, and the second set of patterned wafers used the first set of highly reliable wafers. It may be generated by executing a second S-D processing sequence. The second S-D processing sequence may be performed by using one or more subsystems (110, 115, 120, 125, 130, 135, 140, 145, 150, and 155) in the processing system 100. The one or more second patterning layers are aligned with the one or more first patterning layers by using the scanner subsystem 115. In addition, second reliability data and / or second S-D risk data for the second set of patterned wafers may be set by using the second S-D evaluation process, and the second set High reliability wafers may be created using the first and / or first SD evaluation process.

  In some embodiments, the first S-D processing sequence may be used to create the first damascene layer, and the new S-D processing sequence may be used to create the second damascene layer.

  In various embodiments, one or more processing sequences may be performed in real time, and the one or more processing sequences may include one or more SD lithography related processes, one or more SD scanner related processes, one or more SD inspection related processing, one or more SD measurement related processing, one or more SD evaluation related processing, one or more SD etching related processing, one or more SD deposition related processing, one or more SD heat treatment, 1 One or more SD coating related processes, one or more SD alignment related processes, one or more SD polishing related processes, one or more SD storage related processes, one or more SD transport processes, one or more SD cleaning May have related processing, one or more SD rework related processing, one or more SD oxidation related processing, one or more SD nitridation related processing, or one or more S-external processing, or a combination thereof .

  FIG. 3 shows a simplified diagram of a wafer map according to an embodiment of the present invention. In the illustrated embodiment, a wafer map having 125 chips / dies is shown, but this is not essential to the invention. Alternatively, a different number of chips / dies may be shown. In addition, circular is for illustrative purposes, and circular is not essential to the present invention. For example, a circular wafer may be replaced by a non-circular wafer and the chip / die may have a non-circular shape.

  The figure represents a wafer map 302 on a wafer 300 having one or more chips / dies 310. For illustration purposes, rows and columns numbered from 0 to 20 are shown. In addition, the twelve sites labeled (1a-12a) may be used to identify locations for the S-D process associated with the illustrated wafer map 320. In addition, two annular lines (301 and 302) are shown and these lines may be used to set the outer region 305, middle region 306, and inner region 307 on the wafer 300. Alternatively, different numbers of regions with different shapes may be set on the wafer map 320, and different numbers of sites for SD and / or non-SD processing are set at different locations on the wafer. good. When an S-D measurement, inspection, and / or evaluation plan is generated for a wafer, one or more measurement, inspection, and / or evaluation sites may be established within one or more wafer regions. For example, when an S-D strategy, plan, and / or recipe is generated, the measurement, inspection, and / or evaluation process need not include and / or use all of the sites 330 illustrated in FIG.

  The S-D process may be implemented by a semiconductor manufacturer based on data stored in a history database. For example, the semiconductor manufacturer can select the number of positions on the wafer based on the history when performing SEM measurement, and the measurement data, inspection data, and / or evaluation data from one apparatus can be Correlate to data measured using a device, TEM device, and / or FIB device.

  In addition, the number of sites used for S-D and / or non-S-D processing is reduced as the manufacturer gains confidence that the process continues to produce quality products and / or devices.

  When new and / or additional measurement data, inspection data, and / or evaluation data is needed, additional S-D data may be obtained from one or more sites on the wafer. For example, measurement sites on the wafer, such as periodic gratings, periodic arrays, and / or other periodic structures, may be measured at one or more sites illustrated in FIG.

  The S-D measurement, inspection, and / or evaluation process is time consuming and may affect the throughput of the processing system. During processing, the manufacturer will want to minimize the time used for wafer measurement, inspection, verification, and / or evaluation. The S-D process is independent of time, and each different S-D process may be selected based on its execution time. If the run time is too long, you can reduce the number of sites.

  During the development process in a semiconductor process, one or more SD reference maps may be generated and stored for use in subsequent processes. The S-D reference map may include measurement data at a site different from the site illustrated in FIG. The S-D inspection map may include inspection data at a site different from the site illustrated in FIG. The S-D verification map may include verification data at a site different from the site illustrated in FIG. The S-D evaluation map may include evaluation data at a site different from the site illustrated in FIG. Alternatively, the reference map may use the same site set. Alternatively, one or more reference maps may not be needed.

  In addition, during SD processing, one or more SD prediction maps may be generated and / or modified, and the SD prediction map is predicted measurement data, predicted inspection data, predicted verification. Data, predicted evaluation data, and / or predicted process data. For example, the prediction data may be acquired using an S-D model.

  Further, one or more SD and / or non-SD reliability maps may be generated and / or modified, and the reliability map may be measured data, inspection data, verification data, evaluation data, prediction data, and / or There may be a confidence value for the process data.

  A wafer map is one or more goodness of fit (GOF) maps, one or more grating thickness maps, one or more via-related maps, one or more critical dimension (CD) maps, one or more CDs There may be a profile map, one or more material related maps, one or more groove related maps, one or more sidewall angle maps, one or more width difference maps, or a combination thereof. The data may also include site result data, site number data, CD measurement flag data, measurement site number data, x coordinate data, and y coordinate data, among others.

  In some embodiments, a process that fits the curve may be performed to calculate data for sites on the wafer that are not included in the SD process. Alternatively, the wafer map may be determined using surface estimation methods, surface fitting methods, or other mathematical techniques. When a map is generated for a wafer, a measurement site may be selected based on expectations, predictions, and / or actual accuracy values and / or requirements.

  Some of the errors generated by the mapping application are sent to the FDC system. The FDC system may determine how the processing system responds to errors. Other errors can be resolved by the mapping application.

  When a wafer map is generated and / or modified, values for the entire wafer may not be calculated and / or required, and the wafer map may be one or more sites, one or more chips / Data about the die, one or more different regions, and / or one or more differently shaped regions may be included. For example, the processing chamber may have unique characteristics that are believed to affect the quality of process results in a particular area of the wafer. In addition, manufacturers can maximize yields due to inaccurate process and / or evaluation data for chips / dies in one or more regions of the wafer. Mapping applications and / or FDC systems may use business rules to determine reliability, risk, uniformity, and / or accuracy limits.

  When a value in the map is near the limit, the confidence value may be lower than when the value in the map is not near the limit. In addition, the accuracy value may be weighted for each different area of the different chip / die and / or wafer. For example, higher reliability weights may be assigned to accuracy calculations and / or accuracy data associated with one or more previously used evaluation sites.

  In addition, process results, measurements, inspections, verifications, evaluations, and / or prediction maps associated with one or more processes may be used to calculate a reliability map for the wafer. For example, values from other maps may be used as weighting factors.

  FIG. 4 shows a simplified block diagram of an exemplary subsystem according to an embodiment of the present invention. In the illustrated embodiment, an exemplary SD subsystem 400 is illustrated. The exemplary S-D subsystem 400 includes five S-D devices (410, 420, 430, 440, and 450), a first S-D transport subsystem 460, and a second S-D transport subsystem 470. The first SD transport subsystem 460 may be coupled to the first non-SD transport subsystem 401 and the second non-SD transport subsystem 402. The second SD transport subsystem 470 may be coupled to the first non-SD transport subsystem 401 and the second non-SD transport subsystem 402. The first non-S-D transport subsystem 401 and the second non-S-D transport subsystem 402 may be coupled to the transport subsystem (101, 102, 103 in FIG. 1) (and / or part thereof). Alternatively, a different number of subsystems may be used, a different number of transport subsystems may be used, and the subsystems may be configured differently. In addition, non-S-D subsystems may be used.

  A typical S-D subsystem 400 may have five S-D load lock devices (415, 425, 435, 445, and 455). The five S-D load lock devices (415, 425, 435, 445, and 455) may be coupled to the first S-D transport subsystem 460 and the second S-D transport subsystem 470. Alternatively, a different number of load lock devices may be used and different configurations may be used. In other embodiments, a load lock device may not be necessary. The S-D load lock device 415 may be combined with one or more S-D processing devices 410. The S-D load lock device 425 may be coupled to one or more S-D processing devices 420. The S-D load lock device 435 may be combined with one or more S-D processing devices 430. The S-D load lock device 445 may be combined with one or more S-D processing devices 440. The S-D load lock device 455 may be coupled to one or more S-D processing devices 450. In various embodiments, the SD load lock device (415, 425, 435, 445, and 455) is an internal transfer that transfers, graces, stores, aligns, and / or inspects one or more wafers substantially simultaneously. Devices (417, 427, 437, 447, and 457, respectively) may be included.

  The first S-D transport subsystem 460 may include a first S-D supply device 467 that can be coupled to a first number of first S-D transport devices (461, 462, 463, 464, and 465). In some embodiments, the first S-D transport device may be dynamically coupled or separated from the first S-D supply device 467 and may move in one or more directions 469. In addition, the coupling and / or separation may be SD, and the first S-D supply device 467, the first S-D transfer device, wafer data, system data, processing sequence data, or transfer sequence data, or these It can be determined using a combination. The first S-D feeder 467 may have one or more levels (not shown) and may operate at one or more speeds. Alternatively, other wafer transfer methods may be used.

  In addition, the first S-D transfer subsystem 460 and the second S-D transfer subsystem 470 include a processing sequence, a transfer sequence, an operation state, a wafer and / or a processing state, a processing time, a current time, wafer data, and a site on the wafer. Wafers may be loaded, loaded, and / or unloaded based on the number, type of sites on the wafer, number of required sites, number of completed sites, number of remaining sites, or reliability data, or a combination thereof. .

  Five first SD transport devices (461, 462, 463, 464, and 465) are shown in the illustrated embodiment. However, this is not essential for the present invention. In other embodiments, a different number of first SD transport devices may be used. In addition, the illustrated first SD transport devices (461, 462, 463, 464, and 465) are shown at the first transport point in FIG. 4, but this is not essential to the invention. . When the first SD transfer device is located at the first transfer point, one or more wafers (not shown) may be transferred between the first SD transfer device and the SD load lock device. .

  The second S-D transport subsystem 470 may include a second S-D supply device 477 that can be coupled to a second number of second S-D transport devices (471, 472, 473, 474, and 475). In some embodiments, the second SD transport device may be dynamically coupled to or disconnected from the second SD feed device 477 and moved in one or more directions 469. In addition, the coupling and / or separation may be SD and the second S-D supply device 477, the second S-D transfer device, wafer data, system data, processing sequence data, or transfer sequence data, or these It can be determined using a combination. The second S-D supply device 477 may have one or more levels (not shown) and may operate at one or more speeds. Alternatively, other wafer transfer methods may be used.

  Five second SD transport devices (471, 472, 473, 474, and 475) are shown in the illustrated embodiment. However, this is not essential for the present invention. In other embodiments, a different number of second SD transport devices may be used. In addition, the illustrated second SD transport devices (471, 472, 473, 474, and 475) are shown at the second transport point in FIG. 4, but this is not essential to the invention. . When the second SD transport device is located at the second transport point, one or more wafers (not shown) may be transported between the second SD transport device and the SD load lock device. .

  For example, the S-D processing sequence and / or the S-D transfer sequence may be used by the first S-D transfer subsystem 460 and the second S-D transfer subsystem 470 that transfer the wafer.

  A typical S-D subsystem 400 may have five controllers (414, 424, 434, 444, and 454). The first control device 414 may be combined with one or more first S-D processing devices 410, and is used to control one or more first S-D processing devices 410 and first S-D load lock devices 415. It ’s good. In addition, the first controller 414 may be coupled with the data transfer subsystem (106 in FIG. 1) 411. The second control device 424 may be coupled to one or more second S-D processing devices 420, and is used to control one or more second S-D processing devices 420 and second S-D load lock devices 425. It ’s good. In addition, the second controller 424 may be coupled with a data transfer subsystem (106 in FIG. 1) 421. The third control device 434 may be combined with one or more third S-D processing devices 430 and is used to control one or more third S-D processing devices 430 and the third S-D load lock device 435. It ’s good. In addition, the third controller 434 may be coupled 431 with a data transfer subsystem (106 in FIG. 1). The fourth control device 444 may be combined with one or more fourth S-D processing devices 440, and is used to control one or more fourth S-D processing devices 440 and the fourth S-D load lock device 445. It ’s good. In addition, the fourth controller 444 may be coupled with a data transfer subsystem (106 in FIG. 1) 441. The fifth control device 454 may be combined with one or more fifth S-D processing devices 450, and is used to control one or more fifth S-D processing devices 450 and the fifth S-D load lock device 455. It ’s good. In addition, the fifth controller 454 may be coupled 451 with a data transfer subsystem (106 in FIG. 1). Alternatively, a different number of control devices may be used, a different number of processing devices may be used, and the data transfer subsystem may have a different configuration.

  One or more controllers (414, 424, 434, 444, and 454) may generate, process, modify, transmit, and / or receive one or more messages in real time. The first S-D transport subsystem 460 is coupled to the data transfer subsystem (106 in FIG. 1) at 466 and generates, processes, modifies, transmits, and / or receives one or more messages in real time. good. The second S-D transport subsystem 470 is coupled with the data transfer subsystem (106 in FIG. 1) at 466, and generates, processes, modifies, transmits, and / or receives one or more messages in real time. good. Data transfer subsystem 106 may also generate, process, modify, send, and / or receive one or more messages in real time. The message may comprise S-D data and / or non-S-D data. The message may include real time data and / or historical data.

  In some embodiments, one or more wafers may be received by the first SD transport subsystem 460 and the second SD transport subsystem 470. A processing sequence for the wafer may be set by the system 400. For example, wafer and / or process status data may be used by the wafer to set up a process sequence when and / or before the wafer is received. Alternatively, the wafer may be received by a processing apparatus.

  One or more messages may be processed in real time by one or more controllers (414, 424, 434, 444, and 454). One or more wafers may be processed substantially simultaneously by one or more subsystems (410, 420, 430, 440, and 450). One or more messages may be used to determine the processing sequence for each wafer. For example, the first wafer may be sent to the first processing device 410 using the first load lock device 415, and the second wafer may be sent to the second processing device 420 using the second load lock device 425, The third wafer may be sent to the third processing device 430 using the third load lock device 435, the fourth wafer may be sent to the fourth processing device 440 using the fourth load lock device 445, and The fifth wafer may be sent to the fifth processing unit 450 using the fifth load lock device 455. In addition, the one or more messages may include wafer data, recipe data, profile data, modeling data, device data, and / or processing data.

  One or more controllers (414, 424, 434, 444, and 454) can process one or more wafers using one or more SD processors (410, 420, 430, 440, and 450). It can be used to determine when and how to do it. The controller may be used to determine when the S-D processing device in the S-D subsystem becomes available and / or when the S-D processing device in the S-D subsystem becomes unavailable. For example, due to timing issues, the S-D message and / or data may not be available, and the controller may wait until the S-D message and / or data is available. In addition, when new (updated) S-D data is not available, the wafer may be processed using non-updated S-D data.

  In some embodiments, the first number of wafers to be processed may be set using the first processing sequence. A second number of available processing devices in the S-D subsystem may be identified by querying one or more processing devices in the S-D subsystem. For example, the operating state for each processing device may be determined, and the first operating state for the second number of available processing devices may be the first value when the processing device is available, The second value may be used when the processing device is not available.

  When the second number is greater than or equal to the first number, the first number of wafers may be transferred to a second number of available processing equipment in the S-D subsystem. When the second number is less than or equal to the first number, one or more corrective actions may be performed.

  The corrective action is: 1) process as many wafers as possible and store the remaining wafers, 2) process as many wafers as possible and as soon as the processing equipment is available, the remaining wafers And 3) processing as many wafers as possible and sending the remaining wafers to other subsystems as soon as the processing equipment is available.

  In some embodiments, a first S-D mask process may be performed. For example, a mask deposition process may be performed using the first S-D apparatus 410, an exposure process may be performed using the second S-D apparatus 420, and a drying and / or inspection process may be performed using the third S-D apparatus 430. , The rework process may be performed using the fourth S-D apparatus 440, and the development process may be performed using the fifth S-D apparatus 450. In other examples, other subsystems may be replaced and / or additional subsystems may be used. Other S-D processing sequences may be used to determine the number and / or type of subsystems and when to use the subsystems.

  In additional embodiments, an S-D measurement process may be performed. An S-D processing sequence and / or an S-D transfer sequence for some wafers may be set using wafer data. The sequence may include an S-D measurement process. The S-D processing sequence and / or the S-D transport sequence may be performed using the S-D processing apparatus (410, 420, 430, 440, and 450) and the transport subsystem (401, 460, and 470). For example, the first non-S-D transport subsystem 401 and / or the second non-S-D transport subsystem 402 may receive a number of wafers including S-D wafers and / or non-S-D wafers. The first set of wafers may be received by the first SD transport subsystem 460 and the second SD transport subsystem 470.

  Each wafer may have associated wafer data. The wafer data may include S-D data and / or non-S-D data. One or more wafers have one or more evaluation structures thereon. S-D reliability data and / or non-S-D reliability data for wafers, subsystems, processing equipment, processing, or processing result data, or combinations thereof may be determined.

  A first set of S-D measurement wafers may be fabricated. One or more evaluation structures may be provided on each wafer in the first set of S-D measurement wafers. The first set of S-D measurement wafers may be fabricated using S-D data and / or non-S-D data. The first set of S-D measurement wafers may be transferred to one or more S-D processing devices (410, 420, 430, 440, and 450). For example, reliability data, wafer state data, processing sequence data, or history data may be used.

  A first S-D measurement process may be determined for a first set of S-D measurement wafers. The first set of S-D measurement wafers is measured in the first S-D evaluation apparatus 410 by using the first S-D measurement process. For example, reliability data, wafer state data, process sequence data, or history data may be used for setting the first S-D measurement process.

  The first set of SD measurement wafers is transferred to one or more first S-D measurement related devices 410 in the first S-D subsystem 400 by using one or more SD transfer subsystems (460, 470). May be good. The first S-D transport sequence, the first S-D processing sequence, or the first S-D measurement process, or a combination thereof, may be used to determine one or more first S-D measurement related devices 410. One or more first S-D measurement related devices 410 may perform a first S-D measurement process.

  In some embodiments, the first measurement wafer may be selected from a first set of S-D measurement wafers, and the first measurement wafer may have a first S-D evaluation site thereon. First measurement data including measurement signal data from the first S-D site may be acquired. The first S-D best estimate signal and the associated first S-D test estimation structure may be selected from a library of S-D measurement signals and associated structures. For example, the signal may comprise a diffraction signal and / or spectrum, a refraction signal and / or spectrum, a reflected signal and / or spectrum, a transmitted signal and / or spectrum, or a combination thereof.

  In addition, SD evaluation sites include mask structure, etching structure, doping structure, buried structure, half-filled structure, damage structure, dielectric structure, gate structure, gate electrode structure, gate stack structure, transistor structure, A FinFET structure, a CMOS structure, a photoresist structure, a periodic structure, an alignment structure, a groove structure, a via structure, an array structure, a diffraction grating structure, or a combination thereof may be included.

  A first S-D difference between the first S-D measurement signal data and the first S-D best estimate signal data may be calculated. First S-D reliability data for the first measurement wafer may be set using the first S-D difference. The first S-D reliability data may be compared with the first S-D product requirements. If one or more S-D product requirements are met, the first measurement data can be qualified as the first reliable wafer and processing can continue. Alternatively, the first corrective action may be applied if one or more SD product requirements are not met.

  S-D measurement signal data may be obtained from an S-D evaluation structure, or other structure, or a combination thereof.

  When one or more first S-D product requirements are met, an S-D evaluation site may be created using the first S-D best estimation structure and associated first S-D best estimation signal data.

  In some embodiments, the first corrective action is a selection step of selecting new SD best estimate signal data and an associated new SD best estimate structure from a library of SD diffraction signals and associated structures, the first S-D measurement A calculation process for calculating a new SD difference between the signal data and the new SD best estimate signal data, a setting process for setting new SD reliability data for the first measurement wafer by using the new SD difference, a new A comparison process that compares SD reliability data with new SD product requirements, and if one or more new SD product requirements are met, the first measurement wafer is certified as a new high reliability wafer and processed. Continue certification process or, if one or more new SD product requirements are not met, the selection process, the calculation process, the setting process, the comparison process, and the cancellation process to stop the certification process Possess Good. When the first S-D profile library generation criterion is satisfied, the first S-D evaluation site may be created using the new S-D best estimation structure and the related new S-D best estimation signal data. Alternatively, other best estimate data may be used and other comparisons may be made.

  In another embodiment, the first correction act is a step of selecting a second measurement wafer from the first set of SD measurement wafers, the second measurement wafer having a first S-D evaluation portion on the first measurement wafer, First selection step, acquisition step for acquiring second measurement data including second S-D measurement signal data from the first S-D region, first S-D best from library of SD measurement data (diffraction signal) and related structure A second selection step for selecting estimated signal data and an associated second S-D best estimation structure; a calculation step for calculating a second S-D difference between the second S-D measurement signal data and the second S-D best estimation signal data; A comparison process that compares the second S-D reliability data with the second S-D product requirements, and if one or more second S-D product requirements are met, the second measurement wafer is designated as the second high-reliability wafer. An accreditation process that is accredited and processed, or an amendment that applies a second amendment if one or more second S-D product requirements are not met It may have any of the use process.

  In yet another embodiment, the first correction act includes a first selection step of selecting a second S-D evaluation site on the measurement wafer, and a second S-D measurement signal data from the second S-D site. An acquisition process for acquiring measurement data, a second selection process for selecting a first S-D best estimation signal data and an associated second S-D best estimation structure from a library of SD measurement data (diffraction signal) and related structures, a second S A calculation process for calculating the second S-D difference between the -D measurement signal data and the second S-D best estimated signal data, and the second S-D reliability data for the first measurement wafer is obtained by using the second S-D difference. A setup process to set up, a comparison process to compare the second S-D reliability data with the second S-D product requirements, and the second measurement product to the second if one or more second S-D product requirements are met A qualification process that qualifies as a reliable wafer and continues processing, or if one or more second S-D product requirements are not met May have one of the compensation applied applying a second corrective actions.

  In some embodiments, the additional correction act is a first selection step of selecting additional SD evaluation sites on one or more measurement wafers, and acquiring additional measurement data including additional SD measurement signal data from the additional SD sites. A second selection step of selecting additional SD best estimation signal data and related additional SD best estimation structure from a library of acquisition processes, SD measurement data and related structures, and additional SD measurement signal data and additional SD best estimation signal data Calculation process to calculate additional SD differences, setting process to set additional SD reliability data for one or more measurement wafers by using additional SD differences, comparison process to compare additional SD reliability data with additional SD product requirements And one or more additional SD product requirements, if one or more additional SD product requirements are met, qualify the process to qualify one or more measurement wafers as additional high-reliability wafers, or one or more additional SD When the product requirement is not satisfied, the method may include any of the selection step, the calculation step, the setting step, the comparison step, and a cancellation step for stopping the certification step.

  Library creation rules may be used when a new site is selected.

  In other embodiments, a double patterning process sequence may be performed by using one or more SD processes. A first set of wafers may be received by the first SD transport subsystem 460 and the second SD transport subsystem 470. The first set of wafers may be transferred to one or more first SD devices 410. A first mask layer may be deposited on each wafer by using a first S-D mask deposition process. A first set of high reliability wafers may be created by using the first SD evaluation process. The first set of high reliability wafers may be received by the first SD transport subsystem 460 and the second SD transport subsystem 470. The first set of high reliability wafers may be transferred to one or more second SD devices 420. The mask layer on each wafer may be exposed to the first patterning radiation by using a first SD exposure process. The second set of high reliability wafers may be received by the first SD transport subsystem 460 and the second SD transport subsystem 470. The first set of high reliability wafers may be transferred to one or more third S-D devices 430. The exposed layer may be developed using an SD development process. A third set of high reliability wafers may be created by using a third evaluation process. The third set of high reliability wafers may be received by the first SD transport subsystem 460 and the second SD transport subsystem 470. The third set of high reliability wafers may be transferred to one or more fourth SD devices 440. The developed wafer may be etched using an S-D etching process. A first set of etching structures may be created in one or more layers on each wafer. A fourth set of high reliability wafers may be created by using a fourth evaluation process. The fourth set of reliable wafers may be received by the first SD transport subsystem 460 and the second SD transport subsystem 470. The fourth set of high reliability wafers may be transferred to one or more fifth S-D devices 450. One or more first materials may be deposited on the etched wafer by using an S-D deposition process. A first set of embedded structures may be created in one or more layers on each wafer. A fifth set of high reliability wafers may be created by using the fifth evaluation process.

  A fifth set of high reliability wafers may be received by the first SD transport subsystem 460 and the second SD transport subsystem 470. The fifth set of high reliability wafers may be transferred to one or more first SD devices 410. A second mask layer may be deposited on each wafer by using a second S-D mask deposition process. A sixth set of high-reliability wafers may be created by using a sixth S-D evaluation process. A sixth set of high reliability wafers may be received by the first SD transport subsystem 460 and the second SD transport subsystem 470. The sixth set of high reliability wafers may be transferred to one or more second SD devices 420. The second mask layer on each wafer may be exposed to the second patterning radiation by using a second SD exposure process. A seventh set of high-reliability wafers may be created by using the seventh S-D evaluation process. The seventh set of high reliability wafers may be received by the first SD transport subsystem 460 and the second SD transport subsystem 470. The seventh set of high reliability wafers may be transferred to one or more third S-D devices 430. The second exposed layer may be developed by using a second SD development process. An eighth set of high reliability wafers may be created by using the eighth evaluation process. The eighth set of reliable wafers may be received by the first SD transport subsystem 460 and the second SD transport subsystem 470. The eighth set of high reliability wafers may be transferred to one or more fourth S-D devices 440. The developed wafer may be etched using an S-D etching process. A second set of etching structures may be created in one or more layers on each wafer. The ninth set of high reliability wafers may be created by using the ninth evaluation process. The ninth set of high reliability wafers may be received by the first SD transport subsystem 460 and the second SD transport subsystem 470. The ninth set of high reliability wafers may be transferred to one or more fifth S-D devices 450. One or more second materials may be deposited on the etched wafer by using an S-D deposition process. A second set of embedded structures may be created in one or more layers on each wafer. A tenth set of high reliability wafers may be created by using the tenth evaluation process.

  The first set of high-reliability wafers is: 1a) SD reliability data is acquired from one or more mask generation evaluation sites during the first S-D mask generation process; 2a) for each wafer in the first set of wafers The SD reliability data of the first set is compared with one or more reliability requirements set for one or more mask generation evaluation sites, and 3a) if the first mask generation reliability requirements are met, Can be created by qualifying a wafer in a first set of wafers as a member of a highly reliable wafer.

  The second set of high-reliability wafers is 1b) SD reliability (mapping) data is acquired from one or more exposure-dependent sites during the SD exposure process, and 2b) each wafer in the first set of high-reliability wafers. Compare SD reliability (mapping) data with one or more reliability (mapping) requirements set for one or more exposure dependent sites, and 3b) the first exposure related reliability (mapping) requirements If satisfied, may be created by qualifying a wafer in the first set of high-reliability wafers as a member of the second set of high-reliability wafers.

  The third set of high-reliability wafers is 1c) SD reliability (mapping) data is acquired from one or more development-dependent sites during the SD development process, and 2c) each wafer in the second set of high-reliability wafers. Compare SD reliability (mapping) data with one or more reliability (mapping) requirements set for one or more development-dependent sites, and 3c) the first development-related reliability (mapping) requirement If satisfied, may be created by qualifying a wafer in the second set of high-reliability wafers as a member of the third set of high-reliability wafers.

  The fourth set of high-reliability wafers is 1d) SD SD (mapping) data is acquired from one or more etch-dependent sites during the SD etching process, and 2d) each wafer in the third set of high-reliability wafers. Compare SD reliability (mapping) data with one or more reliability (mapping) requirements set for one or more etch dependent sites, and 3d) the first etch related reliability (mapping) requirements If satisfied, it may be created by qualifying a wafer in a third set of high reliability wafers as a member of a fourth set of high reliability wafers.

  The fifth set of high-reliability wafers is 1e) SD reliability (mapping) data is acquired from one or more deposition-dependent sites during the SD deposition process, and 2e) each wafer in the fourth set of high-reliability wafers. Compare SD reliability (mapping) data with one or more reliability (mapping) requirements set for one or more deposition dependent sites, and 3e) the first deposition related reliability (mapping) requirements If satisfied, it may be created by qualifying a wafer in the fourth set of high reliability wafers as a member of the fifth set of high reliability wafers.

  Additional high reliability wafer sets may be created using similar techniques.

  The evaluation site may include a process dependent site, a measurement dependent site, an inspection dependent site, a layer dependent site, and a wafer dependent site. The S-D reliability data may have a confidence value for the S-D (mask generation) data. The S-D (mask generation) data may include accuracy data, S-D processing data, S-D measurement data, S-D inspection data, S-D simulation data, S-D prediction data, or S-D history data, or a combination thereof. The first mask generation reliability requirement may have a reliability data limit for the mask generation data. The mask generation data may have accuracy limits, process data limits, measurement data limits, inspection data limits, simulation data limits, prediction data limits, and / or historical data limits.

  In some additional embodiments, the first non-S-D transport subsystem 401 and / or the second non-S-D transport subsystem 402 may receive S-D and / or non-S-D wafers. The S-D wafer may be transferred to the first S-D transfer subsystem 460 and the second S-D transfer subsystem 470. The wafer related data may include S-D reliability data and / or non-S-D reliability data.

  A first set of S-D wafers may be created using S-D reliability data and / or non-S-D reliability data. A first S-D processing sequence for the first set of S-D wafers may be determined. The first set of S-D wafers may be processed in the S-D apparatus (410, 420, 430, 440, and 450) by using the first S-D processing sequence. The wafer state data may be used for setting the first SD processing sequence. The first set of S-D wafers may be transferred to one or more S-D processing equipment (410, 420, 430, 440, and 450). The first S-D processing sequence may be used to determine one or more first S-D processing devices.

  In addition, the first S-D subsystem processing data may be collected before, during and / or after the first S-D processing sequence is performed using the first set of SD wafers and First SD reliability data for one or more wafers in a set of SD wafers may be set by using the wafer data and / or the first SD subsystem processing data. In some examples, first S-D reliability data for a first S-D wafer in a first set of S-D wafers may be set by using first S-D subsystem processing data. The first SD reliability value for the first SD wafer may be about the first SD reliability limit. If the first SD reliability limit is met, the processing of the first set of SD wafers may be continued. Alternatively, if the first SD reliability limit is not satisfied, the first SD correction act may be applied. The first S-D correction act is a setting step for setting an SD confidence value for one or more wafers in the first set of SD wafers by using the first S-D subsystem processing data, and one or more additional wafers. A comparison process that compares the SD confidence value for the additional first S-D confidence value, and the processing of the first set of SD wafers if one or more additional first S-D reliability limits are met Continuing or stopping the setting step and the comparison step if one or more additional first SD reliability limits are not met.

  Other sets of S-D wafers may also be created by using S-D reliability data and / or non-S-D reliability data. Other S-D processing sequences may be determined for other sets of S-D wafers. Wafer state data may be used to set other S-D processing sequences. Other sets of S-D wafers may be transferred to one or more other S-D processing equipment in other S-D subsystems. Other S-D processing sequences may be used to determine one or more other S-D processing devices. For example, other sets of S-D wafers may be transferred to one or more S-D processing equipment in one or more other S-D subsystems.

  During wafer processing, a first set of non-SD wafers may be created using SD reliability data and / or non-SD reliability data, and a first non-SD processing sequence for the first set of non-SD wafers is determined. May be good. In some cases, the first set of non-SD wafers may be processed within the non-SD subsystem by using the first non-SD processing sequence, and the wafer status data is set to the first non-SD processing sequence. May be used. The first set of non-SD wafers may be transferred to one or more non-SD processing equipment in one or more non-SD subsystems, and the first non-SD processing sequence may include one or more first non-SD processing. It can be used to determine the device. For example, the first set of non-S-D wafers may be transferred to one or more non-S-D processing equipment in other subsystems.

  In various embodiments, non-SD wafers may be processed in a non-SD subsystem by using a non-SD processing sequence, or non-SD wafers are processed in an SD subsystem by using a non-SD processing sequence. Alternatively, non-SD wafers may be processed within the non-SD subsystem by using an SD processing sequence, and the wafer status data may be used to set the processing sequence. In addition, non-S-D wafers may be transferred by using non-S-D transfer sequences and / or SD transfer sequences. The processing sequence can be used to determine the transport sequence.

  In addition, the first non-SD subsystem processing data may be collected before, during, and / or after the first non-SD processing sequence is performed using the first set of non-SD wafers, and First non-SD reliability data for one or more wafers in the first set of non-SD wafers may be set by using wafer data and / or first non-SD subsystem processing data. In some examples, first non-S-D reliability data for a first non-S-D wafer in a first set of non-S-D wafers may be set by using first non-S-D subsystem processing data. The first non-S-D reliability value for the first non-S-D wafer may be about the first non-S-D reliability limit. If the first non-S-D reliability limit is met, the processing of the first set of non-S-D wafers may continue. Alternatively, if the first non-S-D reliability limit is not satisfied, the first non-S-D correction action may be applied. The first non-SD correction act is a setting step that sets a non-SD confidence value for one or more wafers in the first set of non-SD wafers by using the first non-SD subsystem processing data, A comparison process that compares the non-SD confidence value for the additional wafer with the additional first non-SD confidence value, and a first set of non-SD if one or more additional first non-SD reliability limits are met Continue processing the wafer, or if the one or more additional first non-SD reliability limits are not met, discontinuing the setting step and the comparison step.

  Other sets of non-S-D wafers may also be created by using S-D reliability data and / or non-S-D reliability data. Other non-S-D processing sequences may be determined for other sets of non-S-D wafers. Wafer state data may be used to set other non-S-D processing sequences. Other sets of non-S-D wafers may be transferred to one or more other non-S-D processing equipment in other non-S-D subsystems. Other non-S-D processing sequences may be used to determine one or more other non-S-D processing devices. For example, other sets of non-S-D wafers may be transferred to one or more processing equipment in one or more other subsystems.

  An SD processing sequence and / or a non-SD processing sequence may include one or more coating processes, one or more etching processes, one or more heat treatments, one or more exposure processes, one or more oxidation processes, one or more oxidation processes. Nitriding, one or more development processes, one or more lithography processes, one or more scanner related processes, one or more measurement processes, one or more inspection processes, one or more evaluation processes, one or more evaluation processes Simulation process, one or more prediction processes, one or more rework processes, one or more storage processes, one or more transport processes, one or more load lock processes, or one or more cleaning processes, or these There may be a bond of

  SD processing subsystem and / or non-SD processing subsystem may include one or more coating subsystems, one or more etching subsystems, one or more thermal subsystems, one or more exposure subsystems, one or more Oxidation subsystem, one or more nitridation subsystems, one or more development subsystems, one or more lithography subsystems, one or more scanner related subsystems, one or more measurement subsystems, one or more inspections Subsystem, one or more evaluation subsystems, one or more simulation subsystems, one or more prediction subsystems, one or more rework subsystems, one or more storage subsystems, one or more transport subsystems There may be a system, one or more load lock subsystems, or one or more cleaning subsystems, or a combination thereof.

  SD processing equipment and / or non-SD processing equipment is one or more coating processing equipment, one or more etching processing equipment, one or more heat treatment equipment, one or more exposure processing equipment, one or more oxidation processing equipment One or more nitriding processing devices, one or more development processing devices, one or more lithography processing devices, one or more scanner related processing devices, one or more measurement processing devices, one or more inspection processing devices, One or more evaluation processing devices, one or more simulation processing devices, one or more prediction processing devices, one or more rework processing devices, one or more storage processing devices, one or more transport processing devices, 1 There may be one or more load lock processing devices, or one or more cleaning processing devices, or a combination thereof.

  FIG. 5 depicts an exemplary flow diagram of a verification method for an S-D site, an S-D wafer, and / or an S-D process according to an embodiment of the present invention.

  In 510, one or more wafers may be received by one or more SD processing units in the processing subsystem, one or more SD processing units may be combined with one or more SD transfer subsystems, And wafer data for one or more wafers may be received. Alternatively, the wafer may be received by one or more SD transport subsystems. Wafer data may include historical data and / or real-time data. Wafer status data may be set for one or more wafers. The wafer state data may include S-D data, chip dependent data, and / or die dependent data.

  At 515, an S-D process and / or transfer sequence for the S-D wafer may be determined. In some cases, different S-D processing sequences may be determined for some S-D wafers. Alternatively, a non-S-D processing sequence may be set instead.

  At 520, one or more wafers may be processed. In some embodiments, a first set of unverified SD wafers may be generated by performing a first SD generation process using one or more SD processing devices, and one or more unverified SD wafers. Verification verification sites may be generated at the first number of evaluation sites on each unverified SD wafer. S-D wafer state data may be set for each unverified S-D wafer. The S-D wafer status data may include a number of required generation sites and a number of required evaluation sites for each unverified S-D wafer.

  At 525, a query may be executed to determine whether one or more S-D generation processes have been executed correctly. If one or more S-D generation processes have been performed correctly, process 500 may branch to step 530. If one or more S-D generation processes were not performed correctly, process 500 may branch to step 580. For example, device data, chamber data, particle data, image data, and / or failure data may be used.

  At 580, the wafer may be post-processed using one or more additional processes. The one or more additional processes may include wafer remeasurement, re-evaluation, rework, and / or removal of the wafer from the processing sequence.

  In 545, the S-D wafer may be evaluated using the selected site. In some cases, the first wafer verification data may be obtained from the first site on the first SD evaluation wafer. The first wafer verification data may include first S-D measurement data and / or first S-D inspection data. The first S-D measurement data and / or the first S-D inspection data may be obtained by using an SD measurement process executed in the SD measurement apparatus and / or an SD inspection process executed in the SD inspection apparatus. . Next, first verified data may be set for the first site on the first S-D evaluation wafer, the first verified data being the first verified measurement data and / or the first And the first verified measurement data and / or the first verified test data may be obtained from a history and / or real-time database. Subsequently, the first confidence value for the first site on the first S-D evaluation wafer may be set by using the first wafer verification difference, and the first wafer verification difference is determined by the first wafer verification difference. It can be calculated by using the data and the first verification data.

  The first risk factor for the first site on the first S-D evaluation wafer may be set by using a first confidence value, a first wafer verification difference, or wafer data, or a combination thereof. The first total risk factor for the first S-D evaluation wafer may be set by using a first risk factor, a first confidence value, a first wafer verification difference, or wafer data, or a combination thereof.

  At 550, a query may be performed to determine whether one or more S-D evaluation wafers have been verified. When one or more S-D evaluation wafers are verified, the process 500 may branch to step 565. If one or more S-D evaluation wafers have not been verified, the process 500 may branch to step 555.

  When the first total risk factor is less than or equal to the first wafer verification limit, the first S-D evaluation wafer is certified as the first verified SD wafer with the first total risk factor and the remaining number of sites is one. The number of accessed sites is increased by one, and the first S-D generation process related to the first S-D evaluation wafer may be certified as the first verified SD process.

  When the first total risk factor is greater than the first wafer verification limit, the first site is recognized as the first unverified site with the first risk factor, the remaining number of sites is reduced by 1, and the number of visited sites is 1. You can add more. The first verified S-D evaluation wafer may have verified wafer data.

  At 555, a query may be performed to determine whether additional sites are needed. When additional sites are needed, process 500 may branch back to step 540. When no additional sites are needed, process 500 may branch to step 555.

  When additional sites are needed for the current wafer, the following steps may be performed. The following steps are: a) a new site having a new unverified site for evaluation generated using the first S-D generation process from the number of necessary sites on the first S-D evaluation wafer. Selecting, b) obtaining new wafer verification data from a new site having new SD measurement and / or new SD inspection data existing on the first S-D evaluation wafer, c) first S-D D is a step of setting new verification data for a new site on the evaluation wafer, the new verification data having newly verified measurement and / or inspection data, d) for new wafer verification Setting a new confidence value for a new site on the first S-D evaluation wafer by using the new wafer verification difference calculated by using the data and the new verification data; e) New Reliability, new wafer verification differences Setting a new risk factor for a new site on the first SD evaluation wafer by using the first confidence value, the first wafer verification difference, or wafer data, or a combination thereof; f) new Risk factor, new confidence value, new wafer verification difference, first risk factor, first confidence value, first wafer verification difference, or wafer data, or first S-D using a combination of these Setting a new total risk factor for the new site on the evaluation wafer; g) if the new total risk factor is less than or equal to the new wafer verification limit, then 1Certify the first SD evaluation wafer as the verified wafer, reduce the number of required sites by 1 and increase the number of accessed sites by 1 and the 1st S related to the 1st S-D evaluation wafer -D generation process is new Qualifying as validated SD process, h) When all new risk factors are greater than new wafer verification limits, certify new site as new unverified site with associated new risk factors I) increase the required number of sites by 1 and decrease the number of accessed sites by 1, i) repeat the steps a)-h) when the required number of sites is greater than 0, and j) the required number of sites is 0 Is the step of stopping verification of the first wafer.

  Alternatively, other processing may be used instead.

  At 560, a query may be performed to determine whether additional evaluation wafers are needed. When additional evaluation wafers are needed, the process 500 may branch back to step 535. When no additional sites are needed, process 500 may branch to step 565.

  When additional evaluation wafers are needed, the following steps may be performed. The following steps are: a1) a step of selecting an additional SD evaluation wafer, b1) a step of determining the first required site for the additional SD evaluation wafer, c1) on the additional SD evaluation wafer A step of selecting an additional site from the first required number of sites, wherein the additional site has an additional unverified evaluation site generated using the first S-D generation process, d1) Obtaining additional wafer verification data from an additional site on the SD evaluation wafer, wherein the additional wafer verification data includes additional SD measurement and / or SD inspection data; e1) additional SD Setting additional verification data for additional sites on the evaluation wafer, where the additional verification data has additional verified measurement and / or inspection data; f1) additional wafer verification data and additional By using the verification data of Setting additional confidence values for additional sites on additional SD evaluation wafers by using the calculated additional wafer verification differences; g1) additional confidence values, additional wafer verification differences, new Additional sites on additional SD evaluation wafers using new confidence values, new wafer verification differences, first confidence values, first wafer verification differences, or wafer data, or a combination of these H1) additional risk factors, additional confidence values, additional wafer verification differences, new risk factors, new confidence values, new wafer verification differences, first risk factors Setting all additional risk factors for additional SD evaluation wafers using the first confidence value, the first wafer verification difference, or wafer data, or a combination of these, i1) additional total risk factors When the is below the limit for additional wafer verification, qualify additional SD evaluation wafers as additional verified wafers with all the additional risk factors involved and access by reducing the number of sites required by one Storing the data associated with the additional sites as verified data in the evaluation library, j1) when all additional risk factors are greater than the limit for additional wafer verification Qualifying additional SD evaluation wafers as additional unverified sites with an associated additional first risk factor, increasing the required number of sites by one and reducing the number of accessed sites by one, k1) When an additional SD evaluation wafer is available and the required number of sites on the additional SD evaluation wafer is greater than 0, a1) -j1) is repeated, and l1) the additional SD evaluation wafer is Not possible use, and when necessary the number of sites is equal to 0 is the step of stopping the S-D library generation process.

  At 565, a query may be performed to determine if additional production wafers are needed. When additional production wafers are needed, process 500 may branch back to step 515. When no additional sites are needed, process 500 may branch to step 570. Process 500 ends at 570.

  A typical first corrective action is to use the difference between the first number, which is the number of SD evaluation wafers, and the first number, which is the number of available evaluation devices, to remove the first number of deferred SD wafers. Storing the first number of deferred SD wafers for the first period using one or more transfer devices that have means to support and support two or more wafers that exist in the SD transfer subsystem And / or a grace period.

  The additional corrective action is to determine the first number of deferred SD wafers by using the difference between the first number that is the number of SD evaluation wafers and the first number that is the number of available evaluation devices. Determining updated SD wafer status data for the first graced SD wafer; determining operational status data for one or more SD evaluation devices in the first evaluation subsystem; updated The step of identifying one or more newly available SD evaluation devices using the operating state data, the first updated when the first newly available SD evaluation device is available Transporting the first suspended SD evaluation wafer to the first newly available SD evaluation device in one or more evaluation subsystems using the transport sequence, and the first new SD evaluation device that can be used for If not, a step of applying the second correction act may be included.

  Other corrective actions include: aborting the process, aborting the process, re-evaluating one or more SD evaluation wafers, re-measuring one or more SD evaluation wafers, one or more A process for re-inspecting an SD evaluation wafer, a process for reworking one or more SD evaluation wafers, a process for storing one or more SD evaluation wafers, a process for cleaning one or more SD evaluation wafers, Alternatively, one or more SD evaluation wafers may be removed, or a combination thereof may be included.

  In addition, an SD reliability map and / or an SD risk assessment map may be used to verify the wafer.

  FIG. 6 shows an exemplary flow diagram of a method for generating an S-D evaluation library according to an embodiment of the present invention. The first set of S-D wafers may be received by one or more S-D processing equipment in one or more processing subsystems. One or more S-D processing devices may be combined with one or more S-D transport subsystems. Each wafer may have wafer data. Wafer data may include historical data and / or real-time data. Alternatively, the wafer may be received by a different subsystem. Wafer status data may be set for one or more wafers. The wafer state data may include S-D data, chip dependent data, and / or die dependent data. In addition, one or more S-D processing sequences may be set for the wafer. The S-D processing sequence may be set using S-D wafer state data, chip-dependent wafer state data, and / or die-dependent wafer state data.

  Wafer state data may be set for each S-D wafer. The wafer status data may include a number of required generation sites and a number of evaluation sites for each wafer.

  In 610, a library generation processing sequence for generating a library of S-D evaluation data may be set, and a library generation processing sequence may be generated using the wafer state data. The library generation process sequence may include an SD transport process, an SD generation process, an SD evaluation process, or a combination thereof.

  In 620, the first number of SD processing wafers to be processed may be determined by using the first library generation processing sequence, and the first S-D generation processing and the first S-D evaluation processing are generated by the first library generation. It can be determined by using a processing sequence.

  A first operating state is set for a plurality of S-D processing devices in one or more processing subsystems. The first number of available processing devices may be determined using the first operating state for one or more S-D processing devices.

  A first SD transport sequence may be established by using wafer data, wafer state data, or a first number of available processing devices, or a combination thereof.

  In 625, the first number of SD processing wafers uses the first SD transfer sequence when the first number of SD processing wafers is less than or equal to the first number of available processing devices. And may be transported to a first number of available processing devices within one or more processing subsystems. When the first number, which is the number of wafers for S-D processing, is greater than the first number, which is the number of available processing apparatuses, the first correcting action may be applied.

  In 630, a first S-D generation process may be performed and one or more library-related reference sites may be generated at a first number of evaluation sites on each S-D processing wafer. The updated wafer data and / or updated wafer state data is generated using the first SD generation process. The updated wafer status data may have a number of necessary evaluation sites for each SD processing wafer.

  In 635, a query may be executed to determine whether one or more S-D generation processes have been executed correctly. If one or more S-D generation processes have been performed correctly, process 600 may branch to step 640. If one or more S-D generation processes are not performed correctly, process 600 may branch to step 690. For example, device data, chamber data, particle data, image data, and / or failure data may be used.

  At 640, the first number of S-D evaluation wafers to be evaluated may be determined using the first S-D evaluation process. The required number of sites for each S-D evaluation wafer may be determined by updated wafer data, updated wafer status data, wafer data, wafer status data, or a combination thereof.

  First operating states for a plurality of S-D evaluation devices within one evaluation subsystem may be determined. The S-D transport subsystem may be coupled to one or more S-D evaluation devices.

  The first number of available evaluation devices may be determined by using operating states for one or more S-D evaluation devices. The second SD transfer sequence is updated wafer data, updated wafer status data, wafer data, wafer status data, the first number of SD evaluation wafers, or the first number of available evaluation devices, or these May be set by combining.

  In 645, when the first number of SD evaluation wafers is equal to or less than the first number of available evaluation devices, the first number of SD evaluation wafers uses the second SD transfer sequence. And may be transported to a first number of available evaluation devices within one or more evaluation subsystems. When the first number, which is the number of S-D evaluation wafers, is greater than the first number, which is the number of available evaluation devices, the second correction action may be applied.

  In 650, the first site may be selected from a number of required sites on the first S-D evaluation wafer, and the first site is associated with the first library generated using the first S-D generation process. It may have a site (for evaluation).

  In 655, an evaluation process may be performed. Evaluation data related to the first library may be obtained from the first site on the first S-D wafer. The first site may have measurement and / or inspection data associated with the first library. First prediction data may be set for the first site on the first S-D wafer. The first prediction data may include predicted measurement and / or inspection data. The first confidence value for the first site may be set by using the first library-related difference calculated using the difference between the first library-related evaluation data and the first prediction data. A first risk factor for the first site may be set by using a first confidence value, a first library related difference, or wafer data, or a combination thereof. The first total risk factor for the first site may be set by using a first risk factor, a first confidence value, a first library related difference, or wafer data, or a combination thereof.

In 660, when the first total risk factor is less than or equal to the first library-related generation limit, the first site as the first verified site may have the first total risk factor and the remaining number of sites is The number of sites accessed may be decreased by one, and the data related to the first site may be stored as verified data in the evaluation library.
When the first total risk factor is greater than the first library-related generation limit, the first site is identified as the first unverified site with the second risk factor, the remaining number of sites is reduced by one, and the number of sites visited Can be increased by one. The first verified site may have verified library related data.

  At 665, a query may be performed to determine if additional sites are needed. When additional sites are needed, the process 600 may branch back to step 650. When no additional sites are needed, process 600 may branch to step 670.

  When a new site is needed for the first wafer, the following steps may be performed. The following steps are: a) a new site having a new library-related reference site generated using the first S-D generation process from the number of necessary sites on the first S-D evaluation wafer. Selecting, b) obtaining new library-related evaluation data from a new site having new library-related measurement and / or inspection data existing on the first S-D evaluation wafer, c) first S -D: setting new prediction data for a new site on the wafer, the new prediction data having newly predicted measurement and / or inspection data; d) new library related evaluation Setting a new confidence value for the new site by using the new library-related differences calculated by using the data for the site and the new prediction data, e) a new confidence value, a new library Setting new risk factors for new sites by using related differences, first confidence values, first library related differences, or wafer data, or a combination thereof, f) new risk factors, new New confidence factors, new library-related differences, first risk factors, first confidence values, first library-related differences, or wafer data, or new total risk factors for new sites by using a combination of these G) when all new risk factors are below the new library-related generation limits, the new site is identified as a new verified wafer with all relevant new risk factors and is required Reduce the number of new sites by one and increase the number of visited sites, and evaluate the data related to the new site as verified data The process of storing in the library, h) when all new risk factors are greater than the new library-related generation limit, the new site is identified as a new unverified site with the associated second risk factor and needed Increase the number of new sites by 1 and decrease the number of accessed sites by 1, i) repeat the steps a)-h) when the required number of sites is greater than 0, and j) when the required number of sites is equal to 0 A step of stopping verification of the first wafer. The new verified site now has new verified library related data.

  At 670, a query may be performed to determine whether one or more S-D evaluation wafers are needed. When one or more S-D evaluation wafers are needed, the process 600 may branch back to step 645. When one or more S-D evaluation wafers are not needed, the process 600 may branch to step 675.

  When additional wafers are used, one or more controllers may use the following steps. The following steps are a1) a step of selecting an additional site from a number of necessary sites on an additional SD evaluation wafer, and the additional site was generated using the first S-D generation process. A step having an additional library-related reference (evaluation) part; b1) obtaining additional library-related evaluation data from an additional site on an additional SD wafer, wherein the additional site is a related additional library C1) setting additional prediction data for additional sites on additional SD wafers, the additional prediction data being additional predicted measurements and / or having related measurement and / or inspection data; Process with inspection data, d1) additional libraries by using additional library-related differences calculated by using additional library-related evaluation data and additional prediction data. E1) additional confidence values, additional library related differences, new confidence values, new library related differences, first confidence values, first library related differences, or wafers Setting additional risk factors for additional sites by using data, or a combination of these, f1) additional risk factors, additional confidence values, additional library-related differences, new risk factors, new trust Setting all additional risk factors for additional sites by using values, new library-related differences, first risk factors, first confidence values, first library-related differences, or wafer data, or combinations thereof G1) Additional verification with all additional risk factors associated when all the additional risk factors are below the additional library-related generation limits Qualify additional sites as verified sites, reduce the number of required sites by one and increase the number of accessed sites by one, and store the data related to the additional sites as verified data in the evaluation library H1) If all additional risk factors are greater than the additional library-related generation limits, certify the additional sites as additional unverified sites with an additional second risk factor associated with the required sites. I1) When an additional SD evaluation wafer is available and the required number of sites on the additional SD evaluation wafer is greater than 0 a1) a step of repeating -h1), and j1) a step of stopping the SD library generation process when an additional SD evaluation wafer is not available and the required number of sites is equal to zero. Here the additional verified site has associated additional verified library related data.

  In addition, the delayed S-D evaluation wafer may be processed and / or evaluated at various times. Data from the deferred wafer is used as soon as it becomes available. For example, data from a deferred wafer may be fed back or fed forward for use in other processes.

  In 675, a query may be performed to determine if additional production wafers are needed. When additional production wafers are needed, the process 600 branches back to step 615 and the process may proceed as shown in FIG. When no additional sites are needed, process 600 may branch to step 680. The process 600 ends at 680.

  FIG. 7 shows a typical flow diagram of a method for fabricating a dual damascene structure on a wafer using S-D processing.

  At 710, one or more wafers can be received by the SD transport subsystem and wafer data for one or more wafers can be received. Alternatively, the wafer may be received by a different subsystem. Wafer data may include historical data and / or real-time data. Wafer status data may be set for one or more wafers. The wafer state data may include S-D data, chip dependent data, and / or die dependent data. In addition, one or more SD processing sequences may be set for the wafer, and the SD processing sequence is set using SD wafer state data, chip dependent wafer state data, and / or die dependent wafer state data. good.

  Returning to FIG. 1, in a first exemplary embodiment, the S-D wafer may be received by one of the S-D transport subsystems (101, 102) that can be coupled to the first lithography subsystem 110. One or more controllers (114, 119, 124, 129, 134, 139, 144, 149, 154, 159, and 195) may receive the data. In some embodiments, when a wafer is received, data associated with the wafer and / or lot may also be received, and the data may include SD and / or non-SD data and / or messages. For example, the data may include an S-D map. SD maps include, for example, reliability maps, process maps, risk assessment maps, damage assessment maps, reference maps, measurement maps, prediction maps, imaging maps, library-related maps for incoming wafers and / or incoming lots. , And / or other wafer related maps. The data may include data and / or messages from one or more subsystems, host systems, and / or other processing systems associated with the processing system. For example, S-D messages and / or data may be used to determine and / or control processing sequences and / or transport sequences.

  That data may be processed to obtain wafer data. The wafer data may include history and / or real time data. S-D wafer data may be determined for each wafer. The S-D wafer data may include S-D wafer state data and / or S-D reliability data.

  In cases where additional SD wafers require processing, when the first SD processing equipment is available, the additional SD wafers can be obtained by using an SD transfer subsystem that is coupled to one or more processing subsystems. The additional SD wafer may be transferred to an additional SD processing unit in one or more processing subsystems, and the additional SD wafer may be combined with one or more processing subsystems when the first SD processing unit is not available You can be deferred by using the SD transport subsystem. A transfer device in the SD transfer subsystem may be used to store and / or hold the wafer for a period of time.

  In 715, one or more S-D processing sequences for each S-D wafer may be set using the wafer data. Wafer data and / or S-D wafer status data may be used to set up an S-D processing sequence for each S-D wafer when and / or before the wafer is received. In addition, a first processing subsystem for each wafer may be identified by using the first SD process sequence and / or SD wafer data. In one example, a first processing sequence may be set up to create multiple etch sites in one or more layers on the wafer.

  In the first exemplary embodiment, an SD dual damascene (DD) processing sequence may be set, and the SD DD processing sequence includes a first damascene generation process, a first damascene evaluation process, a second damascene generation process, and a second damascene generation process. A damascene evaluation process may be included. A first set of S-D processing wafers may be set. The S-D wafer data may be used to identify the first set of S-D processing wafers. The first set of S-D processing wafers may be processed by using a first damascene generation process.

  At 720, unprocessed S-D wafers may be transferred and / or suspended. A first SD process for the first unprocessed SD wafer may be determined. The first S-D process may include one or more process related processes. When the first S-D processing apparatus is available, the first unprocessed SD wafer is processed in the first processing subsystem by using an SD transfer subsystem coupled to the first processing subsystem. It can be transported to the device. When the first SD processing apparatus is not available, the first unprocessed SD wafer may be deferred by using an SD transport subsystem that is coupled to the first processing subsystem.

  In the first exemplary embodiment, an SD transfer sequence may be set for the first set of SD processing wafers. Real-time operational states for one or more first SD processing devices 112 in the first lithography subsystem 110 may be set. The operation state may be changed by loading / unloading the wafer into / from the S-D processing apparatus. The real-time transfer sequence may be set up and used to load / unload wafers to / from the first S-D processing apparatus 110 in the lithography related subsystem. In addition, an internal transfer device 113 may be used. An S-D transfer sequence may be set for the first set of S-D processing wafers. A real-time operational state may be set for one or more first SD processing devices 112 in the first lithography subsystem 110. The operation state may be changed by loading / unloading the wafer into / from the S-D processing apparatus. A real-time transport sequence may be set and may change over time. When the first number of first S-D processing devices are available, the first number of first set of SD processing wafers is the first in the first lithography subsystem 110 by using the SD transport subsystem. A number of first SD processing devices 112 may be conveyed. When the first number of first SD processing devices are not available for other SD wafers in the first set of SD processing wafers, the other SD wafers in the first set of SD processing wafers are By using the SD transport subsystem, the first period may be delayed. When the first set of SD processing wafers is transferred, a first SD transfer sequence may be used. For example, other S-D wafers in the first set of S-D processing wafers may be delayed for a first period by using one or more transfer devices in the S-D transfer subsystem. A transfer device may be provided to support two or more wafers. The other S-D wafers in the first set of S-D processing wafers may be processed after the first period. When the S-D wafer is delayed, a new S-D transfer sequence may be set.

  When a delayed unprocessed S-D wafer is identified, updated wafer status data for the delayed unprocessed S-D wafer may be determined. After the first grace period, updated operating state data for one or more SD processing devices in one or more processing subsystems may be determined and one or more newly available SD processing devices. May be identified by using updated operating state data. When newly available SD processing equipment is available, deferred unprocessed SD wafers can be processed one or more by using an SD transfer subsystem combined with one or more processing subsystems. It may be transported to the first newly available SD processor in the subsystem. When the first S-D processing equipment is not available, the first suspended unprocessed SD wafer may be suspended for a second period by using one or more SD transport subsystems coupled to the processing subsystem. . The postponed unprocessed SD wafer may be post-processed after the second period. Post-processing is the process of stopping the process, suspending the process, reevaluating one or more wafers, re-measuring one or more wafers, and re-inspecting one or more wafers. Reworking one or more wafers, storing one or more wafers, cleaning one or more wafers, removing one or more wafers, or a combination thereof good.

  One or more S-D wafers may be transferred to one or more S-D processing devices in one or more processing subsystems created by an S-D processing sequence for the wafer. In addition, one or more S-D wafers may be transferred using an S-D transfer sequence.

  In 725, one or more S-D wafers may be processed in one or more S-D processing apparatuses in one or more processing subsystems. The first SD process may be used to process the first unprocessed SD wafer. The first S-D process may include one or more process related processes. In alternative embodiments, one or more wafers may be processed in a non-S-D subsystem. For example, the first processing in the S-D processing sequence may be executed in the first processing subsystem, and the additional processing in the S-D processing sequence may be executed in the additional subsystem.

  When the first S-D verification process is performed, a first set of unverified SD verification sites may be generated on the first verification wafer, and the first set of unverified SD verification sites is the first The first site on the verification wafer may have a first unverified verification part.

  When an additional unprocessed SD wafer is identified, the additional unprocessed SD wafer may be processed using the first SD process. An additional first set of unverified S-D verification sites may be generated on the additional verification wafer. The additional first set of unverified S-D verification sites may have a first unverified verification site at a first site on each additional verification wafer.

  When a postponed unprocessed S-D wafer is identified, the postponed unprocessed S-D wafer may be processed later using the first SD process. An additional first set of unverified S-D verification sites may be generated on the deferred verification wafer. The additional first set of unverified S-D verification sites may have a first unverified verification site at a first site on each additional verification wafer. Alternatively, other unverified S-D processes may be performed by using additional unprocessed wafers.

  Continuing with the first exemplary embodiment, the first generation process may be performed when the first damascene layer is generated, and the second generation process is performed when the second damascene layer is generated. May be good. During the first generation process, a first number of first set of S-D processing wafers may be created by using the first damascene generation process and the first set of processed wafers may be identified. The first damascene generation process may be used to generate a first set of S-D damascene sites on a first number of first sets of S-D wafers. The first set of S-D damascene sites may have one or more verification sites at one or more sites on each of the first set of S-D processing wafers. During the second generation process, a first number of second sets of S-D processing wafers may be created by using a second damascene generation process, and a second set of processed wafers may be identified. The second damascene generation process may be used to generate a second set of S-D damascene sites on a first number of second sets of S-D wafers. The second set of S-D damascene sites may have one or more verification sites at one or more sites on each of the second set of S-D processing wafers. During and / or after the first generation process, a first set of SD evaluation wafers may be identified, and the first set of SD evaluation wafers includes one or more first sets of processed wafers. You can do it. In addition, during and / or after the first generation process, a first set of SD evaluation wafers may be identified, and the first set of SD evaluation wafers may be processed by one or more first sets. You may have a wafer.

  In 730, one or more processed S-D wafers may be transferred and / or suspended. In various embodiments, the processed SD wafer is a site verification, process verification, wafer verification, site verification, image verification, library verification, or process verification wafer, or a combination thereof. Good. When an SD evaluator is available, processed SD wafers are transferred to the SD evaluator in one or more evaluation subsystems by using an SD transfer subsystem that is coupled to one or more evaluation subsystems. May be good. When the S-D evaluation apparatus is not available, processed S-D wafers may be deferred by using an S-D transfer subsystem that is coupled to one or more evaluation subsystems.

  When a deferred S-D process wafer is identified, updated wafer status data for the deferred process wafer may be determined. After the first grace period, updated operating state data for one or more SD evaluation devices in one or more processing subsystems may be determined and one or more newly available SD evaluation devices. May be identified by using updated operating state data. When newly available SD evaluation equipment is available, deferred SD wafers can be evaluated one or more by using an SD transfer subsystem combined with one or more evaluation subsystems. It can be transported to the first newly available SD evaluation device in the subsystem. When the first S-D evaluation device is not available, the first suspended SD wafer to be processed is suspended for a second period by using one or more SD transfer subsystems coupled to the first processing subsystem. Good. The delayed processing target S-D wafer may be post-processed after the second period. Post-processing is the process of stopping the process, suspending the process, reevaluating one or more wafers, re-measuring one or more wafers, and re-inspecting one or more wafers. Reworking one or more wafers, storing one or more wafers, cleaning one or more wafers, removing one or more wafers, or a combination thereof good. One or more wafers may be deferred by using a transfer device in the SD transfer subsystem in one or more periods. The transfer device may include means for supporting two or more wafers.

  Continuing with the first exemplary embodiment, a second SD transport sequence may be set for each S-D wafer in the first set of evaluation wafers. A real-time operation state for one or more first S-D evaluation devices 152 in the evaluation subsystem 150 may be set. The operation state may be changed by loading / unloading the wafer into / from the S-D evaluation apparatus 152. The real-time transfer sequence may be set and used to load / unload a wafer to / from the first SD evaluation device 152 in the evaluation subsystem 150. In addition, the S-D evaluation device 137 in the inspection subsystem 135 may be used. When the first number of first S-D evaluation devices are available, the first number of first set of SD evaluation wafers are within the evaluation subsystem 150 by using the SD transfer subsystem (101, 102). To the first number of first S-D evaluation devices 152. When the first number of first SD evaluation devices is not available for other SD wafers in the first set of SD evaluation wafers, the other SD wafers in the first set of SD processing wafers are By using the SD transport subsystem, the second period may be delayed. For example, other SD wafers in the first set of SD processing wafers are suspended for a second period by using one or more transfer devices 104 in the SD transfer subsystem (101, 102). good. The transfer device 104 may be provided to support two or more wafers. The other S-D wafers in the first set of S-D processing wafers may be processed after the second period. A similar set of steps may be used when the S-D wafer requires processing for the second damascene layer. For example, the third and fourth transfer sequences may be used.

  At 735, a query may be performed to determine whether the wafer requires evaluation. When the wafer needs evaluation, the process 700 may branch to step 740. If the wafer does not require evaluation, process 700 may branch to step 745.

  In 740, one or more sites may be selected on one or more S-D wafers. In various embodiments, the site may be used in SD processing. The S-D process may include a site verification process, a part verification process, an image verification process, a library verification process, a process verification process, or a combination thereof. The site may be selected from a number of remaining sites on the S-D wafer. The site may have an associated unverified or verified site.

  In 745, one or more processed S-D wafers may be evaluated using data from one or more selected sites. For example, the first site is the most important site, and some verification decisions may be made using only the first site. Reliability data and / or risk assessment data may be used within the assessment process. For example, one or more confidence values for a selected site may be set by using the difference between unverified and verified data and one or more updated risk factors for SD processing May be set.

  In addition, updated confidence values can be set using additional reliability data from additional sites on one or more wafers, and all risk factors can be set from additional sites on one or more wafers. May be updated using additional reliability data. In other cases, verification decisions may be made by using confidence values and / or risk factors from one or more sites on one or more wafers. A confidence value may be determined for an unprocessed wafer, a processed wafer, or a deferred wafer, or a combination thereof.

  Continuing with the first exemplary embodiment, the first evaluation process may be performed when the first damascene layer is being evaluated, and the second evaluation process may be performed when the second damascene layer is being evaluated. Good to be executed. During the first evaluation process, one or more S-D first evaluation processes may be performed. The first number of first set of S-D evaluation wafers may be evaluated by using the first damascene evaluation process, and the first set of verified wafers may be identified. The first damascene evaluation process may be used to generate a first set of S-D damascene sites on a first number of first sets of S-D wafers. The first set of S-D damascene sites may have one or more verification sites at one or more sites on each of the first set of S-D evaluation wafers. During the second evaluation process, a first number of second sets of S-D evaluation wafers may be evaluated using a second damascene evaluation process, and a second set of verified wafers may be identified. The second damascene evaluation process may be used to generate a second set of S-D damascene sites on the first number of second sets of S-D wafers. The second set of S-D damascene sites may have one or more verification sites at one or more sites on each of the second set of S-D evaluation wafers.

  During and / or after the first evaluation process, a second set of S-D processes may be established, and the second set of S-D processes may include one or more first sets of verified wafers.

  In 745, a query may be performed to determine when additional S-D evaluation wafers are needed. When additional S-D evaluation wafers require processing, process 700 may branch to 740. When no additional S-D evaluation wafer is needed, process 700 may branch to 750.

  At 750, a query may be performed to determine when additional SD generation wafers are needed. The process 700 may branch to 720 when additional S-D generation wafers require processing. The process 700 may branch to 755 when no additional S-D generation wafer is required. In addition, additional verification data may be obtained from one or more sites on one or more additional S-D wafers. Additional confidence values may be set for additional sites on additional S-D wafers. Additional risk factors may also be set by using additional reliability data. Further, when verifying the S-D process, data from a postponed S-D wafer that has been processed thereafter may be evaluated.

  In 755, a query may be performed to determine when additional SD and / or non-S-D processing is required. When additional S-D and / or non-S-D processing is required, process 700 may branch to 715. The process 700 may branch to 760 when additional SD and / or non-SD processing is not required.

  In some multi-step examples, the lithography-related and / or scanner-related processing device may perform mask deposition processing, mask layer exposure processing, and / or development processing, and the SD evaluation device may perform mask deposition processing. , Mask layer exposure processing and / or development processing verification. The mask deposition process, mask layer exposure process, and / or development process may be SD and / or non-SD. In addition, one or more layers may be etched using an etching-related processing device, and the etched site may be evaluated by using one or more S-D evaluation devices.

  In other multi-step examples, dual damascene processing may be performed on one or more wafers. During the dual damascene process, a first damascene process may be performed followed by a second damascene process. In some embodiments, a via first trench last (VFTL) process may be performed. In some embodiments, trench first via last (TFVL) processing may be performed. The S-D measurement, inspection, verification, and / or evaluation process may be performed before, during, and / or after the damascene process. Alternatively, one or more non-S-D processes may be required instead. For example, the etched site on the first patterned damascene layer may be measured after a “via first” or “trench first” etch process is performed. One or more S-D data collection (DC) plans and / or S-D mapping applications may be used. Alternatively, different processing may be used instead.

  SD wafer thickness data and / or wafer temperature data is generated during lithographic processing, SD mask (photoresist) data generation, SD mask post-immersion cleaning and / or drying data generation, and SD mask development and / or baking. It can be used to generate data. In addition, the S-D wafer thickness data and / or wafer temperature data may be used by the etching subsystem 140 to generate S-D etching and / or ashing data. For example, the data may include etch chemistry data, etch time data, process gas ratio data, expected endpoint data, heater output data, and / or RF output data. In addition, the SD wafer thickness data and / or wafer temperature data may be used by the thermal processing subsystem 130 to generate SD heating and / or cooling data. The S-D wafer thickness data and / or wafer temperature data may be used by the inspection subsystem 135 to generate S-D inspection, verification, and / or examination data. In other examples, the S-D wafer thickness data and / or wafer temperature data may be used by the rework subsystem 155 to perform an S-D rework process.

  FIG. 8 shows another exemplary flow diagram for generating an S-D evaluation library. In the illustrated process 800, a number of steps are shown. Alternatively, a different number of steps and a different number of sequences may be used.

  At 810, one or more S-D wafers can be received by using one or more S-D transfer systems. Alternatively, one or more non-S-D wafers may be received. In addition, wafer data for one or more wafers may be received. Wafer data may include historical data and / or real-time data. Alternatively, the wafer may be received by a different subsystem.

  At 815, one or more S-D wafer data and / or non-S-D wafer data may be determined for one or more wafers that can be received by using one or more SD transport systems. The wafer data can be used to identify a set of S-D wafers and non-S-D wafers. In various embodiments, S-D wafer data associated with an S-D wafer may be S-D, chip-dependent, product-dependent, position-dependent, layer-dependent, wafer-dependent, or die-dependent, or a combination thereof. In addition, one or more SD processing sequences may be set for a wafer, and the SD processing sequence is set by using SD wafer data, chip-dependent wafer state data, and / or die-dependent wafer state data. May be good.

  In 820, one or more S-D wafers may be transferred to one or more S-D processing apparatuses by using an S-D transfer system.

  In 825, one or more processed S-D wafers may be generated. The processed S-D wafer may have one or more S-D library related sites on it. The one or more S-D library-related parts may be generated at one or more sites by using one or more S-D generation processes.

  At 830, a query may be executed to determine whether one or more S-D generation processes have been performed correctly. If one or more S-D generation processes are performed correctly, process 800 may branch to step 835. If one or more S-D generation processes are not performed correctly, process 800 may branch to step 880. For example, device data, chamber data, and / or failure data may be used.

  One or more sets of S-D evaluation wafers may be produced by using one or more sets of processed S-D wafers.

  In 835, one or more sets of S-D evaluation wafers may be transferred to one or more evaluation devices using an S-D transfer system. In addition, one or more other sets of S-D evaluation wafers may be suspended and / or stored by using the S-D transfer system.

  In 840, one or more S-D evaluation processes may be performed by using one or more S-D evaluation wafers transferred to one or more S-D evaluation apparatuses. In addition, by using one or more SD evaluation wafers that have been transferred to the one or more evaluation units when one or more evaluation units become available after the grace period, SD evaluation process may be executed.

  During some evaluation processes, the first reliability data for the first S-D evaluation wafer is set by evaluating the SD library-related parts at the first site on the first S-D evaluation wafer. good. The first reliability data for the first S-D evaluation wafer may be about one or more first reliability limits. Different levels of reliability may be associated with different reliability limits.

  When the first reliability limit is satisfied, the reference portion related to the first library may be certified as a highly reliable portion having the first level of reliability, and the first S-D evaluation wafer is the first one. The first library-related evaluation data related to the high-reliability part and the first S-D evaluation wafer may be certified as a high-reliability wafer having a level of reliability and stored in the SD evaluation library. good. High reliability sites and S-D evaluation wafers may have one or more reliability levels.

  At 845, a query may be executed to determine whether one or more S-D evaluation processes have been performed correctly. If one or more S-D evaluation processes are performed correctly, process 800 may branch to step 850. If one or more S-D evaluation processes are not performed correctly, the process 800 may branch to step 880. For example, device data, chamber data, and / or failure data may be used.

  At 850, one or more corrective actions can be performed when one or more reliability limits are not met.

  At 855, a query may be performed to determine whether additional evaluation wafers require evaluation. When an additional evaluation wafer requires evaluation, process 800 may branch to step 835. If the additional evaluation wafer does not require evaluation, the process 800 may branch to step 860.

  At 860, a query may be performed to determine whether additional production wafers are available for further processing. Process 800 may branch to step 810 when additional production wafers are available. If no additional production wafers are available, the process 800 may branch to step 870. Process 800 ends at 870.

  In some examples, the step of applying the corrective action may include the following steps. The following steps are a) a step of determining the maximum number of evaluation sites on the first S-D evaluation wafer, and b) a step of determining the minimum number of evaluation sites on the first S-D evaluation wafer. C) generating a first reliability map for the first S-D evaluation wafer, d) determining a required number of evaluation sites on the first S-D evaluation wafer, e) first S-D Selecting a new site on the D evaluation wafer; f) setting new reliability data for the first S-D evaluation wafer by using a new SD evaluation process, the first S- The process of evaluating SD library-related parts at a new site on the D wafer, g) The process of adding a new site to the new first reliability map for the first S-D evaluation wafer, h) New Comparing new reliability data with new reliability limits for the first S-D evaluation wafer, i) meeting the new first reliability limits When the first S-D evaluation wafer is identified, the SD library-related part of the new site on the first S-D evaluation wafer is recognized as a new high-reliability part having a new first level of reliability. Is recognized as a new high-reliability wafer having a new first-level reliability, and the first library-related evaluation data related to the new high-reliability part and the first S-D evaluation wafer is SD. Step of storing in the evaluation library, j) When the new first reliability limit is not satisfied, the SD library related part of the new site on the first S-D evaluation wafer is newly stored with new reliability data. A step of reducing the necessary number of sites by 1 and increasing the number of accessed sites by 1; k) When the required number of sites on the first S-D evaluation wafer is greater than 0 , Steps e) -j), and l) first S-D evaluation wafer When the required number on-site is equal to zero, step to stop the evaluation of the 1S-D evaluation wafer is.

  In another example, the step of applying the corrective action may include the following steps. The following steps include a1) a step of receiving an additional SD wafer by using an SD transfer system, and b1) an additional SD wafer to an additional first SD processing apparatus by using the first SD transfer system. C1) a step of generating one or more additional SD wafers to be processed, wherein one or more SD library-related parts are used for each additional SD target wafer by using the first S-D generation process. Steps generated at one or more sites above, d1) determining additional SD evaluation wafers by using additional processed SD wafers, e1) additional first S by using SD transport subsystem A step of transporting an additional SD wafer to the -D evaluation device; f1) a step of setting additional first reliability data for the additional SD evaluation wafer by using the additional first S-D evaluation process; The first size on the additional SD evaluation wafer G1) comparing the additional first reliability data with the additional first reliability data for the additional SD evaluation wafer, h1) the additional first reliability data. When the reliability limit is satisfied, the SD library-related part at the first site on the additional SD evaluation wafer is identified as an additional high-reliability part having an additional first level of reliability, and an additional SD evaluation is performed. Qualify the additional wafer as an additional high-reliability wafer with an additional first level of reliability and provide additional library-related evaluation data related to the additional high-reliability site and additional SD evaluation wafer Saving in the SD evaluation library; i1) applying the second correction action when the additional first reliability limit is not met.

  In addition, the step of applying the second correction act may include the following steps. The following steps are: a2) determining the maximum number of evaluation sites on the additional SD evaluation wafer, b2) determining the minimum number of evaluation sites on the additional SD evaluation wafer, c2 ) Generating a first reliability map for the additional SD evaluation wafer, d2) determining a required number of evaluation sites on the additional SD evaluation wafer, e2) on the additional SD evaluation wafer F2) using the additional new SD evaluation process to set new additional reliability data for the additional SD evaluation wafer, on the additional SD wafer. G2) adding new sites to the first reliability map for additional SD evaluation wafers, h2) new additional reliability data A new first for additional SD evaluation wafers I2) When the additional new first reliability limit is met, the SD site associated with the new site on the additional SD evaluation wafer is replaced with the additional new first level Recognize as an additional new high-reliability part with reliability, certify the first S-D evaluation wafer as an additional new high-reliability wafer with an additional new first level of reliability, and Storing new additional library-related evaluation data related to the additional new high-reliability site and additional SD evaluation wafer in the SD evaluation library, j2) additional new first reliability limit Is not satisfied, the SD library-related part of the new site on the additional SD evaluation wafer is recognized as an additional new unverified part having new reliability data, and the number of necessary sites is reduced by one, And the number of visited sites is 1 K2) When the number of necessary sites on the additional SD evaluation wafer is larger than 0, the steps e2) to j2) are repeated, and l2) The number of necessary sites on the additional SD evaluation wafer is zero. Is the step of stopping the evaluation of the additional SD evaluation wafer.

  In some examples, the first site may be one of the most important sites, and the determination may be based on results from first site data from one or more wafers.

  Data from SD and / or non-SD processes is used to determine when to change measurement, inspection, verification, and / or evaluation processes, new measurement, inspection, verification, and / or evaluation sites It ’s good. In addition, one or more new sites may be set when the confidence value is low in one or more regions of the wafer or when an error occurs. In addition, when the value on the reliability map is consistently high for a particular process and / or the accuracy value for a particular process is consistently within acceptable limits, a new measurement, inspection, verification, And / or an evaluation plan may be established. The plan can use fewer sites and reduce the throughput time for each wafer.

  In some cases, data for the entire wafer may be calculated during the SD process. Alternatively, data for a portion of the wafer may be calculated and / or predicted. For example, the portion may have one or more radial regions and / or quadrants. An error condition may be declared when one or more measured values and / or calculated / predicted values are outside the accuracy limits set for the wafer. Some errors can be resolved by using the SD system improvement process. Other errors can be resolved by the subsystem and / or controller.

  A portion of the wafer may have products with various confidence values. S-D processing can be used to obtain the maximum amount of product from an S-D wafer at many different stages in the product development cycle.

  Tolerances and / or tolerance limits associated with process results and / or other maps may be used to identify acceptable variability in one or more processes. In addition, process results and / or other maps may be used to set confidence data and / or risk factors for one or more processes in the process sequence. For example, process results and / or other maps may vary depending on the chamber cleaning process, and SD processing is used to improve and / or solve the “first wafer” problem that occurs after chamber cleaning. good.

  In some embodiments, the S-D data may include layer manufacturing information, and the layer manufacturing information may be different for different layers. New SD layer data is acquired during SD processing and used to update and / or optimize process recipes, used to update and / or optimize process models, and update and / or update profile data. Can be used to optimize. In addition, the SD process may send new SD layer data to other subsystems and / or controllers in the factory system. For example, new S-D data may include new wafer thickness and / or uniformity data.

  The S-D process may use information related to the state. Information related to the state includes, for example, a site ID, chip ID, die ID, product ID, subsystem ID, time, wafer ID, slot ID, lot ID, recipe, as means for configuring and numbering wafer data And / or the ID of the patterning structure.

  In addition to that, the SD modeling process includes wafer model, accuracy model, recipe model, optical property model, structure model, FDC model, prediction model, reliability model, measurement model, etching model, deposition model, first wafer effect model , Chamber models, equipment models, drift models, grace period models, electrical property models, or device models, or combinations thereof, may be generated, refined, and / or used.

  SD processing also includes history data, wafer data, accuracy data, process data, optical property data, structure data, FDC data, prediction data, reliability data, measurement data, etching data, chamber data, equipment data, drift data, electrical Characteristic data, device data, or a combination thereof may also be used.

  The S-D parameter may include SD layer information. S-D thickness data may be provided after lithographic processing. S-D processing can be used to send this information to the scanner subsystem. In addition, the thickness data can be provided after the deposition process, and the S-D process can be used to send this information to other subsystems. Wafer processing can be improved by feeding forward the S-D wafer data to the measurement and / or processing subsystem in real time. Material variations and / or process variations that may affect layer thickness may vary from site to site, from wafer to wafer, and from lot to lot. Thickness variations are believed to occur because the deposition process is not uniform across the wafer. This is believed to include chamber-to-chamber variation and chamber drift over time. Variations in thickness can cause variations in optical properties and / or variations in heat. S-D processing can be used to mitigate and / or eliminate these variations.

  The system and / or subsystem may have non-S-D and / or S-D data. Non-SD and / or SD data is setup data, configuration data, history data, input data, output data, priority data, grace data, failure data, response data, error data, feed forward data, feedback data, passing data, internal Data, external data, optimization data, status data, timing data, process result data, and / or measurement data may be included.

  In some embodiments, the S-D wafer data and / or wafer data may include bottom CD data, intermediate CD data, top CD data, or angle data, or a combination thereof. For example, the subsystem may have an etcher, and the etcher uses the new wafer and / or process state data that is SD to reduce the etch time when etching a deep trench on the wafer. The etching time for etching the dual damascene structure on the wafer may be determined, and the etching time for etching the gate structure on the wafer may be determined. In addition, the real-time processing data may have a calculated CD, a calculated depth, and / or a calculated sidewall angle.

  An S-D control application may be used to prevent the wafer from being transferred to the processing equipment until the processing equipment is ready to accept the wafer. An S-D control application may be used to prevent the S-D message maintenance and / or data from being sent until the recipient is ready to use the S-D message maintenance and / or data. S-D control applications can use grace period variables to grace wafers, calculations, processes, and / or measurements. For example, the grace period may be used to prevent the S-D data from reaching before it can be used by calculations, processes, and / or measurements on the wafer. The grace period may be determined by using wafer data, sequence data, control data, and / or history data. The grace period variable may be used by one or more controllers (114, 119, 124, 129, 134, 139, 144, 149, 154, and 159).

  In addition, these determinations and / or intervention rules may be performed when the determinations and / or intervention rules are associated with SD processing. Intervention and / or decision rules for the evaluation process and / or limits may be performed based on historical processing, device user experience, process knowledge, and may be obtained from the host computer. Rules may be used in S-D FDC processing to determine how to respond to warning, error, fault, and / or caution conditions. FDC SD processing prioritizes and / or classifies failures, predicts system performance, predicts preventive maintenance schedules, reduces maintenance downtime, and extends the service life of available methods in the system. Is possible.

  Depending on the nature of the warning / failure, the subsystem can take various actions depending on the warning / failure. The action taken for a warning / failure may be based on the situation. The situation may be SD, and the rules, system / process recipe, chamber type, identification number, loading port number, cassette number, lot number, control job ID, process job ID, slot number ID, and / or It may be specified by the data type.

  One or more S-D simulation applications may be used to calculate predictive data for the wafer based on input conditions, process characteristics, and process modes. The S-D metrology model can be used to predict and / or calculate smaller structures and / or sites associated with sub 65nm design nodes. For example, the prediction model may include a process chemical model, a chamber model, an EM model, an SPC chart, a PLS model, a PCA model, an FDC model, and a multivariate analysis (MVA) model.

  The reduction in the physical dimensions of the structure may require real-time S-D processing for most of the wafers to obtain more accurate data. In addition, some wafers may be used for verification of new S-D processes and / or evaluation of existing S-D processes. When a new S-D process is used and / or verified, the process results may vary and an evaluation or verification process may be performed on most wafers. When the evaluation or verification process is performed, the S-D process may be used.

  An S-D processing sequence may be executed and used to set when and how to use the evaluation site. The S-D processing sequence may be specified by a semiconductor manufacturer based on data stored in a history database. For example, the semiconductor manufacturer can select the number of positions on the wafer based on the history when performing SEM measurement, and the measurement data, inspection data, and / or evaluation data from one apparatus can be Correlate to data measured using a device, TEM device, and / or FIB device. In addition, the number of evaluation sites used can be reduced by the semiconductor manufacturer gaining confidence that the process continues to produce high quality products and / or devices.

  The evaluation / inspection / measurement process is time consuming and is thought to affect the throughput of the processing system. During processing, the manufacturer will want to minimize the time used for wafer generation and evaluation. S-D processing is considered to be performed depending on the state. Various S-D processes may be performed based on the state of the wafer. For example, one or more wafers may not be measured and / or inspected, and S-D processing may be performed using a subset of evaluation sites included in the evaluation plan.

  During development of a semiconductor process, SD and / or non-SD history data may be generated and stored for future use. S-D history data may include data at multiple sites.

  Simulation and / or prediction data may be generated and / or modified before, during and / or after execution of the process. The simulation and / or prediction data may include S-D and / or non-S-D data. New simulation and / or prediction data may be used in real time to update calculations, models, and / or results. In addition, reliability data for simulation and / or prediction data may be generated and / or modified before, during and / or after execution of the process.

  SD history data has GOF data, thermal data, thickness data, via related data, CD data, CD profile data, material related data, groove related data, sidewall angle data, differential width data, or a combination thereof. good. The data may also include, among other things, site result data, site number data, CD measurement flag data, measurement site number data, X coordinate data, and Y coordinate data.

  S-D processing can be used by subsystems to process 3D structures by adjusting recipes and / or models in real time. Examples of the three-dimensional structure include a memory structure, a dual damascene structure, a trench, a via, and a multi-gate structure. In addition, SD processing can be used by subsystems to evaluate, inspect, and / or measure 3D structures by adjusting evaluation, inspection, verification, and / or measurement recipes and / or models in real time. Can do. Three-dimensional structures can increase the S-D sensitivity of thickness variations and require modeling and / or measurement of the structure in multiple directions. The evaluation subsystem can cause throughput problems. Higher measurement throughput can be obtained by dynamically adjusting the sampling position and structure in the SD process.

  In an S-D semiconductor processing system, there are a plurality of processing and / or measurement apparatuses, and the compatibility of the apparatuses is considered to be an important problem. In some cases, data from internal devices must be compatible with data from external and / or reference devices. S-D processing can be used to fit data between devices and can be used to make calibration adjustments required by the subsystem. These adjustments may be made by R2R calculations.

  One or more S-D processes may be used to enable two-way communication for S-D data exchange and handshaking. The S-D process may query the subsystem, controller, and / or S-D process for the current state and settings. S-D processing may be used to interact with multiple devices in the subsystem by separating parameters unique to each device and supplying information to each device. For example, the S-D parameter may be sent to a control device, a processing device, a measurement device, an OES device, an RF sensor, a camera, an optical sensor, a CCD, an end point detector, a temperature sensor, and a depth sensor.

  When a wafer is processed within the subsystem by using SD data, the processed wafer is qualified as a processed SD wafer by changing the wafer status data for that wafer, and the processing data associated with the wafer. May be certified and / or stored as new SD processing data. When a wafer is processed in the subsystem by using non-SD data, the processed wafer is qualified as a processed non-SD wafer by modifying the wafer status data for that wafer and is associated with the wafer. The processing data may be authorized and / or stored as new non-SD processing data.

  The wafer data may include modeling data for the processed wafer that has been generated, refined, and / or modified in the subsystem. When S-D modeling data is used, new models and associated model parameters can be qualified and stored as S-D models and data. When non-S-D data is used, the model and associated model parameters may be qualified and stored as non-S-D models and data. For example, S-D models and data may be stored in S-D libraries and / or databases, and non-S-D models and data may be stored in non-S-D libraries and / or databases. When simulation is performed using S-D or non-S-D data, the simulation model and / or simulation data may be qualified and / or stored.

  The S-D process may generate, use, change, and / or verify wafer profile data. For example, with smaller dimensions, SD wafer profile data may have a greater impact during alignment, measurement, and / or processing, and wafer profile data may be radial data, curve data, site data. Temperature data and / or thickness data.

  In some subsystems, S-D and / or non-S-D wafer data may be used to determine contamination level, contamination probability, and / or outgassing rate. In other subsystems, the nozzle position during the deposition process and / or the probe position during the alignment and / or measurement process may be determined. The amount of energy released by the wafer in the chamber may be determined. For example, the optical elements, nozzles, and / or probes used may be position sensitive, point sensitive, site sensitive, and / or temperature sensitive. In addition, optical properties for the wafer and / or calibration factors for the optical properties may be determined. For example, the properties of the mask to be processed and / or the material layer may be determined.

  The system data may include wafer state information, point information, measurement information, vendor information, design information, chip layout information, library information, apparatus information, or survey information, or a combination thereof.

  In some embodiments, one or more subsystems may receive one or more wafers and / or associated wafer data. The subsystem may include multiple processing devices that process one or more wafers substantially simultaneously. For example, the inspection subsystem may include two or more inspection devices / modules that inspect one or more wafers substantially simultaneously. The control apparatus related to the subsystem may determine which wafer is processed by each processing apparatus by using the S-D processing sequence. Transfer devices inside and / or outside the subsystem may be used for wafer movement and / or storage. In addition, one or more processing devices in one or more subsystems may be used to process one or more wafers in non-real time. A current wafer is certified for each processing apparatus, wafer data is set for each wafer, and the wafer data may include real-time and / or historical wafer data. The processing sequence may include internal and / or external processing. For internal and / or external processing, the wafer may be sent to external measurement and / or processing equipment. Other wafers in the wafer lot may be sent to other subsystems or other IM devices.

  Yet another embodiment of the present invention provides a method for generating an S-D image library. The method is a step of acquiring a first S-D inspection image from a first S-D portion in and / or on a patterned mask layer, wherein the first S-D portion is located at a first predetermined site on a wafer. And the SD inspection subsystem generates a first S-D inspection image, calculates a first S-D simulation image corresponding to a virtual image of the first S-D region, SD inspection image and first S-D Calculating the first difference with the simulation image, comparing the first difference with the first S-D image generation criterion, and using the virtual image when the first S-D constructability criterion is satisfied. 1S-D site is identified and the first S-D inspection image and related site data are stored in the SD inspection image library, or the first corrective action is taken when the first S-D constructability standard is not satisfied The step of applying may be included.

  In some embodiments, the wafer may be processed by one or more lithography subsystems by using one or more SD processes, and the SD wafer thickness is generated in real time by one or more lithography subsystems. Good. The wafer may then be transferred to the etching subsystem. One or more lithography subsystems may send SD messages and / or data to the etching subsystem. The etch subsystem may receive and process the S-D message and extract S-D wafer thickness data. The etching subsystem may set the S-D etching data by using the S-D wafer thickness data. The S-D etching data may include an etching recipe, etching time, and / or etching chemicals. The etching subsystem may then etch the wafer using the S-D etching data. In addition, when the S-D layer thickness data is provided to the etching apparatus, the calculation time is reduced and the accuracy can be improved.

  Accuracy values may be determined for S-D or non-S-D processing and / or results. The accuracy value may be about the accuracy limit. If the accuracy value does not satisfy the accuracy limit, the refinement process may be performed. Alternatively, other processes may be performed, other sites may be used, or other wafers may be used.

  When the refinement process is used, the refinement process includes bilinear method, Lagrangian method, cubic spline method, Aitken method, weighted average method, multi-order method, bi-cubic method, Chulan method, wavelet Method, Bessel method, Everett method, finite difference method, Gauss method, Hermite method, Newton division difference method, contact method, seal method, or a combination thereof may be used.

  In some embodiments, completion time and / or execution time may be determined for SD and / or non-SD processing. To determine whether there is sufficient time to set up an updated recipe, the completion time and / or execution time may be comparable to the measurement and / or processing start time. If the completion time and / or execution time is shorter than the process start time, the wafer may be measured and / or processed using the updated measurement recipe. Alternatively, if the completion time and / or execution time is not shorter than the process start time, the wafer may be measured and / or processed using a measurement recipe that has not been updated.

  The S-D processing sequence may change over time. When the S-D processing sequence is created, the throughput is considered to be inferior to what is expected. This is because the confidence value for the new process decreases, the risk factor increases, and an additional measurement step is required to improve the confidence value and reduce the risk factor. Additional time is required when the wafer is measured separately and / or using an external measurement device.

  When an S-D system, subsystem, and / or process is being created, a stable S-D process may be created first, and then a stable S-D process may be optimized. S-D processing may be used during process stabilization, process improvement, and in process optimum vortices.

  During the stabilization sequence, one or more additional S-D measurement steps may be used to improve confidence values and / or reduce risk factors before the optimization sequence is established. The grace time may be used to wait for S-D data before process execution.

  One or more S-D measurements may be made prior to performing the etching process. Thereby, S-D data can be obtained for the patterned mask layer that can be used for comparison with the S-D data from the patterned etching layer. In addition, S-D measurements may be performed after the deposition process, and these S-D measurements may provide S-D thickness data, uniformity data, and / or optical property data. These data may be fed forward in real time as S-D data or history data. The S-D wafer data may be acquired from a processing apparatus, a measurement apparatus, an alignment apparatus, a transfer apparatus, an inspection apparatus, and / or a pattern recognition apparatus.

  In some manufacturing environments, SD processing provides SD data that was previously unavailable, provides faster processing, provides a more complete understanding of the process, replaces harmful methods, and provides higher confidence. Higher transfer speeds can be provided, uniformity can be improved, the number of dangerous wafers can be reduced, and a shorter reaction time can be provided for processing and / or equipment trajectories.

  As mentioned above, current manufacturing methods and factory designs used in integrated circuits are either provided as stand-alone platforms or grouped in most areas-usually over 2000 feet apart-many Requires equipment. Therefore, the equipment for operating these devices must be widely distributed throughout the factory. Typical functions required by these platforms are substrate coating (bonding, BARC, TARC, resist, top coating), baking (post-application baking, post-exposure baking), imaging (exposure), metrology (overlay, limit) Dimensions, defects, and film thickness), pre-exposure and post-exposure cleaning in an immersion process, etching (determining the pattern in the underlying thin film), and post-etch cleaning (removal of polymers and other by-products). Technologies aimed at gate lengths of less than 32 nm require repeating these operations until one active layer of a semiconductor device is completed--double BARC, double or triple patterning, or triple drawing, etc. . In order to move integrated circuits between these manufacturing “islands”, FOUPs are used to move ICs between separate platforms.

  Coating, baking, exposure, development, full inspection, etching, post-etch cleaning, wafer disposal, and wafer rework to improve processing speed and better manufacture 300mm, 450mm, or other diameter wafers The entire manufacturing process, including the ideal, can be completed within a single platform controlled by internal common control software. The one platform also has feed-forward and / or feedback APC (automatic processing control) for post-etch results associated with fairly early processing steps. APC is a post-etch CD (critical dimension), overlay, and defect information that is evaluated and feed forward (leading to future processing for the same wafer) data and / or feedback (current processing for the current wafer, (Or lead the current process for future wafers), allowing it to be acted on immediately.

  In addition, feed forward and / or feedback APC systems and associated SD transport subsystems may be used in conjunction with site specific methods. For example, the SD transport subsystem may be used to transport a wafer to a specific processing apparatus, and APC adjustments may be made for specific sites on the wafer. In addition, manufacturing processes and transfer sequences may be created based on site specific information collected from processes performed at specific sites on the wafer.

  In addition, the manufacturing process and transfer sequence can be impacted on FAB (manufacturing plant) usage by using “send ahead” wafers (ie, processing and evaluating one complete wafer before processing the lot). Can be created and completed with minimal. It is impossible to do this with conventional processes without significantly reducing FAB productivity. For example, by using an S-D transfer sequence, “forward” wafers are processed via etching and inspection, while the main lot is processed upstream. This allows the upstream manufacturing process to be adjusted while minimizing the impact on overall throughput.

  Thus, a wafer obtained from thin film processing enters one end of the platform, and a well-finished wafer exits the other end. In other words, the FOUP supplies a wafer for processing at one end and a new FOUP is received at the other end. In contrast to the manufacturing "island" system described above, an FOUP with an intermediate supply is no longer necessary after all wafers have been loaded into the photolithography system.

  To complete these necessary processing, the platform may have a number of modules. The numerous modules include all the necessary equipment to process the wafer from bonding to post-etch cleaning inspection. Each module is removable. No replacement is required to “reboot” the device. This helps repair and minimizes production time loss due to unplanned module level equipment problems. In addition, the basic block design with removable modules provides sufficient space for specialized sub-assemblies (modules) without long downtime and costly removal and re-installation of equipment. Allows additions or deletions.

  As the wafer moves between modules, the wafer may be managed by a robot on a rail type system. The robot used to move the wafer may have a balance system of double or triple tweezers that rotates on a central axis. These robots that move wafers between points may move on rails on either side of the scanner. It allows for all possible configurations of processing steps that achieve fast cycle times and improved process versatility. Thus, the “surface transfer” system allows the wafer to be easily transferred from IM after development to the start of a coating process or rework for multiple lithography (double patterning or lithography). Thereby, utilization of the exposure apparatus can be improved. In addition, multiple patterning is possible with a “surface transfer” system. Thereby, one wafer can be transferred from the IM after development to the input of the photolithography system for multiple lithography. If rework processing is available in the prelithographic part of the photolithography system, wafers that require rework may also be processed in this way. Thus, the wafer does not need to be re-loaded into the FOUP and does not need to be moved between devices by human or indirect automation. This reduces defects at the wafer level.

  As a result of using the rail system described above, the system does not need to sequentially process wafers. The modules that make up the entire process may be grouped to include one or more robots that provide the set of modules. In addition, lots do not have to wait for wafer rework or disposal. While good wafers can be processed at the end of the line, a “child lot” of reworked wafers can be generated and processed and catch up to the main lot after etching. This same idea can be used to select wafers to be discarded from the basic lot without delaying good wafers in the main lot. Reworking wafers that do not meet specifications can be quick and automatic. Thus, the overall manufacturing, inspection, and control functions can be built into a single device with common software. The common software controls and monitors output to adjust process inputs in real time.

  In one embodiment of the present invention, there is a module that includes all the equipment needed to process the wafer from bonding to post-etch cleaning inspection. The modules need not be arranged in order, as illustrated in FIG.

  As illustrated in FIG. 9, a wafer from a thin film process (or other upstream process) enters the first end and the verified completed wafer exits the other end. For example, modules 1 and 3 may have a resist spinner, a baking plate, and a pre-immersion cleaning process. Module 2 may have a “dirty” baking process that may contaminate the wafer. Thus, the present invention allows these “dirty” processes to be isolated from the rest of the equipment, thereby reducing defects and minimizing potential contamination. Atmospheric particle counters can be installed in the wafer path and critical processing areas to monitor ambient defect levels. Detection may serve to set warning conditions. Furthermore, a robot wafer handler may ride on a multi-rail system from the wafer entrance to the scanner found in module 4. The scanner may have its own internal wafer handler. Thus, the wafer may be transported to modules 5 and 6 for post-immersion cleaning, PEB, BWEE, and development after exposure by other robots on the multi-rail system. The wafer then goes to the IM module 7 (imaging module) for overlay, defect, and critical dimension checking.

  In this regard, if a wafer fails, the wafer may be reworked, and if it cannot be reworked, it may be discarded, articulated for double or triple patterning or single wafer “sidetrack” ”Is sent back through. Also, APC adjustment for the photolithography system PAB, PEB, scanner, or development process may be performed based on the measurement results at this point. However, APC adjustments and site-specific APC adjustments may also be made at any point in the process. For example, in the present invention, information about the wafer and a specific site on the wafer may be obtained from any step in the process, even if the IM module 7 is the first module to generate an image of the wafer. For example, a scanner found in module 4 may provide information regarding processes performed on the wafer or information regarding processes performed at a particular site on the wafer. Thus, APC adjustments can be made according to specific sites on the wafer and can be done using information from various sources in the process.

  In addition, the etching process may be performed within its own internal handler (module 8). Also included are post-etch cleaning equipment (module 9) and final IM equipment (module 10). The final IM has critical dimensions, defects, and overlay sites as needed. Good and bad wafers can be classified in this respect. A true complete APC may be implemented such that post-etch critical dimension data drives a resist photolithography system, PAB, PEB, exposure apparatus, or photolithography system developer recipe.

  Even if only certain exemplary embodiments of the present invention are described in detail, those skilled in the art will readily appreciate that many modifications are possible without departing substantially from the novel teachings and advantages of the present invention. to understand. Accordingly, it is understood that many such modified types are included within the technical scope of the present invention.

  Accordingly, this description does not limit the invention. The setup, operation, and behavior of the present invention are described with the understanding that modifications and variations of the embodiments are possible given the level of detail present herein. Accordingly, the foregoing detailed description is not intended to limit the invention in any way. The scope of the invention is defined by the claims, rather than by this detailed description.

Claims (47)

A method for processing a plurality of wafers comprising:
Receiving the plurality of wafers by a processing system, the processing system having site dependent (SD) and non-site dependent (NSD) subsystems, each wafer having associated wafer data, the wafer data Has SD reliability data and / or NSD reliability data;
Producing a first set of SD wafers using said SD reliability data and / or NSD reliability data;
Determining a first SD processing sequence for the first set of SD wafers, wherein the first set of SD wafers is used in the first SD subsystem by using the first SD processing sequence; Processed and wafer state data is used to set the first SD processing sequence; and
Transporting the first set of SD wafers to one or more first S-D processing devices in the first S-D subsystem, wherein the first S-D processing sequence is the one or more first S-D processing sequences. -D used to determine the processing equipment;
Having a method. Producing a first set of NSD wafers using said SD reliability data and / or NSD reliability data;
Determining a first SD processing sequence for the first set of NSD wafers, wherein the first set of NSD wafers is used in the first N-SD subsystem by using the first N-SD processing sequence; Processed and wafer state data is used to set the first N-SD processing sequence; and
Transporting the first set of NSD wafers to one or more first N-SD processing devices in the first N-SD subsystem, wherein the first N-SD processing sequence is the one or more first N-N processing sequences. -The process used to determine the SD processor;
The method of claim 1, further comprising: Producing another set of NSD wafers using the SD reliability data and / or NSD reliability data;
Determining another SD processing sequence for the other set of NSD wafers, wherein the other set of NSD wafers is processed in another NSD subsystem by using the other NSD processing sequence; Wafer state data is used to set the other NSD processing sequence; and
Transporting the other set of NSD wafers to one or more other NSD processing devices in the other NSD subsystem, wherein the other NSD processing sequence is the one or more other NSD processing devices. Used to determine the process;
The method of claim 2, further comprising: Producing another set of SD wafers using the SD reliability data and / or NSD reliability data;
Determining another SD processing sequence for the other set of SD wafers, wherein the other set of SD wafers is processed in another SD subsystem by using the other SD processing sequence; Wafer status data is used to set the other SD processing sequence; and
Transferring the other set of SD wafers to one or more other SD processing devices in the other SD subsystem, wherein the other SD processing sequence is the one or more other SD processing devices. Used to determine the process;
The method of claim 1, further comprising: Collecting first SD subsystem processing data before, during and / or after the first SD process sequence is performed by using the first set of SD wafers;
Setting first S-D reliability data for one or more wafers in the first set of SD wafers by using the wafer data and / or the first S-D subsystem processing data;
Creating an additional set of SD wafers by using the first S-D reliability data, the SD reliability data, or the NSD reliability data, or a combination thereof; and
Transferring the additional set of SD wafers to one or more additional SD processing devices in an additional subsystem, wherein an additional SD processing sequence is used to determine the one or more additional SD processing devices; A process;
The method of claim 1, further comprising: The step of setting the first S-D reliability data includes:
Setting a first S-D confidence value for a first S-D wafer in the first set of SD wafers by using the first S-D subsystem processing data;
Comparing a first S-D confidence value for the first S-D wafer with a first S-D confidence limit; and
Continuing the processing of the first set of SD wafers when the first SD confidence limit is met, or applying a first SD correction action when the first SD confidence limit is not met;
6. The method according to claim 5, comprising: The step of applying the first S-D correction act is:
A setting step of setting SD confidence values for one or more additional wafers in the first set of SD wafers by using the first S-D subsystem processing data;
Comparing the SD confidence value for the one or more additional wafers with an additional first SD confidence limit; and
Continue processing the first set of SD wafers when the additional first S-D confidence limit is met, or cancel the setting step and the comparison step when the additional first S-D confidence limit is not met. The step of:
The method of claim 6, comprising: Collecting first N-SD subsystem processing data before, during and / or after the first N-SD processing sequence is performed by using the first set of NSD wafers;
Setting first N-SD reliability data for one or more wafers in the first set of NSD wafers by using the wafer data and / or the first N-SD subsystem processing data;
Creating an additional set of NSD wafers by using the first N-SD reliability data, the SD reliability data, or the NSD reliability data, or a combination thereof; and
Transferring the additional set of NSD wafers to one or more additional NSD processing units in an additional subsystem, wherein an additional NSD processing sequence is used to determine the one or more additional NSD processing units A process;
The method of claim 2, further comprising: The step of setting the first NSD reliability data is as follows:
Setting a first N-SD confidence value for a first N-SD wafer in the first set of NSD wafers by using the first NSD subsystem processing data;
Comparing a first N-SD confidence value for the first N-SD wafer to a first N-SD confidence limit; and
Continuing the processing of the first set of NSD wafers when the first N-SD confidence limit is met, or applying a first N-SD correction action when the first N-SD confidence limit is not met;
9. The method of claim 8, comprising: The step of applying the first N-SD correction act is:
Setting the NSD confidence value for one or more additional wafers in the first set of NSD wafers by using the first N-SD subsystem processing data;
Comparing the NSD confidence value for the one or more additional wafers with an additional first N-SD confidence limit; and
Continue processing the first set of NSD wafers when the additional first N-SD confidence limit is met, or stop the setting and comparing steps when the additional first N-SD confidence limit is not met The step of:
The method of claim 9, comprising: Collecting other NSD subsystem processing data before, during, and / or after the other NSD processing sequence is performed by using the other set of NSD wafers;
Setting other NSD reliability data for one or more wafers in the other set of NSD wafers by using the wafer data and / or the other NSD subsystem processing data;
Creating an additional set of NSD wafers by using the other NSD reliability data, the SD reliability data, or the NSD reliability data, or a combination thereof; and
Transferring the additional set of NSD wafers to one or more additional NSD processing units in an additional subsystem, wherein an additional NSD processing sequence is used to determine the one or more additional NSD processing units A process;
The method of claim 3, further comprising: The steps for setting the other NSD reliability data include:
Setting a first N-SD confidence value for a first N-SD wafer in the other set of NSD wafers by using the other NSD subsystem processing data;
Comparing a first N-SD confidence value for the first N-SD wafer to a first N-SD confidence limit; and
Continuing the processing of the first set of NSD wafers when the first N-SD confidence limit is met, or applying a first N-SD correction action when the first N-SD confidence limit is not met;
The method of claim 11, comprising: The step of applying the first N-SD correction act is:
Setting the NSD confidence value for one or more additional wafers in the other set of NSD wafers by using the other NSD subsystem processing data;
Comparing the NSD confidence value for the one or more additional wafers with an additional first N-SD confidence limit; and
Continue processing the first set of NSD wafers when the additional first N-SD confidence limit is met, or stop the setting and comparing steps when the additional first N-SD confidence limit is not met The step of:
13. The method of claim 12, comprising: Collecting other SD subsystem processing data before, during, and / or after the other SD processing sequence is performed by using the other set of SD wafers;
Setting other SD reliability data for one or more wafers in the other set of SD wafers by using the wafer data and / or the other SD subsystem processing data;
Creating an additional set of SD wafers by using the other SD reliability data, the SD reliability data, or the NSD reliability data, or a combination thereof; and
Transferring the additional set of SD wafers to one or more additional SD processing devices in an additional subsystem, wherein an additional SD processing sequence is used to determine the one or more additional SD processing devices; A process;
5. The method of claim 4, further comprising: The other SD reliability data setting steps include:
Setting a first S-D confidence value for a first S-D wafer in the other set of SD wafers by using the other SD subsystem processing data;
Comparing a first N-SD confidence value for the first S-D wafer with a first S-D confidence limit; and
Continuing the processing of the first set of SD wafers when the first SD confidence limit is met, or applying a first SD correction action when the first SD confidence limit is not met;
15. The method of claim 14, comprising: The step of applying the first S-D correction act is:
Setting the SD confidence value for one or more additional wafers in the other set of SD wafers by using the other SD subsystem processing data;
Comparing the SD confidence value for the one or more additional wafers with an additional first SD confidence limit; and
Continue processing the first set of SD wafers when the additional first S-D confidence limit is met, or cancel the setting step and the comparison step when the additional first S-D confidence limit is not met. The step of:
16. The method according to claim 15, comprising:   The first S-D processing sequence includes one or more coating processes, one or more etching processes, one or more heat treatments, one or more exposure processes, one or more oxidation processes, one or more nitriding processes, One or more development processes, one or more lithography processes, one or more scanner related processes, one or more measurement processes, one or more inspection processes, one or more evaluation processes, one or more simulation processes, One or more prediction processes, one or more rework processes, one or more storage processes, one or more transport processes, one or more load lock processes, or one or more cleaning processes, or a combination of these 2. The method of claim 1, comprising at least one of them.   The first S-D subsystem comprises one or more coating subsystems, one or more etching subsystems, one or more thermal subsystems, one or more exposure subsystems, one or more oxidation subsystems, 1 One or more nitriding subsystems, one or more development subsystems, one or more lithography subsystems, one or more scanner related subsystems, one or more measurement subsystems, one or more inspection subsystems, one More than one evaluation subsystem, one or more simulation subsystems, one or more prediction subsystems, one or more rework subsystems, one or more storage subsystems, one or more transport subsystems, one or more The method of claim 1, comprising at least one of a plurality of load lock subsystems, or one or more cleaning subsystems, or a combination thereof.   The first S-D processing apparatus includes one or more coating processing apparatuses, one or more etching processing apparatuses, one or more heat treatment apparatuses, one or more exposure processing apparatuses, one or more oxidation processing apparatuses, and one More than one nitriding device, more than one development processing device, more than one lithography processing device, more than one scanner related processing device, more than one measurement processing device, more than one inspection processing device, more than one Evaluation processing device, one or more simulation processing devices, one or more prediction processing devices, one or more rework processing devices, one or more storage processing devices, one or more transport processing devices, one or more The method according to claim 1, comprising at least one of a load lock processing device, or one or more cleaning processing devices, or a combination thereof.   The plurality of wafers includes at least one of a semiconductor material, a carbon material, a dielectric material, a glass material, a ceramic material, a metal material, an oxide material, a mask material, or a planarizing material, or a combination thereof. Item 2. The method according to Item 1. A method for processing a plurality of wafers comprising:
Receiving the plurality of wafers by a non-site dependent transport subsystem in a processing system, the processing system having a site dependent (SD) and a non site dependent (NSD) subsystem, each wafer being associated Having wafer data, the wafer data having SD reliability data and / or NSD reliability data, and at least one wafer having one or more evaluation structures thereon;
A step of producing a first set of SD measurement wafers using the SD reliability data and / or NSD reliability data, each wafer of the first set of SD measurement wafers having one or more wafers thereon; A process having an evaluation structure, wherein the first set of SD measurement wafers is transferred from the NSD transfer subsystem to the SD transfer subsystem;
Determining a first S-D measurement process for the first set of SD measurement wafers, wherein the first set of SD measurement wafers uses the first S-D measurement process to determine the first S-D measurement process; A process that is processed in a -D measurement subsystem and wherein the wafer data is used to set up the first S-D measurement process;
Transferring the first set of SD measurement wafers to one or more first S-D measurement related devices in the first S-D subsystem by using the SD transfer subsystem; A -D transport sequence, a first S-D processing sequence, or a first S-D measurement sequence, or a combination thereof, is used to determine the one or more first S-D measurement related devices; and
Performing the first S-D measurement process;
Having a method. The steps of performing the first S-D measurement process are:
Selecting a first measurement wafer from the first set of SD measurement wafers, wherein the first measurement wafer has a first S-D evaluation portion thereon;
Obtaining first measurement data having first S-D measurement signal data from the SD evaluation site;
Selecting a first S-D best estimate signal and an associated first S-D best estimate structure from a library of SD measurement signals and associated structures;
Calculating a first S-D difference between the first S-D measurement signal data and the first S-D best estimate signal data;
Setting first S-D reliability data for the first measurement wafer by using the first S-D difference;
Comparing the first S-D reliability data to a first S-D product requirement; and
When one or more of the first S-D product requirements are met, the first measurement wafer is certified as a first high-reliability wafer and the process is continued, or one of the first S-D product requirements Applying the first corrective action when the above are not satisfied;
The method of claim 21, comprising:   When one or more of the first S-D product requirements are met, the first S-D best estimation structure and the associated first S-D best estimation signal data are used to determine the first S-D evaluation site. 23. The method of claim 22, further comprising the step of qualifying. The step of applying the first correction act includes:
Selecting a new SD best estimate signal and an associated new SD best estimate structure from a library of SD diffraction signals and related structures;
Calculating a new SD difference between the new SD measurement signal data and the new SD best estimate signal data;
A setting step of setting new SD reliability data for the first measurement wafer by using the new SD difference;
A comparison step of comparing the new SD reliability data with new SD product requirements; and
When one or more of the new SD product requirements are met, the first measurement wafer is certified as a new high-reliability wafer and the process is continued, or one or more of the new SD product requirements If not satisfied, the selection step, the calculation step, the setting step, the comparison step, and the step of canceling the authorization;
23. The method of claim 22, comprising:   When the first S-D profile library generation criterion is satisfied, the step of certifying the first S-D evaluation site by using the new SD best estimation structure and the related new SD best estimation signal data is further included. 25. The method of claim 24, comprising: The steps of performing the first S-D measurement process are:
Selecting a second measurement wafer from the first set of SD measurement wafers, wherein the second measurement wafer has the first S-D evaluation portion thereon;
Obtaining second measurement data having second S-D measurement signal data from the SD evaluation site;
Selecting a second S-D best estimate signal and a related second S-D best estimate structure from the SD measurement signal and related structure library, or from the SD diffraction signal and related structure library;
Calculating a second S-D difference between the second S-D measurement signal data and the second S-D best estimate signal data;
Setting second S-D reliability data for the second measurement wafer by using the second S-D difference;
Comparing the second S-D reliability data with a second S-D product requirement; and
When one or more of the second S-D product requirements are met, the second measurement wafer is certified as a second high-reliability wafer and the process is continued, or one of the second S-D product requirements Applying the second corrective action when the above are not satisfied;
23. The method of claim 22, comprising:   When one or more of the second S-D product requirements are met, the second S-D best estimation structure and the associated second S-D best estimation signal data are used to determine the first S-D evaluation site. 27. The method of claim 26, further comprising the step of qualifying. The step of applying the second correction act includes:
A selection step of selecting a new second S-D best estimate signal and a related new second S-D best estimate structure from the SD diffraction signal and related structure library, or from the SD diffraction signal and related structure library;
A calculating step of calculating a new second S-D difference between the new second S-D measurement signal data and the new second S-D best estimate signal data;
A setting step of setting new second S-D reliability data for the first measurement wafer by using the new second S-D difference;
A comparing step of comparing the new second S-D reliability data with the new second S-D product requirements; and
When one or more of the new second S-D product requirements are met, the second measurement wafer is certified as a new second high-reliability wafer and the process is continued, or the new second S -D when one or more of the product requirements are not met, the selecting step, the calculating step, the setting step, the comparing step, and the step of canceling the certification;
23. The method of claim 22, comprising:   When the new second S-D profile library generation criteria are met, the first second S-D best estimation signal data is used by using the new second S-D best estimation structure and the associated new second S-D best estimation signal data. 30. The method of claim 28, further comprising the step of qualifying the site for evaluation.   The step of applying the second correction act is a step of re-inspecting the first measurement wafer, the second measurement wafer, the first set of SD measurement wafers, or a combination thereof, and re-inspecting. 29. The method of claim 28, comprising the steps of: reworking, storing, washing, and / or removing. The steps of performing the first S-D measurement process are:
Selecting a second S-D evaluation site on the first SD measurement wafer;
Obtaining second measurement data having second S-D measurement signal data from the second S-D evaluation site;
Selecting a second S-D best estimate signal and a related second S-D best estimate structure from the SD measurement signal and a library of related structures;
Calculating a second S-D difference between the second S-D measurement signal data and the second S-D best estimate signal data;
Setting second S-D reliability data for the first measurement wafer by using the second S-D difference;
Comparing the second S-D reliability data with a second S-D product requirement; and
When one or more of the second S-D product requirements are met, the first measurement wafer is certified as a second high-reliability wafer and the process is continued, or one of the second S-D product requirements Applying the second corrective action when the above are not satisfied;
23. The method of claim 22, comprising: The steps of performing the second S-D measurement process are:
Selecting a third SD evaluation site on the first SD measurement wafer;
Obtaining third measurement data having third S-D measurement signal data from the third S-D evaluation site;
A selection step of selecting a third S-D best estimate signal and a related third S-D best estimate structure from a library of SD measurement signals and related structures, or a library of SD diffraction signals and related structures;
A calculating step of calculating a third S-D difference between the third S-D measurement signal data and the third S-D best estimated signal data;
A setting step of setting third S-D reliability data for the first measurement wafer by using the third S-D difference;
A comparing step of comparing the third S-D reliability data with a third S-D product requirement; and
When one or more of the third S-D product requirements are met, the first measurement wafer is certified as a third high-reliability wafer and the process is continued, or one of the third S-D product requirements When the above is not satisfied, the selection step, the calculation step, the setting step, the comparison step, and the step of canceling the authorization;
The method of claim 21, comprising: The steps of performing the first S-D measurement process are:
Selecting a second measurement wafer having a second S-D evaluation portion thereon;
Obtaining second measurement data having second S-D measurement signal data from the second S-D evaluation site;
Selecting a second S-D best estimate signal and a related second S-D best estimate structure from the SD measurement signal and a library of related structures;
Calculating a second S-D difference between the second S-D measurement signal data and the second S-D best estimate signal data;
Setting second S-D reliability data for the second measurement wafer by using the second S-D difference;
Comparing the second S-D reliability data with a second S-D product requirement; and
When one or more of the second S-D product requirements are met, the second measurement wafer is certified as a second high-reliability wafer and the process is continued, or one of the second S-D product requirements Applying the second corrective action when the above are not satisfied;
23. The method of claim 22, comprising: The step of applying the second correction act includes:
Selecting a new second S-D best estimate signal data and a related new second S-D best estimate structure from the SD measurement data and a library of related structures;
A calculating step of calculating a new second SD difference between the second measurement signal data and the new second SD best estimated signal data;
A setting step of setting new second S-D reliability data for the second measurement wafer by using the new second S-D difference;
A comparing step of comparing the new second S-D reliability data with the new second S-D product requirements; and
When one or more of the new second S-D product requirements are met, the second measurement wafer is certified as a new second high-reliability wafer and the process is continued, or the new second S -D when one or more of the product requirements are not met, the selecting step, the calculating step, the setting step, the comparing step, and the step of canceling the certification;
24. The method of claim 23, comprising:   The step of applying the first correction act is a step of re-measuring one or more of the first set of measurement wafers, a step of re-inspection, a step of re-processing, a step of storing, a step of washing, 23. The method of claim 22, comprising: and / or removing. The step of applying the first correction act includes:
From the SD measurement signal and the related structure library, or from the new profile space existing outside the profile space related to the SD diffraction signal and the related structure library, the first S-D calculated evaluation structure and the related Generating the first S-D calculated signal data;
Determining a first S-D calculated difference between the first measurement signal data and the first S-D calculated signal data;
Setting first S-D calculated reliability data for the first measurement wafer by using the first S-D calculated difference;
Comparing the first S-D calculated reliability data to a first S-D profile library generation criterion; and
When the one or more first S-D profile library generation criteria are satisfied, the first measurement wafer is certified as a first calculated high-reliability wafer and the process is continued, or the one or more first S-D profile library generation criteria are satisfied. Applying the second corrective action when the first S-D profile library generation criteria are not satisfied;
23. The method of claim 22, comprising: Change height, width, thickness, depth, volume, area, angle, dielectric properties, process recipe parameters, processing time, critical dimensions, spacing, duration, position, or line width, or a combination of two or more of the above Generating a new SD calculated evaluation structure and associated new SD calculated signal data by:
A determining step of determining a new SD calculated difference between the first measurement signal and the new SD calculated signal data;
A setting step of setting new SD calculated reliability data for the first measurement wafer by using the new SD calculated difference;
Comparing the new SD calculated reliability data with a new SD profile library generation criteria; and
When one or more of the new SD profile library generation criteria are satisfied, the first measurement wafer is certified as a new calculated high-reliability wafer and the processing is continued, or the new SD profile library When one or more of the generation criteria are not satisfied, the generation step, the determination step, the setting step, the comparison step, and the step of canceling the authorization;
40. The method of claim 36, further comprising:   The evaluation structure calculated in the first S-D and the related first S-D calculated signal data are stored in the SD measurement signal and the related structure library, or the SD diffraction signal library. 40. The method of claim 36, further comprising the step.   When the first S-D profile library generation criteria are satisfied, the first S-D evaluation site is identified by using the first S-D calculated evaluation structure and the related first calculated signal data 40. The method of claim 36, further comprising the step of: The step of applying the first correction act includes:
Determining a first outer data point within a first S-D profile data space existing outside a data space associated with the SD profile library, the first outer SD signal data, the first outer SD profile data, 1 outer SD profile parameter data, or the combination is associated with the first outer data point;
Calculating a first outer SD difference between the first S-D measurement signal data and the first outer SD signal data;
A setting step of setting first outer SD reliability data for the first measurement wafer by using the first outer SD difference;
Comparing the first outer SD reliability data with a first outer SD product requirement; and
When one or more of the first outer SD product requirements are met, the first measurement wafer is qualified as an outer reliable wafer and the process is continued, or one or more of the first outer SD product requirements Applying the second corrective action when is not satisfied;
23. The method of claim 22, further comprising:   The method of claim 40, further comprising qualifying the first SD evaluation site by using data associated with the first outer data point when one or more of the first outer SD product requirements are met. The method described. The continuing process includes:
A comparing step of comparing the first SD difference with a first accuracy requirement; and
When one or more of the first accuracy requirements are met, the first set of inspection wafers is certified as a first high-reliability wafer and the process is continued, or one or more of the first accuracy requirements are met If not, applying additional corrective action;
23. The method of claim 22, comprising: A platform for processing wafers:
A plurality of processing modules each having an apparatus for processing the wafer based on processing data;
At least one robot arranged to transfer wafers between the modules and moving on rails on the surface of the modules;
At least one inspection module configured to inspect a completed process on the wafer in the processing module;
A common control unit that controls and receives wafer data from the module, the at least one robot, and the at least one inspection module, and adjusts data within the plurality of processing modules based on the received data ;
A wafer processing platform.   44. The wafer processing platform of claim 43, wherein the wafer data comprises site specific wafer data.   44. The wafer processing platform according to claim 43, wherein the processing data is based on a manufacturing process created for the wafer.   46. The wafer processing platform of claim 45, wherein the manufacturing process is adjusted to respond according to the adjustment of the process data.   47. The wafer processing platform of claim 46, wherein the wafer is a forward wafer used to update the manufacturing process before many wafers are processed by the wafer processing platform.

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