JP5187804B2 - Vertical / horizontal processor - Google Patents

Description

  The present invention provides a novel vertical and horizontal processor (or simply referred to as “vertical processor”) that follows the principle of operation of a neural network, a modified virtual source neural network model that includes the vertical and horizontal processor, and the vertical and horizontal processor. The present invention relates to a processor learning method for learning a single vertical / horizontal processor of a horizontal processor.

  In an arbitrary sequential (sequential type) processor, even if the processor is a teraflop type, each bit is processed one by one. However, in the brain process, thousands of bits are processed at a time, even if it is slow. Several models have been created to mimic the nervous system through software, and many experimental configurations have been proposed that mimic the nature of neural activity. One example is to create an ion channel (see, for example, US Pat. No. 6,057,836) and to incorporate a threshold potential in the response to create a neural modeling device. Neurons are designed using capacitors and floating gate transistors (see, for example, Patent Document 2) and have been analyzed using equivalent neural network models. A physical neural network having a plurality of signal inputs and outputs for enhancing or weakening connectivity has also been realized (see, for example, Patent Document 3). Apart from designing neurons, many models have been created to analyze random networks. However, none of these models has proposed a configuration that can imitate the basic functions of the nervous system with a solid-state device.

  Neural systems that follow these models use electronic components that generate significant heat during information processing and therefore cannot be minimized to nanoscale dimensions. The introduction of molecular electronics creates the concept of a multilayer perceptron using a DNA oligomer (for example, see Patent Document 4), or generates a random path on an information processing surface through a switching molecule (for example, see Patent Document 5). It deals with the basic problems of nanoscale calculations. Most of these random neural networks can operate by constructing a decision function (for example, see Patent Document 6) that mainly applies the principle of operation of our brain (for example, see Patent Document 7). Become. Although there are several proposals for intelligent control of machines (see, for example, Patent Document 8), the basic problem of signal transmission from neuron to neuron is eventually destroyed by the failure of any system unit. It is to develop a sequential connection (sequential connection). There are some projects that somehow attempt to overcome sequentiality with fuzzy logic, but compromise individual control over the final output signal. One such example is a project nanocell (see, for example, Non-Patent Document 5).

  The problem of integrating molecules into a physical probe is that when creating nanocells (see, for example, Non-Patent Documents 2 to 4), the overall response of a randomly oriented switch is taken as the behavior of a logic gate, eg, a NAND gate, It is solved by learning. The major change of nanocells with other models was to avoid single molecule wiring, which depends on conformational changes. Therefore, such changes may not be reliable in integrated circuits. Therefore, the critical dimension problem was solved by intelligent logic of the fuzzy system. As with nanocells, many models have been created until the day of logicalizing a fuzzy system through several neural modeling devices, and devices that process ANN logic have also been designed. Nanocells differ only in that they have proposed an alternative method of handling molecular electronics with a processor.

Although nanocells have been realized, this has some limitations apart from dimensional requirements. When a particular region stops changing the overall logic pattern, signal input and output are taken at two different ends on the same plane. This signal input / output is susceptible to noise. Such changes (in the input sequence) are only considered if changes in the input signal sequence significantly change the final signal output. Also, different arrangements may be able to finish with the same signal output. The number of signal outputs and the number of signal inputs complement each other within a certain calculation area. As the number of signal inputs increases, the number of signal outputs decreases. The switches work randomly in an absolutely unpredictable way, and the role of individual smart systems or switches or neurons is not considered or necessary. In nanocells, we are only interested in the final change in signal output current. Different signal inputs may cause current to flow in different paths, so that ultimately the same signal output is obtained. Thus, physically, this interacting surface is a black box that supplies different sets of current outputs for different sets of input voltages. This surface may be modeled as an electrode array in which nonlinear electronic components are randomly connected. The switches and paths are non-linear generators.
Nowadays, nanocell applications are realized or proposed in different modes and systems (see, for example, Non-Patent Document 6), so we call all similar systems nanocell systems. Yes.

U.S. 5,378,342 U.S. 5,343,555 U.S.6,889,216 B2 U.S. 6,741,956 B1 U.S.6,820,244 B2 U.S.6,886,008 B2 U.S. 4,954,963 U.S.6.882,992 B1

J. Hopfield, Neural networks and physical systems with emergent collective computational abilities, 79Proc, Nati. Acad. Of Sci. USA 2554 (1982). Summer M. Husband, Programming in Nanocell a random array of molecules, available at http://www.caam.rice.edu/caam/trs/2002/TR02-04.pdf ), Rice University PhD thesis April 2002. Christopher P. Husband, Summer M. Husband, Jonathan S. Daniels, and James M. Tour, Logic and Memory With Nanocell Circuits, IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL.50, No.9 , SEPTEMBER 2003 pp-1865. James M. Tour, William L. Van Zandt, Christopher P. Husband, Summer M. Husband, Lauren S, Wilson, Paul D. Franzon, and David P. Nackashi, Nanocell Logic Gates for Molecular Computing (Nanocells for Molecular Computing) Logic gate), IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL.1, NO.2, JUNE 2002 pp-100. Nanocell project proposals available at http://www.eng.yale.edu/reedlab/protected/proposals/nanocell-full-proposal.pdf. NJ Wu, H. Lee, Y. Amemiya, H. Yasunaga, Methods for determining weight co-efficients for Quantum Boltzman Machine neuron devices, Jpn JAP, 38, 439 (1999). Supriyo Datta, Magnus Paulsson, Ferdows Zahid, Electrical Conduction through Molecules available at http://www.nanohub.org/com.docman/task,down/bid,84/.

  The object of the present invention is to provide a realistic neural model (a set of rules or rules) and a device (processor) that can operate based on the brain operating principle, taking into account the proposed neural model. It is to make up as. Devices based on these principles have a wider range of industrial applications because of faster data processing and higher reliability, and are versatile because they are based on multi-level information processing. Can be freely modified along with system requirements. Until now, it has not been known to process an entirely different kind of information and make decisions at the same time. No model or device that can process more than one bit at a time in a single unit, in principle or practically exists (a supercomputer has several such units in parallel. Neither model survives decision making under the death or noise of fundamental elements like the brain. Our ultimate goal is to provide all these features in a single information processing system.

[Summary of the Invention]
The inventors of the present invention have come up with a 3D multi-bit vertical horizontal processor based on the principle of neuron collective calculation in the brain, and have completed the present invention. That is, the present invention relates to the following vertical horizontal processor, a cluster having the vertical horizontal processor, a modified virtual source neural network model, and a processor learning method using the vertical horizontal processor or the cluster.
First, the present invention provides a plurality of input signals horizontally from any direction on the surface in the center of the surrounding electrode and containing the multilevel system or neuron, and on the surface Provides a vertical and horizontal processor (also referred to as a “standard vertical horizontal processor”) that includes a pair of templates whose output signals are taken vertically at various points.
In this specification, since the signal input and signal output are perpendicular to each other, we will refer to this processor as a “vertical horizontal processor”, or simply “vertical processor” (see FIGS. 1 and 6). The surface of the template on which the multi-level system is located is called an information processing surface. A system that exhibits multilevel conductivity, ie, more than one conductivity at a particular bias, is called a multilevel system or neuron.

Second, the present invention provides a (standard) vertical horizontal processor, a neural node controller, and
A cluster (see FIG. 18) with connection switch sensors connected in the following A, B, and C manner is provided.
A. A part or all of the signal input of the vertical horizontal processor is connected to the array of vertical processors, and the remaining signal input is connected to the signal output of the sensor, which is a free signal input of the entire system;
B. A part of the signal output unit is connected to some of the signal output switches, and the remaining signal output unit is connected to another vertical processor;
C. All free signal outputs are connected to the switch and not connected to any signal inputs in the entire system, but taken vertically as the final cluster signal output.
As used herein, “cluster” means a system comprising a small number of processors, neural node controllers, connections, switches, and input signal converter arrays.

Third, the present invention comprises any one of the vertical and horizontal processors described above, and a modified virtual source neural network model (see FIG. 11) in which the modification includes all of the following A, B, C: For reference).
A. Replace old-concept binary neurons (with values of 0 or 1) or continuum neurons (any value between 0 and 1) with multi-level systems or neurons (selected values between 0 and 1).
B. Introducing virtual sources as effective signal inputs to each neuron does not occur from other neurons.
C. Since the signal outputs are taken vertically, the modification is to access the individual signal outputs. Therefore, the model is a 3D (three-dimensional) model.
This virtual source neural network model was created from the 1982 Hopfield principle (FIG. 11) to fit the vertical and horizontal processors described above. As used herein, “model” means a set of basic principles, procedures, or rules that should be followed while creating learning software for real-time operation.

Fourth, the present invention provides a processor learning method (see FIG. 12) for learning a single vertical horizontal processor of the vertical horizontal processor. There, the signal input and the signal output are correlated with each other by the above-described invented artificial neural network model, and after the main initial setting of the following learning method steps (1) to (3), the virtual neuron Or find rules or weighting factors for multilevel systems.
(1) First, find application ranges for local and global bias (see FIG. 13).
(2) Secondly, their operation level or functional behavior is found for each multi-level logic state (see FIG. 13).
(3) Finally, given an unpredictable signal input, create (or find) a logic function with energy minimization so that it can give the most probable solution to the problem (see FIG. 14) about).

(Comparison with conventional processors)
In US Pat. No. 6,820,244 B2, which describes a learning method for nanocells, it is implied that, for large scale use, this vertical observation on interacting surfaces is not practical.
However, in many ways we can turn the drawbacks into smarter systems when this vertical electrode array system can be viewed as a component of the overall neural network. Being vertical not only changes the basic design but also completely changes its basic operating principle from the default concept of a processor such as a nanocell. Next, on the horizontal plane, we have only various signal inputs coming from all directions, and all signal outputs are taken vertically. Each vertical electrode is a neural network signal output and does not require signal processing via a surface path as in the case of a sequential processor such as a nanocell processor, so it processes data in parallel. . Even a few multilevel units need to be switched for signal output points that are almost independent of each other, so the performance is expected to be extremely fast.

  In our system, we can now see and understand how the signal output is obtained, how it differs from what is expected, and how this signal output is different. The surfaces that interact with each other are no longer black boxes. The electric fields, potentials, and potential gradients at every point on the interacting surface are known, and these are important when we energetically know the multilevel states that may be predicted. Set the smart system to the multi-level state. Although the vertical signal output is different from that of the nanocell, the vertical signal output is a surface having an upward current slope and a downward slope similar to the brain. Also, if a portion of the smart system on this surface does not switch, so that the position of the upslope and downslope does not change, the solution will not be affected at all. The simple problem of a nanocell, such as a processor, whether any signal input has any effect on the solution no longer arises. In many ways, nanocells mimic a highly parallel information processing neural processor like our brain. ANN is used to find the rules followed by this device and develop different aspects with different input signal arrangements. When a “nanocell” learns input and output signals and behaves as a logic gate, our vertical processor has multiple levels of natural motors through sensor arrays and multiple motors for proper operation. Logic gates are not required because it can be an interface to an organ that requires control.

All these advantageous changes are summarized below.
1. Although the model device of the present invention is simple, new features are added to the Hopfield model of the neural network, which can be experimentally realized without compromising the information processing advantages of our brain nervous system. it can. As an example, this model device does not require a logic gate.
2. The model of the present invention is flexible with respect to the dimensional constraints of the computational area used in principle for complex integrated circuits without destroying the materials used and their basic operating parameters.
3. The present invention is the only system that processes more than one bit of information at a time and therefore may operate using extreme parallel bit processing. This is a completely parallel processor. An information processing area of 1 cm ² can process 1 terabit (10 ¹² bits) at the same time if it has an area of 1 switch / 100 nm ^2. However, any processor in the world can process only 1 bit at a time. . This means that if each switch operates at 1 GHz, each switch can process data at a rate of 10 ¹² × 10 ⁹ = 10 ²¹ bits / second.
4). The present invention is the only one where the decision persists even under extreme noise, as in our brain, because the decision is determined by the response in significant coordinates, not by each person's contribution. This is a proposed model.
5. Random interconnections allow fuzzy integrated circuits created by connecting our processors to also generate logic that follows the vertical projection concept we introduced, so the present invention is hardware that can be comparable to the human brain. We can direct us in the direction of making it seriously.
6). The model of the present invention may experimentally implement set computation (eg, see, think, work) without weakening this principle. This is the only neural model that can take into account any significant incentives of the decision-making unit.
7). The model of the present invention is flexible because there is no constraint on the materials used, different functions simultaneously, the dimensions of the information processing surface, or the number of electrodes used and the connectivity. .
8). The model of the present invention can create an extreme sensor device that can generate a 3D pattern of this detection parameter.
9. The model of the present invention is flexible towards the computation of mathematical functions because we can use it in both horizontal and vertical modes and vertical and horizontal modes.
10. The model of the present invention is the only existing model that continues the decision even if some of the information processing units (neurons) cannot be executed on the information processing surface.

Further explanation of the invention

  Next, the present invention will be described in detail.

  As described above, the first invention is provided with a plurality of input signals horizontally from all directions on the plane at the center of the surrounding electrode and containing the multilevel system or neuron. A vertical horizontal processor ("standard vertical horizontal processor") that includes a pair of templates whose output signals are taken vertically at various points on the surface.

  In this specification, the planar shape of the template of these multilevel systems is preferably square or rectangular (see FIGS. 1 to 3). In such a shape, the plurality of input signals are horizontally from any direction on a square or rectangular surface in the center of surrounding p + q + p + q electrodes and containing a multilevel system or neuron. , P × q, and m × n output signals can be taken vertically at various points on the surface. Here, the values of m, n, p, and q are various numbers from 0 to infinity, but both m and n, or both p and q cannot be zero at the same time. .

The planar shape of the templates of these multilevel systems can also be triangular, circular, or polygonal (see FIG. 16). In such a shape, the plurality of input signals are horizontally oriented from any direction on a triangular, circular, or polygonal surface in the center of the surrounding electrode and containing a multilevel system or neuron. And the output signal can be extracted vertically at various points on the surface.
When the planar shape of the template is a triangle, a + b + c (from three sides) input electrodes surrounding the triangle are set on this surface. When the planar shape of the template is a circle, n input electrodes (the number of signal inputs a along the circumference) surrounding this circle are set on this surface. When the planar shape of the template is an n-side polygon, a + b + c +... + N (from n-side) input electrodes surrounding the polygon are set on this surface. Further, the difference in height between the information processing surface and the surrounding electrodes varies for each information processing surface.

  In the vertical horizontal processor described above, preferably the template surface is conductive. A preferred vertical electrode is one that measures STM-based tunneling current flowing into a multilevel system or neuron (see FIG. 6). Here, the conductive surface is preferably grounded, and each electrode in the p × q array is energized and is part of an independent measurement circuit.

  Other preferred vertical electrodes measure AFM-based atomic forces in contact with multilevel systems or neurons. Here, this conductive surface is preferably grounded, and each vertical conductive probe of the p × q electrode array is energized and is part of an independent measurement circuit.

The information processing surface of the vertical horizontal processor of the present invention is preferably a material having a redox action center or a conformation dependent center, and a material having at least two of the following properties A, B, and C ( Has a thin film (on the information processing surface).
A. The material incorporated between a pair of electrodes, in a certain range or application (see FIG. 5B), exhibits the property of exhibiting a stable multilevel conductivity at any particular bias (see FIG. 5C). about),
B. The nature of each state may be brought about by adding different bias states (see FIG. 5B),
C. The property that the transient current response to a rectangular voltage pulse is a Gaussian response, a step response or a ramp response, or an evolved form of a stepped response.
In the present specification, the “information processing surface” means a surface having a multi-level system in the template. In addition, “at least two of the following A, B, and C properties” means that (A and B), (B and C), (C and A), or (A, B, and C) Means.
As described above “materials with redox centers or conformation-dependent centers and containing at least two of the above A, B, C properties” That is, nanowires (narrow wires), or nanoparticles, or quantum dots, or organic or inorganic hybrids thereof, or liquid crystal materials, or various biomolecular systems in the form of polymers, enzymes, lipids, DNA, and their biological bodies Mention may be made of hybrids of molecular systems, or any combination of organic materials, and / or systems comprising any inorganic composite or naturally occurring inorganic material.

In the vertical horizontal processor of the present invention, the multi-level system or neuron preferably includes the following means A, B, C, or D.
A. A sensor for detecting a specific signal, and a sensor for detecting a signal such as real sound, heat, light, or any other form of energy. A sensor specifically designed to be converted into a one-dimensional array of signals.
B. A small information processing unit of any other functional material having a specific function, which converts and transfers the entire information processing surface to a different area so as to have a different function;
C. A multi-level system or neuron that can be reversibly switched between all possible conducting states and remembered longer than the time that the equilibrium state spans the entire surface, updated many times What can be done (RAM);
D. A multi-level system or neuron (ROM) that stays permanently the same once switched to one of the possible multi-level states.

In the vertical horizontal processor of the present invention, the vertical electrode is preferably a structure having a nanoscale width height and a microscale length, such as a probe having a single atom tip, and in a certain electrode system. Some of the probes preferably include A or B.
A. A probe with a single atom tip such that a solution point is considered to be a single atom tip (see FIG. 16).
B. A defined number of atom tips in a single electrode unit such that the solution point is considered the average response of the aggregate output signal for every atom tip (see FIG. 16). As the vertical electrodes described above, we can mention, for example, metal nanowires, semiconductor nanowires, carbon nanotubes, and any other metal or semiconductor nanorods, nanotubes, or bundles thereof.

In the vertical horizontal processor of the present invention, the signal input is preferably connected to a neural node controller (see FIG. 6), where all input signals are different prior to this vertical horizontal processor. The units are divided into units in parallel and are switched between the units including the next A, B, C, D, or E (see FIG. 7).
A. Units that may change the sequence order and intermediate ground connection,
B. A unit for changing the arranged identical signal inputs into an arrangement in a different order;
C. A unit that passes the arranged signal inputs in parallel through different forms of processors to produce a combined output;
D. A unit for replacing a part of the signal input with a pulsed array source;
E. A unit that passes an input signal through a channel where the input signal is multiplied or divided to match the input impedance of the entire information processing surface.
Here, the neural node controller is a package of hardware software that can modify this input in different ways before sending the arranged identical input signals to the vertical processor.

  In the vertical and horizontal processor of the present invention, the number of ground connections for p × q signal inputs preferably varies from 1 to pq−1 in order to process the same set of arranged input signals. (In region A of FIG. 6). Each combination of earth preferably creates a specific action node, and each node preferably has its own neural network, and after training and creating rules, a special kind of These nodes are used in various situations that require information processing.

We can also reverse use this invented vertical and horizontal processor (inverse processor). When this neural model is reversed, that is, the voltage is applied in the vertical direction and the output signal is taken in the horizontal direction.
That is, the present invention also provides a plurality of input signals vertically from above on a horizontal surface in the center of the surrounding electrodes and containing a multilevel system or neuron, and through those electrodes. A vertical horizontal processor is also provided that includes a pair of templates from which output signals are extracted horizontally.

In the above-described (vertically used) vertical horizontal processor, the vertical multiple input electrodes preferably have a flat or spherical leading edge that generates a local bias over a large area on the information processing surface, and the vertical electrodes The front edge region of each of these preferably forms the following A, B, and C.
A. A total area that is the sum of all individual vertical electrodes that covers a certain percentage of the information processing surface, from which a total area in which a signal input operation node is created for each type of operation,
B. Relational area of bundled electrodes or individual vertical electrodes to variously adjust the control of individual signal inputs on the final solution surface,
C. The form of the front edge corrected to adjust the potential distribution of contour lines on the information processing surface.

As described above, the second invention is a cluster comprising the standard vertical horizontal processor, the neural node controller, and the connection switch sensor connected in the following A, B and C manner (see FIG. 18). See).
A. A part or all of the signal input unit of the vertical and horizontal processor is connected to the array of vertical processors, and the remaining signal input unit is connected to the signal output unit of the sensor which is a free signal input unit of the entire system. .
B. A part of the signal output unit is connected to some of the signal output switchers, and the remaining signal output unit is connected to another vertical processor.
C. All free signal outputs are connected to the switch and not connected to any signal inputs in the entire system, but taken vertically as the final cluster signal output.

As mentioned above, the third invention is a modified virtual source neural network model (see FIG. 11) comprising any one of the above vertical and horizontal processors, the modification being The model includes the following A, B, and C.
A. Replace old-concept binary neurons (with values of 0 or 1) or continuum neurons (any value between 0 and 1) with multi-level systems or neurons (selected values between 0 and 1).
B. Introducing virtual sources as effective signal inputs to each neuron does not occur from other neurons.
C. Since the signal outputs are taken vertically, the modification is to access the individual signal outputs. Therefore, the model is a 3D (three-dimensional) model.
The invented virtual source neural network model was created from the 1982 Hopfield principle (see FIG. 11) to fit the vertical and horizontal processor described above. As used herein, “model” means a set of basic principles, procedures, or rules to be followed while creating training software for real-time operation.

  In the above model, the form includes a vector sum of the products of the weights generated by the effective signal input from the virtual source, i.e. the global weights, and the weights generated by the vertical probe, i.e. the local weights. It can be made by minimizing the energy term (see Figure 14), and for these two positive contributions, using the weights generated by the multi-level thresholds , Negative operations can be performed.

One preferred embodiment of the model includes A, B, and / or C.
A. A feedforward network by reverting the signal output of some or all of the model of the vertical and horizontal processor and connecting it directly or indirectly to its own signal input (see FIG. 12).
B. With one or more hidden layers of multi-level neurons (see FIG. 11), fewer or equal numbers of signal outputs can be generated at various levels to produce the final signal output. Model to reach.
C. An intermediate layer composed of mixed multi-level logic neurons that contain two or more types of logic neurons, as in a quaternary or octal system, or other logic systems (see Figure 11) .

As described above, the fourth invention is a processor learning method (see FIG. 12) for learning a single vertical horizontal processor of the vertical horizontal processor invented above. Here, the signal input and the signal output are correlated with each other by the above-described invented artificial neural network model, and after the main initial setting of the following learning steps (1) to (3), the virtual neuron or Find rules or weighting factors for multilevel systems.
(1) First, find application ranges for local and global bias (see FIG. 13).
(2) Secondly, their operation level or functional behavior is found for each multi-level logic state (see FIG. 13).
(3) Finally, given an unpredictable signal input, create (or find) a logic function with energy minimization so that it can give the most probable solution to the problem (see FIG. 14) about).

In the processor learning method described above, a processor that creates a logical function in the above step (3) and performs a mathematical operation (see FIG. 17) is preferably an A that handles a function criterion including C or D below. Or B is included.
A. For the vertical signal input and horizontal signal output of the invented (standard) vertical horizontal processor, through the concept of an inverse matrix process that reverses the 3D matrix to a linearized array.
B. Through conversion of linearized array to 3D matrix for horizontal signal input and vertical signal output. This is the basic operation method for the processor of an inverted vertical horizontal processor.
C. Information processing of mathematical functions using probe bias as an operator.
D. The number of ground connections for p × q signal inputs varies from 1 to pq−1 in order to process the same set of arranged input signals. Each combination of earths creates a specific motion node, and each node has its own neural network, and after learning and creating rules, it needs a special kind of information processing These nodes are used in various situations. In this case, using a geometric information processing surface variant of the above invented standard vertical horizontal processor or inverse vertical horizontal processor to generate a specific function criterion.
As the mathematical operations described above, we list mathematical operations such as matrix transformations, operators, tensor information processing, integration, and other functionality.

In the processor learning method for the cluster (see FIGS. 18-19), learning is preferably performed according to the model including basic considerations A, B, C.
A. The signal input of this processor is the free signal input of the cluster considered as a 2D input signal array, and the signal output of this processor is the final signal output of the cluster considered as a 3D array, The basic processor component is replaced with one or more layers of multilevel neurons.
B. First, the individual components of this cluster are learned, then their importance in the final signal output is determined by finding the functional relationship with the most similar part in the final signal output pattern .
C. Since there are two different types of signal inputs in the cluster, either directly from the sensor or from any other processor, the importance of the two different types of signal inputs to this final pattern therefore finds a functional relationship. Determined by

In the processor learning method for the inverse processor, a learning method including the following step A, step B, and step C is preferably performed.
A. Finding an application range for local and global biases using an additional criterion of neuron crosscheck reproducibility on contours on the information processing surface generated by electric field projection from the vertical electrode;
B. Finding the functional behavior for the transition to each multi-level state, along with the electric field distribution contours generated by the interaction of adjacent vertical electrodes with each other;
C. Creating a logic function by energy minimization taking into account the minimum energy path from horizontal electrode to horizontal electrode.

  In our dynamic brain, connectivity changes continuously, which allows the brain to make some basic rules that are executed in unknown situations. Creating a rule is just a permanent change to the 3D processor network. However, no matter what individual device we create, we cannot change the form of this system. Therefore, an equivalent individual system should have three basic criteria. First, the system will be a system with extreme parallel information processing, ie the death of any element on the information processing path or noise should not significantly affect the final decision making. Second, the system must be able to generate a 3D pattern solution to provide a collective output of the superimposed signal. Finally, the operating principle of the embedded processor can be freely modified, or can be freely converted to a processor with a different function, or can be freely configured as a RAM and ROM-based processor, a sensor of unusual operation, etc. There must be. The principle of operation must support all kinds of general-purpose data that is processed by a single information processing unit (ie, all kinds of signals coming from different functional sources are superimposed during the collection of that data). In addition, this principle of operation should not weaken the effectiveness of these data as part of its own data processing.

BEST MODE FOR CARRYING OUT THE INVENTION

FIG. 1 shows a schematic diagram of the vertical processor of the present invention. The horizontal and vertical portions are both electronically and physically independent, and these portions are shown in a coupled state. 2 shows the structural design stage of the horizontal plane (part) and its external connection part, and FIG. 3 shows the structural design stage of the vertical plane (part) and the external connection part shown in FIG.
The operating principle of our model processor may satisfy all the basic requirements mentioned above. Before describing the model and method of the present invention, a model device capable of implementing this principle will be described for clarity. This processor has two templates, one with an information processing surface unit 101 and the other with a vertical electrode array unit 102 facing the unit. Cables from the respective vertical electrodes 103 and horizontal electrodes 104 are bundled and output for signal input or signal output from the information processing surface 105 or the collection surface 106. The information processing surface has neurons 107, and the vertical electrodes are at a distance from these neurons by a tunnel distance. Between the information processing surface and the electrode, an interval 108 that does not confirm any tunneling is secured, and the ground is also connected to the signal output unit 109. We need to create an electric field distribution on the horizontal plane. Therefore, the external electrode thickness d ₁ (201) must be greater than the thickness of the horizontal conductive surface d ₂ (202). The combination of the metal electrode surface and the substrate depends on the type of neuron used and also on the technology used to manufacture this structure. As an example, we have deposited a low resistance Si (111) substrate by depositing SiO ₂ on a Si substrate 203 by chemical vapor deposition (204) and further depositing an external Au electrode E by electron beam lithography (205). Can be mentioned. Subsequently, SiO ₂ is lifted off by dry etching (206, 207), and finally, an Au-treated surface P is deposited (208). This structure is part of a larger structure in which each electrode is connected to an outer circuit 209 with an information processing surface or ground. The size of the electrode array p × q or m × n is determined by the system requirements 210. The Au surface is made atomically flat by a one-step heat treatment of H ₂ . Therefore, in order to realize this, two-stage lithography is required. A vertical electrode array is not required in the present invention, but may be useful for industrial applications. In the vertical electrode array, we can mention chemical vapor deposition of low resistance Si (111) plane was deposited a SiO ₂ to Si plane 301 using (302) as an example, shown in Figure 3B Such an Au pattern is formed on this plane using electron beam lithography 303. The entire surface is covered with resin (304), and a portion is dry etched (305) to grow an isolated array of nanorods or nanowires only within the selected region. (306). The entire process depicted in FIG. 3A may be performed on a high resistance Si substrate without depositing SiO ₂ . To initiate nanowire or nanorod growth, it may be necessary to spin coat a shaped catalytic metal between 305 and 306. The vertical growth of nanowires for different metal and semiconductor materials has been established in publications by standard methods such as growing chemical bath deposition, chemical vapor deposition and the like. All electrode connections are part of a large structure that leads them to an external external electronic circuit.

  The above sample is replaced with the horizontal information processing unit 401 in an arbitrary STM / AFM mechanism (FIG. 4), and an m × n cable is taken out from the system 402, and the PC (personal computer) is used as basic information. A processing device can be connected to a voltage source having a GPIB / RS control system. Dedicated software can control the magnitude or time of the pulse or applied signal input. The vertical signal output section is generally an STM or AFM probe 403 connected to the original STM (scanning tunneling microscope) / AFM (atomic force microscope) body 404 as far as the applicability of the model of the present invention is concerned. We sometimes design a back-to-back system for this coupling system 405 based on two dedicated piezoelectric element drive mechanisms. For industrial applications, a bundled vertical electrode similar to the design we have proposed may replace the probes 406, 407 in the main STM / AFM body 408. The case of a bundle-structured vertical electrode may be considered a very representative case of our invention because of its very limited theoretical modeling. For this vertical signal output, a p × q cable is removed from the system 406 and each signal output has an independent current measurement unit with a horizontal ground as a common ground. During approach 409, 410, 411, one or more of this signal output is connected to the probe's positive voltage, and ground is the probe's ground. As soon as the tunnel current is received, some of these electrodes are considered as close to the tunnel distance. By moving the position of the substrate or the tunnel electrode, the vertical and horizontal portions are brought into appropriate positions. In FIG. 4C, a simple procedure is proposed in order to obtain an accurate position. One of the four switches S1, S2, S3, S4 is switched on, and scanning is performed in the STM system with respect to the points A ', B', C ', D'. We try to enlarge the common areas 412, 413, 414 until the corresponding information processing surface, i.e. the maximum common area is reached. Since it is impossible to prepare all electrodes vertically at the same height, we cannot guarantee how many of these electrodes will be connected or which system will have the maximum signal output. For the most part, the electrode response is also non-linear. However, this system can show that bits are processed simultaneously, and uses fixtures 415 to secure horizontal and vertical units to tunnel distance 416 after reaching the maximum common area Helps create concepts for commercial units that can. Thus, we have constructed a conceptual device for horizontal signal input / vertical signal output, and vice versa (for vertical signal input / horizontal signal output).

Since we have built a concept for boxes that can implement the present invention, we need to build a concept for neurons that can have multiple levels of conduction. The term “neuron” means an equivalent system composed of any material that behaves as a group on a horizontal plane and exhibits multi-valued conductivity. The term multi-valued conductivity means that an equivalent group system can be switched to different conductivity states, and at a specific probe bias, the measured conductivity can be different after switching. Means. By acquiring or emitting electrons, or by conformational changes, the system may remain at a different energy (U _ij ) minimum in the configuration space (q _ij ) (FIG. 5A). The respective energy minimum values correspond to the system conductivity 501, 502, as well as the multi-value levels 503, 504. The difference in conductivity between different states must be large. We need to prepare thin films using organic or inorganic materials that can provide a multi-valued conductivity system on a horizontal plane. Many systems can be selected according to such basic criteria. We can also select molecules that exhibit multiple electron reversible redox in cyclic voltammetry so that each time they accept or emit electrons, the molecular system is led to a different conducting state. I will. We can also select nanowires immobilized with ligands / molecules that oxidize / reduce, and thus multi-value systems can be realized with varying degrees of oxidation or reduction Will. Molecular systems such as DNA, polymers or long-chain molecules, biomolecules in which (π) conjugates are switched to molecules or nanoparticles that switch in the longitudinal direction (molecules), or oxidants / reducing agents Conformational states that are part of an example that can have multiple oxidation levels or reduction levels, or that have different conductivities, may be considered a multilevel system. Such thin films are grown by self-assembly and conformational changes are controlled by various parameters until the most desirable system of our preference is reached. A multi-level system has a certain energy required for each level, which is applied by an electric field. Applying a series of voltages (505), causing different conductivity states 506, and examining several times in the meantime (507) with the same probe bias should find different conductivities for each sequence of probes 508. is there. Such written state could be erased by applying the appropriate pulse 509 and the attenuation of state 510 would be apparent. If this system is irreversible, it will be used as a ROM and one neuron could be used only once. Any system manufactured as described above exhibits the nature of “write / read / erase / read” as analyzed, which is considered a multi-level neuron.

The arithmetic circuit network for the entire test system has two coupling circuits, a horizontal circuit and a vertical circuit (FIG. 6). The horizontal information processing surface 601 is connected to the neural node controller 603 via the mn cable 602, and the signal output unit of the neural node controller 603 is connected to an independent voltage source 604 or sensor array. Sometimes. The different function sensor arrays F1, F2, F3, F4 (605) may be connected to a neural node controller. This signal output is read by scanning the response of all neurons 606 using an STM probe (FIG. 6C) and whether the signal output is measured using an array of independent ammeters 607. (FIG. 6D) Alternatively, those ammeters can even be connected to the connection switch 608 (FIG. 6B). Here, a neural node controller (NNC) (FIG. 7) that is an interface between the sensors / sources 701 and 702 and the corrected node signal input for the horizontal information processing surfaces 703 and 704 needs to be described. NNC has two aspects. In general, the change in electric field distribution due to the effective current source {I _n } at a specific point on the information processing surface 705 is determined because the number and direction of the ground connection portions are determined, and the geometric shape of the information processing surface is circular. Alternatively, to be either a triangle or a polygon, i.e. a defined geometry, some rules will be followed. Second, in virtual neurons, which are specific composites of organic or inorganic materials, their response functions change to represent the mysterious characteristics of supramolecules. The purpose of the neural node controller is to get the signal source {S _n } and change the ground connection, external bias, pulse sequence, pattern control, create different routes by hardware, when the signal passes The signal reproduces the newly defined voltage change route exactly the same. Only a random change of the signal source {S _n } can produce a unique electric field distribution according to defined rules. Therefore, the response function of the neuron, that is, the relationship between the original signal input and signal output of the neuron will be more clearly defined. We generate different electrical circuits capable of generating a set of {I _n } signals on a horizontal information processing surface from a set of {S _n } signal sources. Every set is a source for a random electric field distribution on this surface, which is called a neural node. It is possible to switch between nodes N1, N2, N3,..., Nn (706). Each node corresponds to a function F1, F2,..., Fn (707). All of these functions may be generalized to form the final criterion function F (708). We distributed the electric field on a rectangular surface including the field lines 801 and the equipotential surface 802. The ground connection indicated by G in column C of FIG. 8 and sometimes in columns A and B of FIG. 8 indicates that the basic and most prominent feature of the electric field distribution is determined. As soon as the electric field distribution is created, the neurons in the information processing surface try to reach an equilibrium conformation in response to this electric field. The dimensions of the allowed quantum wells 901, 902 determine the energy level of the conductive neuron conformation (σ _n ) that will be allowed in each quantum well. In other words, the dimensions of the 3D (three-dimensional) box 903 determine which conductive sphere fits into the 904. Each time an STM / AFM probe is filled with a sphere of neurons, a tunneling current is applied to produce different heights 906, 907, 908. All of these nanoscale multivalued response columns give rise to a microscale (uneven) surface 909. Every peak on this surface can be considered a solution to the problem of the input signal. Therefore, signals such as light, sound, and heat are converted from an actual sensor into an electronic signal sequence 1001, and all these signal sequences are sent to the horizontal plane 1002. This signal generates an electric field distribution, and neurons having multi-level levels interact with each other to reach an equilibrium state (1003). A random distribution 1004 of the 3D quantum well in which the neuron is contained is forced to the neuron. To reach an allowed state. The vertical electrode array 1005 reads the state of the neural without applying a low voltage and destroying the 3D quantum well 1006. The 3D signal sequence of the signal output obtained as a result is multivalued (1008), and the connected motor 1007 can be controlled. A realistic model of a neural network creates a logical relationship 1009 between an input sequence 1002 of electronic pulses and an output 3D sequence 1006. This logical relationship is used to predict the outcome in an unknown situation.

We create the model of the invention as follows. Each multi-level system on this processor is regarded as a neuron 1101, 1102, 1103 that can have conductivity in a particular configuration of virtual sources 1104, 1105, 1106, and that neuron is switched to a different state. At any instant, the state of the neural network surface is a two-dimensional m × n component matrix V = [V ₁₁ , V ₂₁ , V ₃₁ ,..., V _mn ]. In this case, there is an mn multilevel system on the surface. The component values range from 0 to n-1. So we see that the signal output activity of neuron X _j is a time-dependent polynomial parameter equal to 0-n−1; X _j (t) = (0) V (n−1). Correct discrete and deterministic continuous models. Here, V (n−1) is a logical function 1107 of n input signals and one output signal. Unlike the standard neural network model, here we have no presynaptic neurons, but instead have elements of the matrix χ _ij of the potential and electric field distributions, ie the electrical of the surrounding electrode array It has a virtual source effect 1108 on each neuron signal input generated by the signal. However, we set the synaptic connection weight W _ij so that the neuron provides an output signal that depends on the effective potential between earth and the probe, and the interaction between the individual elements and the probe. have. When taking multi-level logic into account, each time a state is realized, it has n thresholds. A set of threshold voltages {θ _i } can be considered for a given system, taking into account that each neuron threshold is randomly distributed within the applied voltage range. The neuron output signal 1109 is a function determined by an electric field matrix element as an input signal, a multilevel threshold, a transition probability in this matrix, and an individually measured response function. Our invention (20) removes presynaptic neurons leading to virtual sources, (b) introduces multilevel logic, and (c) takes into account individual output signals, The concept of neural network is corrected.

Here, each element of the output tunneling current pulse measured by a vertical electrode or a bundle of nanowires is basically a Gaussian function f (x), eg, for a negative differential resistance system given by It can be written as there is.

The output function may be a step function, a ramp function, or a sigmoid function that depends on the type of input voltage pulse applied to the system. The function variable x depends on the synaptic signal input from the ambient electrode signal sequence, the probe bias from the nanowire tunnel current measurement circuit, and the weighted average of the thresholds for multilevel switching.

In the equation, ij is the coordinates of the neuron on the information processing surface where the current is measured, and k is the order of the input electrodes among a total of e electrodes each spaced at least by r _k . V _p is the probe voltage, and θ _k is the threshold of the kth state. Here, clustering of multi-level systems and excessive correction of electronic states due to defects in geometric planes are ignored, but synaptic weights take into account interactions between systems.
Every multilevel system or neuron on this information processing surface has the most probable state θ _{k in} which the energy of this state is minimal for a given weight. The energy of this system is given by:

Since this energy change is a multilevel neuron, it is controlled by a search bias and a threshold value. Here, _sk is the effective potential for the electrode (ie, virtual neuron). Based on this energy logic equation, the main state is determined. Use θ _m to find the weight change. The most probable set of states is used in this system to determine how the neuron can generate multilevel logic. For example, when there are 8 levels of logical values, θ _m varies from 0 to 7. In this system, 3 + 5 = 0 and 5 + 5 = 2. Therefore, after applying the voltage array from the external electrode, various numbers from 0 to 7 are randomly distributed on the information processing surface.

After selecting θ _k , the output signal error is calculated for each, and the most probable weight is continued by the back propagation algorithm, ie, feedback of the resulting weight until the error is minimized. Selected by calculation. We can devise a hidden neuron level between this information processing surface and the output signal layer 1110. Here, the case of only one hidden layer will be described. This is a case where pq has signal input nodes 1111 and 1113, st as hidden nodes 1110 and 1114, and finally ij as a signal output node. In hidden mode, this hidden layer may be our model 1114 or Hopfield's neurons 1110. Since there are mn input electrodes, the entire information processing surface is divided into mn cells. However, each of the mn cells can have several multilevel systems. For example, the number is ab. V _pq is the signal input for each of these input cells, and pq varies from 11 (p = 1, q = 1) to ab. The output signal of these cells is

Given by. Therefore, when the hidden layer of neurons is cd, st varies from 11 (s = 1, t = 1) to cd. Here we have one output signal I _{ij to} STM / AFM, or several to nanowires or nanorods or nanotubes imitating bundled electrodes that can be substituted for STM / AFM tips (eg, uv) output signals. therefore,

Thus, finally, the output signal for this modeled neural system is:

As mentioned earlier, the concepts of threshold voltage θ _k and search voltage V _p can be incorporated into this function. Here, the introduction of the above principle into programming will be described. First, it is necessary to determine θ _k and further weight combinations corresponding to the respective states. How such a state can be obtained in a cyclic manner, in other words, for any random voltage array signal input, we have an output signal from 0 to 7 as an 8-level logic system. I would like to use this system as an analog-to-digital converter as always available. This cyclic behavior may not be assured because we need to create some rules that specify how to change the logic response in a particular domain simply by changing a certain signal input bias. Absent. By this method, consistency with the computer processor used every day can be constructed.

First, a range in which the sum of potentials whose output responses are affected is determined for a specific search bias V _p .

Must be determined. _Where V _iL is the lowest potential sum below which the neuron cannot respond at all below (1201), and V _iH is the highest sum above which significant noise _surpasses significant changes (1202). ). Similarly, we must determine the extent of the search the potential V _P, at the lowest place of its range, the minimum voltage necessary to detect neurons is determined (1203), and the maximum voltage Beyond that, the electrode potential change is meaningless (1204). Second, neurons are not sensitive to all logic states, but are sensitive to the range of logic states and, ultimately, the sum of potentials required to achieve the state of each neuron. Not expensive. In our case, since we have a multi-level system, we need to examine the minimum energy or the sum of potentials for threshold and synaptic weights. We have determined how the potential summation or weight changes for the specific state where the node changes in the specific neuron shown in FIGS. 13A and 13B. The average of node effects was plotted in FIG. 13C to determine the most promising sequence combinations needed to exert a particular state on a particular neuron. From such an array, the array having the highest probability of inducing the neuron is selected from FIG. 13D, and these arrays are applied to all possible combinations to determine the rules of the multilevel logic shown in FIG. 13E. make.

The inventors have summarized a step-by-step procedure for the learning process that can be implemented in many ways. In the case of the present invention, as shown in FIG. 14, a very special case has been described in which there are no hidden neurons on the neural network. Our energy variables are three sets of parameters, and the goal is to find the most promising state that is active for any given input signal sequence. Therefore, we will minimize the energy value (1401), or determine the variational function _Gij of the multilevel level from the previous step 1402 (1403). Due to the nature of it, learning will connect the switch, so that our model device will be the main source for the output signal whenever it encounters any unknown set of input signals. Replace the inverse function that determines the threshold in Equation 1404 with another one. As with our model probe, the horizontal electrodes and threshold voltages are all different, and therefore, as a default for the second minimization process, the first set of synaptic weights and probe effects In some cases, the entire error is minimized by repeating the back propagation algorithm several times.

Since it is impossible to simultaneously perform vertical acquisition of output signal data while having a molecular scale resolution, it is not possible to take out such a large number of cables from such a small area. In fact, we use STM to access the signal output and verify our invention model experimentally. Since the STM has only one probe, it is considered that a set of output signals are generated all at once after the scan is completed, and signals are output simultaneously by using the memory of the multilevel system. Will be.
To verify this model, we are applying a steady voltage rather than a pulse to each input electrode array. Therefore, the STM / AFN probe current is basically a ramp function or sigmoid function, and the sigmoid function f (x) is given by f (x) = 1 / (1 + exp (−ax)), where a is the gradient parameter of the sigmoid function. By examining the multilevel neuron and the vertical network concept using STM, we will experimentally examine the theoretical concept of the hidden neuron. Therefore, because STM can scan all over this surface, all multi-level systems on that surface will be searched when potentials and electric fields are applied from the external surrounding external electrode array. . As a result, the number of signal outputs is less than the number of signal inputs. The higher the spatial resolution at which data is acquired, the better the efficiency of the device and hence the smaller the difference between the number of multilevel systems and the number of signal outputs.

The error generated after selecting each weight is fed back to the signal input unit, and the input signal is corrected. This error is basically the MSE, or mean square error. When more hidden layers are provided based on the above mathematical procedure, the error function is changed as appropriate. On this information processing surface, errors that occur during operation are normally transferred in the horizontal direction, and therefore the influence of the vertical direction is minimal. In addition, since this system is not a sequential information processing, the spatial distribution of the error function needs to obscure the resulting pattern in order to block the neural response across all regions. In FIG. 15A, electric force lines obtained with respect to the input signal are plotted, and the most significant solution points S ₁ , S ₂ , S ₃ ,..., Sn on the surface are connected. Here, even if individual vectors are modified, these vectors cannot change their combined pattern solution because no error can be harmonized across the information processing surface. With this simple logic, our processors can withstand extreme noise, like our brain. Furthermore, by introducing the concept of hidden neurons 1502, error-mediated decision changes can be suppressed. Furthermore, if the neural decision-making cluster is reduced, the error-mediated decision change frequency can be reduced (1503).

Finally, we would like to explain some of the real-time parameters and the importance of these parameters in the model device of the present invention, which can be completely avoided using ANN during solution analysis. Yes. When a set of electrical biases are applied to the information processing surface, a potential is generated at every point on the information processing surface. In general, there is no multilevel system on the information processing surface, or the information processing surface is considered to have a constant conductivity. In this case, the potential φ (x, x, y) is the Laplace equation, ie, the solution of V ² φ (x, y) = 0.
For the sake of simplicity, consider a circular information processing surface of radius b surrounded by 16 electrodes of radius a. Due to the principle of superposition, the total potential at any point on this surface is the sum of the potentials generated by the respective electrodes and is given by:

Where z = x + ii, and

In this expansion, the first term represents the potential generated by a monopole inside the nth electrode, and k is a non-uniform charge distribution dipole on the nth electrode. It corresponds to a moment, a quadrupole moment, and an octupole moment. The value of C can be obtained from the points a and b according to the boundary condition.
Here, a multi-level system is placed on the information processing surface. It can be seen that there is a charge distribution on this information processing surface while applying various electrical signals. However, when measuring the output current using STM, the Laplace equation may not need to be changed even if the dynamic quantum effect of the non-uniform charge on the potential surface is taken into account. Using quantum path integral molecular dynamics (QUPID) based on the discrete system of Feynman's path integral method, the electrons interacting with N particle clusters are:

In the equation, P is the number of contributions considering the superposition of the harmonic potential and the cluster potential. When this tunneling current is measured, the effective sample bias is the sum of the potential generated by the surface electrode and the effective potential generated by the classical ions as shown in the following equation.
φ _sample = φ ₂ + <V _eff >, the height of this barrier is approximately the average of the sample and the tip / bias. φ _barrier = 1/2 (φ _sample + φ _tip ). So the current is

Can be expressed by the following equation.

Where E is energy and ρ is local density of states. Here, the electric field generated by the probe bias is a local action, and the electric field generated by the surrounding electrode is a global action, and these actions interact with each other. We choose both values so that in the realization of the proposed model, the change in conductivity externally induced by the electric field (generated by the external electrode) is most significant. Normally, the electric field on this probe is on the order of ~ 10 ⁸ V / m (eg 1V / 2nm), and the electric field (generated by the external electrode) is on the order of about ~ 10 ⁶ V / m, The conductivity can only be changed by thermal hopping, and the conductivity increases with the electric field as:

Therefore, the external electric field should be greater than the aforementioned value (ie, about ˜10 ⁷ V / m), which contributes significantly to the probe bias, but does not completely overcome the probe bias. Must do so. Therefore, the tunnel current is only noise. Therefore, for example, in the case of a system in which 16 electrodes are arranged at an interval of 1000 nm, if +5 V is applied to any electrode at a certain point on this information processing surface, ˜8 × 10 ⁷ V / m is obtained. can get. Therefore, the operating voltage range of the device is optimized based on the thickness of the thin film, the electrical characteristics of the multilevel system used, the probe bias, the molecular plane conformation, and the geometry of the information processing plane. There is a need.

In Bardeen's method,

Where f (E) is the Fermi function, V is again the applied voltage, M _μv is the tunnel matrix element between states, determined by the wave vector k, and k is It depends on φ _barrier and E is the energy corresponding to the state.
In the nonequilibrium Green function formulation (NEGF), a virtual medium 1504 is conceptually connected to a conductor 1505 that hangs between an atomic surface 1506 and an STM / AFM probe or vertical electrode 1507. The potential term for the Hamilton operator H _c is given by U (r) = φ _sample + φ. Hamilton operator _Hc is Green's function
,


Is used to determine that This current is given by:

Despite taking various parameters into account, it is impossible to directly predict the signal output and transition to different states. For effective realistic prediction, several parameters such as atomic flat surface defects, existence of different planes, various intermolecular interactions, fluctuation of transition probability of multi-level system in different states, etc. Cannot be incorporated into the calculation process. Therefore, as explained above, all the parameters can be avoided with the ANN-based concept. Furthermore, the information processing surface may be changed to a triangle 1601, a rectangle 1602, an n-side polygon 1603, and a circle 1604. In that case, the logical response change in this aspect becomes more and more complex, and it seems almost impossible to work without ANN.
I would like to add some comments about the versatility of this processor. The first is reversible use. When reversing the neural model, i.e., applying voltage vertically and taking the signal output horizontally, results are obtained according to this proposed neural network model, except that the STM / AFM search is performed. If the needle randomly brings local path adjustments, the learning method needs to be changed. The physical description of this system described above is not valid in this case. In this case, the horizontal information processing of signals is the main physical phenomenon, and the above theory is insufficient. So ANN gives a constructive result, but it cannot take versatility. Second, using the STM / AFM probe 1605, the entire information processing surface is scanned (1606) to find the result. In such a case, the maximum value is obtained as the solution point. We take into account design constraints when using vertical electrode arrays, with one probe 1608 having a single point information processing surface 1609 and four probes 1610 having four local points. It has an information processing surface 1611 having a cluster effect, and the eight probes 1612 have information processing surfaces 1613 having eight local cluster effects. When plotting the efficiency E of this device along with the change in the number of probes n, initially the average response is taken into account when the average response is taken into account, but if n is further increased, the probe-to-probe The interaction will reduce the efficiency of the device (1614).
The model of the present invention is itself a complete example of matrix linearization, as shown in FIG. 17A. Even reverse operation can be achieved by changing the signal input / signal output configuration. As long as we determine how to modify the local solution pattern as shown in FIG. 13E, we can create rules for individual mathematical functions as shown in FIG. 17B. it can. Therefore, a set of weighting factors that predict mathematical operations is generated. This processor corresponds to performing quantum mechanics operations, eg operator functions. The probe bias is learned as an operator, and a rule for quantum mechanical algebra calculation is created as shown in FIG. 17C.

  When creating the concept of a vertical processor, a combination of several processors for the overall output signal matrix of the entire system is among the applications that may be realized for the time being, as shown in FIG. Application example. Any type of processor signal input can be connected to any other type of processor, but any signal output can be significantly connected to any signal input and the equivalent voltage can be In order to supply to the signal input unit 1801, it is necessary to have a manual converter. The ROM processor 1901 is randomly connected to the RAM processor 1902, and this combined vertical projection gives a matrix in which some of these elements are fixed for the ROM. The 3D matrix of the processor inside the plane ABCD-plane EFGH shown in FIG. 19 has a projection of the signal output connection on the ABCD plane. Therefore, the signal output coming out vertically from this surface is basically “vertical signal output” as described above. We can apply the same concept using the correlation matrix source 1903 of the output signal matrix cluster 1904 in a larger random integration of processors with different sizes or functions. Therefore, the final processor follows the above principle as the above theory as being accessed vertically from a random 3D input source. There are only two basic changes. The first is that the weighting function for the synaptic signal input for the virtual source is here the weighting coefficient for the processor output signal matrix for that signal input, thereby the output signal matrix that is the seed of another matrix The element is to be obtained. We can also apply the projection theorem to find the effective output signal from random clusters. Therefore, the concept of horizontal signal input / vertical signal output and vertical signal input / horizontal signal output is a universal concept for developing a fuzzy neural network system into a future processor such as the brain. .

Example 1 and Example 2
The horizontal basic p × q as 1 × 0 is the most basic of the above-described processor. This means that global control is done by the two outer electrodes facing each other, while the information processing surface is between the electrodes and the data is taken vertically by STM. In addition, we succeeded in confirming whether the dual mode was adjusted. Next, the number of electrodes was increased by 1 to make 1 × 1 and p × q. The third electrode is called r. This system was made as follows. The template described above begins with a combination of electron beam lithography and gold electron beam deposition on a Si (111) substrate. In this case, the horizontal electrode pair (the height of p, q, r is ~ 100 nm) and the information processing surface (the height of the information processing surface is 50 nm) between these electrodes are separated by ~ 80 nm. Yes. Since this gap is theoretically simulated in a state exceeding the critical value, even if the electric bias is increased, charge injection to the information processing surface may not be brought within a certain limit. Nanoscale two-stage lithography has reduced the final pattern manufacturing success rate by about 30% to provide an elevation difference of ˜50 nm between the electrode and the information processing surface. The area of information processing surface is varied between 100 nm ² to 200 nm ^2. A large area atomic flat surface (rms <1.5 nm) and a symmetrical STM probe (electrochemical etching and subsequent structural examination) were essential for global tuning of quantum phenomena. After the gold template is manufactured on the Si (111) substrate, the substrate is heat-treated in a 100% hydrogen gas flow in a quartz chamber at a flow rate of 60 mL / min. This is followed by a heat treatment at a rate of 15 ° C./minute, heat treated at a temperature of 400 ° C. (600 ° C. for gold on newly cleaved mica), held for 30 minutes, and then shut off the heat source. Allow to cool. The substrate is kept at an angle of 15 ° optimized within the best operating range of 9 ° to 22 °, with its horizontal plane pointing in the direction of hydrogen gas flow. Very important is to create an atomically flat gold Au (111) substrate with a reconstructed surface structure over a large area. Further, to minimize defects, the template is immersed in a DMF solution, in which case the solution is continuously tilted at a rate of 3 degrees / second relative to the horizontal plane for 60 minutes, and Leave uninclined for 2 hours. This cycle is repeated three times, after which heat treatment in the hydrogen gas stream is performed as described above. This described method can produce a large area atomic flat surface (rms ˜8 nm to ˜500 nm ² ) with fewer defects than any other method. The survival rate of the final template was about 10%.
The newly heat-treated template is immersed in a micromolar ethanol solution of RB (Rose Bengal) for 5 hours, and is a self-assembled film having a 1.2 monolayer covering range having a thickness of rms to 1.5 nm. Produced. Quantum holes at specific locations were observed in various areas on the surface coating film. Optimization of the design and manufacture of a dedicated electrode system uses STM to apply a perturbation to this electrode system locally (vertically) and at the same time stabilize its environment and apply a global electric field (horizontally) It was effective to realize that. The physical events that occur in the quantum well (2nm ² ) were adjusted by balancing the two operations. In that case, the transition probability between the conformational states of the xanthene dyes was determined by both local and global bias. A single xanthene dye RB in a quantum well showed a Gaussian probability distribution with various conformational transitions. The bandwidth of the Gaussian Q band was adjusted to a maximum of 25% by horizontal bias. This revealed that the local bias could be controlled globally (this is a basic requirement for this processor). Also, the adjustable data we get is processing information that is simulated in software to find logic in the adjustment. This therefore functions as the most basic processor, as described above.

The perspective view of the vertical and horizontal processor of this invention. The horizontal and vertical portions are both electronically and physically independent, and these portions are shown in a coupled state. The external connection part of the horizontal plane design stage and the horizontal plane design stage of the vertical and horizontal processors shown in FIG. A shows the schematic (process drawing) of the main steps which manufacture the template of a horizontal surface. B shows the final structure (perspective view) constructed with dimensions of p × q. C shows an external wiring diagram created by photolithography or direct contact of a metal mask for the interface of the external electronic circuit to the horizontal plane. A vertical plane design stage with external connections of the vertical and horizontal processors shown in FIG. A shows a schematic (process diagram) of the main steps for producing a vertical surface template for STM / AFM probe replacement and for industrial applications. B shows the final vertical electrode array template (plan view). C shows an external wiring diagram created by photolithography or direct contact of a metal mask. Unit connection and mechanism representing the characteristics of checking the model proposed in the present invention. A is a schematic view (perspective view) of the STM / AFM unit. In this case, the sample is replaced with an m × n cable network connected to the horizontal information processing surface. B is a schematic (perspective view) of the single system of the present invention. C is a schematic diagram of the exact coupling between a horizontal processor and a vertical processor in the present invention. Selection of the smart system used for this processor. A is a schematic energy diagram for the smart system or neuron of the present invention. B is a schematic diagram of a test of a multi-level RAM of the present invention, ie, a smart system that performs a multi-level process of “write / read / erase / read”.

1 is a schematic diagram of a hardware control unit proposed for actually applying the present invention. A is an electronic circuit for creating a unique electric field distribution via a neural node controller. B is a vertical electrode connected to each motor that may be controlled by the PC 4. C is a circuit that reads the solution via STM / AFM. D indicates that the vertical electrode reading may be taken directly through an independent ammeter. E indicates the inherent horizontal field distribution generation through the functional sensor, which may be connected before or after the neural node controller. The neural node controller of the present invention. A is a variety of ways to generate neural nodes. B is the usage of the neural node controller in various modes. Theoretical simulation results of the electric field distribution on the horizontal information processing surface with 16 electrodes in the special case of the present invention. A is a simulation for different ground connections for a set of high voltage ranges. B is a simulation for different ground connections for a set of low voltage ranges. 1 is a schematic diagram of an operating mechanism of a model processor of the present invention. The figure of the real operation | movement of the processor of this invention, and the simultaneous ANN learning method of this invention.

Model conceptual diagram. The upper three electrodes show a schematic representation of the virtual source concept leading to the model of the present invention, as directed by the arrows. Our model is essentially different from the prior art Hopfield 1982 neural model, as described in the reference [see Non-Patent Document 1]. Below is a schematic representation of the neuron equivalent including the hidden layer of the present invention. Procedure (flow sheet) for finding the scope or field of application for real processors of the present invention. Determination of rules for adjusting specific states of neurons in a very local area of the real processor of the present invention. A is a schematic diagram (flow sheet) for classifying the performance level of the processor. B is a multi-level (graph) for classifying neuron responses and basic behavior. C is a classification diagram of basic behavior for a potential response, a specific set of input signals. D is a procedure (flow sheet) for determining a minimum response array for a specific state. E is a procedure (flow sheet) for determining these rules. The learning method process (flow sheet) of the processor of this invention. Survival of processor signal output under noise and real parameters to adjust the signal output of this processor. A is a figure which processes the noise of this processor in this invention. B is a schematic representation of the actual parameters that control the performance of the processor of the present invention. C is a schematic diagram of the NEGF formulation of Non-Patent Document 7.

The schematic which shows the versatility of the information processing surface of a processor and the effect of a probe in this invention. This schematic also shows the solution surface coverage for the different cases when the STM / AFM case is optimal. The figure which shows the mathematical operation using the vertical and horizontal processor of this invention. FIG. 5 illustrates the versatility of the vertical and horizontal processor constraints and combinations of the present invention to a number of similar types of processors of the present invention. The figure which shows the universality of the vertical access concept of this invention in the case of constructing | assembling the concept of a huge processor network using the processor of this invention.

Explanation of symbols

101: One information processing surface unit 102: Vertical electrode array unit 103: Vertical electrode 104: Horizontal electrode 107: Neuron 402: Interface connecting information processing surface and source 405: Interface connecting signal output surface and motor 501: Energy minimum for a certain conduction state of a neuron.
508: Multilevel response 802: Electric field distribution on the information processing plane 904: The nth state neuron occupies an acceptable well.
1607: All solution surfaces scanned with STM / AFM.
1613: Selected Solution Aspect 1901: ROM Processor 1902: RAM Processor Others: See text.

Claims (13)

  Multiple input signals are applied horizontally from any direction on the surface in the center of the surrounding electrode and containing the multilevel system or neuron, and the output signal at various points on the surface A vertical and horizontal processor that includes a pair of templates that are vertically extracted. The plurality of input signals are only p × q horizontally from all directions on a square or rectangular surface in the center of surrounding p + q + p + q electrodes and containing a multilevel system or neuron. And at various points on the surface, m × n output signals are taken vertically,
The values of m, n, p, q are non-negative integers, but both m and n, or both p and q cannot be zero at the same time.
The vertical / horizontal processor according to claim 1. The plurality of input signals are applied horizontally from any direction on a triangular, circular, or polygonal surface in the center of the surrounding electrode and containing a multilevel system or neuron, and 2. A vertical and horizontal processor according to claim 1, wherein the output signals are taken vertically at various points on the surface. The vertical / horizontal according to any one of claims 1 to 3, wherein the surface of the template is electrically conductive, and the vertical electrode measures a STM-based tunnel current flowing to a multilevel system or a neuron. Processor. The surface of the template is electrically conductive, and the vertical electrode is in contact with a multilevel system or neuron to measure AFM-based atomic force. Vertical and horizontal processor. The material having an oxidation-reduction acting molecule or a conformational change molecule and having a thin film as an information processing surface including a material having at least two of the following properties A, B, and C: The vertical / horizontal processor according to claim 5.
A. The property that the material incorporated between a pair of electrodes exhibits a stable multilevel conductivity at any particular bias in a range or application;
B. The fact that adding different bias states may result in states corresponding to each of the multi-valued ranks ;
C. The property that the transient current response to a rectangular voltage pulse is a Gaussian response, a step response or a ramp response, or an evolved form of a stepped response. The vertical / horizontal processor according to any one of claims 1 to 6, wherein the multi-level system or neuron includes the following A, B, C, or D.
A. A sensor for detecting a specific signal, and a sensor for detecting a signal such as real sound, heat, light, or any other form of energy. A sensor specifically designed to be converted into a one-dimensional array of signals;
B. A small information processing unit on the information processing surface that converts different areas of the information processing surface to have different functions;
C. A multi-level system or neuron that can reversibly switch the conducting state of the surface between possible conducting states and remember the state longer than the time that the equilibrium state spans the entire surface. Can be updated any number of times (RAM);
D. A multi-level system or neuron (ROM) that stays in the same state permanently once switched to one of the possible multi-level states. The vertical electrode is a structure having a nanoscale width and a microscale length, like a probe with a single atom tip, in which some probes in an electrode system are: The vertical / horizontal processor according to claim 1, comprising A or B.
A. A probe with a single atom tip such that a solution point is considered to be a single atom tip,
B. Multiple atom tips in a single electrode unit such that the solution point is considered to be the average response of the sum of outputs at all atom tips in the single electrode unit. The signal input is connected to a neural node controller, where all input signals are divided in parallel into different units preceding a vertical and horizontal processor, and the following A, B, C, 9. A vertical / horizontal processor according to any of claims 1 to 8, wherein the vertical and horizontal processor switches between each unit including D or E.
A. Unit that can change the terminal to take the ground connection,
B. A unit for changing the arranged identical input signals into an arrangement in a different order;
C. A unit that passes the arranged input signals through different forms of the processor in parallel to produce a combined output signal;
D. A unit for replacing a part of the input signal with a pulsed array source;
E. A unit that passes an input signal through a channel where it matches the input impedance of the entire information processing surface by converting the input signal.   The number of ground connections for the p × q inputs varies from 1 to pq−1 to process the same set of arranged inputs, and defines the ground connection. The operation nodes are determined by the above, and after the neural network is determined by the nodes and learned, and information processing rules are found, these nodes can be used in various situations that require special information processing. 10. A vertical and horizontal processor according to any of claims 1 to 9, wherein:   On the horizontal surface in the center of the surrounding electrode and containing the multilevel system or neuron, multiple input signals are given vertically from above, and the output signal is taken horizontally through these electrodes Vertical and horizontal processor containing a pair of templates. The vertical multiple input electrode has a flat or spherical front edge that generates a local bias over a wide area on the information processing surface, and the front edge area of the vertical electrode includes the following A, B, and C: 12. Vertical / horizontal processor according to claim 11.
A. A total area consisting of all individual vertical electrodes covering a certain percentage of the information processing surface, from which a total area in which signal input operation nodes are created for each type of operation,
B. Relational area of bundled electrodes or individual vertical electrodes to variously adjust the control of individual signal inputs on the surface given the final solution,
C. The form of the front edge corrected to adjust the potential distribution of contour lines on the information processing surface. A plurality of vertical and horizontal processors according to any one of claims 1 to 8,
A neural node controller, and
Cluster with connection switch sensor connected in the following A, B and C manner.
A. A part or all of the signal input units of the vertical and horizontal processors are connected to the array of the vertical and horizontal processors, and the remaining signal input units are output from sensors which are free signal input units of the entire system. How to connect to the department,
B. Connect some of its outputs to some of the output switches and connect the remaining outputs to other vertical and horizontal processors;
C. All vacant outputs are connected to a switch, not connected to any signal input in the entire system, but taken vertically as the final cluster output.