JP5179975B2 - Signal processing device - Google Patents

Description

  The present invention relates to a signal processing apparatus that performs equalization processing of a received signal.

  In a signal processing apparatus of a receiver used in a system using single carrier modulation such as PHS (Personal Handyphone System), propagation characteristics are estimated and equalization processing is performed to improve reception characteristics.

  For equalization, an equalizer such as LMS (Least Mean Square) is widely used. An equalizer such as an LMS obtains a difference (equalization error) between a received signal and a reference signal, and updates (feeds back) tap coefficients used for tap calculation in the equalizer so that the equalization error is reduced. However, the deterioration due to the propagation path included in the received signal is reduced.

  However, when the propagation path state fluctuates, an error occurs in the propagation path estimation result, which may deteriorate the reception characteristics.

  For example, in a situation where the propagation path state fluctuates, such as in a fading environment, the propagation path state changes while performing propagation path estimation, reflecting a propagation path state that is older than the propagation path state to be corrected by the equalizer. The equalization processing is performed in the propagation path estimation, and as a result, the reception characteristics may be deteriorated when the equalizer is operated.

  Each tap coefficient in the equalizer obtained by propagation path estimation has a greater equalization error as the level variation of the received signal is larger, and is strongly influenced by the fluctuation. For example, there may be a case where unnecessary noise or the like is superimposed on the received signal that has suddenly changed greatly, and this noise increases the error of the propagation path estimation result.

  Note that a feedback gain (also called a convergence coefficient) is used to calculate the tap coefficient so that the operation of the equalizer does not become unstable due to the update of the tap coefficient. There are also technologies that respond to fluctuations.

For example, Patent Document 1 discloses a conventional technique in which a received signal is first adjusted by an AGC (auto gain controller), and a convergence coefficient is set to 0 with respect to a sudden level fluctuation of the received signal that is not adjusted by the AGC. An adaptive automatic equalizer which is invented with respect to the above and discriminates Gaussian noise and a modulation signal containing a large amount of Gaussian noise and adjusts the convergence coefficient is disclosed.
Japanese Patent Application Laid-Open No. 08-316883

  However, in the conventional technique, the adjustment by the AGC in the previous stage is not performed according to the level of the reception signal, and the adjustment by the level fluctuation of the reception signal is performed only in the subsequent stage of the AGC. Therefore, the influence due to the level fluctuation may not be completely removed.

  In the technique described in Patent Document 1, first, the energy extractor calculates the square of the absolute value of the complex equalization error signal, averages the calculation results, and then sets a comparison value λ that is set in advance. In comparison, the convergence coefficient α is selected or α = 0 is selected. However, in this technique, since the averaging process is performed before the comparison, the accuracy of the gain control is reduced. . Further, in the technique described in Patent Document 1, the reference signal to be compared when calculating the equalization error is determined and determined based on the tap calculation result, but a determination error may occur at the time of this determination. In this respect, the accuracy of gain control may be reduced.

  The present invention has been proposed to solve the above-described problems, and an object of the present invention is to provide a signal processing apparatus capable of performing equalization processing with high accuracy even when the state of the propagation path varies.

  To achieve the above object, a signal processing apparatus according to claim 1 of the present invention includes an amplifier that amplifies a received signal, a first power converter that converts the received signal amplified by the amplifier into a power signal, A first gain adjusting unit that adjusts the gain of the amplifier so that the level of the power signal converted by the first power converter becomes a value within a predetermined range; and the received signal amplified by the amplifier is delayed by a predetermined time. A multiplier group having a plurality of delay units connected in series and a plurality of multipliers for multiplying an input received signal by a tap coefficient, wherein one of the plurality of multipliers is connected to the delay unit A multiplier group connected to the input terminal of the first delay unit of the group of multipliers, and the multiplication result of each of the multipliers of the multiplier group, each of the remaining multipliers connected to each of the output terminals of the delay unit. An adder for adding and outputting the addition result; and the adder A second power converter that converts the addition result output from the second power converter into a power signal, and a difference between the power signal converted by the second power converter and a predetermined reference signal is output as a first difference signal. And a second gain for detecting a fluctuation of the power signal converted by the first power converter and adjusting a gain for obtaining the tap coefficient so as to be a gain corresponding to the detected fluctuation. An adjustment unit; a first difference signal output from the first difference unit; a gain adjusted by the second gain adjustment unit; an addition result output from the adder; and a multiplier of the multiplier group Each of the tap coefficients used in each of the plurality of multipliers is calculated by multiplying each of the received signals input to each of the plurality of multipliers and adding each of the multiplication results to each of the previously calculated tap coefficients. A tap coefficient calculator to perform, Equipped and are configured.

  According to such a configuration, the gain of the amplifier that amplifies the received signal is adjusted according to the power signal obtained by converting the received signal, and the fluctuation of the power signal is obtained by the second gain adjusting unit. Since the gain when calculating the tap coefficient can be adjusted using this, equalization processing can be performed with high accuracy irrespective of propagation path fluctuation.

  Further, in the present invention, the second gain adjustment unit adjusts the gain for obtaining the tap coefficient based on the detection result of the power fluctuation itself without performing the averaging process as in the related art, so that the gain is accurately obtained. Can be adjusted. Furthermore, the reference signal is not determined and determined based on the tap calculation result, but is a predetermined signal, so that it is not affected by the determination error of the determiner in the prior art. Therefore, equalization processing can be performed with high accuracy.

  According to a second aspect of the present invention, the second gain adjustment unit of the signal processing device according to the first aspect includes a power signal delay device that delays the power signal converted by the first power converter for a predetermined time, and the first A second differencer that outputs a signal indicating an absolute value of a difference between a power signal converted by one power converter and a power signal delayed by the power signal delay unit as a signal indicating fluctuation of the power signal; And an adjustment unit that adjusts the gain for obtaining the tap coefficient so as to be a gain corresponding to the signal output from the second differentiator. .

  Thus, the fluctuation | variation of an electric power signal can be calculated | required by calculating | requiring a 2nd difference signal.

  According to a third aspect of the present invention, a smoothing filter that smoothes the signal output from the second differentiator and outputs the smoothed filter to the adjustment unit in the second gain adjustment unit of the signal processing device according to claim 2. Further provided.

  According to such a configuration, the noise of the differential signal is removed, and the gain adjustment in the second gain adjustment unit can be performed with high accuracy.

According to a fourth aspect of the present invention, there is provided a signal processing device that amplifies a received signal, a first power converter that converts a received signal amplified by the amplifier into a power signal, and a signal that is converted by the first power converter. A first gain adjustment unit that adjusts the gain of the amplifier so that the level of the power signal becomes a value within a predetermined range and a plurality of delay devices that delay the reception signal amplified by the amplifier for a predetermined time are connected in series. A multiplier group having a delay group and a plurality of multipliers for multiplying an input received signal by a tap coefficient, wherein one of the plurality of multipliers is connected to an input terminal of a first delay unit of the delay group A multiplier group in which each of the remaining multipliers is connected to each of the output terminals of the delay unit, and an adder for adding the multiplication results of the multipliers of the multiplier group and outputting the addition result And the addition result output from the adder as a power signal A second power converter for converting a differential unit for outputting a difference between a predetermined reference signal and the converted power signal at the second power converter as a differential signal, the differential signal outputted from said differentiator an absolute value converter for converting the absolute value signal indicating the absolute value of the difference and a ratio arithmetic unit for obtaining the ratio of the reference signal of the converted absolute value signal by the absolute value converter, a pre-Symbol tap coefficients A second gain adjusting unit that adjusts a gain to be obtained so as to be a gain corresponding to the ratio determined by the ratio calculator; a differential signal output from the difference unit; and a second gain adjusting unit. Multiplying the adjusted gain, the addition result output from the adder, and each of the received signals input to each of the multipliers of the multiplier group, and each of the multiplication results is a previously calculated tap Add to each of the coefficients The Rukoto is configured to include a tap coefficient calculating unit for calculating each of the tap coefficients used by each of the plurality of multipliers.

According to such a configuration, the gain of the amplifier that amplifies the received signal is adjusted in accordance with the power signal obtained by converting the received signal, and the difference signal output from the differentiator is converted to the absolute value of the difference. It is possible to obtain the ratio of the absolute value signal with respect to the reference signal, and to adjust the gain when calculating the tap coefficient based on this, so that the accuracy is high regardless of the propagation path fluctuation. Can be processed.

In the present invention, the second gain adjustment unit does not perform the averaging process as in the prior art, and the gain for obtaining the tap coefficient is an absolute value signal converted from the difference signal output from the differentiator. to adjust based on the percentage relative to the reference signal, can be accurately gain adjustment. Furthermore, the reference signal is not determined and determined based on the tap calculation result, but is a predetermined signal, so that it is not affected by the determination error of the determiner in the prior art. Therefore, equalization processing can be performed with high accuracy.

  For example, it can be estimated that the power fluctuation of the received signal is large if the ratio of the absolute value signal converted from the difference signal to the reference signal is large, and the power fluctuation of the received signal is small if the ratio is small.

According to a fifth aspect of the present invention, the reference signal is set in advance as a power of 2, and the first gain adjustment unit is configured so that the average power of the received signal corresponds to the power of the reference signal. Gain adjustment is performed, and the ratio calculator obtains the ratio by bit-shifting the absolute value signal by a power of 2 of the reference signal.

  According to such a configuration, the ratio can be obtained without providing a division circuit having a large circuit scale.

  As described above, according to the present invention, there is an effect that equalization processing can be performed with high accuracy even if the state of the propagation path varies.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings.

  [First Embodiment]

  In the present embodiment, a signal processing apparatus provided in a receiver of a system using single carrier modulation of PHS (Personal Handyphone System) will be described as an example. In the PHS system, one frame is composed of 4 slots each for transmission and reception. Here, description will be made on the assumption that slots at the same time position are allocated while the line is connected.

  FIG. 1 is a diagram illustrating a configuration example of a signal processing device according to the first embodiment. The signal processing apparatus according to the present embodiment includes a gain variable amplifier (VGA) 10, an A / D converter (ADC) 12, a timing synchronization circuit 14, an equalizer 16, a power detector 18, an auto gain controller (AGC) 20, A D / A converter (DAC) 22 and a gain control unit 24 are provided.

  An analog reception signal received from the outside is input to the VGA 10. The VGA 10 amplifies the input received signal with a gain set by the AGC 20. The VGA 10 includes, for example, an RF (high frequency) amplifier, a mixer, an IF (intermediate frequency) amplifier, and the like.

  The received signal amplified by the VGA 10 is input to the ADC 12. The ADC 12 converts the input received signal from analog to digital.

  The timing synchronization circuit 14 receives the received signal converted into digital by the ADC 12. The timing synchronization circuit 14 converts the input received signal into a signal cycle to be demodulated. Here, the received signal converted into a desired signal period is input to the equalizer 16 and the power detector 18.

  The power detector 18 detects power by converting the input received signal into a power signal, and inputs the power signal to the AGC 20 and the gain control unit 24.

  In the present embodiment, power detection is performed by the power detector 18 after processing by the timing synchronization circuit 14, but power detection may be performed before the timing synchronization circuit 14. Since the timing of this power detection depends on the structure of the power detector 18 and does not depend on the effect of the present invention, further explanation is omitted here.

  Based on the power signal input from the power detector 18, the AGC 20 allows a received signal having a level within a predetermined range to be input to the equalizer 16 regardless of the state of the reception level when the received signal is received. A gain is obtained, and a gain signal indicating the gain is input to the DAC 22. The DAC 22 converts the input gain signal from digital to analog and supplies the converted signal to the VGA 10. The VGA 10 amplifies the received signal with the gain indicated by the given gain signal. Thereby, even if a sudden level fluctuation occurs in the received signal, the level between the slots of the received signal is controlled so as to approach a desired level.

  The equalizer 16 is an adaptive filter such as LMS (Least Mean Square) that reduces the deterioration due to the propagation path included in the received signal by extracting and feeding back the error of the temporarily determined signal. FIG. 2 shows the configuration of the equalizer 16.

The equalizer 16 includes n-1 delay devices 40 ₁ to 40 _n−1 connected in series, n tap arithmetic units 42 _{1 to} 42 _n , an adder 44 (for example, a complex adder), and power conversion. A comparator 46, a comparator 48, a multiplier 50, and a complex multiplier 52. Since each of the delay units 40 ₁ to 40 _n−1 has the same configuration, hereinafter, when they are described without distinction, the last symbol is omitted and simply referred to as the delay unit 40. In addition, since each of the tap calculators 42 _{1 to} 42 _n has the same configuration, in the following description, when they are described without being distinguished from each other, the last symbol is omitted and referred to as a tap calculator 42.

  Each of the delay units 40 is connected in series, delays the reception signal input from the timing synchronization circuit 14 by one frame, and outputs the delayed signal to the subsequent delay unit 40 and the tap calculator 42.

The leading tap calculator 42 ₁ is connected to the input terminal of the leading delay unit 40 ₁ . The other tap calculators 42 _{2 to} 42 _n are connected to the output terminals of the delay units 40 ₁ to 40 _n−1 . Each of the tap arithmetic unit 42 obtains the tap coefficients by using a multiplication result of complex multiplier 52, the corresponding time of the received signal (the beginning of the tap arithmetic unit 42 ₁ is input from the delay unit 40, the timing synchronization circuit 14) and the obtained tap coefficient are complex-multiplied.

  Here, the configuration of the tap calculator 42 will be described. The tap calculator 42 includes a complex multiplier 54, an integrator 56, and a complex multiplier 58.

The complex multiplier 54, and the received signal at time corresponding input from the delay device 40 (for the beginning of the tap arithmetic unit 42 _1, the received signal without the delay that is input from the timing synchronization circuit 14), a complex multiplier The multiplication result of 52 is subjected to complex multiplication and output to the integrator 56.

  The integrator 56 adds the calculation result of the complex multiplier 54 to the previously calculated tap coefficient, and outputs the addition result to the complex multiplier 58 as a new tap coefficient. That is, the integrator 56 updates the tap coefficient by cumulatively adding the operation results of the complex multiplier 54.

Complex multiplier 58, a reception signal of the corresponding time input from the delay device 40 (for the beginning of the tap arithmetic unit 42 _1, the received signal without the delay that is input from the timing synchronization circuit 14), the integrator 56 The input tap coefficient is complex-multiplied and output to the adder 44.

  The adder 44 outputs a signal obtained by adding the calculation results input from the tap calculators 42.

  The power converter 46 converts the signal input from the adder 44 into a power signal and outputs it to the comparator 48.

  The comparator 48 obtains a difference between a preset reference signal and the power signal input from the power converter 46 and outputs a signal indicating the difference to the multiplier 50. The difference obtained here is called an equalization error, and a signal indicating the equalization error is called an equalization error signal.

  The multiplier 50 multiplies the equalization error signal input from the comparator 48 by the feedback gain provided from the gain control unit 24 and outputs the result to the complex multiplier 52.

  The complex multiplier 52 performs complex multiplication on the multiplication result input from the multiplier 50 and the addition result input from the adder 44 and outputs the result to each tap calculator 42.

  Next, the gain control unit 24 that gives a feedback gain to the equalizer 16 will be described. The gain control unit 24 includes a delay unit 30, a difference unit 32, a filter 34, a selector 36, and a table 38.

  The delay unit 30 delays the power signal input from the power detector 18 by one frame.

  The subtractor 32 calculates the difference between the power signal input from the power detector 18 and the power signal of the previous frame, and outputs a difference signal indicating the absolute value of the difference. Here, a power fluctuation that cannot be adjusted by the AGC 20 is detected. Specifically, in the control of the AGC 20, the level adjustment between the slots is performed (see FIGS. 3A and 3B), but the level fluctuation may still remain in each slot ( (See FIG. 3C). Therefore, the difference calculator 32 detects such a power fluctuation that has not been adjusted by the AGC 20.

  The filter 34 smoothes the difference signal output from the differentiator 32. Thereby, the noise of the difference signal is removed, and the gain control in the selector 36 can be performed with high accuracy.

  When the difference signal smoothed by the filter 34 is input, the selector 36 selects a gain value corresponding to the difference signal from the table 38, and uses the selected gain value as a feedback gain. This is given to the multiplier 50.

  The table 38 is composed of a nonvolatile memory. The table 38 is a lookup table in which the difference signal value and the feedback gain value are stored in association with each other, and is referred to by the selector 36.

  More specifically, the table 38 stores a feedback gain value that is set in advance as an effective value that improves the accuracy of the propagation path estimation result for a difference signal that is equal to or smaller than a predetermined value. For a difference signal larger than a predetermined value, a value smaller than the predetermined feedback gain or “0” is stored as a feedback gain value.

  For a difference signal larger than a predetermined value, a gain value that becomes smaller as the difference signal becomes larger may be stored in the table 38 as a feedback gain value instead of a constant value.

  When the difference signal is less than or equal to a predetermined value, it is estimated that the incoming received signal has a small power fluctuation and no strong fading has occurred. In such a case, the selector 36 selects a feedback gain value determined in advance as an effective value for improving the accuracy of the propagation path estimation result from the table 38 and supplies the selected value to the multiplier 50. As a result, the tap coefficient is updated as usual, and each of the tap calculators 42 performs an operation using the updated tap coefficient.

  When the difference signal exceeds the predetermined value, it is estimated that the incoming received signal has a large power fluctuation and that strong fading has occurred. In such a case, the selector 36 selects a feedback gain smaller than normal, or “0”, from the table 38 and supplies it to the multiplier 50. By reducing the feedback gain, it is possible to suppress the tap coefficient from being greatly changed. By setting the feedback gain to 0, the multiplication result in the multiplier 50 is also 0, so that the complex multiplication of the complex multiplier 58 is performed with the same tap coefficient as the previously calculated tap coefficient (without changing the tap coefficient). Done. Therefore, it is possible to reduce the influence of a signal including sudden noise or the like.

  As described above, since the gain control unit 24 is provided and the feedback gain is adaptively changed with respect to the received power fluctuation due to fading, the effect of improving the reception characteristics by the equalizer can be obtained.

  In the above-described embodiment, an example in which the gain is selected from the table 38 has been described. However, the present invention is not limited to this. For example, the selector 36 is provided with a comparison circuit that compares the input difference signal with a predetermined value, and the difference is calculated. When the signal is less than or equal to a predetermined value, the feedback gain value predetermined as an effective value for improving the accuracy of the propagation path estimation result is output to the multiplier 50 of the equalizer 16, and the difference signal exceeds the predetermined value. In such a case, a constant gain value (for example, “0”) smaller than the predetermined feedback gain value may be output. That is, it is good also as a structure which does not use a table.

  Moreover, although the case where the delay unit 30 delays the result of power detection input from the power detector 18 by one frame has been described, it may be delayed by a plurality of frames.

  [Second Embodiment]

  In the first embodiment, the example in which the feedback gain is obtained based on the received signal before being input to the equalizer 16 has been described. However, in the second embodiment, the comparator 48 in the equalizer 16 is used. An example of obtaining the feedback gain based on the comparison result will be described.

  In the present embodiment, a signal processing apparatus is configured by providing a gain control section 60 shown in FIG. 4 instead of the gain control section 24 of the signal processing apparatus of the first embodiment. The power signal converted by the power detector 18 is input to the AGC 20 but is not input to the gain control unit 60. The other configuration is the same as that of the first embodiment.

  FIG. 4 is a diagram illustrating a configuration of the equalizer 16 and the gain control unit 60 according to the second embodiment. As described above, the configuration of the equalizer 16 is the same as that of the first embodiment.

  The gain control unit 60 according to the present embodiment includes an absolute value converter 62, a scaler 64, a selector 66, and a table 68.

  The absolute value converter 62 converts the equalization error signal output from the comparator 48 in the equalizer 16 into an absolute value signal indicating the absolute value of the equalization error.

  The scaler 64 obtains the ratio (hereinafter referred to as relative value) of the absolute value signal converted by the absolute value converter 62 to the reference signal. Specifically, the relative value is obtained by dividing the absolute value signal by the reference signal. A relative value signal indicating the relative value is output to the selector 66.

  When the relative value signal is input, the selector 66 selects a gain value corresponding to the relative value signal from the table 68 and supplies the selected gain value as a feedback gain to the multiplier 50 of the equalizer 16. .

  The table 68 is composed of a nonvolatile memory. The table 68 is a lookup table that stores relative values and feedback gain values in association with each other, and is referred to by the selector 66.

  More specifically, the table 68 stores a feedback gain value that is set in advance as an effective value that improves the accuracy of the propagation path estimation result for a relative value that is equal to or less than a predetermined value. For a relative value larger than a predetermined value, a value smaller than the predetermined feedback gain or “0” is stored as a feedback gain value.

  For the relative value larger than the predetermined value, the feedback gain value may be stored in the table 68 as a value that becomes smaller as the relative value becomes larger than the constant value.

  When the relative value is less than or equal to the predetermined value, the incoming received signal is estimated to be a signal with less unnecessary power such as sudden noise. In such a case, the selector 66 selects a predetermined feedback gain value from the table 68 as an effective value that improves the accuracy of the propagation path estimation result, and provides it to the multiplier 50. As a result, the tap coefficient is updated as usual, and each of the tap calculators 42 performs an operation using the updated tap coefficient.

  When the relative value exceeds a predetermined value, the incoming received signal is estimated to be a signal that requires a large amount of unnecessary power such as sudden noise and increases the error of the propagation path estimation result. In such a case, the selector 66 selects a feedback gain smaller than normal, or “0”, from the table 68 and supplies it to the multiplier 50. It is possible to suppress the tap coefficient from being greatly changed. By setting the feedback gain to 0, the multiplication result in the multiplier 50 is also 0, so that the complex multiplication of the complex multiplier 58 is performed with the same tap coefficient as the previously calculated tap coefficient (without changing the tap coefficient). Done. Therefore, it is possible to reduce the influence of a signal including sudden noise or the like.

  As described above, the gain control unit 60 is provided to adaptively change the feedback gain against large power fluctuations due to sudden signal fluctuations or fading, etc., thus improving the reception characteristics of the equalizer Effect is obtained.

  In the above-described embodiment, the example of selecting the gain from the table 68 has been described. However, the present invention is not limited to this. For example, a comparison circuit that compares the relative value with a predetermined value is provided in the selector 66 and the relative value is predetermined. When the value is equal to or smaller than the value, a feedback gain value predetermined as an effective value for improving the accuracy of the propagation path estimation result is output to the multiplier 50 of the equalizer 16, and the relative value exceeds the predetermined value. Alternatively, a constant gain value (for example, “0”) smaller than the predetermined feedback gain value may be output. That is, it is good also as a structure which does not use a table.

  The scaling device 64 can be configured by a division circuit that divides the absolute value signal by the reference signal. However, if there is a concern that the division circuit becomes large, the signal processing circuit is configured as follows. You may make it do.

  First, the reference signal is set in advance as a power of 2. Then, the level of the received signal is adjusted by performing gain control of the VGA 10 with the AGC 20 in the previous stage so that the average power of the received signal input to the equalizer 16 corresponds to the reference signal. Further, the scaler 64 is composed of a shift circuit that bit-shifts the absolute value signal input from the absolute value converter 62 by a power of 2 of the reference signal.

  With such a configuration, the relative value between the absolute value signal and the reference signal can be obtained without providing a divider circuit with a large circuit scale, and the feedback gain can be adaptively changed as described above. .

It is a figure which shows the structural example of the signal processing apparatus of 1st Embodiment. It is a figure which shows the structure of the equalizer of 1st Embodiment. It is explanatory drawing explaining the level fluctuation | variation adjustment by AGC. It is a figure which shows the structure of the equalizer and gain control part of 2nd Embodiment.

Explanation of symbols

10 VGA
12 ADC
14 Timing synchronization circuit 16 Equalizer 18 Power detector 20 AGC
22 DAC
24 gain control unit 30 delay unit 32 difference unit 34 filter 36 selector 38 table 40 delay unit 42 tap calculator 44 adder 46 power converter 48 comparator 50 multiplier 52 complex multiplier 54 complex multiplier 56 integrator 58 complex Multiplier 60 Gain control unit 62 Absolute value converter 64 Scaling unit 66 Selector 68 Table

Claims (5)

An amplifier for amplifying the received signal;
A first power converter that converts a received signal amplified by the amplifier into a power signal;
A first gain adjustment unit that adjusts the gain of the amplifier so that the level of the power signal converted by the first power converter becomes a value within a predetermined range;
A group of delay units connected in series with a plurality of delay units for delaying the reception signal amplified by the amplifier for a predetermined time;
A multiplier group having a plurality of multipliers for multiplying an input received signal by a tap coefficient, wherein one of the plurality of multipliers is connected to an input terminal of a first delay unit of the delay group; A multiplier group in which each of the multipliers is connected to each of the output terminals of the delay unit;
An adder for adding the multiplication results of the multipliers of the multiplier group and outputting the addition result;
A second power converter that converts the addition result output from the adder into a power signal;
A first differencer that outputs a difference between a power signal converted by the second power converter and a predetermined reference signal as a first difference signal;
A second gain adjusting unit that detects a fluctuation of the power signal converted by the first power converter and adjusts a gain for obtaining the tap coefficient so as to be a gain corresponding to the detected fluctuation;
The first difference signal output from the first differentiator, the gain adjusted by the second gain adjustment unit, the addition result output from the adder, and the multiplier of the multiplier group are input to each of the multipliers. A tap coefficient calculation that calculates each of the tap coefficients used in each of the plurality of multipliers by multiplying each of the received signals and adding each of the multiplication results to each of the previously calculated tap coefficients. And
A signal processing apparatus comprising: The second gain adjustment unit;
A power signal delay device for delaying the power signal converted by the first power converter for a predetermined time;
A second subtractor for outputting a signal indicating an absolute value of a difference between the power signal converted by the first power converter and the power signal delayed by the power signal delay as a signal indicating fluctuation of the power signal; ,
An adjustment unit for adjusting a gain for obtaining the tap coefficient so as to be a gain corresponding to a signal output from the second differentiator;
The signal processing device according to claim 1, comprising: The signal processing apparatus according to claim 2, wherein the second gain adjustment unit is further provided with a smoothing filter that smoothes the signal output from the second differentiator and outputs the smoothed signal to the adjustment unit. An amplifier for amplifying the received signal;
A first power converter that converts a received signal amplified by the amplifier into a power signal;
A first gain adjustment unit that adjusts the gain of the amplifier so that the level of the power signal converted by the first power converter becomes a value within a predetermined range;
A group of delay units connected in series with a plurality of delay units for delaying the reception signal amplified by the amplifier for a predetermined time;
A multiplier group having a plurality of multipliers for multiplying an input received signal by a tap coefficient, wherein one of the plurality of multipliers is connected to an input terminal of a first delay unit of the delay group; A multiplier group in which each of the multipliers is connected to each of the output terminals of the delay unit;
An adder for adding the multiplication results of the multipliers of the multiplier group and outputting the addition result;
A second power converter that converts the addition result output from the adder into a power signal;
A differencer that outputs a difference between the power signal converted by the second power converter and a predetermined reference signal as a difference signal;
An absolute value converter that converts the difference signal output from the difference unit into an absolute value signal indicating an absolute value of the difference;
A ratio calculator for obtaining a ratio of the absolute value signal converted by the absolute value converter to the reference signal;
A gain for determining the pre-Symbol tap coefficients, and the second gain adjustment section that adjusts so that the gain corresponding to the ratio determined by the ratio calculator,
The difference signal output from the difference unit, the gain adjusted by the second gain adjustment unit, the addition result output from the adder, and the received signal input to each multiplier of the multiplier group A tap coefficient calculation unit that calculates each of the tap coefficients used in each of the plurality of multipliers by multiplying each of the multiplication results with each of the previously calculated tap coefficients,
A signal processing apparatus comprising: The reference signal is set in advance as a power of 2,
The first gain adjustment unit adjusts the gain of the amplifier so that the average power of the received signal corresponds to the power of the reference signal,
The signal processing apparatus according to claim 4 , wherein the ratio calculator obtains the ratio by bit-shifting the absolute value signal by a power of 2 of the reference signal.

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