JP5168869B2 - ReRAM - Google Patents

Description

  The present invention relates to a ReRAM in which the arrangement structure of a memory cell composed of variable resistance elements, that is, a ReRAM (resistive random access memory) element, is improved to cope with further miniaturization of a memory cell selection transistor.

  Conventionally, a system LSI in which a CMOS logic circuit and a memory are mixedly mounted is widely used. In this case, the memory is usually built in a semiconductor layer stacked on a layer in which a memory cell selection transistor formed of a CMOS circuit is formed.

In general, the size of the memory cell is defined by the minimum processing dimension F, that is, the half pitch of the first layer metal wiring. For example, in the case of a ReRAM element of 1 memory cell selection transistor and 1 variable resistance element (1T1R), the design is basically made based on the design rules of the CMOS transistor so that the memory cell size is 8F ² . .

  FIG. 4 is a cutaway side view showing a main part of a conventional ReRAM. In FIG. 4, 1 is a gate (= word line WL) of a memory cell selection transistor, 2 is an insulating film, 3 is a conductive plug, and 4 is a 0 layer. Eye metal wiring, 5 is an insulating film, 6 is a lower electrode contact, 7 is a ReRAM element manufactured using transition metal oxide (TMO), 8 is an insulating film, 9 is an upper electrode contact, and 10 is a first electrode contact. The first-layer metal wiring (= bit line BL) and GND indicate ground lines (see, for example, Non-Patent Document 1 or Patent Document 1). Note that the “0th layer” in the 0th layer metal wiring 4 is a display that is based on faithful transcription of the literature, and is generally “first layer”.

  In recent years, the miniaturization of CMOS devices is further progressing, and there is a concern that the memory cell miniaturization cannot catch up with the miniaturization of the transistor after the 32 nm generation when the half pitch of the first layer metal wiring is used as a reference. is there.

FIG. 5 is a cutaway side view showing the main part of the ReRAM for explaining a problem that occurs when the memory cell selection transistor is miniaturized. The parts indicated by the same symbols as those used in FIG. 4 are the same or the same. are those representing the portion of the effect, also, M1 represents a first-layer metal wiring, P _H is the half pitch of the first-layer metal wirings M1, G _R the distance ReRAM element 7, BL is a bit line, respectively ing.

In the ReRAM shown, by applying the processing rule of the memory cell selection transistors, for example, when laying out the half pitch P _H indicated by an arrow as 32 nm, the spacing G _R of the ReRAM element 7 turned processing rule violation End up. In general, since it is difficult to process compared to the ReRAM element 7 is normally metal wires, the spacing G _R is required to take a large.

Conversely, processing the distance G _R of the ReRAM device 7 rules, for example, when adapted for 100nm in half pitch, in the portion of the memory cell select transistor, sparse layout, i.e., becomes much wasted space .

  6A and 6B are explanatory views of a main part showing a ReRAM configured by applying a processing rule to the interval between ReRAM elements. FIG. 6A is a cut side view of the main part, and FIG. 6B is a main part plane of a memory cell array composed of ReRAM elements. (C) shows the plane of the principal part of the memory cell selection transistor array, and the parts designated by the same symbols as those used in FIGS. 4 and 5 represent the same or equivalent parts. SL denotes a ground (GND) line, WL denotes a word line, 11 denotes a column control circuit, and 12 denotes a connection region. The column-related control circuit 11 includes a read circuit, a write circuit, a column selector, and the like.

In the figure, since the dimensional relationship between the ReRAM element and the memory cell selection transistor is expressed relatively accurately, when processing is performed by applying a processing rule to the interval G _R between the ReRAM elements, the memory cell selection transistor array has a large size. Let's see that there is a void.
JP 2005-25914 A I. G. Baek et al. , “Highly scalable non-volatile resilient memory using simple binary drive by asymmetry unipolar voltage pulses”, Tech. Digest IEDM 2004, p. 587

  In the present invention, by applying a simple modification to the arrangement structure of electrodes (vias) and ReRAM elements in ReRAM, the memory cell selection transistor array to be miniaturized is processed by applying a required processing rule, and The ReRAM element can be processed by applying another processing rule so that the interval between the ReRAM elements does not violate the rule.

In the ReRAM according to the present invention, a multilayer metal wiring layer formed on the memory cell selection transistor, and a ReRAM element that is in an upper layer portion of the multilayer metal wiring layer and connected to the memory cell selection transistor are provided. provided, the element pitch of the ReRAM device, the lower layer portion of the multilayer metal wiring layer connected to the ReRAM device via a wire located in the upper part is connected to the source or drain of the memory cell select transistor Basically, the pitch is wider than the pitch of existing wiring.

  By adopting the above means, even if the ReRAM element is larger than the memory cell selection transistor, the ReRAM element array can be processed without difficulty according to an appropriate processing rule, and the entire memory can be processed. As a result, the size can be reduced.

  As described above, an area in the memory sufficient to incorporate a ReRAM element larger than the memory cell selection transistor is an interval between vias formed in each layer between the memory cell selection transistor and the ReRAM element in the upper wiring layer. Therefore, it is created by taking means for gradually increasing the interval between wirings, and the area that is newly required by performing the incremental increase uses the empty space above the peripheral circuit. In the case of the embedded memory, the wiring layer extending on the memory area among the 4th to 10th metal wiring layers for constituting the logic of the system LSI is a dummy. The system LSI can be miniaturized by using the connection wiring layer.

  In the present invention, the ReRAM element is fabricated in the upper layer portion of the metal wiring layer, and the ReRAM element larger than the memory cell selection transistor is arranged. In order to enable this, the memory cell selection transistor and the ReRAM element are arranged. When the metal wiring and the via (Via) are connected in the period up to the metal wiring layer connecting the two, the interval between the adjacent vias, that is, the interval between the adjacent ReRAM elements is increased.

FIG. 1 is a sectional side view of an essential part of a ReRAM for explaining the principle of the present invention. The parts indicated by the same symbols as those used in FIGS. 4 to 6 represent the same or equivalent parts. Then, M1, M2, M3 first layer is the second layer, the third layer metal wiring, V1 to V5 are first to fifth vias, P _L is the wiring pitch, P _R is ReRAM device pitch Respectively. The fourth via V4 is a lower electrode of the ReRAM element, and the fifth via V5 is an upper electrode of the ReRAM element.

In the figure, since the distance between the fourth via V4 is a lower electrode of the ReRAM device are enlarged in comparison to the distance between the third via V3, is also expanded in the same manner the pitch P _R of the ReRAM element 7, the processing rules Has cleared.

  In this case, since it is impossible to carry out the above-mentioned means by collecting all the ReRAM elements in the chip, the ReRAM element array is divided into small groups of blocks and arranged in the chip, and the peripheral areas of the respective blocks are arranged. Peripheral circuits such as column control circuits and connection areas are built in, and the via spacing is increased as each wiring layer in the multilayer wiring layer becomes an upper layer, which is newly required to arrange the ReRAM elements in accordance with the processing rules. The enlarged region is obtained on the peripheral circuit.

  Even if this configuration, that is, the region where the ReRAM element array is formed extends to the peripheral circuit, no problem occurs. Especially, in the case of a system LSI embedded memory, the ReRAM part usually includes the peripheral circuit. It is sufficient to use about 3 metal wiring layers, and logic requires about 4 to 10 metal wiring layers. These metal wiring layers are dummy wirings on the ReRAM portion. Since the current pattern is in the form of a pattern, the area where the ReRAM element array is formed extends to the peripheral circuit, and even if it enters a layer formed for use in logic, it affects other circuits. There is nothing to give.

  In other words, the design rule of the memory cell selection transistor which is 1T in the 1T1R memory cell in the ReRAM is different from the design rule of the ReRAM element which is 1R. Conventionally, it becomes possible to form a memory cell on a region where a peripheral circuit of the memory cell array has been formed.

  According to the present invention, even if the size of the ReRAM element is increased to some extent, the area of the ReRAM can be kept small overall, and the memory cell is formed in a later process. There is also a secondary advantage that it is difficult to receive.

  2A and 2B are main part explanatory views showing the ReRAM according to the first embodiment of the present invention, in which FIG. 2A is a cut side view of the main part, FIG. 2B is a main part plane of a memory cell array composed of ReRAM elements, and FIG. Indicates the principal planes of the memory cell selection transistor array, and the parts designated by the same symbols as those used in FIGS. 1 and 4 to 6 represent the same or equivalent parts.

  The illustrated ReRAM represents approximately half a block as viewed from the center C, and the connection between the metal wiring and the via is gradually extended from the center C in the peripheral direction, and a peripheral circuit is configured in the peripheral area of the block. A region in which about 2 to 3 layers of a CMOS transistor region and a metal wiring layer can be provided is secured.

  In the illustrated ReRAM for one block, there are eight word lines WL (four are shown), eight ground lines BL (four are shown), and metal wirings M1 to M5. This is a 64-bit memory cell array block consisting of five layers to which symbols are assigned.

  As is apparent from the figure, the connection point between the metal wiring and the via extends from the metal wiring M2 to the metal wiring M3 in the peripheral direction, and expands from the via V2 to V4 as the upper layer. . The column-related control circuit 11 is formed using up to three layers of metal wiring, and is coupled to the end of the bit line BL in the connection region 12.

  FIG. 3 is a cutaway side view showing an essential part of a ReRAM according to a second embodiment of the present invention, showing an example in which ReRAM elements are stacked, and is used in FIGS. 1 and 2 and FIGS. The parts indicated by the same symbols as those shown represent the same or equivalent parts.

  The second embodiment is different from the first embodiment in that two layers of metal wirings M6 and M7 are added, and the ReRAM element array has a total of three layers. Even if such a configuration is adopted, in the case of a system LSI mixed memory, as described above, the wiring in the logic exists only as a dummy above the ReRAM element array, so there is no problem. Does not happen.

It is a principal part cutting side view of ReRAM explaining the principle of this invention. FIG. 3 is a main part explanatory diagram illustrating a ReRAM that is Embodiment 1. It is a principal part cutting side view showing ReRAM which is Example 2. FIG. It is a principal part cutting side view showing the conventional ReRAM. It is a principal part cutting side view showing ReRAM for demonstrating the problem which arises when reducing in size. It is principal part explanatory drawing showing ReRAM comprised by applying a process rule to the space | interval of a ReRAM element.

Explanation of symbols

M1 to M7 Metal wiring V1 to V5 Via P _L Wiring pitch P _R ReRAM element pitch WL Word line SL Ground (GND) line BL Bit line 7 ReRAM element 11 Column (column) system control circuit 12 Connection region

Claims (3)

A multilayer metal wiring layer formed on the memory cell selection transistor;
A ReRAM element in an upper layer portion of the multilayer metal wiring layer and connected to the memory cell selection transistor;
Element pitch of the ReRAM device is located in the lower portion of the multilayer metal wiring layer connected to the ReRAM device via a wire located in the upper part is connected to the source or drain of the memory cell select transistor A ReRAM characterized in that the pitch is wider than the pitch of wiring. In the multilayer metal wiring layer formed on the memory cell selection transistor,
ReRAM of claim 1 in which the wiring layer interposed between reaching the upper metal wiring layer, wherein the ReRAM device from the lower metal wiring layer is formed is characterized by comprising formed by increasing the pitch. And ReRAM peripheral circuit formed in the in the lower metal wiring layer in the multilayer metal wiring layer,
ReRAM of claim 1 or claim 2 part is characterized by including a ReRAM element spread on the peripheral circuit.

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