JP5157336B2 - Power semiconductor element evaluation method and evaluation apparatus - Google Patents

Description

  The present invention relates to a power semiconductor element evaluation method and an evaluation apparatus capable of estimating current-voltage characteristics when the power semiconductor element is not self-heating.

  FIG. 11 is a longitudinal sectional view showing a main part of a p-channel LDMOSFET (Lateral Diffused Metal Oxide Semiconductor Field Effect Transistor: hereinafter abbreviated as LDMOS) which is an example of a power semiconductor element.

  The LDMOS 4 is formed on an SOI (Silicon On Insulator) substrate 40. The SOI substrate 40 includes a support substrate 41 having a thickness of several hundred μm, a buried oxide film (silicon oxide) 42 formed in the surface region, and an element formation layer 43 formed in the surface region. Further, the element formation layer 43 includes a p layer 4a formed in the surface region of the buried oxide film 42, a p well 4b formed therein, a p type diffusion layer 4i formed therein, and a p layer. A channel n-well 4h formed in 4a, an n-type diffusion layer 4e for taking the potential of the channel n-well 4h, a p-type diffusion layer 4f formed in the channel n-well 4h, and a p-well LOCOS (Local Oxidation of Silicon) oxide film 4j formed in the surface region of 4b.

Further, the element formation layer 43 includes a gate oxide film 4k formed in the surface region of the channel n well 4h, a gate electrode 4g formed on the gate oxide film 4k, a p-type diffusion layer 4f, and an n-type diffusion. It has a source electrode 4s formed on the surface region of the layer 4e and a drain electrode 4d formed on the surface region of the p-type diffusion layer 4i. As described above, the LDMOS 4 has a structure in which the respective electrodes are arranged in the horizontal direction.
The LDMOS 4 operates using the p-type diffusion layer 4f as a source region, the p-type diffusion layer 4i as a drain region, and the p-well 4b under the LOCOS oxide film 4j as a drift region.

FIG. 12 shows a source-drain current (hereinafter also referred to as drain current) when the LDMOS shown in FIG. 11 does not generate heat (no heat generation) and when it generates heat (with heat generation) (Id) It is a graph which shows the voltage between drains (henceforth drain voltage) (Vd) characteristic. Although not shown, the LDMOS shown in FIG. 11 has a drain current (Id), a gate-source voltage (hereinafter referred to as a gate) when heat is not generated (no heat generation) and when heat is generated (heat is generated). (Also referred to as voltage) (Vg) characteristics also exist.
In the following description, the term “current / voltage characteristic” refers to both the drain current-drain voltage characteristic and the drain current-gate voltage characteristic.
As shown in the figure, the drain current Id increases as the drain voltage Vd increases, and eventually becomes saturated.

  However, as shown in FIG. 12, when the LDMOS is generating heat, the drain current Id is greatly reduced as compared with the case where the LDMOS is not generating heat. Further, the degree of decrease differs depending on the drain voltage Vd, and the degree of decrease is particularly large when the drain voltage Vd is high. In particular, the higher the gate-source voltage (hereinafter referred to as the gate voltage) Vg, the more the drain Id current drops due to heat generation.

  In particular, an LDMOS formed on an SOI substrate, such as the LDMOS 4 shown in FIG. 11, has a buried oxide film 42, so that heat generated in the LDMOS 4 is likely to be trapped inside the substrate and the temperature is likely to rise. The degree of decrease in the drain current Id described above is further increased.

  Therefore, even if the current / voltage characteristics of the LDMOS in the self-heated state are measured, the measurement results greatly deviate from the current / voltage characteristics in the non-heated state, so the data can be used for circuit design. Can not. Specifically, it is as shown below.

  The temperature rise ΔT of the LDMOS due to self-heating is calculated by using ΔT = Id × Vd × Rth (Rth is LDMOS) using the drain current Id and the drain voltage Vd at each measurement point of the measurement performed by increasing the drain voltage Vd by a predetermined voltage. The thermal resistance can be approximately expressed as:

  At first glance, the above formulas (Id × Vd) and temperature rise ΔT correspond to 1: 1, so it seems that there is no problem even if the self-heating current / voltage characteristics are used for circuit design. . However, in practice, the thermal resistance Rth is a value that changes depending on the speed of measurement (operation), that is, the speed of increasing the drain voltage Vd. It does not correspond to the exothermic temperature. In particular, the thermal resistance Rth decreases as the measurement speed increases. For this reason, the current / voltage characteristics measured in a heated state do not make sense.

  Further, in circuit design, circuit simulation is frequently used. However, it is meaningless to extract parameters of a device model for circuit simulation based on the modified current / voltage characteristics as described above.

Therefore, conventionally, as a technique for solving the above problem, a technique described in Patent Document 1 (Japanese Patent Laid-Open No. 2006-278360) has been proposed. This is because a region where the LDMOS generates heat (measurement conditions Vd and Vg) is detected, and in the region where the heat is generated, a pulse shorter than the applied pulse width of the electrode to the drain is applied to the gate electrode with the drain voltage Vd applied. This is a method of measuring current / voltage characteristics while suppressing self-heating by shortening the application time to the electrode (for example, the pulse width applied to the gate electrode is 10 μs).
JP 2006-278360 A (19th to 22nd paragraphs, FIG. 1)

  However, in the above-described conventional method, there is a possibility that the drain current value actually changes due to the temperature rise even in the region where it is determined that the self-heating is not performed. In addition, the discrete LDMOS with a heat sink with high heat dissipation efficiency is less affected by self-heating, but the LDMOS formed on the SOI substrate has a large thermal resistance, and most of the current / voltage characteristics are in the heat generation region. There is no point in determining the area that generates heat.

  Furthermore, in order to perform measurement without self-heating, the pulse width applied to the gate is not sufficient at 10 μs, and it is necessary to make it 1 μs or less. However, if the applied pulse width is shortened, measurement waveform rounding and ringing occur due to the influence of the inductance of the measurement system, and it is difficult to measure accurately. Even if the applied pulse width is 1 μs, the harmonics include a very high frequency in terms of frequency, and therefore it is necessary to take measures against high frequency in the measurement system.

  On the other hand, as a method for measuring in a state where no self-heating is performed (non-heating state), there is a high-speed pulse measuring method mainly for a fine MOS (SOI). In this case, a measurement circuit system is assembled on the premise of a high frequency, but an object to be measured (TEG) designed specifically for it is required. In addition, the characteristic impedance is a complicated configuration, for example, matching the characteristic impedance to 50Ω, which is a standard for high-frequency systems, is an essential condition. In general, the measurable current has a structure of up to several tens of mA, which is not suitable for measuring the current / voltage characteristics of a target power semiconductor element of 0.1 A to several tens of A.

  Therefore, the present invention realizes a power semiconductor element evaluation method and evaluation apparatus that can accurately obtain the current / voltage characteristics of a power semiconductor element that is not self-heating by a relatively simple method and configuration. Objective.

A first feature of the present invention is a power semiconductor element evaluation method for estimating current / voltage characteristics of the power semiconductor element (4) in a state where the power semiconductor element (4) is not self-heating using an evaluation apparatus. Current / voltage characteristics of the power semiconductor element (4) in a self-heating state, comprising temperature measuring means for measuring the absolute temperature of the power semiconductor element and current / voltage characteristic measuring means for measuring current / voltage characteristics of the power semiconductor element. Is measured by the current-voltage characteristic measuring means, the drain current value Id0 in the state where self-heating is not performed, the drain current value measured in the first step is Id, and the drain-source voltage Vd, and the absolute temperature of the power semiconductor element measured by the temperature measuring means at the start of measurement in the first step is To, When the temperature rise of the power semiconductor element measured by the temperature measuring means when the rain-source voltage (Vd) is increased is ΔT, n = 1.5 to 2, Id0 = Id × ((To + ΔT) / To) There is a second step (S2) for obtaining a drain current value Ido when no self-heating is performed using ⁿ , and a method for evaluating a power semiconductor device.

According to a second aspect of the present invention, in the power semiconductor element evaluation apparatus for estimating the current / voltage characteristics of the power semiconductor element (4) in a state where the power semiconductor element (4) is not self-heating , the absolute temperature of the power semiconductor element is determined. A temperature measuring means for measuring, a measuring device (21) for measuring a current / voltage characteristic of a power semiconductor element in a self-heating state, a drain current value Id0 in a non-self-heating state, and a drain measured by the measuring device The current value is Id, the drain-source voltage is Vd, the absolute temperature of the power semiconductor element measured by the temperature measuring means at the start of measurement by the measuring device is To, and the drain-source voltage (Vd) is increased. When the temperature rise of the power semiconductor element measured by the temperature measuring means is ΔT and n = 1.5 to 2, Id0 = Id × ((To + ΔT) / To) ^An arithmetic unit (11, 12, 14) for obtaining a drain current value Id0 when ⁿ does not self-heat using ⁿ , and a power semiconductor element evaluation apparatus (1) is there.

The drain current flowing in the power semiconductor element is proportional to the mobility of carriers in the element, and the mobility is proportional to the absolute temperature T minus the nth power. That is, when the mobility is μ, the relationship of drain current = a × μ and μ = μ ₀ × T ⁻ⁿ is established (a and μ ₀ are proportional constants). If the drain current value of the power semiconductor element is not self-heating, Id0, the drain current value measured in the self-heated state is Id, the absolute temperature is To, and the temperature rise of the power semiconductor element due to self-heating is ΔT. ,

I d0 = a × μ ₀ × To ⁻ⁿ (A) formula

Id = a * [mu] ₀ * (To + [Delta] T) ^-n (B) formula

Is established. From equation (B)

a × μ ₀ = Id / (To + ΔT) ⁻ⁿ (C) formula

Is obtained. Substituting this equation (C) into equation (A),

Id0 = (Id / (To + ΔT) ⁻ⁿ ) × To− ⁿ
= Id × ((To + ΔT) / To) ⁿ (Equation D)

Is obtained.
That is, if the drain current value Id in the state where the power semiconductor element is self-heated, the absolute temperature is To, and the temperature rise ΔT due to self-heating is measured, the drain current value Id0 in the state where the power semiconductor element is not self-heating is obtained. be able to.
Therefore, the current / voltage characteristics of the power semiconductor element that is not self-heating can be obtained with high accuracy by a relatively simple method.

A third feature of the present invention is a power semiconductor element evaluation method for estimating current / voltage characteristics of the power semiconductor element (4) in a state where the power semiconductor element (4) is not self-heating using an evaluation apparatus. Current / voltage in a self-heating state of the power semiconductor element to be evaluated , comprising temperature measuring means for measuring the absolute temperature of the power semiconductor element and current / voltage characteristic measuring means for measuring current / voltage characteristics of the power semiconductor element A first step (S10, S11) for measuring characteristics and current / voltage characteristics of a power semiconductor element having a sufficiently small temperature rise due to self-heating by the current-voltage characteristic measuring means; Drain current in the drain current-drain-source voltage characteristics of power semiconductor devices with a small increase in temperature due to heat generation When the change amount of (Idref) is ΔIdref and the change amount of the drain-source voltage (Vd) is ΔVd, the slope of the drain current (Idref) -drain-source voltage (Vd) characteristics in the saturation region (ΔIdref / A second step (S12) for determining a relationship between a normalized gradient ((ΔIdref / ΔVd) / Idref) and a drain-source voltage (Vd) obtained by standardizing the gradient based on ΔVd), The drain current value in a state where the power semiconductor element is not self-heating is Id0, the drain current value measured in the first step is Id, and the temperature measurement unit measures the temperature at the start of the measurement in the first step. The absolute temperature of the power semiconductor element is To, the temperature rise when the drain-source voltage (Vd) is increased is ΔT, n = 1.5-2, and the power to be evaluated The thermal resistance of the semiconductor element when the Rth, determine the [Delta] T by substituting the predetermined value Rt h at ΔT = Id × Vd × Rth ··· (1) formula, further, Id0 = Id × ((To + ΔT) / To) ⁿ ... Temporary current / voltage in the state where the power semiconductor element to be evaluated is not self-heated by substituting the obtained ΔT into the equation (2) to obtain the drain current value Id0. The third step (S13) for obtaining the characteristics, and the change in the drain current (Id0) in the temporary current / voltage characteristic obtained in the third step is ΔId0, and the change in the drain-source voltage (Vd) is ΔVd. In this case, the standardization is performed by standardizing the gradient based on the gradient (ΔId0 / ΔVd) in the saturation region of the temporary drain current (Id0) / drain-source voltage (Vd) characteristics obtained in the third step. Gradient ((Δ d0 / ΔVd) / Id0) and the drain-source voltage Vd, a fourth step (S14), the third and fourth steps are executed while changing the thermal resistance Rth, and the fourth step And a fifth step (S15, S16) for obtaining the thermal resistance Rth closest to the relationship obtained in the second step.

According to a fourth aspect of the present invention, there is provided a power semiconductor element evaluation apparatus for estimating current / voltage characteristics of the power semiconductor element (4) in a state where the power semiconductor element (4) is not self-heating. Measuring device (21) for measuring current / voltage characteristics in a state and current / voltage characteristics of a power semiconductor element in which temperature rise due to self-heating is sufficiently small, temperature measuring means for measuring the absolute temperature of the power semiconductor element, The change in the drain current (Idref) in the drain current-drain-source voltage characteristics of the power semiconductor element, which is measured by the measuring device and has a sufficiently small temperature rise due to self-heating, is ΔIdref, and the drain-source voltage (Vd) In the saturation region of the drain current (Idref) / drain-source voltage (Vd) characteristics when ΔVd First arithmetic processing (S12) for determining the relationship between the normalized gradient ((ΔIdref / ΔVd) / Idref) obtained by standardizing the gradient and the drain-source voltage (Vd) based on the gradient (ΔIdref / ΔVd) The drain current value of the power semiconductor element to be evaluated in a state where the power semiconductor element is not self-heating is Id0, the drain current value measured by the measuring device is Id, and the temperature measuring means at the start of the measurement by the measuring device The measured absolute temperature of the power semiconductor element is To, the temperature rise when the drain-source voltage (Vd) is increased is ΔT, n = 1.5-2, and the heat of the power semiconductor element to be evaluated When the resistance is Rth, ΔT = Id × Vd × Rth (1), a predetermined value is substituted into Rth to obtain ΔT, and Id0 = Id × ((To + ΔT) / To) ⁿ ·・ ・2) Substituting ΔT obtained above into equation (2) to obtain the drain current value Id0, a second calculation process for obtaining a temporary current / voltage characteristic in a state where the power semiconductor element to be evaluated is not self-heating ( S13), and when the change of the drain current (Id0) in the temporary current / voltage characteristic obtained by the second calculation process is ΔId0 and the change of the drain-source voltage (Vd) is ΔVd, 2. Relationship between the standardized gradient ((ΔId0 / ΔVd) / Id0) and the voltage Vd based on the gradient (ΔId0 / ΔVd) in the saturation region of the temporary current / voltage characteristics obtained by the arithmetic processing. The third calculation process (S14) for obtaining the value and the second and third calculation processes are executed while changing the thermal resistance Rth, and the relationship obtained by the third calculation process is the function obtained in the first calculation process. In the evaluation device of the fourth arithmetic processing (S15, S16) and, further comprising a power semiconductor element calculation device (11, 12, 13, 14) to perform the seeking comes closest thermal resistance Rth in.

That is, the thermal resistance Rth of the power semiconductor element to be evaluated can be obtained using the current / voltage characteristics of the power semiconductor element in which the temperature rise due to self-heating is sufficiently small.
First, the current / voltage characteristics of the power semiconductor element to be evaluated in the self-heating state and the current / voltage characteristics of the power semiconductor element in which the temperature rise due to self-heating is sufficiently small are measured (first step).

  Next, the change in the drain current (Idref) in the current / voltage characteristics of the power semiconductor element that is measured in the first step and the temperature rise due to self-heating is sufficiently small is expressed as ΔIdref, and the change in the drain-source voltage (Vd). Based on the gradient (ΔIdref / ΔVd) in the saturation region of the drain current (Idref) / drain-source voltage (Vd) characteristic when ΔVd is set, a normalized gradient ((ΔIdref / ΔVd) in which the gradient is normalized / Idref) and the drain-source voltage (Vd) are obtained (second step, first calculation process).

  Since the influence of heat generation appears significantly in the gradient of the saturation region, the gradient (ΔIdref / ΔVd) is calculated. Considering the case where there is no heat generation, for example, the drain current Idref increases as the element size increases (for example, when the size is doubled, the gradient is also doubled). Therefore, the gradient is divided by the drain Idref. To standardize. Next, the relationship between the normalized gradient ((ΔIdref / ΔVd) / Idref) and the drain-source voltage (Vd) is obtained.

Next, Id0 is the drain current value of the power semiconductor element to be evaluated when it is not self-heating, Id is the drain current value measured in the first step, and the absolute value of the power semiconductor element at the start of measurement in the first step ΔT = Id when the temperature is To, the temperature rise when the drain-source voltage (Vd) is raised is ΔT, n = 1.5-2, and the thermal resistance of the power semiconductor element to be evaluated is Rth. × Vd × Rth (1) In equation (1), a predetermined value is substituted for Rth to obtain ΔT.
That is, the temperature of the power semiconductor element to be evaluated when the drain-source voltage (Vd) is increased is proportional to the drain current Id, the drain-source voltage Vd, and the thermal resistance Rth when self-heating is performed. Therefore, the temperature rise ΔT of the power semiconductor element is obtained by the equation: ΔT = Id × Vd × Rth (1)

At this stage, since the thermal resistance Rth is unknown, an appropriate predetermined value is substituted as a temporary value for Rth in the equation (1) to obtain the temperature rise ΔT. Then, Id0 = Id × ((To + ΔT) / To) ⁿ described in the first feature is substituted by ΔT obtained by the above equation (1) into the equation (2) to obtain the drain current value Id0. By determining, a provisional current / voltage characteristic in a state where the power semiconductor element to be evaluated is not self-heating is determined (third step, second calculation process).

  Next, when the change amount of the drain current (Id0) in the temporary current / voltage characteristic obtained by the third step or the second calculation process is ΔId0 and the change amount of the drain-source voltage (Vd) is ΔVd, Based on the gradient (ΔId0 / ΔVd) in the saturation region of the temporary current / voltage characteristic obtained by the third step or the second calculation process, a normalized gradient ((ΔId0 / ΔVd) / Id0) obtained by normalizing the gradient; The relationship with the drain-source voltage Vd is obtained (fourth step, third calculation process).

Next, the third and fourth steps are executed while changing the thermal resistance Rth, and the thermal resistance Rth in which the relationship obtained in the fourth step is closest to the relationship obtained in the second step is obtained (fifth step, second step). 4 arithmetic processing). For example, the thermal resistance Rth at which the curve indicating the relationship obtained in the fourth step or the third calculation process is closest to the curve indicating the relationship obtained in the second step or the first calculation process is obtained.
That is, according to the third and fourth characteristics, the thermal resistance Rth of the power semiconductor element to be evaluated can be measured without measuring the temperature of the power semiconductor element to be evaluated simultaneously with the measurement of the current / voltage characteristics. Can be requested.

  As a result, it is possible to obtain the current / voltage characteristics of the power semiconductor element to be evaluated in a state where self-heating is not performed.

  The fifth feature of the present invention is that the self-heating of the power semiconductor element to be evaluated using the thermal resistance Rth obtained in the fifth step and the equations (1) and (2) in the third feature described above. The sixth step is to obtain a drain current (Id0) in a state where the drain current is not.

  According to a sixth feature of the present invention, in the fourth feature described above, the arithmetic unit (11, 12, 13, 14) is configured such that the thermal resistance Rth obtained by the fourth arithmetic processing (S15, S16) and the formula (1) And the fifth calculation process (S18) for obtaining the drain current (Id0) in the state where the power semiconductor element to be evaluated is not self-heating using the equation (2).

That is, the thermal resistance Rth obtained by the fifth step or the fourth process is substituted into the equation (1) to obtain the temperature rise ΔT, and the temperature rise ΔT is substituted into the equation (2) to be an evaluation object. A drain current (Id0) in a state where the power semiconductor element is not self-heating is obtained.
Therefore, even if the temperature of the power semiconductor element to be evaluated is not measured, the current / voltage characteristics of the power semiconductor element that is not self-heating can be obtained with high accuracy by a relatively simple method.

  The seventh feature of the present invention is that, in the third or fifth feature described above, when the channel width of the power semiconductor element (4) to be evaluated is Weff, the normalized gradient is used in the fourth step (S14). ((ΔId0 / ΔVd) / Weff) is obtained.

  The eighth feature of the present invention is that, in the fourth or sixth feature described above, when the channel width of the power semiconductor element (4) to be evaluated is set to Weff, the third arithmetic processing (S14) is normalized. The purpose is to obtain ((ΔId0 / ΔVd) / Weff) as the gradient.

  That is, since the channel width Weff increases as the element size increases, normalization can be achieved by dividing the gradient (ΔId0 / ΔVd) by the channel width Weff.

  In addition, the code | symbol in the said parenthesis shows the correspondence with the specific means as described in embodiment mentioned later.

<First Embodiment>
A first embodiment according to the present invention will be described with reference to the drawings. FIG. 1 is an explanatory diagram showing the main electrical configuration of a power semiconductor element evaluation apparatus (hereinafter referred to as an evaluation apparatus) according to this embodiment in blocks.

[Main electrical configuration of evaluation equipment]
As shown in FIG. 1, the evaluation device 1 includes a data processing device 10 and a measurement device 20. The data processing device 10 includes a measurement control unit 11, a determination unit 12, a thermal resistance calculation unit 13, a uniform temperature IV characteristic calculation unit 14, and a parameter extraction unit 15. An input device 2 is connected to the measurement control unit 11, and an output device 3 is connected to the parameter extraction unit 15.

The measuring device 20 includes an IV characteristic measuring device 21 that measures current / voltage characteristics (IV characteristics) of the LDMOS 4. Further, as shown in the figure, a temperature measuring device 22 for measuring the temperature of the LDMOS 4 can be provided. The IV characteristic measuring device 21 and the temperature measuring device 22 are connected to the LDMOS 4.
The data processing device 10 is composed of a computer or the like, and the input device 2 is composed of a keyboard, a mouse or the like. The input device 2 inputs under what measurement conditions (voltage, temperature) the LDMOS 4 is measured, under what conditions the parameters are extracted, and the like.

  The measurement control unit 11 gives the measurement conditions input by the input device 2 to the IV characteristic measurement device 21 to measure the current / voltage characteristics of the LDMOS 4. Further, the measurement control unit 11 gives the measurement conditions input by the input device 2 to the temperature measurement device 22 to measure the temperature of the LDMOS 4. Further, the measurement control unit 11 takes in measurement data from the IV characteristic measurement device 21 and the temperature measurement device 22.

  As the temperature measurement device 22, an infrared temperature measurement device that measures the temperature by detecting infrared rays emitted from the measurement object by heat with a sensor can be used. In addition, an apparatus that irradiates a measurement target with laser light and measures the surface temperature of the measurement target from a change in the phase of the reflected light intensity can also be used.

  The determination unit 12 determines whether or not temperature data indicating the temperature of the LDMOS 4 measured by the temperature measurement device 22 is taken into the measurement control unit 11. The thermal resistance calculation unit 13 calculates the thermal resistance Rth of the LDMOS 4 according to the flow shown in FIG. 4 when the determination unit 12 makes a negative determination, that is, when there is no temperature data of the LDMOS 4.

  If the determination unit 12 makes a positive determination, that is, if temperature data of the LDMOS 4 exists, the uniform temperature IV characteristic calculation unit 14 uses the temperature data to follow the flow shown in FIG. Calculate the current / voltage characteristics when there is no (at uniform temperature). Further, the uniform temperature IV characteristic calculation unit 14 does not self-heat the LDMOS 4 according to the flow shown in FIG. 4 using the thermal resistance calculated by the thermal resistance calculation unit 13 when the temperature data of the LDMOS 4 does not exist. Calculate the current / voltage characteristics at the time (at uniform temperature).

  The parameter extraction unit 15 extracts model parameters for circuit simulation using the LDMOS 4 based on the current / voltage characteristics calculated by the uniform temperature IV characteristic calculation unit 14. For example, a model parameter group (10 to several hundreds) that defines a function I = f (Vd, Vg) representing a current flowing in the circuit when the drain voltage Vd and the gate voltage Vg are changed is extracted.

  The output device 3 includes a printer, a monitor, and a storage device (for example, a hard disk memory, a USB (Universal Serial Bus) memory, etc.).

[Evaluation Method 1]
With reference to FIG. 2, an evaluation method 1 for determining the current / voltage characteristics of the evaluation target LDMOS in a state where it does not self-heat by measuring the temperature of the evaluation target LDMOS (hereinafter referred to as the evaluation target LDMOS) will be described. . FIG. 2 is a flowchart showing a flow of processing executed by the data processing apparatus 10 in order to execute the evaluation method 1.

  First, the measurement control unit 11 of the data processing apparatus 10 applies a constant gate voltage Vg to the LDMOS 4 to be evaluated, measures the value of the drain current Id while changing the drain voltage Vd, and in the self-heating state of the LDMOS 4. The drain current (Id) / drain voltage (Vd) characteristics are measured by the IV characteristic measuring device 21 (step (hereinafter abbreviated as S) 1). This is performed for a plurality of gate voltages. Further, the drain current (Id) / gate voltage (Vg) characteristics when the gate voltage Vg is changed are caused to be measured by the IV characteristic measuring device 21 (S1). This is performed for a plurality of drain voltages.

Further, the measurement control unit 11 causes the temperature measuring device 22 to measure the absolute temperature of the evaluation target LDMOS 4 at each measurement point (Vd, Vg) simultaneously with the measurement of the above characteristics (S1). Subsequently, the determination unit 12 determines that temperature data indicating the temperature of the evaluation target LDMOS 4 measured by the temperature measurement device 22 is taken into the measurement control unit 11 and exists.
Subsequently, the uniform temperature IV characteristic calculation unit 14 performs drain current (Id0) / drain voltage (Vd) characteristics and drain current (Id0) / evaluation of the LDMOS 4 to be evaluated in a state where it does not generate heat (uniform temperature state). The gate voltage (Vg) characteristic is calculated using the following equation (1) (S2).

Id0 = Id × ((To + ΔT) / To) ⁿ (1)

  Here, Id is the drain current of the evaluation target LDMOS 4 in the self-heating state measured in the previous S1, To is the absolute temperature of the evaluation target LDMOS 4 at the start of measurement, and ΔT is the LDMOS 4 when the drain voltage Vd is increased. Each temperature rise is shown. Further, n is 1.5 to 2, and is a value depending on the concentration distribution of the p layer and the n layer constituting the evaluation target LDMOS 4. In this embodiment, n = 1.5.

  Subsequently, the parameter extraction unit 15 extracts a model parameter for circuit simulation based on each characteristic calculated in S2 (S3). This parameter extraction can be performed using known model parameter extraction software (computer program).

  FIG. 3 is a graph showing drain current (Id) / drain voltage (Vd) characteristics of the LDMOS. In the figure, the curve indicated by the broken line is a graph (simulation result) of the self-heating state, and the curve indicated by the alternate long and short dash line is a graph of the non-self-heating state (non-heating state) obtained by S1 to S3, A curve indicated by a solid line is a graph in a state where no self-heating occurs (non-heating state) (simulation result).

  Comparing the curve indicated by the alternate long and short dash line and the curve indicated by the solid line, it can be seen that there is only a few percent error between the two. That is, according to the evaluation method 1 of this embodiment, the drain current (Id) / drain voltage (Vd) characteristics and the drain current (Id) / gate voltage (Vg) characteristics of the LDMOS 4 to be evaluated in a state where self-heating is not performed. It can be obtained with high accuracy.

Further, unlike the conventional high-speed pulse measurement method, a measurement object (TEG) designed exclusively is not necessary. Furthermore, it is not necessary to match the characteristic impedance to 50Ω, which is a standard for high frequency systems.
Therefore, according to the evaluation method 1 described above, the current / voltage characteristics of the evaluation target LDMOS that is not self-heating can be obtained with high accuracy by a relatively simple method and configuration.

[Evaluation Method 2]
Evaluation method 2 will be described with reference to FIG. FIG. 4 is a flowchart showing a flow of processing executed by the data processing apparatus 10 in order to execute the evaluation method 2. This evaluation method is characterized in that the current / voltage characteristics of the evaluation target LDMOS in a state where it is not self-heating can be obtained without directly measuring the temperature of the evaluation target LDMOS. In addition, this evaluation method 2 is performed using the evaluation apparatus 1 (FIG. 1) used in the above-described evaluation method 1.

  First, the measurement control unit 11 of the data processing apparatus 10 performs the drain current (Id) / drain voltage (Vd) characteristics and drain current (Id) in the self-heating state of the evaluation target LDMOS 4 in the same manner as S1 of the evaluation method 1 described above. The gate voltage (Vg) characteristic is measured by the IV characteristic measuring device 21 (S10). Subsequently, the drain current (Idref) / drain voltage (Vd) characteristics of the small-sized LDMOS are measured (S11).

  A small-sized LDMOS that hardly self-heats (for example, an LDMOS of one to several cells) is a reference for obtaining current / voltage characteristics in a state where a larger LDMOS is not self-heating (non-heat-generating state). can do.

FIG. 5 shows drain current (Id) / drain voltage (Vd) characteristics (actual measurement values) when the gate voltage Vg = −4.5 V and the drain voltage Vd is changed from 0 to −12 V in LDMOS of various sizes. It is a characteristic view shown with the electric current per cell. In the figure, a curve indicated by a thin solid line is an LDMOS consisting of 1 × 1 cells (hereinafter referred to as LDMOS-A), and a curve indicated by a thin one-dot chain line is an LDMOS consisting of 1 × 3 cells (hereinafter referred to as LDMOS−). B), a curve indicated by a broken line is an LDMOS (hereinafter referred to as LDMOS-C) composed of 3 × 3 cells, and a curve indicated by a thick solid line is an LDMOS (hereinafter referred to as LDMOS) of 0.01 mm ² (126 cells). -D), and a curve indicated by a thick alternate long and short dash line shows a characteristic diagram of an LDMOS (hereinafter referred to as LDMOS-E) of 0.1 mm ² (1116 cells).

  The effect of self-heating appears prominently in the gradient of the saturation region (in FIG. 5, a relatively flat region of −4 V or less). If this gradient is negative, the effect of self-heating is clearly apparent. Become. As shown in FIG. 5, the larger the size of the LDMOS, the more negative the gradient. Further, the power consumption increases and the temperature rise increases toward the left side of the graph of FIG. Further, the absolute value of the drain current value Id decreases as the temperature increases. In this embodiment, the LDMOS-A having the minimum size is set as a reference LDMOS having no self-heating, and the other LDMOS-B to E larger than the LDMOS-A are evaluation target LDMOSs.

  The uniform temperature IV characteristic calculation unit 14 determines ((ΔIdref / ΔVd) / Idref) and the drain voltage (based on the drain current (Idref) / drain voltage (Vd) characteristics of the small-sized LDMOS-A measured in S11. Vd) is calculated (S12). Here, (ΔIdref / ΔVd) is a gradient in the saturation region of the drain current (Idref) / drain voltage (Vd) characteristics, and ((ΔIdref / ΔVd) / Idref) is a normalized gradient obtained by normalizing the gradient. It is.

In other words, when there is no self-heating, the drain current value Idref increases as the size of the LDMOS increases (for example, when the size is doubled, the slope is also doubled), so the slope (ΔIdref / ΔVd) is the drain current value. Normalize by dividing by Idref.
The normalized gradient can also be calculated by ((ΔId 0 / ΔVd) / Weff). Here, Weff is the channel width of LDMOS-A.

A solid line A in FIG. 6 is a graph showing a relationship between the normalized gradient ((ΔIdref / ΔVd) / Idref) calculated in S12 and the drain voltage Vd.
The thermal resistance calculator 13 (FIG. 1) calculates the temperature rise ΔT at each voltage (Vd, Vg) of the evaluation target LDMOS in S10 by the following equation (1) (S13).

  ΔT = Id × Vd × Rth (1)

  Here, Id and Vd are the drain current value and drain voltage value measured in S10, respectively, and Rth is the thermal resistance. For example, as shown in FIG. 5, the drain current value Id and the drain voltage value Vd use part of the drain current (Id) / drain voltage (Vd) characteristics when the gate voltage (Vg) is −4.5 V, respectively. And ask. Further, since the thermal resistance Rth is unknown, a predetermined value is substituted as the thermal resistance Rth. Note that the temperature increase ΔT can be calculated by the following equation (1a) instead of the equation (1).

  ΔT = Id × Vd × (rth0 / Weff) (1a)

  Here, rth0 = Rth × Weff. rth0 is the normalized thermal resistance, and Weff is the channel width of the LDMOS-A. When the area of the LDMOS is large, rth0 has a constant value. In such a case, ΔT can be easily calculated using the equation (1a).

  Subsequently, the uniform temperature IV characteristic calculation unit 14 (FIG. 1) calculates the drain current value Id0 of the evaluation target LDMOS in a state where the self-heating is not performed (non-heating state) by the following equation (2) ( S13).

Id0 = Id × ((To + ΔT) / To) ⁿ (2)

Here, Id is the drain current value in the self-heating state of the evaluation target LDMOS measured in S10, To is the absolute temperature of the evaluation target LDMOS at the start of measurement in S10, and ΔT is the temperature increase calculated earlier. is there. In this embodiment, n = 1.5.
Further, based on the calculated drain current value Id0, the provisional drain current (Id0) / drain voltage (Vd) characteristics and drain current (Id0) / gate voltage of the LDMOS to be evaluated in a state where self-heating is not performed ( Vg) characteristics are calculated (S13).

Subsequently, based on the drain current (Id0) / drain voltage (Vd) characteristics calculated in S13, the normalized gradient ((ΔId0 / ΔVd) / Id0) and the drain voltage Vd of the LDMOS to be evaluated in a state where self-heating is not performed. (S14).
Subsequently, the relationship between the normalized gradient ((ΔIdref / ΔVd) / Idref) calculated in S12 and the drain voltage Vd, and the normalized gradient ((ΔId0 / ΔVd) / Id0) calculated in S14 and the drain voltage Vd. The relationship is compared (S15). That is, the relationship between the standardized gradient of the small size LDMOS-A as a reference and the drain voltage is compared with the relationship between the standardized gradient of the evaluation LDMOS and the drain voltage.

  Subsequently, it is determined whether or not the above relations are substantially the same (S16). If it is determined that they are not the same (S16: No), the value of the thermal resistance Rth is changed (S17), and again from S13 to S13. S15 is executed. That is, in the graph shown in FIG. 6, the value of the thermal resistance Rth is changed so that the curves of the LDMOS-B to E to be evaluated substantially coincide with the curve of the reference LDMOS-A. In the determination as to whether or not the above relations substantially coincide, the error in the actual use drain voltage (corresponding to −6 to −12 V in this case) is minimized from the drain voltage at which the saturation region starts in FIG. Sometimes it is determined that they are almost the same. For example, if the absolute value of the error is approximately within 10%, it is determined that they are almost the same.

  FIG. 7 is a graph showing a state in which the curves of LDMOS-B to E substantially coincide with the curve of the reference LDMOS-A by changing the value of the thermal resistance Rth. In this embodiment, the normalized thermal resistance rth0 of the LDMOS-A is 0.001 mK / W, and as shown in FIG. 7, the LDMOS-B to E when the LDMOS-A is substantially in agreement with the curve of the LDMOS-A. The normalized thermal resistances rth0 were 0.004, 0.01, 0.042, and 0.1 mK / W in this order. Further, the channel widths of LDMOS-B to E are 3.48e-5, 1.04e-4, 1.462e-3, 1.295e-2m, and Rth = rth0 / Weff. The thermal resistance Rth is 115, 95.8, 28.7, and 7.72 in this order.

  Subsequently, when an affirmative determination is made in S16 (S16: Yes), a state in which self-heating is not performed using the thermal resistance Rth changed in S17 of the processing cycle (S13 to S17) immediately before the positive determination is made (nothing) The drain current (Id0) / drain voltage (Vd) characteristics and the drain current (Id0) / gate voltage (Vg) characteristics of the evaluation target LDMOS in the heat generation state are calculated (S18). Subsequently, the parameter extraction unit 15 extracts model parameters for circuit simulation based on the characteristics calculated in S18 (S19).

As described above, according to the evaluation method 2 of this embodiment, even if the temperature of the LDMOS to be evaluated is not measured simultaneously with the measurement of the current / voltage characteristics, it is based on the current / voltage characteristics of the small-sized LDMOS. Thus, the current / voltage characteristics of the evaluation target LDMOS in a state where it is not self-heating can be obtained.
Further, unlike the conventional high-speed pulse measurement method, a measurement object (TEG) designed exclusively is not necessary. Furthermore, it is not necessary to match the characteristic impedance to 50Ω, which is a standard for high frequency systems.

Second Embodiment
Next, a second embodiment of the present invention will be described with reference to the drawings.
FIG. 8 is an explanatory diagram showing the arrangement of diodes for measuring the temperature of the LDMOS, where (a) shows a state where one diode is arranged, (b) shows a state where three diodes are arranged, and (c) shows In this state, the diode is arranged on the LDMOS. FIG. 9 is a flowchart showing the flow of processing executed by the data processing apparatus 10. FIG. 10 is a graph showing the relationship between the forward voltage of the diode and the temperature of the LDMOS.

This embodiment is characterized in that the temperature of the evaluation target LDMOS is measured based on the forward voltage of a temperature detection diode arranged in the vicinity of the evaluation target LDMOS.
As shown in FIG. 8A, an evaluation target LDMOS 4 is arranged, and a temperature detection diode D is arranged in the vicinity thereof. The evaluation object LDMOS 4 and the temperature detection diode D are arranged on the same SOI substrate.

The measurement control unit 11 (FIG. 1) of the data processing apparatus 10 measures the forward voltage-temperature characteristics of the temperature detection diode D (S30 in FIG. 9). While gradually changing the temperature, the forward voltage-temperature characteristic is measured by a forward voltage-temperature characteristic measuring device (not shown) provided in the measuring device 20.
As shown in FIG. 10, the forward voltage Vf of the diode D decreases as the temperature of the evaluation target LDMOS 4 increases between the forward voltage and the temperature of the temperature detection diode D.

  Subsequently, the measurement control unit 11 determines the drain current (Id) / drain voltage (Vd) characteristics and the drain current (Id) / gate voltage (Vg) characteristics in the self-heating state of the LDMOS 4 to be evaluated as the IV characteristic measuring device 21. (S31). Further, when performing the measurement, the forward voltage-temperature characteristic measuring device (not shown) is used to convert the forward voltage of the temperature measuring diode D arranged in the vicinity of the evaluation target LDMOS 4 at each measurement point of the drain voltage Vd. (S31).

Subsequently, the uniform temperature IV characteristic calculation unit 14 calculates the absolute temperature To of the evaluation target LDMOS 4 at each measurement point from the forward voltage of the temperature detection diode D at each measurement point measured in S31 ( S32).
Subsequently, the drain current value Id0 in a state where the evaluation target LDMOS 4 is not self-heating (non-heating state) is calculated by the following equation (2) (S33).

Id0 = Id × ((To + ΔT) / To) ⁿ (2)

  Here, Id is the drain current value of the evaluation target LDMOS 4 in the self-heating state measured in S31, To is the absolute temperature at the start of measurement, and To + ΔT is the evaluation target LDMOS 4 at each measurement point calculated in S32. It is an absolute temperature, ΔT is the temperature rise of the evaluation target LDMOS 4 between each measurement point, and n is 1.5-2. In this embodiment, n = 1.5.

  As a result, the drain current (Id0) / drain voltage (Vd) characteristics and drain current (Id0) / gate voltage (Vg) characteristics of the LDMOS 4 to be evaluated in a state where no self-heating is generated (non-heating state) are calculated (S33). ). Subsequently, the parameter extraction unit 15 extracts model parameters for circuit simulation based on the characteristics calculated in S34 (S34).

As described above, according to the evaluation apparatus and the evaluation method of the second embodiment, by measuring the forward voltage of the temperature detection diode D arranged in the vicinity of the evaluation target LDMOS 4, the evaluation in a state where no self-heating is performed. The current / voltage characteristics of the target LDMOS 4 can be obtained.
That is, the current / voltage characteristics of the LDMOS 4 to be evaluated in a state where it does not generate heat can be obtained with high accuracy by a relatively simple method and configuration.

[Modification 1]
As shown in FIG. 8B, three temperature detection diodes D1, D2, and D3 having different distances from the evaluation target LDMOS 4 are arranged in the vicinity of the evaluation target LDMOS 4. Then, each forward voltage of each temperature detection diode is measured, a linear function or a quadratic function is calculated from the measured value, and an average temperature of the evaluation target LDMOS 4 is obtained. The temperature of the LDMOS is higher at the center and decreases as it is farther from the LDMOS. Thus, the temperature can be measured with higher accuracy by converting the temperature distribution into a function. Note that the number of temperature detecting diodes to be arranged may be plural, and may be two or four or more.

[Modification 2]
As shown in FIG. 8C, the temperature detection diode D is directly arranged on the surface of the evaluation target LDMOS 4. Then, the forward voltage of the temperature detecting diode D is measured, and the temperature of the central portion of the evaluation target LDMOS 4 is obtained based on the measured value. Since the temperature detection diode D is directly arranged on the surface of the evaluation target LDMOS 4, the temperature at the center of the evaluation target LDMOS 4 can be reflected in the forward voltage of the temperature detection diode D with high accuracy. Current / voltage characteristics can be calculated with high accuracy.

[Modification 3]
As shown in FIG. 8A, one diode D is arranged in the vicinity of the evaluation target LDMOS 4. Then, each forward voltage when two different currents are passed through the diode D is measured, and the temperature of the evaluation target LDMOS 4 is calculated based on the difference ΔV between the measured values.
For example, the first forward voltage Vf1 of the diode D when the first forward current If flows, and the second of the diode D when the second forward current N · If N times that of the first forward voltage Vf1 flows. The forward voltage Vf2 is measured. The difference ΔV between the first forward voltage Vf1 and the second forward voltage Vf2 is expressed by the following equation (3).

  ΔV = η (kT / q) ln (N) (3)

Here, q is the charge amount of electrons (1.6 × 10 ⁻¹⁹ C), k is the Boltzmann constant (1.38 × 10 ⁻²³ J / K), T is the absolute temperature (K), and η is an ideal factor. The ideality factor indicates how far the pn junction of the diode deviates from the ideal condition, and this value depends on the manufacturing process. However, η≈1 (about ± 1%). When the above equation (3) is modified, the following equation (4) is obtained.

  T = ΔV · q / η · k · ln (N) (4)

Here, since other than η is known on the right side of the equation (4), the temperature T can be obtained if η is known. η can be calculated by measuring ΔV at an arbitrary temperature (for example, room temperature).
Therefore, according to the modified example 3, it is not necessary to measure the relationship between the forward voltage of the diode D and the temperature in advance.

<Other embodiments>
(1) In S13 of the second embodiment, the temperature increase ΔT of the evaluation target LDMOS is estimated by a calculation formula, but the temperature increase ΔT is calculated by measuring the temperature of the evaluation target LDMOS as in the first embodiment. The thermal resistance Rth can also be obtained by calculation.

(2) In each of the above-described embodiments, the LDMOS formed on the SOI substrate is the evaluation target. However, the LDMOS formed on the bulk wafer can be the evaluation target.

(3) In each of the above-described embodiments, the LDMOS is an evaluation target. However, the device is a device in which the temperature characteristic of the current is dominantly determined by the temperature characteristic of the carrier mobility, and the temperature due to self-heating during the current / voltage characteristic measurement. It is also possible to evaluate devices whose characteristics change due to an increase in the value. For example, vertical power MOSFETs, up drain power MOSFETs, and the like can be evaluated.

It is explanatory drawing which shows the main electrical structures of the evaluation apparatus of a power semiconductor element with a block. 4 is a flowchart showing a flow of processing executed by the data processing device 10 for executing an evaluation method 1. It is a characteristic view which shows the drain current (Id) -drain voltage (Vd) characteristic of LDMOS. 7 is a flowchart showing a flow of processing executed by the data processing device 10 for executing an evaluation method 2. A characteristic diagram showing drain current (Idref) / drain voltage (Vd) characteristics (actually measured values) when the gate voltage Vg = -4.5 V and the drain voltage Vd is changed from 0 to -12 V in LDMOS of various sizes. is there. It is a graph which shows the relationship between the normalization gradient (((DELTA) Idref / (DELTA) Vd) / Idref) calculated in S12, and Vd. It is a graph which shows the state in which the curve of LDMOS-B-E substantially matched with the curve of LDMOS-A used as a reference | standard by changing the value of thermal resistance Rth. It is explanatory drawing which shows arrangement | positioning of the diode for measuring the temperature of LDMOS, (a) is the state which arrange | positioned one diode, (b) is the state which arranged three diodes, (c) is the diode on LDMOS. It is in the state arranged in. 3 is a flowchart showing a flow of processing executed by the data processing apparatus 10. It is a graph which shows the relationship between the forward voltage of a diode, and the temperature of LDMOS. It is a longitudinal cross-sectional view showing a main part of a p-channel LDMOS. 12 is a graph showing drain current (Id) / drain voltage (Vd) characteristics when the LDMOS shown in FIG. 11 is not generating heat (no heat generation) and when it is generating heat.

Explanation of symbols

1 .... Evaluation device, 2 .... Input device, 3 .... Output device, 4 .... LDMOS for evaluation,
10. Data processing device, 11. Measurement control unit, 13. Thermal resistance calculation unit,
14 .. Uniform temperature IV characteristic calculation unit, 15 .... Parameter extraction unit, 20 .... Measuring device,
21..I-V characteristic measuring device, 22..Temperature measuring device.

Claims (8)

For estimating drain current-drain-source voltage characteristics and drain current-gate-source voltage characteristics (hereinafter, both characteristics are referred to as current-voltage characteristics) in a state where the power semiconductor element is not self-heating using an evaluation device . In the evaluation method of the power semiconductor element,
The evaluation apparatus comprises temperature measuring means for measuring the absolute temperature of the power semiconductor element and current-voltage characteristic measuring means for measuring current / voltage characteristics of the power semiconductor element,
A first step of measuring current-voltage characteristics of the power semiconductor element in a self-heating state by the current-voltage characteristic measuring means ;
The drain current value in a state where the self-heating is not performed is Id0, the drain current value measured in the first step is Id, the drain-source voltage is Vd, and the temperature measurement unit measures at the start of the measurement in the first step. been absolute temperature to of the power semiconductor device, the temperature rise of the power semiconductor element measured by said temperature measuring means when raised the drain-source voltage (Vd) ΔT, n = 1.5~ 2
Id0 = Id × ((To + ΔT) / To) ⁿ
A second step of obtaining a drain current value Id0 when self-heating is not performed using
A method for evaluating a power semiconductor element, comprising: In an evaluation method of a power semiconductor element for estimating a current / voltage characteristic in a state where the power semiconductor element is not self-heating using an evaluation apparatus ,
The evaluation apparatus comprises temperature measuring means for measuring the absolute temperature of the power semiconductor element and current-voltage characteristic measuring means for measuring current / voltage characteristics of the power semiconductor element,
A first step of measuring the current / voltage characteristics of the power semiconductor element to be evaluated in the self-heating state and the current / voltage characteristics of the power semiconductor element having a sufficiently small temperature rise due to self-heating by the current-voltage characteristic measuring means ;
The change in the drain current (Idref) in the drain current-drain-source voltage characteristics of the power semiconductor element measured in the first step and having a sufficiently small temperature rise due to self-heating is represented by ΔIdref and the drain-source voltage (Vd). Based on the gradient (ΔIdref / ΔVd) in the saturation region of the drain current (Idref) / drain-source voltage (Vd) characteristics when the change is ΔVd, the normalized gradient ((ΔIdref) / ΔVd) / Idref) and the drain-source voltage (Vd),
The drain current value in a state where the power semiconductor element to be evaluated is not self-heating is Id0, the drain current value measured in the first step is Id, and the temperature measuring means at the start of the measurement in the first step The measured absolute temperature of the power semiconductor element is To, the temperature rise when the drain-source voltage (Vd) is increased is ΔT, n = 1.5-2, and the heat of the power semiconductor element to be evaluated When the resistance is Rth,
Seeking [Delta] T by substituting the predetermined value Rt h at ΔT = Id × Vd × Rth ··· (1) formula, and further,
Id0 = Id × ((To + ΔT) / To) ⁿ ... The self-heating of the power semiconductor element to be evaluated is obtained by substituting the obtained ΔT into the equation (2) to obtain the drain current value Id0. A third step for obtaining a provisional current-voltage characteristic in the absence of
When the change in the drain current (Id0) in the temporary current / voltage characteristics obtained in the third step is ΔId0 and the change in the drain-source voltage (Vd) is ΔVd, the change is obtained in the third step. Based on the gradient (ΔId0 / ΔVd) in the saturation region of the temporary current / voltage characteristics, the relationship between the normalized gradient ((ΔId0 / ΔVd) / Id0) obtained by normalizing the gradient and the drain-source voltage Vd is obtained. The fourth step;
Executing the third and fourth steps while changing the thermal resistance Rth, and a fifth step for obtaining a thermal resistance Rth in which the relationship obtained in the fourth step is closest to the relationship obtained in the second step;
A method for evaluating a power semiconductor element, comprising:   A sixth step for obtaining a drain current (Id0) in a state where the power semiconductor element to be evaluated is not self-heating using the thermal resistance Rth obtained in the fifth step and the equations (1) and (2). The method for evaluating a power semiconductor element according to claim 2, wherein:   3. The method according to claim 2, wherein when the channel width of the power semiconductor element to be evaluated is Weff, ((ΔId0 / ΔVd) / Weff) is obtained as the normalized gradient in the fourth step. 4. The method for evaluating a power semiconductor element according to 3. In the power semiconductor element evaluation apparatus for estimating the current / voltage characteristics when the power semiconductor element is not self-heating,
Temperature measuring means for measuring the absolute temperature of the power semiconductor element;
A measuring device for measuring the current / voltage characteristics of power semiconductor elements in a self-heating state;
The drain current value Id0, the drain current value measured by the measuring device Id in the state where the self-heating is not performed, and the absolute temperature of the power semiconductor element measured by the temperature measuring means at the start of the measurement by the measuring device. To, when the temperature rise of the power semiconductor element measured by the temperature measuring means when the voltage (Vd) is raised is ΔT, n = 1.5-2,
Id0 = Id × ((To + ΔT) / To) ⁿ
An arithmetic unit for obtaining a drain current value Id0 when self-heating is not performed using
An apparatus for evaluating a power semiconductor element, comprising: In the power semiconductor element evaluation apparatus for estimating the current / voltage characteristics when the power semiconductor element is not self-heating,
A measuring device for measuring the current / voltage characteristics of the power semiconductor element to be evaluated in the self-heating state and the current / voltage characteristics of the power semiconductor element in which the temperature rise due to self-heating is sufficiently small ;
Temperature measuring means for measuring the absolute temperature of the power semiconductor element , and
The amount of change in drain current (Idref) in the drain current-drain-source voltage characteristics of a power semiconductor element, which is measured by the measuring device and has a sufficiently small temperature rise due to self-heating, is the amount of change in ΔIdref and drain-source voltage (Vd). Is a normalized gradient ((ΔIdref / ΔVd) based on the gradient (ΔIdref / ΔVd) in the saturation region of the drain current (Idref) / drain-source voltage (Vd) characteristics. ) / Idref) and the drain-source voltage (Vd),
The drain current value of the power semiconductor element to be evaluated in a state where the power semiconductor element is not self-heating is Id0, the drain current value measured by the measuring device is Id, and measured by the temperature measuring means at the start of measurement by the measuring device. Further, the absolute temperature of the power semiconductor element is To, the temperature rise when the drain-source voltage (Vd) is increased is ΔT, n = 1.5-2, and the thermal resistance of the power semiconductor element to be evaluated is In case of Rth,
ΔT = Id × Vd × Rth (1) In equation (1), a predetermined value is substituted into Rth to obtain ΔT, and
Id0 = Id × ((To + ΔT) / To) ⁿ ... The self-heating of the power semiconductor element to be evaluated is obtained by substituting the obtained ΔT into the equation (2) to obtain the drain current value Id0. A second calculation process for obtaining a provisional current / voltage characteristic in the absence of
When the change amount of the drain current (Id0) in the temporary current / voltage characteristic obtained by the second calculation processing is ΔId0 and the change amount of the drain-source voltage (Vd) is ΔVd, the second calculation processing Based on the gradient (ΔId0 / ΔVd) in the saturation region of the provisional current / voltage characteristics obtained, the relationship between the normalized gradient ((ΔId0 / ΔVd) / Id0) normalized to the gradient and the drain-source voltage Vd A third calculation process for obtaining
The second and third arithmetic processes are executed while changing the thermal resistance Rth, and a fourth thermal resistance Rth is obtained in which the relation obtained by the third arithmetic process is closest to the relation obtained in the first arithmetic process. An evaluation device for a power semiconductor element, further comprising: an arithmetic device that executes arithmetic processing.   The arithmetic unit uses the thermal resistance Rth obtained by the fourth arithmetic processing and the drain current (Id0) in the state where the power semiconductor element to be evaluated does not self-heat using the equations (1) and (2). The apparatus for evaluating a power semiconductor element according to claim 6, wherein a fifth calculation process for obtaining the above is executed.   7. When the channel width of the power semiconductor element to be evaluated is set to Weff, ((ΔId0 / ΔVd) / Weff) is obtained as the normalized gradient in the third calculation process. Item 8. The power semiconductor element evaluation apparatus according to Item 7.

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