JP5157194B2 - Data acquisition circuit, data acquisition system, and control method of data acquisition circuit - Google Patents

Data acquisition circuit, data acquisition system, and control method of data acquisition circuit Download PDF

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JP5157194B2
JP5157194B2 JP2007048022A JP2007048022A JP5157194B2 JP 5157194 B2 JP5157194 B2 JP 5157194B2 JP 2007048022 A JP2007048022 A JP 2007048022A JP 2007048022 A JP2007048022 A JP 2007048022A JP 5157194 B2 JP5157194 B2 JP 5157194B2
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signal
data strobe
strobe signal
data
read command
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JP2007265399A (en
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清則 小椋
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富士通セミコンダクター株式会社
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Description

  The present invention relates to a technique for eliminating a high impedance state from a data strobe signal DQS output in synchronization with a data signal DQ in a DDR SDRAM and generating a strobe signal for taking in the data signal DQ.

  In a read operation of a DDR SDRAM (Double Data Rate Synchronous Random Access Memory), data is output from the SDRAM to the memory bus in synchronization with the edge of the data strobe signal DQS. At this time, the ternary data strobe signal DQS transitions from a high impedance state to a low level or a high level. On the other hand, the device that reads data captures the data output on the memory bus in synchronization with the edge of the data strobe signal DQS. Further, when data is actually captured in the device, an internal data strobe signal in which high impedance is masked from the data strobe signal is used. The data strobe signal in the high impedance state is likely to be mixed with noise because the signal level becomes unstable. This is because if the data strobe signal in such a state is used as a data capture clock, erroneous capture may occur.

As a technique for masking the high impedance state from the data strobe signal DQS, an SDRAM interface circuit 100 shown in FIG. 14 is used.
The SDRAM interface circuit 100 receives the read command signal RD, the standby clock number RL, and the clock signal CK, and outputs the BL count start signal BST, the BL count start signal BST, the BL count start signal BST, the burst length BL, and the capture. A BL count comparator 102 that receives the data strobe signal IDQS and outputs the mask signal XMASK, and an AND gate 103 that receives the mask signal XMASK and the data strobe signal DQS and outputs the fetched data strobe signal IDQS. .

The RL count comparison unit 101 starts counting the clock signal CK when the read command signal RD is input, and outputs a BL count start signal BST when the count value reaches the standby clock number RL. Here, the number of standby clocks RL is set in advance.
When the BL count start signal BST is input, the BL count comparison unit 102 activates the mask signal XMASK and starts counting the fetched data strobe signal IDQS. Until the count value reaches the burst length BL, the mask signal Retains the active state of XMASK.

  With the above configuration, the SDRAM interface circuit 100 starts counting the clock signal CK after the read command signal RD is input. When the count value reaches the standby clock number RL, the mask signal is output by the number of clocks of the burst length BL. XMASK is activated. The standby clock number RL is set in advance so as to exceed the period in which the data strobe signal DQS is in the high impedance state. As a result, the data strobe signal DQS is masked during the high impedance period, and as a result, the high impedance state input to the data fetch clock is prevented.

As a technology related to the SDRAM interface circuit, there is a technique disclosed in Patent Document 1.
JP 2003-85974 A

  However, if manufacturing conditions such as process variations and operating conditions such as temperature and voltage change and the delay time between the SDRAM and the SDRAM interface circuit 100 increases, the high impedance state may exceed the period of the number of standby clocks RL. Arise. In such a case, the high-impedance mask period of the data strobe signal DQS is insufficient, and as a result, a high impedance is input to the data fetch clock, which is a problem.

  The present invention has been made in view of the problems of the background art described above, and is a data acquisition circuit that reliably blocks propagation of a high-impedance state of a data strobe signal even when manufacturing conditions and operating conditions change, and a control method therefor The purpose is to provide.

The solution is a data acquisition circuit that masks invalid input of the data strobe signal when the data signal is acquired in synchronization with the data strobe signal together with the data strobe signal in response to a read command signal. A response time measuring unit that measures a response time from the input of the command signal to the effective edge of the data strobe signal, and a standby time that is a time based on the response time in response to a standby start signal based on the read command signal And a standby unit for commanding release of the masking of the data strobe signal, and the data strobe signal outputs the effective edge that transitions from a high impedance to a first logic level in response to the read command signal. The response time measuring unit is configured to output the high impedance of the data strobe signal. A transition detection unit that detects a transition from the first command level to the first logic level, and a measurement unit that measures the response time until the detection result of the transition detection unit is output from the input of the read command signal, the transition detection unit is supplied with the data strobe signal to the inverting input terminal, a first comparator first threshold voltage for detecting the first logic level to the non-inverting input terminal is input, the non-inverting input An inverted data strobe signal that is complementary to the data strobe signal is input to the terminal, and a second threshold voltage that detects a second logic level that is complementary to the first logic level is input to the inverted input terminal. A data acquisition circuit comprising: a second comparator; and a gate circuit that calculates a logical product of outputs of the first comparator and the second comparator.

According to another aspect of the invention, there is provided a data acquisition circuit control method for masking invalid input of the data strobe signal when the data signal is acquired in synchronization with the data strobe signal together with the data strobe signal in response to the read command signal. A step of measuring a response time from an input of the read command signal to an effective edge of the data strobe signal, and after waiting for a standby time that is a time based on the response time according to the read command signal Commanding to cancel the masking of the data strobe signal, wherein the data strobe signal outputs the effective edge that transitions from a high impedance to a first logic level in response to the read command signal, and The step of measuring the response time includes the step of measuring the high impedance of the data strobe signal. Detecting a transition from the input to the first logic level, and measuring the response time from when the read command signal is input until the detection result at the step of detecting the transition is output. , the step of detecting said transition, the data strobe signal as the inverting input, a first threshold voltage for detecting the first logic level as a non-inverting input, the steps of the first comparison, the data strobe A second comparison is performed using an inverted data strobe signal complementary to the signal as a non-inverted input, and a second threshold voltage detecting a second logic level complementary to the first logic level as an inverted input. And a step of calculating a logical product of the comparison result of the first comparison step and the comparison result of the second comparison step. A method of controlling the data acquisition circuitry, characterized in Rukoto.

  In the data acquisition circuit of the present invention, the response time from the input of the read command signal to the effective edge of the data strobe signal is measured, and this response time is set to the standby time in the standby unit (hereinafter also referred to as standby time). . That is, even if the manufacturing conditions such as the process and the operating conditions such as the temperature and the power supply voltage change and the delay time of the read command signal varies, the standby time is set based on the actually measured response time. As a result, it is possible to provide a data acquisition circuit that can reliably mask the propagation of the high impedance of the data strobe signal without being affected by the manufacturing conditions and the operating conditions.

  By applying the present invention, it is possible to provide a data capturing circuit that reliably masks the propagation of a high-impedance state of a data strobe signal and a control method thereof, even if manufacturing conditions and operating conditions change.

  DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of a data acquisition circuit, a data acquisition system, and a data acquisition circuit control method according to an embodiment of the present invention will be described below in detail with reference to FIGS.

  FIG. 1 is a circuit block diagram of a data acquisition system to which the present invention is applied. This system includes a synchronous dynamic random access memory (hereinafter referred to as SDRAM) (R) and a controller (C) that controls the SDRAM (R). Each of the SDRAM (R) and the controller (C) is supplied with a system clock signal SCK to perform a synchronous operation.

  The data read command signal CMD issued from the controller (C) is input to the data fetch circuit 1 provided in the controller (C) and transmitted to the SDRAM (R) via the external bus. This transmission time is the first flight time FT (1). This is the time when the data read command signal CMD issued from the controller (C) propagates through the external bus and is expressed by the number of clocks of the system clock signal SCK.

  The data read command signal CMD that has reached the SDRAM (R) is decoded in the SDRAM (R) and then the data signal DQ is read. The time until the data signal DQ is read from a memory cell (not shown) in the SDRAM (R) is the CAS latency CL. The access time from the input of the data read command signal CMD to the output of the data signal DQ is a time expressed by the number of clocks of the system clock signal SCK. Upon receiving the data read command signal CMD, the SDRAM (R) changes the signal level of the data strobe signal DQS from the high impedance state to the low level. Thereafter, the signal level of the data strobe signal DQS transitions from the low level to the high level in synchronization with the output of the data signal DQ. In SDRAM (R), the transition timing of the data strobe signal DQS from the high impedance state to the low level is defined as a time that is the reverse of the read preamble time (tRPRE) from the elapsed time of the CAS latency CL. For example, the timing is one cycle before.

  The data strobe signals DQS and XDQS and the data signal DQ are transmitted to the controller (C). Here, the data strobe signals DQS and XDQS are complementary to each other. This transmission time is the second flight time FT (2). This is the time when the data strobe signals DQS and XDQS output from the SDRAM (R) and the data signal DQ are transmitted through the external bus and expressed as the number of clocks of the system clock signal SCK.

  A transition from the high impedance state of the data strobe signals DQS and XDQS to the low level and the high level is detected by the data fetch circuit 1 as a valid edge, and from the read command signal RD issued in response to the data read command signal CMD. By measuring the time, the data signal DQ transmitted from the SDRAM (R) can be reliably captured.

  FIG. 2 is a block diagram showing a configuration of a data fetch circuit 1A for fetching the data signal DQ from the SDRAM according to the first embodiment. The data capture circuit 1A is a part of a circuit that captures a data signal DQ that is output in synchronization with the data strobe signal DQS that takes a three-state state, and the captured data strobe from which the high impedance state of the data strobe signal DQS has been eliminated. It is a circuit that generates a signal IDQS.

  The data acquisition circuit 1A receives a read command signal RD, an internal data strobe signal EDQS, which will be described later, and a clock signal CK, inputs an RL measurement unit 10 that outputs a latency measurement value RLB, and a read command signal RD, and performs a delay read. And a delay unit 20 that outputs a command signal RDD.

  Further, the data acquisition circuit 1A receives the delayed read command signal RDD, the latency measurement value RLB, and the clock signal CK, and outputs the BL count start signal BST, the RL count comparison unit 30, the data strobe signal DQS, and the data strobe signal. A transition detection unit 40 that receives an inverted data strobe signal XDQS and an inverted mask signal XMASK, which are signals complementary to DQS, and outputs an internal data strobe signal EDQS is provided.

  Further, the data acquisition circuit 1A receives the BL count start signal BST, the burst length BL, and the acquisition data strobe signal IDQS, and outputs an inverted mask signal XMASK, an inverted mask signal XMASK, and a data strobe. And a gate circuit 60 that receives the signal DQS and outputs the fetched data strobe signal IDQS.

  FIG. 3 is a circuit diagram showing a specific example of the data fetch circuit 1A. The RL measuring unit 10 includes flip-flops 11A to 11H whose inverted clock terminals are connected to the clock signal CK, and 12A to 12H whose clock terminals are connected to the internal data strobe signal EDQS. The flip-flops 11A to 11H constitute a shift register having a serial input terminal as a data input terminal of the flip-flop 11A. Further, the flip-flops 12A to 12H constitute a register that holds the latency count values RLA0 to RLA7, which are outputs of the flip-flops 11A to 11H, according to the internal data strobe signal EDQS. The output terminals of the flip-flops 12A to 12H are connected to the RL count comparison unit 30 as latency measurement values RLB0 to RLB7.

  The delay unit 20 includes a flip-flop having an inverted clock terminal connected to the clock signal CK and a data input terminal connected to the read command signal RD. Thereby, in the delay unit 20, the read command signal RD is delayed by one cycle of the clock signal CK and is output as the delayed read command signal RDD.

  The RL count comparison unit 30 calculates a latency measurement value from one of the flip-flops 31A to 31H whose clock signal CK is connected to each inverted clock terminal and the RL count values RLC0 to 7 output from the flip-flops 31A to 31H. And a comparison circuit 32 that selects according to the values of RLB0 to RLB7. The flip-flops 31A to 31H constitute a shift register using the data input terminal of the flip-flop 31A as a serial input terminal. When the delayed read command signal RDD is input to the data input terminal of the flip-flop 31A, the RL count value RLC is sequentially shifted up. When the RL count value RLC reaches the latency measurement value RLB, the BL count start signal BST transits to a high level.

  The transition detection unit 40 compares the data strobe signal DQS and the inverted data strobe signal XDQS that are complementary to each other with the high level threshold voltage VREFH and the low level threshold voltage VREFL. Thereby, the transition of the data strobe signal DQS from the high impedance to the low level is detected, and the internal data strobe signal EDQS is output.

  FIG. 4 is a circuit diagram illustrating a specific example of the transition detection unit 40. The transition detection unit 40 includes a first comparator 41, a second comparator 42, and gate circuits 43 and 44. In the first comparator 41, the non-inverting input terminal is connected to the low level threshold voltage VREFL, the inverting input terminal is connected to the data strobe signal DQS, and the output is connected to the other input terminal of the gate circuit 43. In the second comparator 42, the non-inverting input terminal is connected to the inverted data strobe signal XDQS, the inverting input terminal is connected to the high level threshold voltage VREFH, and the output terminal is connected to one input terminal of the gate circuit 43. In the gate circuit 44, one input is connected to the output of the gate circuit 43, the other negative logic input is connected to the inverted mask signal XMASK, and the output is connected to the internal data strobe signal EDQS.

Data strobe signal DQS and inverted data strobe signal XDQS have complementary signal levels. That is, when the data strobe signal DQS is at a high level, the inverted data strobe signal XDQS is at a low level, and when the data strobe signal DQS is at a low level, the inverted data strobe signal XDQS is at a high level. However, when the data strobe signal DQS and the inverted data strobe signal XDQS are in a high impedance state, each signal is set to an intermediate voltage between the high level and the low level by a terminal resistor (not shown) connected to the outside. Is done. Since the termination resistance for each signal is the same for all signals, when each signal is in a high impedance state, it takes substantially the same potential.
For the data strobe signal DQS and the inverted data strobe signal XDQS, the high level threshold voltage VREFH is a threshold voltage for detecting a high level, and the low level threshold voltage VREFL is a threshold voltage for detecting a low level.

  When the data strobe signal DQS is at a low level and the inverted data strobe signal XDQS is at a high level, the first comparator 41 outputs a high level because the data strobe signal DQS is lower than the low level threshold voltage VREFL. The second comparator 42 outputs a high level because the inverted data strobe signal XDQS is higher than the high level threshold voltage VREFH. As a result, a high level is output from the gate circuit 43.

  Next, when the data strobe signal DQS is at a high level or the inverted data strobe signal XDQS is at a low level, the first comparator 41 is low because the data strobe signal DQS is higher than the low level threshold voltage VREFL. The second comparator 42 outputs a low level because the inverted data strobe signal XDQS is lower than the high level threshold voltage VREFH. As a result, a low level is output from the gate circuit 43.

  Finally, when both the data strobe signal DQS and the inverted data strobe signal XDQS have high impedance, the respective signals have the same potential, and therefore at least one of the first comparator 41 and the second comparator 42. Output becomes low level. As a result, a low level is output from the gate circuit 43.

  As described above, when the data strobe signal DQS is high impedance and low level, the gate circuit 43 outputs a low level, so that the internal data strobe signal EDQS outputs a low level. Further, when the data strobe signal DQS is at a high level, a high level is output from the gate circuit 43. Therefore, a high level is output to the internal data strobe signal EDQS during a period when the inverted mask signal XMASK is at a low level. .

  Returning to FIG. 3, the BL count comparison unit 50 will be described. The BL count comparison unit 50 includes a count comparator 51 in which the burst length BL is connected to the comparison input terminal C, the inverted mask signal XMASK is connected to the count enable terminal EN, and the capture data strobe signal IDQS is connected to the inverted clock terminal. The output of the counting comparator 51 is connected to the input terminal, the gate circuit 52 is connected to the non-inverted input terminal and the inverted mask signal XMASK, the data input terminal is the output of the gate circuit 52, and the inverted clock terminal is the captured data strobe signal. And a flip-flop 53 connected to the IDQS. Here, the fetched data strobe signal IDQS is a signal obtained by ANDing the inverted mask signal XMASK and the data strobe signal DQS in the gate circuit 60.

  The BL count start signal BST is connected to the clear terminal CLR of the count comparator 51 and the preset terminal PR of the flip-flop 53. Thus, when the BL count start signal BST becomes high level, the count comparator 51 is reset, the flip-flop 53 is preset, and the BL count comparison unit 50 is initialized.

  When the BL count comparison unit 50 is initialized, a high level is output to the inverted mask signal XMASK, and the count value of the count comparator 51 is set to zero. Further, the count comparator 51 counts for each falling edge of the captured data strobe signal IDQS, and outputs a high level when the count value reaches the burst length BL. Then, a low level is output to the output of the gate circuit 52. Further, in flip-flop 53, at the falling edge of the next fetched data strobe signal IDQS, the inverted mask signal XMASK, which is the output thereof, transitions to a low level.

Next, the operation of the data fetch circuit 1A will be described. FIG. 5 is a timing chart showing the operation of the data fetch circuit 1A according to the first embodiment.
Here, the clock signal CK is a clock signal of the data capturing circuit 1A having a frequency relationship twice that of the system clock signal SCK. The data read command signal CMD is a signal for instructing the SDRAM (R) (see FIG. 1) by the controller (C) (see FIG. 1). That is, the data read command signal CMD is issued from the controller (C) to the SDRAM (R). In FIG. 5, “CMD (controller)” indicates an output from the controller (C), and “CMD (SDRAM)” indicates an input to the SDRAM (R). Yes. Further, “(count value in 51)” indicates an internal count value in the count comparator 51. Other symbols are symbols based on the signal names described in FIG.

  In FIG. 5, “FT (1)” and “FT (2)” indicate the first and second flight times, respectively, and “CL” indicates CAS latency. In this example, the flight time FT (1) = FT (2) = 1.5 and the CAS latency CL = 2.

  The data read command signal CMD issued in the controller (C) reaches the SDRAM (R) at the first flight time FT (1). When the read preamble time (tRPRE) of the SDRAM (R) is one cycle of the system clock signal SCK, the data strobe signal DQS is changed from the high impedance state to the low level after receiving the data read command signal CMD. The number of clocks until the valid edge transitioning to is 1 obtained by subtracting 1 from 2 which is the CAS latency CL. Further, the data strobe signal DQS transitioned to the low level in the SDRAM (R) reaches the controller (C) at the second flight time FT (2). That is, the latency RL, which is the number of clocks from the data read command signal CMD issuance (transition of the read command signal RD to the high level) by the controller (C) to the valid edge of the data strobe signal DQS, is 4.0. The response time TRL from the input of the read command signal RD to the valid edge of the data strobe signal DQS is represented by a period of 4.0 × system clock signal SCK.

  In (1), when “Read” is issued as the data read command signal CMD and the read command signal RD transits to a high level, the RL measuring unit 10 starts counting the latency count value RLA. Also in (2), counting of the RL count value RLC is started after being delayed by one cycle of the clock signal CK which is a delay time by the delay unit 20. Since the count values of the latency count value RLA and the RL count value RLC are both count values by the shift register, they take values shifted bit by bit from the least significant bit. In other words, the count values are output in octal numbers in the order of 01, 02, 04, 08, 10, 20, 40, 80.

  In (3), when the data strobe signal DQS transitions from a high impedance to a low level, the transition detection unit 40 detects this state transition and outputs a high level to the internal data strobe signal EDQS. When the internal data strobe signal EDQS transitions to a high level, the RL measurement unit 10 holds the value of the latency count value RLA and outputs 20 as the latency measurement value RLB. The value of the latency measurement value RLB is a value corresponding to the response time TRL in which the data strobe signal DQS transitions from the high impedance to the low level from the input of the read command signal RD.

  In (4), when the output value 20 of the latency measurement value RLB matches the output value 20 of the RL count value RLC, the RL count comparison unit 30 starts the BL count only for a period in which the RL count value RLC takes a value of 20. A high level is output as the signal BST. The RL count comparison unit 30 starts counting by delaying by one cycle of the clock signal CK that is a delay time by the delay unit 20 in advance, and the RL count value RLC is 1 of the clock signal CK rather than the latency count value RLA. Since it is delayed by the period, the BL count start signal BST is output from the next cycle of the response time TRL.

  When the BL count start signal BST transitions to a high level, the count value in the count comparator 51 is initialized to 0, and the BL count comparison unit 50 outputs a high level to the inverted mask signal XMASK. When the inverted mask signal XMASK transitions to a high level, the level of the data strobe signal DQS is propagated through the gate circuit 60, and the strobe signal is output to the fetched data strobe signal IDQS.

  In (5), when the count value of the count comparator 51 reaches a value set to the burst length BL (BL = 1 when the burst length = 2), the inversion mask is set at the falling edge of the captured data strobe signal IDQS. A low level is output to the signal XMASK. As a result, the subsequent data strobe signal DQS is blocked by the gate circuit 60.

  In the SDRAM (R), when the read operation for the data read command signal CMD is not completed and the data read command signal CMD is issued, the Burst READ Interrupt by READ mode is performed. In this case, the data strobe signal DQS outputs the data strobe signal DQS for the second data read command signal CMD without transitioning to high impedance. The RL count comparison unit 30 starts counting the RL count value RLC from the time when the read command signal RD corresponding to the second data read command signal CMD is issued. When the count value reaches 20, the BL count start signal BST is output again. As a result, the inversion mask signal XMASK reflects the latency (that is, 4.0) with respect to the second read command signal RD, and the cutoff control of the data strobe signal DQS is performed at the output timing of the strobe signal of the data strobe signal DQS. Will be done accurately along.

  In the data acquisition circuit 1A according to the first embodiment, the latency measurement value RLB obtained by measuring the time from the input of the read command signal RD to the internal data strobe signal EDQS is set as the response time TRL in the RL count comparison unit 30. . As a result, the flight times FT (1) and FT (2) are different from each other in manufacturing conditions such as a difference in wiring length and wiring load of the external bus connecting the controller (C) and the SDRAM (R), and / or process variations, Even if operating conditions such as temperature and power supply voltage change, the data strobe signal can be controlled to be cut off by adjusting the latency according to the change. Therefore, it is possible to provide a data acquisition circuit 1A that reliably blocks propagation of a high impedance state without being affected by changes in flight times FT (1) and FT (2).

  Instead of the delay unit 20, a shift unit 20A that shifts a later-described latency measurement value RLB to the left and outputs a latency measurement value RLB2 may be provided. Thereby, the flip-flops 31A to 31H are shifted at the same timing as the flip-flops 11A to 11H, but the latency measurement value RLB2 is shifted to the left, so that the BL count is the same as when the delay unit 20 is used. A start signal BST can be output.

  If the number of shift bits is fixed for the shift unit 20A, it is sufficient to connect the latency measurement value RLB from the RL measurement unit 10 to the RL count comparison unit 30 so that the bit arrangement is shifted. Thereby, it is possible to make the circuit configuration simpler than when the delay unit 20 is used. Even when the delay time of the latency measurement value RLB is changed, it can be easily realized by using a barrel shifter or the like for the shift unit 20A.

  Next, the data fetch circuit 1B according to the second embodiment will be described. FIG. 6 is a block diagram showing the structure of the data fetch circuit 1B. The data acquisition circuit 1B is different from the data acquisition circuit 1A of the first embodiment in that the measurement command signal RLE and the clock signal CK are input and a gate circuit 80 that outputs to the clock terminal of the RL measurement unit 10 is provided. Other components are the same as those of the data fetch circuit 1A. Therefore, different parts from the data acquisition circuit 1A of the first embodiment will be mainly described, and description of other parts will be simplified or omitted.

  The RL measuring unit 10 receives the first data strobe signal DQS1 indicating the first rising edge after the transition from the high impedance to the low level in the data strobe signal DQS. The first data strobe signal DQS1 includes a transition detection unit 40 similar to the data acquisition circuit 1A in the first embodiment, and delays detection of a transition from a high impedance to a low level of the data strobe signal DQS. It can also be generated.

  In the gate circuit 80, the logical product of the measurement command signal RLE input to one side and the clock signal CK input to the other side is calculated, and the result is output to the clock terminal of the RL measurement unit 10. As a result, the RL measurement unit 10 updates the latency measurement value RLB only during a period in which the measurement command signal RLE is at a high level. The operations after the setting of the latency measurement value RLB are the same as those of the data fetch circuit 1A of the first embodiment.

  Here, the measurement command signal RLE is controlled so as to transition to a high level for a specific period, for example, when the power is turned on or when the system is initially set, thereby counting or updating operation for obtaining the latency measurement value RLB. Can be avoided at every transition from the high impedance to the low level in the data strobe signal DQS. As a result, it is possible to reduce the operating power required for counting and updating operations for obtaining the latency measurement value RLB, and consequently, it is possible to reduce the power consumption of the entire data capturing circuit 1B.

  Next, a data acquisition circuit 1C according to the third embodiment will be described. The data acquisition circuits 1A and 1B (first and second embodiments) measure time by counting the clock signal CK, whereas the data acquisition circuit 1C measures time using a delay line. To do. We are trying to improve the accuracy of time measurement.

  FIG. 7 is a block diagram showing the structure of the data fetch circuit 1C. The data acquisition circuit 1C includes an RL measurement unit 15 and an RL count comparison unit 35 instead of the RL measurement unit 10 and the RL count comparison unit 30 in the data acquisition circuit 1A of the first embodiment. Unlike the data fetch circuit 1A, the delay unit 20 and the shift unit 20A are not provided. Other components are the same as those of the data fetch circuit 1A. Therefore, different parts from the data acquisition circuit 1A of the first embodiment will be mainly described, and description of other parts will be simplified or omitted.

  The RL measuring unit 15 receives the read command signal RD and the internal data strobe signal EDQS, and measures the time from the input of the read command signal RD to the output of the internal data strobe signal EDQS using a delay line. As the measured time, a code signal CODE1 for setting the delay time of the delay line is output. The RL count comparison unit 35 includes a delay line, performs time measurement using the time measured by the RL measurement unit 15 as a standby time according to the input code signal CODE1, and outputs a BL count start signal BST.

  Note that the RL measuring unit 15 can be controlled by the measurement command signal RLE so that the measurement operation can be performed only when the power is turned on or when the system is initially set. If the code signal CODE1 of the measurement time is acquired and held at the time of initialization, thereafter, the delay line of the RL count comparison unit 35 can be set according to the held code signal CODE1. In this case, the measurement end signal END may be output when the measurement operation by the RL measurement unit 15 is completed and the code signal CODE1 is acquired. The acquisition of the code signal CODE1 can be notified.

  FIG. 8 is a specific example of the RL count comparison unit 35. A delay line DL is provided. The read command signal RD is input to the delay line input terminal (DL_IN), and the code signal CODE1 is input to the code input terminal (DLI_CODE). The BL count start signal BST is output from the delay line output terminal (DL_OUT).

  The delay line DL includes delay units DU0 to DUN connected in series in multiple stages from a delay line input terminal (DL_IN). Each of the delay units DU0 to DUN is connected to the next delay unit via a first logic inversion circuit such as an inverter gate, and is further connected to an output tap (via a second logic inversion circuit such as an inverter gate). T0) to (TN). Each output tap (T0) to (TN) is input to the selection unit DLS. In the selection unit DLS, any one of the output taps (T0) to (TN) is selected according to the code signal CODE1 input from the code input terminal (DLI_CODE) and connected to the delay line output terminal (DL_OUT). .

  An RL measurement unit 15A illustrated in FIG. 9 is a first specific example of the RL measurement unit 15 of the third embodiment. The time from the read command signal RD to the internal data strobe signal EDQS is measured by sequentially changing the delay time of the delay line DL by sequentially changing the code signal CODE1.

  The RL measurement unit 15 </ b> A includes a delay line DL having the same configuration as the delay line DL provided in the RL count comparison unit 35, and a measurement determination unit 17. The read command signal RD is input to the delay line input terminal (DL_IN), and the delay signal RD1 output from the delay line output terminal (DL_OUT) is input to the measurement determination unit 17. A code signal CODE1 that changes sequentially is input from the measurement judgment unit 17 to the code input terminal (DLI_CODE). A measurement command signal RLE and an internal data strobe signal EDQS are input to the measurement determination unit 17.

  In the measurement determination unit 17, the code signal CODE1 is initialized in accordance with the input of the measurement command signal RLE (S1). After the initialized code signal CODE1 is sent to the delay line DL and the delay time of the delay line is initialized, the read command signal RD transitions to a high level. From the delay line DL, the delay signal RD1 changes to high level in the initialized time. The logical value of the internal data strobe signal EDQS is confirmed according to the transition of the delay signal RD1 (S2). If the logical value of internal data strobe signal EDQS is at a low level (S2: NO), it is determined that data strobe signal DQS is still high impedance. The code signal CODE1 is incremented by "1" (S3), the process proceeds to step (S2), and the read command signal RD is input again. If the logical value of the internal data strobe signal EDQS is at a high level (S2: YES), the set code signal CODE1 is held and output (S4). At the same time, a measurement end signal END is output.

  With the delay time per delay unit of the delay line DL, the time from the read command signal RD to the internal data strobe signal EDQS can be measured. Since the measured time is held as the code signal CODE1 in the measurement determination unit 17, the delay line DL provided in the RL count comparison unit 35 is set according to the held code signal CODE1, and the waiting time is accurately measured. Can do.

  An RL measurement unit 15B illustrated in FIG. 10 is a second specific example of the RL measurement unit 15 of the third embodiment. In response to the high level transition of the internal data strobe signal EDQS, signals output to the output taps (T0) to (TN) of the delay line DL through which the read command signal RD propagates are acquired. Of these signals, the time from the read command signal RD to the internal data strobe signal EDQS is measured by detecting the position where the logic level switches from the low level to the high level.

  The RL measurement unit 15B is connected to a delay line DL having the same configuration as the delay line DL provided in the RL count comparison unit 35 and an input terminal (D) for each of the output taps (T0) to (TN) of the delay line DL. Flip-flops FF0 to FFN and a detection unit 18 to which output signals Q0 to QN output from the output terminals (Q) of the flip-flops FF0 to FFN are input. The flip-flops FF0 to FFN take in signals output from the output taps (T0) to (TN) at the high level transition of the internal data strobe signal EDQS, and output the signals as output signals Q0 to QN from the output terminals (Q).

  When a high level read command signal RD is input to the delay line input terminal (DL_IN) of the delay line DL, the high level signal sequentially propagates through the delay units DU0 to DUN, and the output taps (T0) to (TN). ) Goes to high level sequentially. The detection unit 18 takes in the output signals Q0 to QN of the output taps (T0) to (TN) at the time when the internal data strobe signal EDQS transits to a high level, and detects the logic level. Of the output signals Q0 to QN, the boundary position between the low level and the high level is specified. The specified position is decoded and output as a code signal CODE1.

  A specific example of the detection unit 18 is shown in FIG. AND gates A0 to AN-1 are provided to which adjacent output signals are input. Of the output signals Q0 to QN input to the AND gates A0 to AN-1, the signal output from the delay unit at the subsequent stage is inverted and input. Thereby, the transition position from the low level to the high level due to the input of the read command signal RD can be detected. The signals detected and output from the AND gates A0 to AN-1 are decoded by the decoding unit 19, and the code signal CODE1 is output.

  In the RL measuring units 15A and 15B of the third embodiment, the time from the read command signal RD to the internal data strobe signal EDQS can be measured by the delay time per delay unit of the delay line DL. The measured time is held as the code signal CODE1 in the measurement determination unit 17 in the first specific example. In the second specific example, it can be held by the detection unit 18. The delay line DL provided in the RL count comparison unit 35 is set according to the held code signal CODE1, and the standby time can be accurately measured.

  Next, a data acquisition circuit 1D according to the fourth embodiment will be described. A combination of coarse time measurement by counting the clock signal CK in the data acquisition circuits 1A and 1B (first and second embodiments) and fine time measurement by the delay line DL in the data acquisition circuit 1C (third embodiment). To measure. A coarse circuit that counts the clock signal CK is used for coarse measurement that does not require measurement accuracy, and a delay line is used for high-precision measurement that requires high-precision measurement after coarse measurement. Measure time. High-precision time measurement can be performed using an optimum measurement means in accordance with the required time measurement resolution.

  FIG. 12 is a block diagram showing the structure of the data fetch circuit 1D. In addition to the data acquisition circuit 1C of the third embodiment, a CL measurement unit 90 is provided. The CL measurement unit 90 receives the read command signal RD, the CAS latency CL, and the clock signal CK, and outputs a CAS latency measurement value CLB. The RL measurement unit 15 and the RL count comparison unit 35 have the same configuration as that of the data acquisition circuit 1C of the third embodiment, but the CAS latency measurement value CLB is input to each input instead of the read command signal RD. Is done. The signal output from the RL measurement unit 15 and input to the RL count comparison unit 35 is a code signal CODE2 instead of the code signal CODE1.

  The CL measuring unit 90 starts the count operation of the clock signal CK in response to the high level transition of the read command signal RD. The count operation is performed the number of times obtained by subtracting “1” from the CAS latency CL. In this case, the read preamble time (tRPRE) is one cycle of the clock signal CK. In the data acquisition system (FIG. 1), the data read command signal CMD issued from the controller (C) reaches the SDRAM (R) through the first flight time FT (1) and is started in the SDRAM (R). The time until the data is output from the SDRAM (R) by the data read operation is the CAS latency CL. At a timing one cycle before the CAS latency CL, the SDRAM (R) changes the data strobe signal DQS from the high impedance to the low level. Thereafter, the low level transition of the data strobe signal DQS is propagated to the controller (C) at the second flight time FT (2). Since the time for the data strobe signal DQS to transition to the low level after the SDRAM (R) receives the data read command signal CMD is determined in advance as the time obtained by subtracting “1” from the CAS latency, the CL measuring unit 90 , Measure this time.

  The CAS latency measurement value CLB output from the CL measurement unit 90 is input to the RL measurement unit 15, and the time until the internal data strobe signal EDQS is output from the CAS latency measurement value CLB is measured by the delay line DL. The measured time is sent to the RL count comparison unit 35 as a code signal CODE2. The RL count comparison unit 35 measures the delay time set by the code signal CODE2 from the CAS latency measurement value CLB as the standby time.

  Of the time from the read command signal RD to the internal data strobe signal EDQS, for the CAS latency measurement value CLB that can be measured with the resolution of the cycle of the clock signal CK, the CL measurement unit 90 counts the cycle of the clock signal CK. Done. The first and second flight times FT (1) and FT (2), which are delay times when signals are propagated between the controller (C) and the SDRAM (R), are added to the load added to the external data bus. It changes continuously in response. By measuring the continuously changing time with the delay line DL, it is possible to accurately measure the time. If both are added, the response time from the read command signal RD to the internal data strobe signal EDQS can be accurately measured with a simple circuit.

  Next, a data acquisition circuit 1E according to the fifth embodiment will be described. The data acquisition circuit 1E shown in FIG. 13 includes a BL count start signal BST of the data acquisition circuits 1A to 1D (first to third embodiments), data acquisition circuits 1A, 1B, and 1D (first, second, and fourth embodiments). Form) clock signal CK, code signal CODE1 of data fetch circuit 1C (third embodiment), and / or code signal CODE2 of data fetch circuit 1D (fourth embodiment). Is provided.

  In a data acquisition system in which a controller (C) and an SDRAM (R) are connected via an external bus, a load on a signal path formed by a signal line or an external bus in the controller (C) and SDRAM (R) Or / and a noise filter or the like inserted in the external bus may cause a delay in signal propagation. In general, these delay times vary depending on the signal path length, the surrounding environment of the signal path, and the signal propagation delay time depending on the noise filter. In order to adjust the delay time, Ji-extension West 95 is provided. It is preferable that the delay adjustment unit 95 can adjust the delay time by the adjustment signal ADJ. Thereby, the delay time can be adjusted according to the system configuration of the data acquisition system.

Note that the present invention is not limited to the above-described embodiment, and it goes without saying that various improvements and modifications can be made without departing from the spirit of the present invention.
For example, in the first and second embodiments, a counter is configured using a shift register in the RL measuring unit 10 and the RL count comparing unit 30, but a counter may be configured using a normal binary counter. Is possible.
In the third and fourth embodiments, the delay line DL is provided in the RL measurement units 15A and 15B separately from the RL count comparison unit 35. However, the present invention is not limited to this. is not. When the time measurement is performed in the RL measurement units 15A and 15B, the delay line DL provided in the RL count comparison unit 35 may be used.

  The RL measurement unit 10 and the transition detection unit 40, the RL measurement unit 15 and the transition detection unit 40, the CL measurement unit 90, the RL measurement unit 15 and the transition detection unit 40 are an example of a response time measurement unit, an RL count comparison unit. 30, the RL count comparison unit 35 is an example of a standby unit, the read command signal RD, the delayed read command signal RDD, and the CAS latency measurement value CLB are examples of the standby start signal, the RL measurement units 10 and 15, and the CL measurement unit 90. The RL measurement unit 15 is an example of a measurement unit, and the delay unit 20 or the shift unit 20A is an example of a standby adjustment unit. The low level is an example of a first logic level, the high level is an example of a second logic level, the low level threshold voltage VREFL is an example of a first threshold voltage, and the high level threshold voltage VREFH is an example of a second threshold voltage. The flip-flops 11A to 11H are an example of a first counter unit, and the flip-flops 12A to 12H are an example of a first holding unit. The measurement determination unit 17, the flip-flops FF0 to FFN, and the detection unit 18 are examples of a selection unit. The flip-flops FF0 to FFN are examples of the delay line signal holding unit. The CL measurement unit 90 is an example of a first measurement unit, and the RL measurement unit 15 of the fourth embodiment is an example of a second measurement unit. Further, the period of the clock signal CK obtained by subtracting “1” from the CAS latency CL, that is, the time from the data read operation in the SDRAM (R) until the data is output is an example of the first time, the controller (C) The first and second flight times FT (1) and FT (2), which are delay times for signal propagation between the signal and SDRAM (R), are examples of the second time.

Here, the means for solving the problems in the background art according to the technical idea of the present invention are listed below.
(Supplementary note 1) A data acquisition circuit for masking invalid input of the data strobe signal when the data signal is acquired in synchronization with the data strobe signal together with the data signal in response to the read command signal, A response time measuring unit that measures a response time from the input of the data strobe signal to the valid edge of the data strobe signal, and a standby time that is a time based on the response time in accordance with a standby start signal based on the read command signal And a standby unit for instructing cancellation of the masking of the data strobe signal.
(Additional remark 2) It is a data acquisition circuit of Additional remark 1, Comprising: The said data strobe signal outputs the effective edge which changes to a 1st logic level from a high impedance according to the said read command signal, The said response time measurement A transition detection unit that detects a transition of the data strobe signal from the high impedance to the first logic level, and the response from the input of the read command signal until the detection result of the transition detection unit is output. A data acquisition circuit comprising: a measuring unit that measures time.
(Additional remark 3) It is a data acquisition circuit of Additional remark 2, Comprising: The said transition detection part is the 1st threshold value by which the said strobe input signal is input into an inverting input terminal, and the said 1st logic level is detected at a non-inverting input terminal A first comparator to which a voltage is input, an inverted data strobe signal complementary to the data strobe signal is input to a non-inverting input terminal, and a second threshold voltage for detecting the second logic level is input to the inverting input terminal. A data acquisition circuit comprising: a second comparator that is input; and a gate circuit that calculates a logical product of outputs of the first comparator and the second comparator.
(Additional remark 4) It is a data acquisition circuit of Additional remark 1, Comprising: The said response time measurement part validates the measurement of the said response time according to a measurement command signal, The data acquisition circuit characterized by the above-mentioned.
(Additional remark 5) It is a data acquisition circuit of Additional remark 1, Comprising: The said response time measurement part is a 1st counter part by which the count of a clock signal is started according to the input of the said read command signal, The said data strobe A data acquisition circuit comprising: a first holding unit that holds an output of the first counter unit in accordance with the valid edge of a signal.
(Additional remark 6) It is a data reading circuit of Additional remark 5, Comprising: The standby adjustment part which makes the said standby time delayed by one period of the said clock signal from the time according to the content hold | maintained of the said 1st holding | maintenance part A data acquisition circuit comprising:
(Additional remark 7) It is a data acquisition circuit of Additional remark 6, Comprising: The said standby adjustment part is provided with the shifter which carries out the left shift of the holding content of a said 1st holding | maintenance part, The data acquisition circuit characterized by the above-mentioned.
(Supplementary note 8) The data capture circuit according to supplementary note 6, wherein the standby adjustment unit includes a flip-flop that delays the read command signal by one cycle of the clock signal.
(Additional remark 9) It is a data acquisition circuit of Additional remark 5, Comprising: The said 1st counter part is provided with the shift register which uses the said read command signal as a data input, and uses the said clock signal as a clock input. Capture circuit.
(Supplementary note 10) The data acquisition circuit according to supplementary note 1, wherein the standby unit includes a delay line to which the standby start signal is input, and the response time measurement unit includes the delay line according to the response time. A data fetch circuit comprising a selection unit that selects an output tap of the data.
(Additional remark 11) It is a data acquisition circuit of Additional remark 10, Comprising: The said selection part switches the output tap of the delay line of the same structure as the said delay line or the said delay line sequentially, and is input into the said delay line A data fetch circuit, wherein a logic level of the data strobe signal is detected by a time when a read command signal is delayed and output.
(Additional remark 12) It is a data acquisition circuit of Additional remark 10, Comprising: The said selection part is the same structure as the said delay line or the said delay line into which the said read command signal is input according to the effective edge of the said data strobe signal A delay line signal holding unit that holds a signal of each output tap of the delay line, and a detection unit that specifies an input timing of the read command signal from the signal held in the delay line signal holding unit. Data acquisition circuit.
(Additional remark 13) It is a data acquisition circuit of Additional remark 11 or 12, Comprising: When the said response time is measured, the said read command signal is input into the said delay line with which the said waiting | standby part is equipped, The data acquisition circuit characterized by the above-mentioned .
(Additional remark 14) It is a data acquisition circuit of Additional remark 1, Comprising: The said response time measurement part removes the said 1st time from the said 1st measurement part which measures the 1st time among the said response times, and the said response time A second measuring unit that measures the second time, wherein the standby start signal is output from the first measuring unit, and the standby unit waits for a time based on the second time. circuit.
(Supplementary note 15) The data capturing circuit according to supplementary note 14, wherein the first time is a fixed time in the response time, and the second time is a time varying in the response time. A data acquisition circuit characterized by that.
(Additional remark 16) It is a data acquisition circuit of Additional remark 14, Comprising: A said 1st measurement part is a 2nd counter part by which the count of a clock signal is started according to the input of the said read command signal, The said data strobe And a second holding unit for holding the output of the second counter unit in accordance with the valid edge of the signal.
(Additional remark 17) It is a data acquisition circuit of Additional remark 1, Comprising: The delay adjustment which variably delays at least any one of the measurement timing or / and measurement result of the said response time measurement part or / and the said waiting | standby part A data capturing circuit comprising a section.
(Supplementary note 18) In the data capturing circuit according to supplementary note 17, when the measurement in the response time measurement unit and / or the standby unit is performed based on a clock signal, the delay of the measurement timing by the delay adjustment unit is: A data fetch circuit characterized by delaying a clock signal.
(Supplementary Note 19) A memory device that outputs a data signal in synchronization with a data strobe signal according to a read command signal, and an invalid input of the data strobe signal when the data signal is captured in synchronization with the data strobe signal A memory control device that masks the response time, a response time measurement unit that measures a response time from the input of the read command signal to an effective edge of the data strobe signal, and a standby based on the read command signal A data capture system comprising: a standby unit that instructs to cancel masking of the data strobe signal after waiting for a time based on the response time in accordance with a start signal.
(Supplementary note 20) A method for controlling a data capturing circuit that masks invalid input of a data strobe signal when capturing the data signal in synchronization with a data strobe signal together with a data signal in accordance with a read command signal, A step of measuring a response time from input of a read command signal to an effective edge of the data strobe signal; and after waiting for a waiting time which is a time based on the response time in accordance with the read command signal, the data strobe And a step of instructing release of the mask of the signal.
(Supplementary note 21) The data capturing circuit control method according to supplementary note 20, wherein the data strobe signal outputs the valid edge that transitions from a high impedance to a first logic level in response to the read command signal. The step of measuring the response time outputs detection results of a step of detecting a transition of the data strobe signal from the high impedance to the first logic level and a step of detecting the transition from the input of the read command signal. Measuring the response time until it is performed, and a method for controlling the data acquisition circuit.
(Supplementary note 22) In the data acquisition circuit control method according to supplementary note 20, the step of counting the response time further includes a step of enabling the measurement of the response time according to a measurement command signal. A method for controlling a data acquisition circuit.
(Supplementary note 23) The method for controlling a data capturing circuit according to supplementary note 20, wherein the step of measuring the response time includes a step of starting counting a clock signal in response to an input of the read command signal, and the data Holding the counting result of the step of starting the counting in accordance with the effective edge of the strobe signal.
(Supplementary note 24) The method for controlling a data capturing circuit according to supplementary note 20, wherein the step of releasing the mask includes a step of delaying a signal by a delay line in accordance with the read command signal, The measuring step includes a step of selecting an output tap of the delay line according to the response time.
(Supplementary note 25) The data capturing circuit control method according to supplementary note 24, wherein the selecting step includes a step of sequentially switching the delay line or an output tap of a delay line having the same configuration as the delay line; And a step of detecting a logic level of the data strobe signal in a time when the read command signal input to the delay line is output after being delayed.
(Supplementary note 26) The data capturing circuit control method according to supplementary note 24, wherein the selecting step includes the delay line or the delay to which the read command signal is input according to an effective edge of the data strobe signal. A step of holding a signal of each output tap of a delay line having the same configuration as the line; and a step of specifying the input timing of the read command signal from the signal held by the holding step Circuit control method.
(Supplementary note 27) The data acquisition circuit control method according to supplementary note 20, wherein the step of measuring the response time includes a step of measuring a first time of the response time, and a step of measuring the first time from the response time. And a step of measuring a second time excluding the step, wherein the step of canceling the mask waits for a time based on the second time.
(Supplementary note 28) The method for controlling the data acquisition circuit according to supplementary note 27, wherein the first time is a fixed time in the response time, and the second time varies in the response time. A method for controlling a data acquisition circuit, characterized by being time.
(Additional remark 29) It is a data acquisition circuit of Additional remark 27, Comprising: The step which measures the said 1st time starts the count of a clock signal according to the input of the said read command signal, The said data strobe signal And a step of holding the counting result of the step of measuring the first time according to the effective edge of the data acquisition circuit.

It is a circuit block diagram which shows the data acquisition system with which this invention is applied. It is a block diagram which shows the structure of the data acquisition circuit concerning 1st Embodiment. It is a circuit diagram which shows the specific example of a data acquisition circuit. It is a circuit diagram which shows the specific example of a transition detection part. It is a timing chart which shows operation | movement of the data acquisition circuit concerning 1st Embodiment. It is a block diagram which shows the structure of the data acquisition circuit concerning 2nd Embodiment. It is a block diagram which shows the structure of the data acquisition circuit concerning 3rd Embodiment. It is a circuit diagram of the RL measurement comparison part of 3rd Embodiment. It is a circuit diagram of the RL measurement part applied to the 1st specific example of 3rd Embodiment. It is a circuit diagram of the RL measurement part applied to the 2nd specific example of 3rd Embodiment. It is a circuit diagram which shows the specific example of the detection part 18 shown in FIG. It is a block diagram which shows the structure of the data acquisition circuit concerning 4th Embodiment. It is a block diagram which shows the structure of the data acquisition circuit concerning 5th Embodiment. It is a circuit block diagram which shows the structure of the data acquisition circuit of a prior art.

1, 1A to 1E Data acquisition circuit 10, 15 RL measurement unit 17 Measurement judgment unit 18 Detection unit 20 Delay unit 20A Shift unit 30, 35 RL count comparison unit 40 Transition detection unit 90 CL measurement unit 95 Delay adjustment unit C Controller DL Delay Line R SDRAM
BST BL count start signal CLB CAS latency measurement value CODE1, CODE2 Code signal EDQS Internal data strobe signal DQS Data strobe signal XDQS Inverted data strobe signal RD Read command signal RLB Latency measured value RLE Measurement command signal XMASK Inverted mask signal

Claims (7)

  1. A data capture circuit that masks invalid input of the data strobe signal when capturing the data signal in synchronization with the data strobe signal together with the data strobe signal in response to a read command signal;
    A response time measuring unit for measuring a response time from an input of the read command signal to an effective edge of the data strobe signal;
    In response to a standby start signal based on the read command signal, after waiting for a standby time that is a time based on the response time, a standby unit that commands release of the mask of the data strobe signal;
    With
    The data strobe signal outputs the effective edge that transitions from a high impedance to a first logic level in response to the read command signal,
    The response time measurement unit
    A transition detector for detecting a transition of the data strobe signal from the high impedance to the first logic level;
    A measuring unit that measures the response time from the input of the read command signal until the detection result of the transition detection unit is output;
    With
    The transition detection unit
    Inverting the data strobe signal to the input terminal is input, a first comparator first threshold voltage for detecting the first logic level to the non-inverting input terminal is inputted,
    An inverted data strobe signal that is complementary to the data strobe signal is input to the non-inverting input terminal, and a second threshold voltage that detects a second logic level that is complementary to the first logic level is input to the inverting input terminal. An input second comparator;
    A gate circuit for calculating a logical product of outputs of the first comparator and the second comparator;
    A data acquisition circuit comprising:
  2. A data acquisition circuit according to claim 1,
    The response time measurement unit
    A first counter unit that starts counting clock signals in response to the input of the read command signal;
    A first holding unit that holds an output of the first counter unit in response to the valid edge of the data strobe signal;
    A data acquisition circuit comprising:
  3. A data reading circuit according to claim 2,
    A data acquisition circuit, comprising: a standby adjustment unit that sets the standby time to a relationship delayed by one cycle of the clock signal from a time corresponding to the content held in the first holding unit.
  4. A data acquisition circuit according to claim 1,
    The standby unit includes a delay line to which the standby start signal is input,
    The response time measurement unit
    A data acquisition circuit comprising: a selection unit that selects an output tap of the delay line according to the response time.
  5. A data acquisition circuit according to claim 1,
    The response time measurement unit
    A first measuring unit for measuring a first time of the response time;
    A second measuring unit for measuring a second time obtained by removing the first time from the response time,
    The data acquisition circuit, wherein the standby start signal is output from the first measurement unit, and the standby unit waits for a time based on the second time.
  6. A memory device that outputs a data signal in synchronization with a data strobe signal in response to a read command signal;
    A memory control device that masks invalid input of the data strobe signal when capturing the data signal in synchronization with the data strobe signal;
    The memory control device
    A response time measuring unit for measuring a response time from an input of the read command signal to an effective edge of the data strobe signal;
    In accordance with a standby start signal based on the read command signal, after waiting for a time based on the response time, a standby unit for commanding release of the mask of the data strobe signal;
    With
    The data strobe signal outputs the effective edge that transitions from a high impedance to a first logic level in response to the read command signal,
    The response time measurement unit
    A transition detector for detecting a transition of the data strobe signal from the high impedance to the first logic level;
    A measuring unit that measures the response time from the input of the read command signal until the detection result of the transition detection unit is output;
    With
    The transition detection unit
    Inverting the data strobe signal to the input terminal is input, a first comparator first threshold voltage for detecting the first logic level to the non-inverting input terminal is inputted,
    An inverted data strobe signal that is complementary to the data strobe signal is input to the non-inverting input terminal, and a second threshold voltage that detects a second logic level that is complementary to the first logic level is input to the inverting input terminal. An input second comparator;
    A gate circuit for calculating a logical product of outputs of the first comparator and the second comparator;
    A data acquisition system comprising:
  7. According to a read command signal, when capturing a data signal in synchronization with the data strobe signal together with a data strobe signal, a method for controlling a data capturing circuit that masks invalid input of the data strobe signal,
    Measuring a response time from an input of the read command signal to an effective edge of the data strobe signal;
    In response to the read command signal, after waiting for a standby time that is a time based on the response time, instructing the mask release of the data strobe signal,
    With
    The data strobe signal outputs the effective edge that transitions from a high impedance to a first logic level in response to the read command signal,
    The step of measuring the response time includes:
    Detecting a transition of the data strobe signal from the high impedance to the first logic level;
    Measuring the response time until the detection result in the step of detecting the transition from the input of the read command signal is output;
    With
    The step of detecting the transition includes:
    The method comprising the inverting input of the data strobe signal, a first threshold voltage for detecting the first logic level as a non-inverting input, a first comparison,
    An inverted data strobe signal that is complementary to the data strobe signal is used as a non-inverting input, and a second threshold voltage that detects a second logic level that is complementary to the first logic level is used as an inverting input. Comparing, and
    Calculating a logical product of the comparison result of the first comparison step and the comparison result of the second comparison step;
    A method for controlling a data acquisition circuit, comprising:
JP2007048022A 2006-02-28 2007-02-27 Data acquisition circuit, data acquisition system, and control method of data acquisition circuit Expired - Fee Related JP5157194B2 (en)

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