JP5153724B2 - Processing time estimation device and processing time estimation program - Google Patents

Description

  The present invention relates to a processing time estimation device that estimates a processing time when a program is operated on an execution device, and the program.

  2. Description of the Related Art In recent years, a system that uses a plurality of program execution devices has been constructed in a system that realizes real-time performance by a sequence operation of a fixed cycle represented by a control controller. When evaluating software on such a system, it is necessary to estimate the processing performance using an actual machine or a simulator, which requires man-hours for performance evaluation.

  When estimating the processing performance using a simulator, for example, in the software porting evaluation apparatus of Patent Document 1, in order to evaluate the processing time when the entire program is transferred from the first processing apparatus to the second processing apparatus, a predetermined value is used. The processing performance is calculated based on the processing performance conversion coefficient obtained by weighting the processing performance evaluation coefficient obtained from the processing performance of the first processing apparatus and the second processing apparatus of the program by the ratio of each module type in the program. It was.

  In the program simulation apparatus of Patent Document 2, processing performance is estimated by accurately simulating the operation of a program in units of clocks one instruction at a time. Further, the statistics for the access time to the register, the memory, and the cache are calculated in consideration of the instruction execution count, the cache hit rate, and the memory read / write count.

  In the program development support apparatus of Patent Document 3, when the program is executed, the data loaded in the microcomputer may not be immediately used for calculation, and the microcomputer may stall for a certain cycle, and the stall penalty is taken into consideration. Processing time was calculated.

JP 2007-299212 A Japanese Patent Laid-Open No. 9-6646 JP 2000-242529 A

Since the conventional processing time estimation apparatus is configured as described above, the apparatus of Patent Document 1 can evaluate the processing time when the entire program is ported to another processing apparatus, but only a part of the programs in the processing apparatus. The processing time could not be evaluated when transplanted to another processing equipment. In addition, since the processing performance of the second processing device is estimated using a conversion coefficient that calculates the processing performance when the entire program is transferred from the first processing device to the second processing device, the computation time and various I / O addresses Access time to was not considered.
Further, in the devices of Patent Documents 2 and 3, access contention when a program is executed simultaneously by a plurality of execution devices is not considered, and the program processing time reflecting the access contention rate from the plurality of execution devices is evaluated. I couldn't.

  Also, with the conventional processing time estimation device, when processing performance is estimated in consideration of access competition from multiple execution devices, it is necessary to perform cycle level simulation to estimate with high accuracy. There are also problems such as taking time and calculating unrealistic processing time by estimating all access conflicts in the worst case.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to calculate the processing time of a program that operates on a plurality of program execution devices at high speed without using a simulator.

  The processing time estimating apparatus according to the present invention extracts, for each of a plurality of partial programs constituting a program, an input address and an output address for accessing each device, an input count and an output count, and an issued instruction count From the analysis unit, the number of issued instructions extracted by the program analysis unit, information on the access time from each program execution device that executes each partial program to each device, and information on the contention rate when accessing each device A processing time calculation unit that calculates an execution time of each partial program, a program operation parameter that indicates an association and execution order between each partial program and a program execution device that executes each partial program, and a processing time calculation unit The program operation that calculates the execution time of each partial program from the execution time of each partial program calculated by From the timing creation unit, the execution time of each partial program for each program execution device calculated by the program operation timing creation unit, and the information of access to each device of each partial program extracted by the program analysis unit, for each time Calculates the processing time by calculating the contention rate of each device from the access contention number of each device calculated by the access destination information creation unit that calculates the number of access contention of each device and the access destination information creation unit And an access contention rate calculation unit for outputting to the unit.

  The processing time estimation program according to the present invention provides a computer with an input address and an output address for accessing each device, an input count and an output count, and an issued instruction count for each of a plurality of partial programs constituting the program. The program analysis means to be extracted, the number of issued instructions extracted by the program analysis means, the information on the access time to each device from each program execution device that executes each partial program, and the previous contention rate at the time of accessing each device A processing time calculation means for calculating the execution time of each partial program from the information, a program operation parameter indicating an association and execution order of each partial program and a program execution device for executing each partial program, Each partial program is calculated from the execution time of each partial program calculated by the processing time calculation means. Program operation timing creation means for calculating the execution time of the program, the execution time of each partial program for each program execution device calculated by the program operation timing creation means, and each partial program extracted by the program analysis means to each device From the access information, the access destination information creation means for calculating the number of access conflicts for each device for each time, and the current time of each device from the number of access conflicts for each device for each time calculated by the access destination information creation means The contention rate is calculated and the current contention rate is output to the processing time calculation means as the previous contention rate, the previous contention rate used by the processing time calculation device to calculate the execution time, and the previous contention rate Compared to the current competition rate calculated using, if this does not match, use the current competition rate as the previous competition rate. Shelf This contention is calculated, in which if the match was to function as a processing time repeating calculation means for outputting the execution time calculated in the course of this competition factor calculated as the processing time of the program.

  According to the present invention, since the execution time of each partial program is calculated using the access contention rate based on information obtained by analyzing the access specifications from the program to each device, it operates on a plurality of program execution devices. The processing time of each partial program can be calculated at high speed without using a simulator.

It is a block diagram which shows the structure of the processing time estimation apparatus which concerns on Embodiment 1 of this invention. It is a flowchart which shows operation | movement of the program analysis part shown in FIG. It is explanatory drawing which shows the structure of process performance DB for every program shown in FIG. It is explanatory drawing which shows the structure of the address range information shown in FIG. It is explanatory drawing which shows the structure of the instruction cycle table shown in FIG. It is a flowchart which shows operation | movement of the program operation timing preparation part shown in FIG. It is explanatory drawing which shows the structure of the program execution apparatus time information shown in FIG. It is explanatory drawing which shows the structure of the program operation parameter shown in FIG. It is a flowchart which shows operation | movement of the information preparation part for every access destination shown in FIG. It is explanatory drawing which shows the structure of every access destination information shown in FIG. It is a flowchart which shows operation | movement of the access competition rate calculation part shown in FIG. It is explanatory drawing which shows the structure of the access conflict information shown in FIG. It is a flowchart which shows operation | movement of the processing time calculation part shown in FIG. It is explanatory drawing which shows the structure of the hardware specification parameter shown in FIG. It is a flowchart which shows operation | movement of the repetition program execution time derivation | leading-out part shown in FIG. It is a flowchart which shows operation | movement of the processing time estimation apparatus which concerns on Embodiment 2 of this invention. It is a flowchart which shows operation | movement of the operation period calculation part of the processing time estimation apparatus which concerns on Embodiment 3 of this invention.

Embodiment 1 FIG.
FIG. 1 is a block diagram showing a configuration of a processing time estimation apparatus according to Embodiment 1 of the present invention. This processing time estimation device uses a simulator for processing performance when a part of a program is operated on another program execution device in a control system having a plurality of program execution devices (hereinafter also simply referred to as execution devices). Without using the program analysis information, it can be estimated at high speed.

  This processing time estimation apparatus analyzes a plurality of programs 101, extracts an address range (that is, a device) for load (LD) / store (ST) access, the number of accesses and the number of issued instructions, and obtains a per-program processing performance database (hereinafter referred to as a program performance database). DB) 105, and a program execution time deriving unit 104 that derives the execution time of each program in the execution unit of the program 101 using these pieces of information.

  The repetitive program execution time deriving unit 104 uses the access contention information 114 and the hardware specification parameters 113 that have been parameterized in advance, the processing time calculation unit 106 that calculates the execution time of each program 101, and the program operation parameters that have been parameterized in advance. 115, a program operation timing creation unit 107 that creates time information 108 for each program execution device using 115, an information creation unit 109 for each access destination that creates information 110 for each access destination indicating an execution device that may have access conflict, and an access destination An access contention rate calculation unit 111 that calculates an access contention rate from each information 110, and a processing time repetition calculation unit 112 that repeatedly executes a series of program execution time derivation processes by each unit until the access contention rate converges. Be equipped That.

  First, details of the program analysis unit 103 will be described. FIG. 2 is a flowchart showing the operation of the program analysis unit 103. The program analysis unit 103 repeats a series of loop processes including steps STP1 to STP9 for the total number (N times) of the processing time estimation target programs 101, and analyzes each corresponding program (partial program). First, in the program reading process of step STP2, the program analysis unit 103 acquires a program file from the program 101. The program analysis unit 103 sets the program IDs in the order of the program files read in step STP2 and registers them in the per-program processing performance DB 105.

  FIG. 3 is an explanatory diagram showing the configuration of the per-program processing performance DB 105 shown in FIG. In the per-program processing performance DB 105, N programs are stored with the program ID 105a set in order from “1” to “N”. For each program ID 105a, information on the LD number 105c and ST number 105d of each address range 105b, the number of instructions 105e as the number of program sequences, and the execution time 105f are stored. In FIG. 3, since it is assumed that one instruction is one cycle, the number of instructions 105e and the execution time 105f are the same value of “1270”. In FIG. 3, since there are four types of devices to be accessed, the types of address IDs are four types of 1, 2, 3, and 4, that is, the number of address ranges is 4 (A, B, C, D). doing.

  In step STP3, the total execution time for each program is initialized. In the loop processing for the number of program columns in steps STP4 to STP10, the corresponding program read in step STP2 is analyzed line by line up to the Mth line which is the last line of the file. One row here is treated as an execution instruction of one column. First, in the LD / ST check process in step STP5, if the program analysis target column is an LD / ST instruction, the program analysis unit 103 proceeds to access address acquisition in the subsequent step STP6. If the instruction is not an LD / ST instruction, the process returns to step STP4 via steps STP9 and STP10 to analyze the next line.

  In the address acquisition process at step STP5, the program analysis unit 103 acquires the access address of the LD / ST instruction. In the subsequent address range comparison process in step STP6, first, using the access address acquired in step STP5 as a key, the address range included in the address range information 102 described later is collated to obtain the address ID of the matching address range. To do.

  FIG. 4 is an explanatory diagram showing the configuration of the address range information 102 shown in FIG. The address range information 102 stores an address range 102a composed of the start address and end address of the device whose processing time is to be estimated, and an address ID 102b for linking the address range 102a to the address range 105b of the per-program processing performance DB 105. It is a table. Note that the address range 105b in FIG. 3 corresponds to the address ID 102b in FIG. 4, and the address range 102a can be acquired from the address range 105b.

  In step STP7, the program analysis unit 103 compares the address range 102a with the access address of the LD / ST instruction, and if the access address is within the address range 102a (step STP7 “present”), the number of accesses in the subsequent step STP8 Proceed to increment processing. If it is outside the address range 102a (step STP7 “No”), the process returns to step STP4 via steps STP9 and STP10, and analysis of the next line is started. In the access count increment process in step STP8, the program analysis unit 103 accesses the per-program processing performance DB 105 to increment the LD count 105c or the ST count 105d in the address range 105b corresponding to the address ID 102b in the corresponding program ID 105a. To do.

  In step STP9, the number of execution cycles of the instruction is acquired from the instruction cycle table 116 using the instruction in the analysis target column of the program as a key. The program analysis unit 103 stores the acquired sum of the number of execution cycles and the execution time in the execution time. FIG. 5 shows an example of the instruction cycle table 116. The program analysis unit 103 calculates an accurate execution time by using the instruction cycle table 116 including the instruction 116a and the number of cycles 116b necessary for executing the instruction. In step STP9, the number of cycles 116b acquired using the type of the instruction 116a as a key is added to the execution time.

  Next, details of the program operation timing creation unit 107 of the repetitive program execution time deriving unit 104 will be described. FIG. 6 is a flowchart showing the operation of the program operation timing creation unit 107 shown in FIG. 1, and shows the operation of creating program operation time information for each execution device from the execution time and execution order of the program. First, in the current time array clear process in step STP11, the program start time for each execution device included in the time information 108 for each program execution device is cleared. FIG. 7 is an explanatory diagram showing a configuration of the program execution device time information 108 shown in FIG. The program execution device time information 108 is a table that stores the execution device ID 108a indicating the ID of the execution device, the program ID executed by each execution device, and the execution time 108b of the program in the order of execution of the program. Each time the program and the execution time of the program are managed.

  Subsequently, the program operation timing creation unit 107 performs a series of loop processes including steps STP12 to STP16 N times. First, in the program execution device ID acquisition process in step STP13, the program operation timing creation unit 107 acquires the ID of the execution device corresponding to the program ID from the program operation parameter 115 using the program ID described above as a key. FIG. 8 is an explanatory diagram showing the configuration of the program operation parameter 115 shown in FIG. The program operation parameter 115 illustrated in FIG. 8 is a table that stores an execution device ID 115a that executes a program and a program ID 115b that indicates a program executed by each execution device. The program ID 115b corresponds to the above-described program ID 105a, and the order of the program ID 115b represents the order of program execution in the execution device.

In the program execution time acquisition process of step STP14, the program operation timing creation unit 107 refers to the per-program processing performance DB 105 and acquires the execution time 105f of the program ID 105a corresponding to the program ID 115b. For example, the program ID 105a “1” in FIG. 3 corresponds to the program ID 115b “1” in FIG.
In the process of storing the program ID and the program execution time in step STP15, the program operation timing creation unit 107 stores the program ID 105a and the execution time 105f in the program execution device time information. In step STP15, the program ID and the execution time of the program are stored in a record in which the index value of each execution device ID 108a is the smallest and is empty.

  Next, details of the access destination information creation unit 109 of the repetitive program execution time deriving unit 104 will be described. FIG. 9 is a flowchart showing the operation of the access destination information creation unit 109 shown in FIG. 1, and calculates the number of accesses (that is, the number of competitions) in each address range for each time based on the time information 108 for each program execution device. The operation for storing in the access destination information 110 is shown. FIG. 10 is an explanatory diagram showing a configuration of the access destination information 110 shown in FIG. The per-access-destination information 110 is a table that stores the number of accesses 110c that may be accessed to the address ID 110b at each time 110a and the last access time 110d to each address ID 110b. For example, the access count 110c “4” stored in the address ID 110b “1” at the time 110a “1” indicates that there is a possibility of access from four execution devices. The address ID 110b corresponds to the address ID 102b shown in FIG.

The access destination information creation unit 109 performs a loop corresponding to the number of address IDs of steps STP22 to STP33 (L times) at every time 110a in a series of times (K times) consisting of steps STP21 to STP34 shown in FIG. The number of accesses 110c to be stored for each address ID 110b is created by processing.
First, in the access count counter clear process in step STP23, the access destination information creation unit 109 clears the access count 110c of the access destination information 110.

  In the loop processing for the number of program execution devices in steps STP24 to STP29 (I times), the access destination information creation unit 109 acquires the presence / absence of access from each program execution device. First, in the program ID acquisition process at step STP25, the access destination information creation unit 109 executes the program from the program execution device time information 108 at that time using the time number loop counter value and the program execution device loop counter value as keys. The program ID 108b of the execution device ID 108a being acquired is acquired.

  In the LD / ST number acquisition process in step STP26, the access destination information creation unit 109 uses the program ID 108b and the address range number loop counter value acquired in step STP25 as keys, and the address of the corresponding program ID 105a from the program performance DB 105. The LD number 105c and the ST number 105d in the range 105b are acquired.

  In the LD + ST number comparison process in step STP27, the access destination information creation unit 109 determines whether the total number of the LD number 105c and the ST number 105d acquired in step STP26 is 1 or more. If the number is 1 or more, there is a possibility of access by the execution device (step STP27 “! = 0”). Therefore, the access destination information creation unit 109 increments the number of accesses in the access number counter increment processing in step STP28. If the total number is 0, there is no possibility of access (step STP27 “== 0”), and the access destination information creation unit 109 ends the loop processing for the number of program execution devices (I times).

  In the access count acquisition process at step STP30, the access destination information creation unit 109 accesses the address ID corresponding to the number of times corresponding to the access destination information 110 using the time count loop counter value and the address range loop counter value as keys. 110c is stored.

  In the access count comparison process at step STP31, the access destination information creation unit 109 determines whether the access count 110c of the address ID 110b during loop processing is “0” or “0 or more (non-zero)”. ", It is determined that there is an access, and the time loop counter value is set to the last access time 110d of the address ID 110b (step STP32). If the access count 110c is “0”, the loop processing is ended as many as the number of address IDs (L times), and a series of processing ends.

  Next, details of the access contention rate calculation unit 111 of the repetitive program execution time deriving unit 104 will be described. FIG. 11 is a flowchart showing the operation of the access contention rate calculation unit 111 shown in FIG. 1, and calculates the program contention rate for each address range based on the program execution time and the number of accesses assigned to each program execution device. The operation to do is shown. FIG. 12 is an explanatory diagram showing the configuration of the access contention information 114 shown in FIG. The access conflict information 114 is a table that stores an address ID 114a and a conflict rate 114b.

  First, in the internal use array clear process in step STP41, the access contention rate calculation unit 111 clears the contention rate 114b of the access contention information 114.

  In a series of address ID number (L times) loop processing including steps STP42 to STP49, the access contention rate calculation unit 111 performs loop processing for the number of address IDs in order to calculate the contention rate 114b for each address ID. First, in the access contention number clear process in step STP43, a variable for setting the access contention number for each address ID included in the access contention rate calculation unit 111 is cleared.

  In the loop processing for the number of times (K times) consisting of steps STP44 to STP47, the access contention rate calculation unit 111 performs loop processing for acquiring the access contention number for each time. First, in the access count acquisition process of step STP45, the access contention rate calculation unit 111 uses the address range loop counter value and the time loop counter value as keys, and accesses the address ID 110b and the access count 110c of the time 110a from the access destination information 110. To get. In the access contention count counting process in step STP46, the access contention rate calculation unit 111 adds the access count 110c acquired in step STP45 to the variable of access contention.

  After the completion of the loop processing for several times (K times), in the access contention rate calculation process in step STP48, the access contention rate calculation unit 111 calculates the contention rate of the address range during the loop processing, and the contention rate of the access contention information 114 114b. The contention rate is (access contention number-1) / (last access time 110d) counted as a variable. (Number of access conflicts−1) is the number of access contention waiting times at all times in the address range, and (last access time 110d) is the time when the address range was last accessed.

  Next, details of the processing time calculation unit 106 of the repetitive program execution time deriving unit 104 will be described. FIG. 13 is a flowchart showing the operation of the processing time calculation unit 106 shown in FIG. FIG. 14 is an explanatory diagram showing the configuration of the hardware specification parameters 113 shown in FIG. The hardware specification parameter 113 is a table that stores, for each program execution device, the LD time 113b and ST time 113c of each address ID 113a from the execution device, and the contention waiting time 113d that occurs when accessing the address ID. . In this table, a specified value acquired from the hardware specification information is set as the LD time 113b and the ST time 113c, and a specified time in which two accesses occur simultaneously and waiting for access is set as the contention waiting time 113d. Keep it.

  The operation of the processing time calculation unit 106 will be described using the per-program processing performance DB 105 in FIG. 3, the access contention information 114 in FIG. 12, and the hardware specification parameters 113 in FIG. The processing time calculation unit 106 repeats the loop processing for the number of programs (N times) consisting of steps STP51 to STP57 (N times) for all the programs 101 for processing time estimation, and sets the processing time for each program. calculate. First, in the access time clear process in step STP52, the device access time of the program being looped is cleared.

  Subsequently, the processing time calculation unit 106 repeats the loop processing for the number of address IDs (L times) consisting of steps STP53 to STP55 (L times) for the total number (L) of the address range 105b to calculate the access time for each address range 105b. To do. In the access time calculation process of step STP54, the processing time calculation unit 106 acquires the LD time 113b, the ST time 113c, and the contention waiting time 113d from the hardware specification parameter 113 using the address ID as a key, and from the access contention information 114. The contention rate 114b is acquired, the LD number 105c and the ST number 105d are acquired from the per-program processing performance DB 105, and the access time of the address range during loop processing is calculated. This access time is {(LD number 105c × LD time 113b) + (ST number 105d × ST time 113c) + contention waiting time 113d} × contention rate 114b.

  After the loop processing for the number of address IDs (L times), in the access time calculation processing in step STP56, the processing time calculation unit 106 calculates the sum of the access time and the number of instructions as the execution time of the program and derives the repeated program execution time. Stored in the unit 104.

Next, the overall operation for the processing time estimation device to calculate the program processing time will be described with reference to FIGS. First, the program analysis unit 103 analyzes the program 101 offline, extracts the LD / ST count and LD / ST address range for each program, and stores them in the per-program processing performance DB 105.
The processing time repetition calculation unit 112 compares the previous competition rate and the current competition rate for each address range as shown in FIG. 12, and determines whether or not to repeat the loop process composed of steps STP61 to STP66. If there is a difference between the previous competition rate and the current competition rate, the processing time repetition calculation unit 112 determines this difference as an error, recalculates the program execution time, and if the previous competition rate and the current competition rate match. It is determined that there is no error, the execution time at that time is determined as the program processing time, and the process is terminated. In this process, since there is no previous competition rate at the start of execution, the in-loop process is executed at least twice.

When performing the loop processing, in step STP62, the processing time calculation unit 106 performs the processing time calculation processing shown in FIG. Specifically, the processing time calculation unit 106 calculates the execution time of each program using the access time calculated for each address ID as described above, and stores it in the processing performance DB 105 for each program.
Subsequently, in step STP63, the program operation timing creation unit 107 performs a program operation timing creation process shown in FIG. Specifically, as described above, the program operation timing creation unit 107 determines each execution device from the execution time of each program calculated by the processing time calculation unit 106 and the execution order of each program acquired from the program operation parameter 115. The time at which each program is executed is calculated and stored in the time information 108 for each program execution device.
Subsequently, in step STP64, the access destination information creation unit 109 performs the access destination information creation process shown in FIG. Specifically, as described above, the access destination information creation unit 109 acquires information on a program group executed by each execution device at each time from the program execution device time information 108, and sets the time ID and device ID (device ID). ) The number of accesses from the program group is calculated every time, and this number of times is set as the number of access conflicts to each device at each time.
Subsequently, in step STP65, the access contention rate calculation unit 111 performs an access contention rate calculation process shown in FIG. Specifically, as described above, the access contention rate calculation unit 111 uses the access count 110c and the last access time 110d for each device from the access destination information 110, and the average access contention count for each device and each execution device. The contention rate is calculated from the quotient of the program execution time and stored in the access contention information 114.
Subsequently, in step STP66, the processing time repetition calculation unit 112 compares the current competition rate calculated in the current loop process with the previous competition rate calculated in the previous loop process. As a result, if the current and previous competition rates are the same for all address IDs, the processing time repetition calculation unit 112 ends the loop processing and executes the per-program processing performance DB 105 calculated and stored in the current loop processing. The time 105f is set as the processing time of each program.
On the other hand, in step STP66, if the current and previous competition rates are not the same for all address IDs, the processing time repetition calculation unit 112 uses the competition rate calculated in the current loop processing in step STP62, and uses the contention rate of each program. A process for calculating the execution time is started and a series of loop processes are executed. This loop processing is repeated until the competition rate calculated in the previous and current loop processing is the same.

  For example, since there is no previous competition rate when the loop processing is executed for the first time, each unit of the repetitive program execution time deriving unit 104 performs the first steps STP61 to STP66 using “0” as the previous competition rate, and the competition rate “A Is calculated. At the time of executing the second loop processing, the contention rate “A” calculated for the first time × access time is added to the program execution time, so a new contention point occurs and the current contention rate becomes “B”. When executing the second loop process, the first competition rate “A” and the second competition rate “B” are compared. If they are the same, it is determined that they have converged, and the process ends. The contention rate “C” is calculated by using the contention rate “B” as the contention rate “B” × access time as the program execution time.

  As described above, according to the first embodiment, the processing time estimation apparatus performs the LD count 105c for each address range 105b for access to each device for each of N partial programs constituting the program 101, ST The program analysis unit 103 that extracts the number of times 105d and the number of instructions 105e to obtain the per-program processing performance DB 105, the number of instructions 105e extracted by the program analysis unit 103, and each device from each program execution device that executes each partial program Processing time for calculating the execution time 105f of each partial program from the hardware specification parameter 113 that is information on the LD / ST time to the device and the access contention information 114 that is information on the contention rate when accessing each device Calculation unit 106, each partial program, and program for executing each partial program The program execution device calculates the execution time of each partial program from the program operation parameter 115 indicating the association with the row device and the execution order and the execution time 105f of each partial program calculated by the processing time calculation unit 106 A program operation timing creation unit 107 that creates hourly information 108, an execution time of each partial program for each program execution device calculated by the program operation timing creation unit 107, and a per-program processing performance DB 105 extracted by the program analysis unit 103 Information for each access destination is generated by calculating the number of access conflicts of each device for each time and the information for each access destination 110 calculated by the information generation unit for each access destination 109. From the contention rate of each device, the access contention information 114 and Was configured with an access contention rate calculation unit 111 outputs to the processing time calculation unit 106 Te. For this reason, it is possible to estimate access conflict without executing or simulating the program from the program-specific information analyzed offline and the hardware parameters, and to calculate the program processing time (execution time 105f) at high speed. .

  Further, according to the first embodiment, the processing time calculation unit 106 compares the previous competition rate used for the calculation of the execution time 105f with the current competition rate calculated using the previous competition rate. If not, the processing time calculation unit 106, the program operation timing generation unit 107, the access destination information generation unit 109, and the access contention rate calculation unit 111 are repeatedly performed using the current competition rate as the previous competition rate. It is configured to include a processing time repetition calculation unit 112 that calculates a new current competition rate and outputs the execution time 105f calculated in the process of calculating the current competition rate as the processing time of the program 101 if they match. For this reason, the execution time 105f when the previous competition rate matches the current competition rate is set as the processing time of the program 101, so that the processing time can be estimated with high accuracy.

Embodiment 2. FIG.
In the first embodiment, when the previous competition rate calculated by the processing time repetition calculation unit 112 matches the current competition rate, the series of processes of the repeated program execution time deriving unit 104 is ended. In the present embodiment, when the difference between the previous competition rate and the current competition rate is smaller than the competition rate calculation end parameter, it is determined that the error is within the allowable range, and the series of processes is ended. The processing time estimation device of the present embodiment has the same configuration on the drawing as the processing time estimation device of the first embodiment shown in FIG. 1 and will be described below with reference to FIG. The description of the same part is omitted.

FIG. 16 is a flowchart showing the operation of the repetitive program execution time deriving unit 104 of the processing time estimation apparatus according to Embodiment 2 of the present invention.
The processing time repetition calculation unit 112 compares the difference between the previous competition rate and the current competition rate with the competition rate calculation end parameter, and determines whether or not to repeat the loop process including steps STP61a to STP66a. In this process, as in the first embodiment, since there is no previous competition rate at the start of execution, the in-loop process is executed at least twice.
The processing time repetition calculation unit 112 performs steps STP62 to STP62 when the error between the contention rate for each address ID calculated by the access contention rate calculation unit 111 and the contention rate calculated in the previous loop processing is equal to or greater than the contention rate calculation end parameter. The processing of STP 65 is performed, and the processing is ended when the error is smaller than the competition rate calculation end parameter. Steps STP62 to STP65 are the same as in FIG.

  As described above, according to the second embodiment, the processing time repetition calculation unit 112 is calculated using the previous competition rate used by the processing time calculation unit 106 to calculate the execution time 105f and the current competition rate calculated using the previous competition rate. Comparing with the competition rate, if the difference is larger than the competition rate calculation end parameter, the current competition rate is used as the previous competition rate, the processing time calculation unit 106, the program operation timing creation unit 107, and the creation of each access destination information The unit 109 and the access contention rate calculation unit 111 are repeatedly processed to calculate a new current contention rate, and if it is equal to or less than the contention rate calculation end parameter, the execution time 105f calculated in the current contention rate calculation process is programmed. A processing time of 101 is output. For this reason, the execution time 105f when the difference between the previous competition rate and the current competition rate is equal to or less than the competition rate calculation end parameter is set as the processing time of the program 101, so that the processing time can be estimated faster than in the first embodiment. It can be performed.

Embodiment 3 FIG.
In the third embodiment, the program execution end time for each execution device is calculated using the per-program processing performance DB 105 and the program operation parameter 115 created in the first and second embodiments, and the execution device with the latest end time is calculated. The operation period calculation unit for deriving the program execution time, that is, the worst execution time is provided. The processing time estimation apparatus according to the present embodiment has the same configuration as the processing time estimation apparatus according to the first embodiment shown in FIG. 1 except that an operation cycle calculation unit is added. 1 is used for explanation, and the explanation for the same part is omitted.

  FIG. 17 is a flowchart showing the operation of the operation cycle calculation unit of the processing time estimation apparatus according to Embodiment 3 of the present invention. Before the operation cycle calculation unit starts the processing shown in FIG. 17, a series of processing by each unit of the repetitive program execution time deriving unit 104 is finished, and the final processing time calculation unit 106 calculates in the per-program processing performance DB 105. It is assumed that a typical processing time is stored in the execution time 105f.

In the loop processing for the number of program execution devices in steps STP71 to STP80 (I times), the operation cycle calculation unit calculates the total program execution time for each program execution device. First, in the variable clear process of step STP72, the operation cycle calculation unit is an operation that is a variable that stores a response time that is a variable that stores an integrated value of the processing time for each program execution device and a response time that has the largest integrated value Clear the cycle.
In the program ID acquisition process in the subsequent step STP73, the operation cycle calculation unit acquires all program IDs 115b operating with the execution device ID 115a from the program operation parameter 115 using the program execution device loop counter value as a key.

  In the loop processing for the number of acquired program IDs in steps STP74 to STP77, the loop processing is performed for the number of program IDs 115b acquired in step STP73, and the response time of each program ID is calculated. First, in the execution time acquisition process of step STP75, the operation cycle calculation unit acquires the execution time 105f from the per-program processing performance DB 105 using the program ID as a key. In the subsequent response time integration process in step STP76, the operation cycle calculation unit adds the execution time 105f acquired in step STP75 to the response time variable to update the response time.

  In the operation cycle / response time comparison process in step STP78, the operation cycle calculation unit compares the operation cycle with the response time obtained by integrating the execution time 105f in steps STP74 to STP77. If the response time is longer than the operation cycle (step STP78 “<”), the operation cycle calculation unit replaces the variable of the operation cycle with the response time (step STP79), and if the response time is less than or equal to the operation cycle (step STP79). In step STP78 “> =”), the loop processing is ended as many times as the number of program execution devices (I times), and a series of operation cycle calculation processing ends.

  As described above, according to the third embodiment, from the execution time 105f of each partial program calculated by the processing time calculation unit 106 and the program operation parameter 115 indicating the execution order of the program execution device that executes each partial program. In addition, an operation period calculation unit is provided that calculates a response time for each program execution device and calculates an operable period of the control system from the response time. Therefore, the operation period of the execution device can be automatically calculated from the processing time for each program calculated by the processing time calculation unit 106 in the first and second embodiments.

  Further, according to the first to third embodiments, the per-program processing performance DB 105, the hardware specification parameter 113, and the program operation parameter 115 do not need to be repeatedly calculated. It can be used during processing, and the amount of calculation can be reduced.

  When the processing time estimation devices of the first to third embodiments are configured by a computer, the processing time estimation program describing the processing contents of the program analysis unit 103 and the repeated program execution time deriving unit 104 is stored in the computer memory. The computer CPU may execute the program stored in the memory.

  101 program, 102 address range information, 102a address range, 102b address ID, 103 program analysis unit, 104 repetitive program execution time deriving unit, 105 program performance DB, 105a program ID, 105b address range, 105c LD count, 105d ST Number of times, 105e Number of instructions, 105d Execution time, 106 Processing time calculation unit, 107 Program operation timing creation unit, 108 Program execution device time information, 108a Execution device ID, 108b Program ID and its execution time, 109 Access destination information creation 110, access destination information, 110a time, 110b address ID, 110c access count, 110d last access time, 111 access contention rate calculation unit, 112 processing time Iterative calculation unit, 113 hardware specification parameter, 113a address ID, 113b LD time, 113c ST time, 113d contention waiting time, 114 access contention information, 114a address ID, 114b contention rate, 115 program operation parameter, 115a execution device ID, 115b Program ID, 116 instruction cycle table, 116a instruction, 116b number of cycles.

Claims (5)

A processing time estimation device for estimating the processing time of a program operating on a control system having a plurality of program execution devices,
For each of a plurality of partial programs constituting the program, a program analysis unit that extracts an input address and an output address for accessing each device, an input count and an output count, and an issued instruction count;
The number of issued instructions extracted by the program analysis unit, information on the access time to each device from each program execution device that executes each partial program, and information on the previous contention rate when accessing each device, From the processing time calculation unit for calculating the execution time of each partial program,
Correspondence between each partial program and a program execution device that executes each partial program and a program operation parameter indicating an execution order, and an execution time of each partial program calculated by the processing time calculation unit, A program operation timing creation unit for calculating the execution time of each partial program;
From the execution time of each partial program for each program execution device calculated by the program operation timing creation unit and the access information to each device of each partial program extracted by the program analysis unit, for each time An access destination information creation unit that calculates the number of access conflicts of each of the devices,
The current competition rate of each device is calculated from the number of access competitions of each device for each time calculated by the access destination information creation unit, and the current competition rate is output to the processing time calculation unit as the previous competition rate. A processing time estimation device comprising: an access contention rate calculation unit.   The previous competition rate used by the processing time calculator to calculate the execution time is compared with the current competition rate calculated using this previous competition rate. It is characterized by comprising a processing time repetition calculation unit that calculates a new current competition rate and outputs the execution time calculated in the process of calculating the current competition rate as the processing time of the program if they match. The processing time estimation device according to claim 1.   The previous competition rate used by the processing time calculation unit to calculate the execution time is compared with the current competition rate calculated using the previous competition rate, and if the difference is greater than a predetermined value, the current competition rate Is used as a previous competition rate to calculate a new current competition rate, and if it is less than a predetermined value, a processing time repetition calculation unit that outputs the execution time calculated in the current competition rate calculation process as the processing time of the program The processing time estimation apparatus according to claim 1, further comprising:   The response time for each program execution device is calculated from the execution time of each partial program calculated by the processing time calculation unit and the program operation parameter indicating the execution order of the program execution device that executes each partial program, The processing time estimation device according to any one of claims 1 to 3, further comprising an operation cycle calculation unit that calculates an operable cycle of the control system from the response time. A processing time estimation program for estimating the processing time of a program operating on a control system having a plurality of program execution devices,
A program analyzing means for extracting, for each of a plurality of partial programs constituting the program, an input address and an output address for accessing each device, an input count and an output count, and an issued instruction count;
The number of issued instructions extracted by the program analysis means, information on the access time to each device from each program execution device that executes each partial program, and information on the previous contention rate when accessing each device, From the processing time calculation means for calculating the execution time of each partial program,
Correspondence between each partial program and a program execution device that executes each partial program and a program operation parameter indicating an execution order, and an execution time of each partial program calculated by the processing time calculation unit, Program operation timing creation means for calculating the execution time of each partial program;
From the execution time of each partial program for each program execution device calculated by the program operation timing creation means and the access information to each device of each partial program extracted by the program analysis means, for each time Access destination information creation means for calculating the number of access conflicts of each of the devices,
The current competition rate of each device is calculated from the number of access competitions of each device for each time calculated by the access destination information creation unit, and the current competition rate is output to the processing time calculation unit as the previous competition rate. Access competition rate calculation means,
The previous competition rate used for calculating the execution time by the processing time calculation means is compared with the current competition rate calculated by using the previous competition rate. In order to function as a processing time iterative calculation means for outputting the execution time calculated in the process of calculating the current competition rate as the processing time of the program if a new current competition rate is calculated using the rate Processing time estimation program.

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