JP5145277B2 - Image processing device - Google Patents

Description

  The present invention relates to an image processing apparatus.

  In an image processing apparatus such as a printer, various types of image processing are performed on image data to be printed, and data compression and data expansion are performed as necessary. At that time, a mode for storing image data in units of pages (hereinafter referred to as “page mode”) and a page of image data are divided into multiple bands of image data (hereinafter referred to as “band data”). One of the modes for storing and processing data (hereinafter referred to as band mode) is used.

  In an image processing apparatus, one of a page mode and a band mode is selected based on the size of a page memory and the size of bitmap data obtained from image data (for example, Patent Document 1).

Japanese Patent Laid-Open No. 10-260804

  However, in the image processing apparatus, when selecting one of the page mode and the band mode, it is necessary to calculate the size of the bitmap data from the image data, and when the image data is supplied to the image processing apparatus. It is difficult to immediately start image processing for the image data.

  The present invention has been made in view of the above-described problems, and it is an object of the present invention to obtain an image processing apparatus capable of immediately starting data processing on image data in page mode or band mode when the image data is supplied. Objective.

  In order to solve the above problems, the present invention is configured as follows.

  The image processing apparatus according to the present invention includes a work type designated by a user and a mode type indicating whether to use a page mode or a band mode when performing a series of image processing corresponding to the work type. A storage device that stores mode designation information to be associated, a data acquisition circuit that acquires image data, a processing circuit that performs data processing on the image data, a first user operation for inputting a work type, and a work start When the second user operation is detected by specifying the mode type corresponding to the work type specified by the first user operation with reference to the input device for detecting the second user operation and the mode specifying information And a control circuit that causes the data acquisition circuit to acquire image data and causes the processing circuit to perform data processing in the specified mode type.

  Thereby, after image data is acquired in the image processing apparatus by the data acquisition circuit, image processing on the image data can be started immediately in the page mode or the band mode. That is, in the band mode, it is possible to start image processing immediately after image data for one band is acquired. In the page mode, image processing is started immediately after image data for one page is acquired. It becomes possible.

  In addition to the image processing apparatus described above, the image processing apparatus according to the present invention may be configured as follows. In this case, the image processing apparatus includes a data storage device capable of storing image data for one page and a memory capable of storing band data obtained by dividing one page of image data. The image data is stored in the memory as band data when the specified mode type is the band mode, and is stored in the data storage device when the specified mode type is the page mode. The processing circuit performs data processing on the band data read from the memory when the specified mode type is the band mode, and when the specified mode type is the page mode, Data processing is performed on the image data read from the data storage device.

  The image processing apparatus according to the present invention may be as follows in addition to any of the image processing apparatuses described above. In this case, the image processing apparatus includes a data compression circuit and a data expansion circuit. When the specified mode type is the page mode, the data compression circuit reads the band data from the memory, compresses the band data, and stores the compressed band data in the data storage device. When the specified mode type is the page mode, the data decompression circuit reads the compressed band data from the data storage device after the band data for one page is stored in the data storage device, and the compressed data is compressed. The band data is decompressed and the band data is stored in the memory.

  Thereby, since the data size is reduced, the capacity of the data storage device can be reduced. In addition, the data compression circuit and the data decompression circuit which are provided and operate independently of the processing circuit and the data acquisition circuit perform data compression and decompression, so that the processing circuit and the data acquisition circuit can be stored without causing a delay. The size of data stored in the apparatus can be reduced.

  The image processing apparatus according to the present invention may be as follows in addition to any of the image processing apparatuses described above. In this case, when the specified mode type is the page mode, the data decompression circuit stores the compressed band required for the data processing of the processing circuit after the band data for one page is stored in the data storage device. Data is read from the data storage device, the compressed band data is decompressed, and the band data is stored in the memory. The processing circuit performs data processing using the band data obtained by the data decompression circuit.

  The image processing apparatus according to the present invention may be as follows in addition to any of the image processing apparatuses described above. In this case, the image processing apparatus includes a data acquisition controller and a data flow controller that controls data input / output of the processing circuit. The memory includes a first band memory and a second band memory. The data acquisition circuit has an output DMA (Direct Memory Access) controller that performs direct memory access for writing data to the first band memory and the second band memory. The processing circuit has an input DMA controller that performs direct memory access for reading data from the first band memory and the second band memory. The data flow controller causes the output DMA controller of the data acquisition circuit to alternately write band data to one of the first band memory and the second band memory, and if the specified mode type is the band mode, In parallel, the previous band data of the band data is read from the other of the first band memory and the second band memory by the input DMA controller of the processing circuit.

  As a result, in the band mode, the processing circuit can start processing the band data immediately after the data acquisition circuit has written the band data to the memory.

  The image processing apparatus according to the present invention may be as follows in addition to any of the image processing apparatuses described above. In this case, when the specified mode type is the band mode, the data flow controller, when the writing of the band data to the first band memory by the data acquisition circuit is completed, the band from the first band memory by the processing circuit. When reading of data is started, writing of the next band data to the second band memory by the data acquisition circuit is started, and when writing of the band data to the second band memory by the data acquisition circuit is completed, the processing circuit Starts reading the band data from the second band memory, and starts writing the next band data to the first band memory by the data acquisition circuit.

  Thereby, in the band mode, a plurality of band data can be sequentially pipeline-processed without delay by the processing circuit.

  The image processing apparatus according to the present invention may be as follows in addition to any of the image processing apparatuses described above. In this case, the image processing apparatus includes an image rotation circuit that generates image data of an image obtained by rotating an image based on one page of image data by 90 degrees or 270 degrees. In the mode designation information, the mode type corresponding to the work type in which a series of image processing corresponding to the work type includes 90 degree rotation or 270 degree rotation of the image indicates a page mode. After the band data for one page is stored in the data storage device, the data decompression circuit reads the compressed band data necessary for the image rotation processing of the image rotation circuit from the data storage device, and reads the compressed band data Decompress and store band data in memory. The image rotation circuit performs image rotation processing using the band data obtained by the data expansion circuit.

  According to the present invention, it is possible to obtain an image processing apparatus capable of starting image processing on image data immediately after the image data is supplied in the page mode or the band mode.

FIG. 1 is a block diagram showing a configuration of an image processing apparatus according to an embodiment of the present invention. FIG. 2 is a block diagram showing the configuration of the data processing apparatus in FIG. FIG. 3 is a diagram showing an example of the mode designation table in FIG. FIG. 4 is a diagram showing a data flow in the band mode in the image processing apparatus shown in FIG. FIG. 5 is a timing chart showing processing of a plurality of processing circuits in the band mode in the image processing apparatus shown in FIG. FIG. 6 is a diagram showing a data flow in the page mode in the image processing apparatus shown in FIG. FIG. 7 is a diagram illustrating a data flow in the work type process involving double-sided scanning in the image processing apparatus illustrated in FIG. 1.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 is a block diagram showing a configuration of an image processing apparatus according to an embodiment of the present invention. FIG. 2 is a block diagram showing a configuration of the data processing apparatus 1 in FIG.

  1 includes a data processing device 1, a main controller 2, a RAM (Random Access Memory) 3, a hard disk drive (HDD) 4, a scanner 5, a print engine control circuit 6, a storage device 7, and a facsimile communication device 8. A network interface 9, an operation panel 10, a print engine (not shown) for printing on paper, and the like.

  The data processing device 1 is a device that processes image data from the scanner 5 or the like in band units or page units and outputs the processed image data to the main controller 2, HDD 4, print engine control circuit 6, or the like. Since the scanner 5 outputs image data and attribute data corresponding to the image data, the data processing apparatus 1 performs predetermined processing on both. The attribute data is used for settings such as color processing and gradation processing in image processing. The attribute data includes information for each pixel such as whether or not the character data. The image data and the attribute data are handled as page data in units of one page or band data corresponding to one of a plurality of bands obtained by dividing one page. For example, the image data has 4 planes of CMYK, and the attribute data has an A plane and an S plane. Each plane of CMYK is a plane having a height of 8 bits. The A plane is a 4-bit high plane, and the S plane is an 8-bit high plane.

  The main controller 2 is a circuit that controls the scanner 5, the facsimile apparatus 8, and the network interface 9 based on a user operation on the operation panel 10 and supplies commands to the data processing apparatus 1. In particular, the main controller 2 refers to the mode designation table 7a of the storage device 7, specifies the mode type corresponding to the work type designated by the user operation, and when the user operation is detected, the data processing device 1 This is a control circuit that acquires image data and causes the data processing apparatus 1 to perform data processing in the specified mode type.

  The main controller 2 is a computer having a CPU (Central Processing Unit), a ROM (Read Only Memory), a RAM, and the like, and outputs a command and performs data processing according to a program stored in the ROM.

  The main controller 2 includes a communication processing unit 2a that controls the facsimile apparatus 8 and the network interface 9 and performs data processing of transmission data.

  The RAM 3 is a memory for temporarily storing band data in processing by the data processing device 1. As the RAM 3, for example, one or more DRAMs (Dynamic RAM) are used.

  The storage areas of the RAM 3 are used as band memories 3a1 and 3a2, band memories 3b1 and 3b2, band memories 3c1 and 3c2, band memories 3d1 and 3d2, band memories 3e1 and 3e2, and band memories 3f1 and 3f2, respectively. . Each band memory has a band data area of a size capable of storing each band data.

  The band memories 3a1, 3a2, 3b1, and 3b2 are used for supplying band data from the data acquisition circuit 15 to the image processing circuit 16. In particular, the band memories 3a1 and 3a2 are used for band data of image data, and the band memories 3b1 and 3b2 are used for band data of attribute data. When there are a plurality of planes, two band memories are secured in advance for each plane.

  The band memories 3c1, 3c2, 3d1, and 3d2 are used for supplying band data from the image processing circuit 16 to the JPEG codec 17 and the RLE codec 18. In particular, the band memories 3c1 and 3c2 are used for band data of image data, and the band memories 3d1 and 3d2 are used for band data of attribute data. When there are a plurality of planes, two band memories are secured in advance for each plane.

  The band memories 3e1, 3e2, 3f1, 3f2 are used to supply band data from the data acquisition circuit 15 to the JPEG codec 17 and the RLE codec 18. In particular, the band memories 3e1 and 3e2 are used for band data of image data, and the band memories 3f1 and 3f2 are used for band data of attribute data. When there are a plurality of planes, two band memories are secured in advance for each plane.

  The HDD 4 is a data storage device for storing page data composed of band data for one page. The HDD 4 is a data storage device having a larger capacity and lower speed than the RAM 3. In this embodiment, the compressed band data is stored in the HDD 4 for each page.

  The scanner 5 is an apparatus that optically reads an image on one or both sides of a document and outputs image data and attribute data obtained by the image reading. The scanner 5 sequentially outputs image data and attribute data generated by image reading as band data.

  The print engine control circuit 6 is a circuit that supplies print image data to the print engine and controls the print engine to execute printing.

  The storage device 7 is a device in which data and programs used by the main controller 2 are stored. As the storage device 7, a ROM, a nonvolatile memory such as a flash memory, a hard disk drive, or the like is used. The storage device 7 stores a mode designation table 7a in advance.

  The mode designation table 7a is a mode designation for associating a work type designated by the user with a mode type indicating whether to use the page mode or the band mode when performing a series of image processing corresponding to the work type. Contains information. In the page mode, in the data processing apparatus 1, image data is stored in the HDD 4 in units of pages before the image processing circuit 16. In the band mode, when image data is transferred from the data acquisition circuit 15 to the image processing circuit 16 in the data processing apparatus 1, the image data is stored in the RAM 3 in band units. FIG. 3 is a diagram showing an example of the mode designation table in FIG.

  The facsimile apparatus 8 is an apparatus that transmits facsimile data generated from image data, receives facsimile data, and generates image data from the facsimile data.

  The network interface 9 is a communication device that is connected to a network and performs data communication with a terminal device via the network.

  The operation panel 10 is disposed on the surface of the apparatus housing and includes a display device that displays various types of information and an input device that detects a user operation and outputs an electrical signal corresponding to the user operation. For example, a liquid crystal display is used as the display device, and a touch panel, a key switch, or the like is used as the input device. The input device of the operation panel 10 detects a first user operation for inputting a work type and a second user operation for starting the work.

  Here, the configuration of the data processing apparatus 1 will be described with reference to FIG.

  The data processing apparatus 1 includes an interface 11, a data flow controller 12, a memory interface 13, an HDD controller 14, a data acquisition circuit 15, an image processing circuit 16, a JPEG codec 17, an RLE codec 18, an image rotation circuit 19, a raster processing circuit 20, A halftone processing circuit 21 and a data output circuit 22 are included.

  The interface 11 is a circuit that transmits and receives data and commands between the main controller 2 and the data flow controller 12.

  The data flow controller 12 is a circuit that controls and operates the DMAC (Direct Memory Access Controller) of the data acquisition circuit 15, the image processing circuit 16, the JPEG codec 17, and the RLE codec 18 in accordance with a command from the main controller 2. The data flow controller 12 writes band data to one of the first band memory and the second band memory by the output DMA controller of a certain processing circuit among the plurality of processing circuits, and in parallel with this, the subsequent stage of the processing circuit The band data immediately before the band data is read from the other of the first band memory and the second band memory by the input DMA controller of the processing circuit.

  The memory interface 13 is a circuit that transmits and receives data and commands between the RAM 3 and the internal signal lines. The internal signal line is a signal line that connects the memory interface 13, the HDD controller 14, and the circuits 15 to 22. Address and data are transmitted and received through the signal line.

  The HDD controller 14 is a circuit that reads and writes data from and to the HDD 4.

  The data acquisition circuit 15 is a circuit that sequentially acquires image data and attribute data as band data from the scanner 5 and stores them in the RAM 3. The data acquisition circuit 15 includes output DMA controllers (output DMAC) 15w1 and 15w2. The output DMA controller (output DMAC) 15w1 of the data acquisition circuit 15 alternately writes the band data of the image data to the band memories 3a1 and 3a2, and alternately writes the band data of the attribute data to the band memories 3b1 and 3b2. The output DMA controller (output DMAC) 15w2 of the data acquisition circuit 15 alternately writes the band data of the image data to the band memories 3e1 and 3e2, and alternately writes the band data of the attribute data to the band memories 3f1 and 3f2.

  The image processing circuit 16 reads band data of image data and attribute data from the RAM 3, and performs predetermined image processing (image enlargement, image reduction, image rotation (only 180 degrees), color conversion, etc.) on the band data. This is a circuit that executes and stores the processed band data in the RAM 3. The image processing circuit 16 has an input DMA controller (input DMAC) 16r and an output DMAC 16w. The input DMAC 16r of the image processing circuit 16 alternately reads the band data of the image data from the band memories 3a1 and 3a2 or the band memories 3e1 and 3e2, and receives the band data of the attribute data from the band memories 3b1 and 3b2 or the band memories 3f1 and 3f2. Read alternately. The output DMAC 16w of the image processing circuit 16 alternately writes the band data of the image data processed in the image processing circuit 16 to the band memories 3c1 and 3c2, and the band data of the attribute data processed in the image processing circuit 16 The band memories 3d1 and 3d2 are alternately written.

  The JPEG codec 17 reads out the band data of the image data stored in the RAM 3, encodes and compresses the band data using a JPEG (Joint Photographic Experts Group) method, stores the band data in the HDD 4, and stores the band data in the HDD 4. This is a circuit that reads band data from page data of image data, decodes the band data by the JPEG method, decompresses the data, and stores it in the RAM 3. The JPEG codec 17 has an input DMAC 17r and an output DMAC 17w. At the time of encoding, the input DMAC 17r of the JPEG codec 17 alternately reads band data from the band memories 3c1 and 3c2 or the band memories 3e1 and 3e2, and the output DMAC 17w of the JPEG codec 17 is band data compressed by the JPEG method. Is written into the HDD 4 via the HDD controller 14. At the time of decoding, the input DMAC 17r reads the band data compressed by the JPEG method from the HDD 4 via the HDD controller 14, and the output DMAC 17w alternately writes the band data to the band memories 3e1 and 3e2.

  The RLE codec 18 reads the band data of the attribute data stored in the RAM 3, encodes and compresses the band data by the RLE (Run Length Encoding) method, stores the band data in the HDD 4, and also stores the attribute data stored in the HDD 4. This is a circuit that reads out band data from the page data of the data, decodes the band data by the RLE method, expands it, and stores it in the RAM 3. The RLE codec 18 has an input DMAC 18r and an output DMAC 18w. At the time of encoding, the input DMAC 18r of the RLE codec 18 alternately reads band data from the band memories 3d1 and 3d2 or the band memories 3f1 and 3f2, and the output DMAC 18w of the RLE codec 18 is band data compressed by the RLE method. Is written into the HDD 4 via the HDD controller 14. At the time of decoding, the input DMAC 18r reads the band data compressed by the RLE method from the HDD 4 via the HDD controller 14, and the output DMAC 18w alternately writes the band data to the band memories 3f1 and 3f2.

  The image rotation circuit 19 is a circuit that generates image data of an image obtained by rotating an image based on image data of one page by 90 degrees or 270 degrees.

  The raster processing circuit 20 is a circuit that reads band data of image data (and attribute data) from the RAM 3, executes rasterization on the band data, and generates raster data. The raster data is compressed by the RLE codec 18 for each band and then stored in the HDD 4. Thereafter, the RLE codec 18 reads and decompresses the compressed raster data for each band, and the raster data is stored in the RAM 3.

  The halftone processing circuit 21 is a circuit that reads raster data for each band from the RAM 3, executes halftone processing, and stores the data after halftone processing in the RAM 3.

  The data output circuit 22 supplies the band data read from the HDD 4 and expanded by the codecs 17 and 18 to the communication processing unit 2a, or reads the data after halftone processing from the RAM 3 and supplies the data to the print engine control circuit 6. It is.

  These circuits 11 to 22 are each realized as an ASIC (Application Specific Integrated Circuit).

  Next, the operation of the above apparatus will be described.

  The user operates the input device of the operation panel 10, designates a work type by a first user operation, and causes the apparatus to execute a work of the work type by a second user operation. The first user operation is an operation of selecting a work type from, for example, a menu on the touch panel on the operation panel 10, and the second user operation is a press of a start button on the operation panel 10, for example.

  The main controller 2 refers to the mode designation table 7a of the storage device 7, specifies the mode type corresponding to the work type designated by the first user operation, and when the second user operation is detected, the data processing device 1, image data is acquired by 1, and the data processing apparatus 1 performs data processing in the specified mode type (band mode or page mode).

  First, the operation of the data processing apparatus 1 in the band mode will be described.

  FIG. 4 is a diagram showing a data flow in the band mode in the image processing apparatus shown in FIG. FIG. 5 is a timing chart showing processing of a plurality of processing circuits in the band mode in the image processing apparatus shown in FIG.

  First, the main controller 2 causes the scanner 5 to start reading an image, and instructs the data flow controller 12 to execute the specified work type processing on the image data and attribute data generated by the scanner 5. To supply.

  When receiving the command, the data flow controller 12 operates the data acquisition circuit 15, the image processing circuit 16, the JPEG codec 17 and the RLE codec 18 as follows.

  The data acquisition circuit 15 sequentially acquires band data of image data (hereinafter referred to as image band data) and band data of attribute data (hereinafter referred to as attribute band data), and the output DMAC 15w1 stores the image band data in the band memory. Write to any of 3a1 and 3a2, and write attribute band data to any of band memories 3b1 and 3b2.

  First, the image band data of band # 0 is written into the band memory 3a1, and the attribute band data of band # 0 is written into the band memory 3b1.

  Next, when the completion of the writing of the band # 0 image band data and attribute band data by the data acquisition circuit 15 is notified to the image processing circuit 16 via the data flow controller 12 by an interruption or the like, the image processing circuit 16 The input DMAC 16r reads the image band data and attribute band data of band # 0 from the band memories 3a1 and 3b1, and the output DMAC 16w receives the image band data and attribute band data of band # 0 after the image processing in the band memories 3c1 and 3d1. Write to each. At this time, the input DMAC 16r and the output DMAC 16w operate in parallel.

  On the other hand, the output DMAC 15w1 of the data acquisition circuit 15 writes the image band data and attribute band data of band # 1 into the band memories 3a2 and 3b2, respectively, after completing the writing of the image band data and attribute band data of band # 0.

  At this time, the writing to the band memories 3a2 and 3b2 by the output DMAC 15w1 and the reading from the band memories 3a1 and 3b1 by the input DMAC 16r are performed in parallel.

  When the processing by the image processing circuit 16 and the writing of the image band data of the band # 0 and the attribute band data to the band memories 3c1 and 3d1 are completed, the band data of the band # 2 from the band memories 3a1 and 3b1 are input to the input DMAC 16r. Activation reservation for reading is performed, and activation reservation for writing band data of band # 1 to the band memories 3c2 and 3d2 is performed for the output DMAC 16w. Note that the activation reservation for reading the band data of the bands # 0 and # 1 and the activation reservation for writing the band data of the band # 0 are performed in advance when the data acquisition circuit 15 is activated. Thereafter, the activation reservation is performed in the same manner.

  Then, the completion of the processing by the image processing circuit 16 and the writing of the image band data and the attribute band data to the band memories 3c1 and 3d1 is notified to the JPEG codec 17 and the RLE codec 18 through the data flow controller 12 by an interrupt or the like. Then, the input DMAC 17r of the JPEG codec 17 reads the image band data of band # 0 from the band memory 3c1, and the output DMAC 17w writes the image band data compressed by the JPEG method to the HDD 4 via the HDD controller 14. The input DMAC 18r of the RLE codec 18 reads the attribute band data of band # 0 from the band memory 3d1, and the output DMAC 18w sends the image band data compressed by the RLE method to the HDD controller 14. To write to the HDD4. At this time, the input DMAC 17r and the output DMAC 17w operate in parallel, and the input DMAC 18r and the output DMAC 18w operate in parallel.

  When the processing for the band # 0 by the JPEG codec 17 is completed, a start-up reservation for reading the band data of the band # 2 from the band memories 3c1 and 3d1 is performed for the input DMAC 17r, and the band # for the output DMAC 17w. A start-up reservation for writing 1 band data is made. Note that the activation reservation for reading the band data of the bands # 0 and # 1 and the activation reservation for writing the band data of the band # 0 are performed in advance when the data acquisition circuit 15 is activated. Thereafter, the activation reservation is performed in the same manner. Similarly, the RLE codec 18 makes an activation reservation.

  When the completion of the writing of the band # 1 image band data and attribute band data by the data acquisition circuit 15 is notified to the image processing circuit 16 via the data flow controller 12 due to an interruption or the like, the image processing circuit 16 The input DMAC 16r reads the image band data and attribute band data of the band # 1 from the band memories 3a2 and 3b2, and the output DMAC 16w stores the image band data and attribute band data of the band # 1 after the image processing in the band memories 3c2 and 3d2. Write each.

  At this time, the writing to the band memories 3c2 and 3d2 by the output DMAC 16w and the reading from the band memories 3c1 and 3d1 by the input DMACs 17r and 18r are performed in parallel.

  On the other hand, the output DMAC 15w1 of the data acquisition circuit 15 writes the image band data and attribute band data of band # 2 into the band memories 3a1 and 3b1, respectively, after the writing of the image band data and attribute band data of band # 1 is completed. At this time, the data acquisition circuit 15 overwrites the image band data and attribute band data of band # 0 in the band memories 3a1 and 3b1 with the image band data and attribute band data of band # 2. The processing time per band of the image processing circuit 16 is set shorter than the processing time per band of the data acquisition circuit 15. Therefore, at this time, the image processing circuit 16 has already completed the processing for the band # 0, and there is no problem caused by data overwriting.

  At this time, the writing to the band memories 3a1 and 3b1 by the output DMAC 15w1 and the reading from the band memories 3a2 and 3b2 by the input DMAC 16r are performed in parallel.

  Then, the completion of the processing by the image processing circuit 16 and the writing of the image band data and attribute band data to the band memories 3c2 and 3d2 is notified to the JPEG codec 17 and the RLE codec 18 through the data flow controller 12 by an interrupt or the like. Then, the input DMAC 17r of the JPEG codec 17 reads the image band data of band # 1 from the band memory 3c2, and the output DMAC 17w writes the image band data compressed by the JPEG method to the HDD 4 via the HDD controller 14. The input DMAC 18r of the RLE codec 18 reads the attribute band data of band # 1 from the band memory 3d2, and the output DMAC 18w sends the image band data compressed by the RLE system to the HDD controller 14. To write to the HDD4.

  When the completion of the writing of the band # 2 image band data and attribute band data by the data acquisition circuit 15 is notified to the image processing circuit 16 via the data flow controller 12 due to an interrupt or the like, the image processing circuit 16 The input DMAC 16r reads the image band data and attribute band data of the band # 2 from the band memories 3a1 and 3b1, and the output DMAC 16w inputs the image band data and attribute band data of the band # 2 after the image processing to the band memories 3c1 and 3d1. Write each. At this time, the output DMAC 16w of the image processing circuit 16 overwrites the image band data and attribute band data of band # 0 in the band memories 3c1 and 3d1 with the image band data and attribute band data of band # 2. The processing time per band of the JPEG codec 17 and the RLE codec 18 is set shorter than the processing time per band of the image processing circuit 16. Therefore, at this point, the JPEG codec 17 and the RLE codec 18 have already completed the processing for the band # 0, and there is no problem caused by data overwriting.

  As described above, in the processing circuits 15 to 18, the processing time for one band data is set to be shorter for the subsequent processing circuits. For example, the data acquisition circuit 15 processes one band data in 25 milliseconds, the image processing circuit 16 processes one band data in 10 milliseconds, and the JPEG codec 17 and the RLE codec 18 have 5 milliseconds. To process one band data.

  At this time, the writing to the band memories 3c1 and 3d1 by the output DMAC 16w and the reading from the band memories 3c2 and 3d2 by the input DMACs 17r and 18r are performed in parallel.

  On the other hand, the output DMAC 15w1 of the data acquisition circuit 15 writes the image band data and attribute band data of band # 3 into the band memories 3a2 and 3b2, respectively, after completing the writing of the image band data and attribute band data of band # 2. At this time, the data acquisition circuit 15 overwrites the image band data and attribute band data of band # 1 in the band memories 3a2 and 3b2 with the image band data and attribute band data of band # 3.

  At this time, the writing to the band memories 3a2 and 3b2 by the output DMAC 15w1 and the reading from the band memories 3a1 and 3b1 by the input DMAC 16r are performed in parallel.

  Then, the completion of the processing by the image processing circuit 16 and the writing of the image band data and the attribute band data to the band memories 3c1 and 3d1 is notified to the JPEG codec 17 and the RLE codec 18 through the data flow controller 12 by an interrupt or the like. Then, the input DMAC 17r of the JPEG codec 17 reads the image band data of band # 2 from the band memory 3c1, and the output DMAC 17w writes the image band data compressed by the JPEG method to the HDD 4 via the HDD controller 14. The input DMAC 18r of the RLE codec 18 reads the attribute band data of band # 2 from the band memory 3d1, and the output DMAC 18w sends the image band data compressed by the RLE method to the HDD controller 14. To write to the HDD4.

  Thereafter, similarly, band data after band # 3 is processed. Thereby, the band data for one page is sequentially pipeline-processed by the data acquisition circuit 15, the image processing circuit 16, and the codecs 17 and 18, and the processed data is stored in the HDD 4.

  When the work type designated by the user is copy, after one page of data is stored in the HDD 4 in this way, rasterization by the raster processing circuit 20 and halftone processing by the halftone processing circuit 21 are performed. Then, print image data is generated from the data, supplied to the print engine control circuit 6 by the data output circuit 22, and printing is executed.

  Further, when the output in the work of the work type designated by the user is network transmission (SEND), after one page of data is stored in the HDD 4 in this way, it is decoded by the codecs 17 and 18. The data output circuit 22 supplies the data to the communication processing unit 2a. The communication processing unit 2a generates a data file in a predetermined file format (for example, PDF format) from the data, and uses a predetermined protocol (file sharing, e-mail, etc.). The data is transmitted to a predetermined terminal device via the network interface 9.

  If the work type designated by the user is facsimile transmission, after data for one page is stored in the HDD 4 in this way, the data is decoded by the codecs 17 and 18, and the data output circuit 22 performs communication processing. Facsimile data is generated from the data by the communication processing unit 2a and transmitted to the facsimile number designated by the user by the communication device 2a.

  Next, the operation of the data processing apparatus 1 in the page mode will be described.

  FIG. 6 is a diagram showing a data flow in the page mode in the image processing apparatus shown in FIG.

  First, the main controller 2 causes the scanner 5 to start reading an image and instructs the data flow controller 12 to execute the specified work type processing on the image data and attribute data generated by the scanner 5. Supply.

  When receiving the command, the data flow controller 12 operates the data acquisition circuit 15, the image processing circuit 16, the JPEG codec 17 and the RLE codec 18 as follows.

  The data acquisition circuit 15 sequentially acquires the image band data and the attribute band data, and the output DMAC 15w2 writes the image band data to any of the band memories 3e1 and 3e2, and the attribute band data to any of the band memories 3f1 and 3f2. Write in.

  First, the image band data of band # 0 is written into the band memory 3e1, and the attribute band data of band # 0 is written into the band memory 3f1.

  Next, when the completion of the writing of the band # 0 image band data and attribute band data by the data acquisition circuit 15 is notified to the JPEG codec 17 and the RLE codec 18 through the data flow controller 12 by an interrupt or the like, The input DMAC 17r of the codec 17 reads the image band data of band # 0 from the band memory 3e1, and the output DMAC 17w writes the image band data compressed by the JPEG method to the HDD 4 via the HDD controller 14, and the RLE codec 18 The input DMAC 18r reads the attribute band data of band # 0 from the band memory 3f1, and the output DMAC 18w writes the image band data compressed by the RLE method to the HDD 4 via the HDD controller 14. At this time, the input DMAC 17r and the output DMAC 17w operate in parallel, and the input DMAC 18r and the output DMAC 18w operate in parallel.

  On the other hand, the output DMAC 15w1 of the data acquisition circuit 15 writes the image band data and attribute band data of band # 1 in the band memories 3e2 and 3f2, respectively, after completing the writing of the image band data and attribute band data of band # 0.

  At this time, the writing to the band memories 3e2 and 3f2 by the output DMAC 15w1 and the reading from the band memories 3e1 and 3f1 by the input DMACs 17r and 18r are performed in parallel.

  Next, when the completion of writing of the image band data and the attribute band data of band # 1 by the data acquisition circuit 15 is notified to the JPEG codec 17 and the RLE codec 18 through the data flow controller 12 by an interrupt or the like, The input DMAC 17r of the codec 17 reads the image band data of band # 1 from the band memory 3e2, and the output DMAC 17w writes the image band data compressed by the JPEG method to the HDD 4 via the HDD controller 14, and the RLE codec 18 The input DMAC 18r reads the attribute band data of band # 1 from the band memory 3f2, and the output DMAC 18w writes the image band data compressed by the RLE method to the HDD 4 via the HDD controller 14.

  On the other hand, the output DMAC 15w1 of the data acquisition circuit 15 writes the image band data and attribute band data of band # 2 in the band memories 3e1 and 3f1, respectively, after completing the writing of the image band data and attribute band data of band # 1. At this time, the data acquisition circuit 15 overwrites the image band data and attribute band data of band # 0 in the band memories 3e1 and 3f1 with the image band data and attribute band data of band # 2. The processing time per band of the JPEG codec 17 and the RLE codec 18 is set shorter than the processing time per band of the data acquisition circuit 15. Therefore, at this time, the codecs 17 and 18 have already completed the processing for the band # 0, and there is no problem caused by data overwriting.

  Similarly, band data after band # 2 is processed. As a result, the band data for one page is sequentially pipelined by the data acquisition circuit 15 and the codecs 17 and 18, and the processed data is stored in the HDD 4.

  Then, after the band data for one page is stored in the HDD 4, each band data is sequentially supplied to the image processing circuit 16. For example, when the image processing circuit 16 performs complicated data processing, it cannot be guaranteed that the processing time for one band by the image processing circuit 16 is shorter than the processing time for one band by the data acquisition circuit 15. For this reason, a page mode is set for such a work type. In the page mode, band data is supplied from the HDD 4 to the image processing circuit 16 via the HDD controller 14 and the codecs 17 and 18 in accordance with the processing speed of the image processing circuit 16.

  Therefore, under the control of the data flow controller 12, the input DMAC 17r of the JPEG codec 17 reads the compressed image band data of band # 0 from the HDD 4 via the HDD controller 14, and the output DMAC 17w The image band data of 0 is written in the band memory 3e1, the input DMAC 18r of the RLE codec 18 reads the compressed attribute band data of band # 0 from the HDD 4 via the HDD controller 14, and the output DMAC 18w The attribute band data of band # 0 is written into the band memory 3f1.

  Next, when the completion of the writing of the band # 0 image band data and the attribute band data by the codecs 17 and 18 is notified to the image processing circuit 16 via the data flow controller 12 by interruption or the like, the image processing circuit 16 The input DMAC 16r reads the image band data and attribute band data of the band # 0 from the band memories 3e1 and 3f1, and the output DMAC 16w stores the image band data and attribute band data of the band # 0 after the image processing in the band memories 3c1 and 3d1. Write to each. At this time, the input DMAC 16r and the output DMAC 16w operate in parallel. Since the processing downstream of the image processing circuit 16 is the same as that in the band mode, the description thereof is omitted.

  On the other hand, after the completion of the writing of the image band data and the attribute band data of the band # 0 by the codecs 17 and 18, the band data is sequentially transferred to the band memories 3e1, 3e2, 3f1, and 3f2 at the time intervals set by the data flow controller 12. As output, the input DMACs 17r and 18r read the compressed image band data and attribute band data of band # 1, and the output DMACs 17w and 18w output the image band data and attribute band data of band # 1 after data decompression. Are written in the band memories 3e2 and 3f2, respectively.

  When the completion of the writing of the band # 1 image band data and attribute band data by the codecs 17 and 18 is notified to the image processing circuit 16 via the data flow controller 12 by an interrupt or the like, the image processing circuit 16 The input DMAC 16r reads the image band data and attribute band data of the band # 1 from the band memories 3e2 and 3f2, and the output DMAC 16w inputs the image band data and attribute band data of the band # 1 after the image processing to the band memories 3c2 and 3d2. Write each.

  On the other hand, after the completion of the writing of the band # 1 image band data and attribute band data by the codecs 17 and 18, the band data is sequentially transferred to the band memories 3e1, 3e2, 3f1, and 3f2 at the time intervals set by the data flow controller 12. As output, the input DMACs 17r and 18r read the compressed image band data and attribute band data of band # 2, and the output DMACs 17w and 18w output the image band data and attribute band data of band # 2 after data decompression. Are written in the band memories 3e1 and 3f1, respectively. At this time, the output DMACs 17w and 18w overwrite the image band data and attribute band data of band # 0 in the band memories 3e1 and 3f1 with the image band data and attribute band data of band # 2.

  Similarly, band data after band # 2 is processed. As a result, the band data for one page is sequentially pipelined in the order of the codecs 17 and 18, the image processing circuit 16, and the codecs 17 and 18, and the processed data is stored in the HDD 4. Note that the processing time for one band by the codecs 17 and 18 is set to be half or less of the processing time for one band by the image processing circuit 16.

  Thereafter, after one page of data after image processing is stored in the HDD 4, after output processing is performed in the same manner as in the band mode, one of printing, network transmission, and facsimile transmission is performed. Is done.

  Next, the operation of the data processing apparatus 1 when a work type involving double-sided scanning is designated will be described. For example, when the mode designation table 7a is as shown in FIG. 3, double-sided scanning is performed by the scanner 5 in the processing of the work types “double-sided copy”, “double-sided network transmission”, and “double-sided facsimile apparatus”.

  In the case of such a work type process, the image processing circuit 16 cannot process a plurality of sets of image data and attribute data at the same time. Therefore, the data flow controller 12 reads the surface data of the document and the document data. One of the back side data obtained by reading the back side image is processed in the band mode, and the other is processed in the page mode. Here, the front surface data is processed in the band mode, and the back surface data is processed in the page mode.

  FIG. 7 is a diagram illustrating a data flow in the work type process involving double-sided scanning in the image processing apparatus illustrated in FIG. 1.

  The data acquisition circuit 15 acquires from the scanner 5 front surface data obtained by reading a front image of a document and back surface data obtained by reading a back image of the document. The front surface data is composed of image data and attribute data, and the back surface data is composed of image data and attribute data.

  Since the surface data is processed in the band mode, it is transferred from the output DMAC 15w1 of the data acquisition circuit 15 to the input DMAC 16r of the image processing circuit 16 via the band memories 3a1, 3a2, 3b1, and 3b2. The surface data is processed by the image processing circuit 16, compressed by the codecs 17 and 18, and stored in the HDD 4.

  Since the back side data is processed in the page mode, it is transferred from the output DMAC 15w2 of the data acquisition circuit 15 to the input DMACs 17r and 18r of the codecs 17 and 18 via the band memories 3e1, 3e2, 3f1, and 3f2. Then, the back data is temporarily stored in the HDD 4 after being compressed by the codecs 17 and 18.

  Then, after the processing of the front surface data in the band mode is completed, the back surface data is read from the HDD 4 and expanded by the codecs 17 and 18, and then output from the output DMACs 17 w and 18 w of the codecs 17 and 18 to the band memories 3 e 1 and 3 e 2. , 3f1, 3f2 to the input DMAC 16r of the image processing circuit 16. The back surface data is processed by the image processing circuit 16, compressed by the codecs 17 and 18, and stored in the HDD 4.

  After data for one page on the front side after image processing is stored in the HDD 4, processing for output is performed, and printing, network transmission, and facsimile transmission are performed, and back side 1 after image processing is performed. After the data for the page is stored in the HDD 4, a process for output is performed, and any one of printing, network transmission, and facsimile transmission is performed.

  As described above, according to the above embodiment, the storage device 7 uses the work mode designated by the user and the page mode or the band mode when performing a series of image processing corresponding to the work type. A mode designation table 7a including mode designation information for associating with a mode type indicating whether to use is stored. The operation panel 10 detects a first user operation for inputting a work type and a second user operation for starting the work. Then, the main controller 2 refers to the mode designation information, specifies the mode type corresponding to the work type designated by the first user operation, and when the second user operation is detected, the data acquisition circuit 15 causes the image to be displayed. Data is acquired, and the image processing circuit 16 performs data processing in the specified mode type.

  Thus, after the image data is acquired by the data acquisition circuit 15 in the image processing apparatus, the image processing for the image data can be started immediately in the page mode or the band mode regardless of the data size. That is, in the band mode, it is possible to start image processing immediately after image data for one band is acquired. In the page mode, image processing is started immediately after image data for one page is acquired. It becomes possible.

  The above-described embodiments are preferred examples of the present invention, but the present invention is not limited to these, and various modifications and changes can be made without departing from the scope of the present invention. is there.

  For example, in the above embodiment, when the image data has four planes CMYK and the attribute data has an A plane and an S plane, the three CMY planes are handled as image data, and the K plane, the A plane, and the S plane. A plane may be handled as attribute data.

  Further, in the above-described embodiment, as the RAM 3, two paired band memories (3a1, 3a2), (3b1, 3b2), (3c1, 3c2), (3d1, 3d2), (3e1, 3e2), (3f1) 3f2), independent RAM modules may be provided for one and the other, and the RAM modules may be accessed in parallel. Alternatively, the RAM 3 may be provided with the same number of independent RAM modules as the band memory so that each RAM module can be accessed in parallel.

  Further, in the above embodiment, in the case of a work type that involves rotation of an image by 90 degrees or 270 degrees, the image processing circuit 16 processes image data and attribute data for one page and stores them in the HDD 4. 18 reads compressed band data necessary for image rotation processing of the image rotation circuit 19 from the HDD 4 via the HDD controller 14, decompresses the compressed band data, stores the band data in the RAM 3, and The rotation circuit 19 performs image rotation processing using the band data obtained by decompression by the codecs 17 and 18. Then, the image rotation circuit 19 performs an image rotation process using the band data obtained by the codecs 17 and 18 being decompressed.

  The present invention can be applied to an image forming apparatus such as a copying machine or a multifunction machine.

2 Main controller (example of control circuit)
3 RAM (an example of memory)
4 HDD (an example of a data storage device)
7 Storage device 10 Operation panel (an example of input device)
12 data flow controller 15 data acquisition circuit 15w1, 15w2 output DMAC
16 Image processing circuit (an example of a processing circuit)
16r input DMAC
17 JPEG codec (example of data compression circuit, example of data decompression circuit)
19 Image rotation circuit

Claims (7)

A storage device that stores mode designation information that associates a work type designated by a user with a mode type indicating whether to use a page mode or a band mode when performing a series of image processing corresponding to the work type When,
A data acquisition circuit for acquiring image data;
A processing circuit for performing data processing on the image data;
An input device for detecting a first user operation for inputting the work type and a second user operation for starting the work;
Referring to the mode designation information, a mode type corresponding to the work type designated by the first user operation is specified, and when the second user operation is detected, image data is obtained by the data obtaining circuit. A control circuit that causes the processing circuit to perform data processing in the identified mode type;
An image processing apparatus comprising: A data storage device capable of storing image data for one page, and a memory capable of storing band data obtained by dividing one page of image data;
The image data is stored in the memory as band data when the specified mode type is a band mode, and stored in the data storage device when the specified mode type is a page mode,
The processing circuit performs data processing on the band data read from the memory when the specified mode type is a band mode, and when the specified mode type is a page mode. Performing data processing on the image data read from the data storage device;
The image processing apparatus according to claim 1. A data compression circuit and a data expansion circuit;
When the specified mode type is a page mode, the data compression circuit reads out the band data from the memory, compresses the band data, and stores the compressed band data in the data storage device,
The data decompression circuit reads the compressed band data from the data storage device after the band data for one page is stored in the data storage device when the specified mode type is the page mode, Decompressing the compressed band data and storing the band data in the memory;
The image processing apparatus according to claim 2. When the specified mode type is the page mode, the data decompression circuit stores the compressed band required for the data processing of the processing circuit after the band data for one page is stored in the data storage device. Read data from the data storage device, decompress the compressed band data, store the band data in the memory,
The processing circuit performs data processing using band data obtained by the data decompression circuit;
The image processing apparatus according to claim 3. A data flow controller for controlling data input / output of the data acquisition circuit and the processing circuit;
The memory includes a first band memory and a second band memory,
The data acquisition circuit includes an output DMA controller that performs direct memory access for writing data to the first band memory and the second band memory,
The processing circuit includes an input DMA controller that performs direct memory access for reading data from the first band memory and the second band memory;
The data flow controller causes the output DMA controller of the data acquisition circuit to alternately write band data to one of the first band memory and the second band memory, and when the specified mode type is a band mode. In parallel therewith, the input DMA controller of the processing circuit causes the previous band data of the band data to be read from the other of the first band memory and the second band memory.
The image processing apparatus according to claim 2.   In the case where the specified mode type is a band mode, the data flow controller, from the first band memory by the processing circuit, completes the writing of the band data to the first band memory by the data acquisition circuit. The reading of the band data at the same time, the writing of the next band data to the second band memory by the data acquisition circuit is started, and the band data of the band data to the second band memory by the data acquisition circuit is started. When the writing is completed, reading of the band data from the second band memory by the processing circuit is started, and writing of the next band data to the first band memory by the data acquisition circuit is started. The image processing apparatus according to claim 5. An image rotation circuit for generating image data of an image obtained by rotating an image based on one page of image data by 90 degrees or 270 degrees;
In the mode designation information, a mode type corresponding to a work type in which a series of image processing corresponding to the work type includes 90 degree rotation or 270 degree rotation of an image indicates a page mode,
The data decompression circuit reads the compressed band data necessary for image rotation processing of the image rotation circuit from the data storage device after the band data for one page is stored in the data storage device, and the compressed data is compressed. Decompress the band data, store the band data in the memory,
The image rotation circuit performs image rotation processing using band data obtained by the data decompression circuit;
The image processing apparatus according to claim 3.

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