JP5116624B2 - Simulation apparatus and simulation method - Google Patents

Description

  The present invention relates to a simulation apparatus and a simulation method for simulating the operation of a processor.

  A simulation apparatus is used for analysis and debugging of a program operating on a processor. The simulation apparatus is designed to perform the same operation as the operation of the processor or a simplified operation thereof. As such a simulation device, an instruction set simulator (ISS; Instruction Set Simulator) is widely known. The ISS operates on a computer such as a personal computer or a workstation, and simulates an operation of a processor instruction, an execution result thereof, a register state, and the like. By using ISS, there is an advantage that it is not necessary to prepare dedicated hardware for program analysis and debugging.

  In analyzing a program using ISS, it is desirable to maximize the performance of the CPU. For that purpose, it is necessary to minimize the processing time loss due to the data hazard, that is, the processing time loss due to the stop of the processing progress of the pipeline stage. Therefore, it is necessary to detect (verify) where and how many data hazards exist in the user application and to show them to the user. As a means for this, there is a method of obtaining information from the CPU actual machine, but a method of detecting a data hazard by a simulator is necessary in order to take into account the time under reproducibility of the CPU under development and multi-core.

  Introduces technologies related to simulation.

  In RealView Profiler (see Non-Patent Document 1), as shown in FIG. 1-1, RealView Trace2 unit is used and connected to RealView ICE. Thereby, RealView Profiler acquires interlock (data hazard) information from the CPU actual machine via RealView ICE and RealView Trace2 unit, and displays it together with the trace information. As shown in FIGS. 1-2 and 1-3, the RealView Profiler displays a mark ● on the source (assembler) view based on the acquired trace information, and notifies the user of an instruction in which a data hazard has occurred. The RealView Profiler also has a mechanism for connecting to a simulator, but it seems that data hazard information cannot be extracted.

  ArchC (see Non-Patent Document 2) provides a SystemC simulator generation tool called arcsim, and automatically generates a SystemC simulator using architecture information AC_ARCHH and ISA information AC_ISA. This AC_ARCH has a part for writing a pipeline stage, and a System C simulator having the pipeline stage is generated. This SystemC simulator is a cycle accumulator, and has a pipeline stage, thereby enabling simulation in consideration of data hazards.

  FIG. 2 is a schematic diagram of a pipeline stage of a processor attempting to perform a simulation. The processor includes a memory in which an instruction group and data are stored, a register, and a pipeline. The processor operates according to the clock, and further, an IF (instruction fetch) stage for fetching an instruction group, a DC (decode) stage for decoding the fetched instruction, and an EX (execution) for executing the decoded instruction. There are provided a stage, a ME (memory access) stage for accessing the memory with respect to the instruction (memory access instruction), and a WB (write back) stage for writing the execution result of the instruction to the register. The processor configures a pipeline by the IF stage, the DC stage, the EX stage, the ME stage, and the WB stage.

“ARM RealView Profiler 1.0 (product brochure)”, [online], [searched on August 20, 2008], Internet <URL: http: // www. arm. com / products / DevTools / RVP. html> “ArchC”, [online], [searched on August 20, 2008], Internet <URL: http: // www. archc. org />

  However, the technique described in Non-Patent Document 1 can detect a data hazard (interlock) based on trace information from an actual machine, but is not a model that takes into account a delay due to a data hazard.

  In the technique described in Non-Patent Document 2, a cycle accurate simulation including a data hazard is realized by implementing a pipeline stage. However, since the pipeline stage includes a mechanism for executing in parallel every cycle, there is a problem that it takes more simulation time than ISS.

  In the following, means for solving the problems will be described using the reference numerals used in the best modes and embodiments for carrying out the invention in parentheses. This reference numeral is added to clarify the correspondence between the description of the claims and the description of the best mode for carrying out the invention / example, and is described in the claims. It should not be used to interpret the technical scope of the invention.

  The simulation apparatus of the present invention simulates the operation of a processor, and includes an instruction execution unit (10), a storage unit (32), a recording unit (31), a generation unit (21), and a calculation unit ( 22). The instruction execution unit (10) is provided with an instruction that can be executed on the processor and executes processing according to the instruction. The storage unit (32) includes a plurality of instruction types, a number of first execution machine cycles executed when no data hazard has occurred, and a data hazard for each of the plurality of instructions. And the number of second execution machine cycles to be executed when the machine is running. When a value is written to the register by the instruction, the generation unit (21) reads the first and second execution machine cycles for the instruction from the storage unit (32), and based on these, the pipeline stall Generate cycle numbers. The generation unit (21) stores the register identifier for identifying the register, the register write access time when the value is written to the register, and the number of pipeline stall cycles in the recording unit (31). When the register is subject to data hazard, the calculation unit (22) stores the register write access time and pipeline stall cycle number stored in the recording unit (31), and the second execution machine cycle number for the instruction. Based on the above, the number of execution machine cycles is calculated.

  According to the simulation apparatus (4) of the present invention, the register write access time and the read prohibition period are provided by including the generation unit (21), the recording unit (31), the calculation unit (22), and the storage unit (32). (The number of pipeline stall cycles) can be recorded, and the execution machine cycle number of each instruction can be determined (calculated) in consideration of the delay due to the data hazard without implementing the pipeline stage. can do.

  As a result, according to the simulation apparatus (4) of the present invention, the operation of the processor can be simulated with a model that takes into account the delay due to the data hazard. For this reason, the problem mentioned in the nonpatent literature 1 can be solved.

  In addition, according to the simulation apparatus (4) according to the embodiment of the present invention, since the pipeline stage is not provided, the problems mentioned in Non-Patent Document 2 can be solved and the simulation speed can be increased. .

  Hereinafter, a simulation apparatus according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

[Constitution]
FIG. 3 shows a configuration of the simulation apparatus 4 according to the embodiment of the present invention. The simulation apparatus 4 according to the embodiment of the present invention performs simulation of a microcomputer having a pipeline structure on a general-purpose computer (personal computer, EWS (engineering workstation)).

  The simulation apparatus 4 includes a user interface unit 5, an instruction data storage unit 6 that is a memory, and a simulation engine unit (simulation program) 7. The user interface unit 5 performs an input by the input device and a control to output to the output device. The instruction data storage unit 6 stores a program to be debugged. The simulation engine unit 7 reads out the debug target program from the instruction data storage unit 6 and processes the instruction group described in the debug target program.

  The simulation engine unit 7 can also be realized as a computer program (simulation program) installed in a computer. FIG. 4 shows the configuration of a computer as an environment in which the simulation apparatus 4 operates. The computer includes an input device 2, an output device 3, and a computer main body 1. The input device 2 and the output device 3 are connected to the computer main body 1. The input device 2 includes a keyboard and a pointing device, and the output device 3 includes a display device and a printer.

  The computer main body 1 includes a storage device (not shown) and a CPU (Central Processing Unit) (not shown). The simulation engine unit 7 is installed in a storage device. In this case, the debug target program stored in the instruction data storage unit 6 is also installed in the storage device. The simulation engine unit 7 (simulation program) reads the debug target program from the storage device, and processes the instruction group described in the debug target program on the CPU.

  The simulation engine unit 7 is used by a designer as software for analyzing and debugging a program (analysis target program) to be run on the processor. The instruction group executed by the processor is, for example, “LD, ADD, SUB, JMP, MOV”. “LD”, “ADD”, “SUB”, “JMP”, “MOV” in mnemonic notation respectively represent a load instruction, an add instruction, a subtract instruction, a jump instruction, and a move instruction for writing data from a memory to a register. Yes. The analysis target program operating on the processor is constituted by these instructions.

  FIG. 5 shows the configuration of the simulation engine unit 7. The simulation engine unit 7 includes an instruction execution unit 10, a register write access information generation unit 21, a data hazard detection and execution machine cycle number calculation unit 22, a register write access information storage unit 31, and an execution machine cycle number information storage unit 32. ing. The instruction execution unit 10 includes an instruction processing unit 11 and an execution cycle number measurement unit 13.

  The register write access information storage unit 31 includes a register identifier (register number) for identifying a register to which a value is written by an instruction, a time when a value is written to the register by an instruction (register write access time), a register A pipeline stall cycle number representing the number of machine cycles (clocks) when a pipeline stall occurs when a value is read is stored. For example, “r0, r1,..., R30, r31” as a register name, “0, 101,..., 123, 0” as a register write access time, and “0, 0,. 2, 0 ″ are stored in the register write access information storage unit 31 in association with each other.

  The execution machine cycle number information storage unit 32 represents a plurality of instruction types for identifying a plurality of instructions, and a machine cycle to be executed when no data hazard has occurred for each of the plurality of instructions. A first execution machine cycle number (the number of execution machine cycles without a hazard), a second execution machine cycle number (a number of execution machine cycles with a hazard) representing a machine cycle executed when a data hazard occurs, and Are stored in association with each other. The number of machine cycles executed when there is a hazard is equal to or greater than the number of machine cycles executed when there is no hazard. For example, “ADD, JMP,..., LD” as a plurality of instructions, “1, 4,..., 1” as the number of execution machine cycles without hazard, and “1, 4,. 3 ″ is stored in the execution machine cycle number information storage unit 32. Here, as for the number of execution machine cycles, a value extremely larger than the actual value is described for convenience of describing the present embodiment. These values are determined by the actual processing speed of the processor. As the determination method, there are a case where measurement is performed in advance using a processor and a case where determination is made in advance based on a design specification of the processor.

  The operations of the instruction execution unit 10 (the instruction processing unit 11 and the execution cycle number measurement unit 13), the register write access information generation unit 21, and the data hazard detection / execution machine cycle number calculation unit 22 will be described later.

[Operation]
FIG. 6 is a flowchart showing the operation of the simulation engine unit 7.

  The instruction processing unit 11 reads the analysis target program from the storage device (corresponding to the instruction data storage unit 6) by the designer's operation of the input device 2. The analysis target program is composed of first to nth instructions as an instruction group. For example, it is assumed that the analysis target program is composed of instructions “ADD, MOV, SUB, SUB, JMP, LD, LD, ADD, MOV”. The instruction processing unit 11 executes a process according to the first instruction of the analysis target program (step S1).

  When a value is written to the register by the instruction, the instruction processing unit 11 obtains a register identifier for identifying the register, a register write access time when the value is written to the register, and a type of the instruction. The data is output to the register write access information generation unit 21. At the same time, the instruction processing unit 11 outputs the register identifier and the type of the instruction to the execution cycle number measuring unit 13 (step S2-YES).

  The register write access information generation unit 21 refers to the execution machine cycle number information storage unit 32 and searches for an instruction that matches the instruction type from the instruction processing unit 11 among a plurality of instruction types. The register write access information generation unit 21 reads the number of execution machine cycles without a hazard and the number of execution machine cycles with a hazard with respect to the instruction from the execution machine cycle number information storage unit 32. The register write access information generation unit 21 generates a pipeline stall when the value of the register is read as a read prohibition period based on the number of execution machine cycles without hazard and the number of execution machine cycles with hazard. Generate a pipeline stall cycle number that represents the machine cycle when it occurs. In this case, a pipeline stall cycle number is generated by subtracting an execution machine cycle number without hazard for the instruction from the execution machine cycle number with hazard for the instruction. The register write access information generation unit 21 stores the register identifier from the instruction processing unit 11, the register write access time, and the number of pipeline stall cycles (read prohibition period) in the register write access information storage unit 31. Recording (storage) is performed (step S3).

  On the other hand, if no value is written to the register by the above instruction, step S3 is not executed.

  When the value of the register is read by the instruction, the execution cycle number measurement unit 13 outputs the register identifier and the instruction type from the instruction processing unit 11 to the data hazard detection / execution machine cycle number calculation unit 22. (Step S4-YES).

  The data hazard detection / execution machine cycle number calculation unit 22 refers to the register write access information storage unit 31 and searches for a register identifier that matches the register identifier from the execution cycle number measurement unit 13. The data hazard detection / execution machine cycle number calculation unit 22 reads the register write access time and the pipeline stall cycle number for the register identifier from the register write access information storage unit 31. The data hazard detection / execution machine cycle number calculation unit 22 determines whether or not a data hazard occurs by checking whether or not the number of pipeline stall cycles is greater than zero. That is, it is checked whether or not the register from which the value has been read is subject to data hazard (step S5).

  If the number of pipeline stall cycles is greater than 0, the register is subject to data hazards. In this case, the data hazard detection / execution machine cycle number calculation unit 22 determines that a data hazard occurs. That is, it is determined that the register is a target of data hazard (step S5-YES).

  In this case, the data hazard detection / execution machine cycle number calculation unit 22 calculates the number of execution wait cycles for which execution is awaited by the data hazard based on the register write access time and the pipeline stall cycle number. In this case, the number of cycles indicating the register write access time and the number of pipeline stall cycles are added to generate the number of cycles waiting for execution. The data hazard detection / execution machine cycle number calculation unit 22 refers to the execution machine cycle number information storage unit 32, and among the plurality of instruction types, an instruction that matches the instruction type from the execution cycle number measurement unit 13 Search for. The data hazard detection / execution machine cycle number calculation unit 22 reads the execution machine cycle number when there is a hazard for the instruction from the execution machine cycle number information storage unit 32. The data hazard detection / execution machine cycle number calculation unit 22 adds the number of execution wait cycles to the number of execution machine cycles when there is a hazard with respect to the instruction to generate an execution machine cycle number (addition execution machine cycle number) (step S6). .

  The data hazard detection / execution machine cycle number calculation unit 22 outputs data hazard presence information indicating that a data hazard has occurred, and the added execution machine cycle number to the execution cycle number measurement unit 13. The execution cycle number measurement unit 13 outputs an execution result 60 including data hazard information and the number of added execution machine cycles to the execution trace log as an output destination file. This output destination file is output to the output device 3. At the same time, the execution cycle number measurement unit 13 outputs an execution result output notification to the instruction processing unit 11 (step S7).

  On the other hand, when the instruction does not read the value of the register, the execution cycle number measurement unit 13 outputs the type of the instruction from the instruction processing unit 11 to the data hazard detection / execution machine cycle number calculation unit 22. (Step S4-NO). Alternatively, when the number of pipeline stall cycles is 0, the data hazard detection / execution machine cycle number calculation unit 22 determines that no data hazard has occurred (step S5-NO).

  In this case, the data hazard detection / execution machine cycle number calculation unit 22 refers to the execution machine cycle number information storage unit 32, and selects the type of instruction from the execution cycle number measurement unit 13 among the plurality of instruction types. Search for matching instructions. The data hazard detection / execution machine cycle number calculation unit 22 reads the execution machine cycle number without hazard for the instruction from the execution machine cycle number information storage unit 32. The data hazard detection / execution machine cycle number calculation unit 22 outputs to the execution cycle number measurement unit 13 data no-hazard information indicating that no data hazard occurs and the number of execution machine cycles when no hazard is present. The execution cycle number measurement unit 13 outputs to the output device 3 an execution result 60 that includes data hazard-free information and the number of machine cycles executed when there is no hazard. At the same time, the execution cycle number measurement unit 13 outputs an execution result output notification to the instruction processing unit 11 (step S9).

  When the next instruction exists in the analysis target program (step S8—NO), the instruction processing unit 11 executes a process according to the next instruction in response to the execution result output notification (step S1). When the next command does not exist (step S8—YES), the operation of the simulation engine unit 7 ends.

[effect]
As described above, in the simulation device 4 according to the embodiment of the present invention, when simulating the operation of the processor, the instruction execution unit 10 is given an instruction that can be executed on the processor and executes a process according to the instruction. The number-of-execution-machine-cycles information storage unit 32 includes a plurality of instruction types, a first execution machine cycle number that is executed when no data hazard has occurred, and a data hazard for each of the plurality of instructions. The second execution machine cycle number to be executed when it occurs is stored. When a value is written to the register by the instruction, the register write access information generation unit 21 reads the first and second execution machine cycle numbers for the instruction from the execution machine cycle number information storage unit 32, and based on them, the read prohibition period Generate the number of pipeline stall cycles. The register write access information generation unit 21 stores in the register write access information storage unit 31 a register identifier for identifying a register, a register write access time when a value is written to the register, and the number of pipeline stall cycles. To do. The data hazard detection / execution machine cycle number calculation unit 22 calculates the register write access time and the pipeline stall cycle number stored in the register write access information storage unit 31 when the register is a data hazard target. The execution machine cycle number is calculated based on the second execution machine cycle number for the instruction.

  Thus, according to the simulation device 4 according to the embodiment of the present invention, the register write access information generation unit 21, the register write access information recording unit 31, the data hazard detection / execution machine cycle number calculation unit 22, and the execution in the ISS simulation device. By providing the machine cycle number information storage unit 32, it is possible to record the register write access time and the read prohibition period (the number of pipeline stall cycles), without having to implement the pipeline stage. In addition, it is possible to determine (calculate) the detection of the data hazard and the number of execution machine cycles of each instruction in consideration of the delay due to the data hazard.

  As a result, according to the simulation device 4 according to the embodiment of the present invention, the operation of the processor can be simulated with a model that takes into account the delay due to the data hazard. For this reason, the problem mentioned in the nonpatent literature 1 can be solved.

  Further, according to the simulation apparatus 4 according to the embodiment of the present invention, since the pipeline stage is not provided, the problems mentioned in Non-Patent Document 2 can be solved and the simulation speed can be increased.

FIG. 1A is a diagram for explaining the technique described in Non-Patent Document 1. FIG. FIG. 1-2 is a diagram for explaining the technique described in Non-Patent Document 1. FIG. 1C is a diagram for explaining the technique described in Non-Patent Document 1. FIG. FIG. 2 is a diagram for explaining the technique described in Non-Patent Document 2, and is a schematic diagram of a pipeline stage. FIG. 3 shows a configuration of the simulation apparatus 4 according to the embodiment of the present invention. FIG. 4 shows the configuration of a computer as an environment in which the simulation apparatus 4 operates. FIG. 5 shows the configuration of the simulation engine unit 7. FIG. 6 is a flowchart showing the operation of the simulation engine unit 7.

Explanation of symbols

1 computer body,
2 input devices,
3 output device,
4 simulation equipment,
5 User interface part,
6 Instruction data storage,
7 Simulation engine part (simulation program),
10 Instruction execution unit,
11 Instruction processing part,
13 execution cycle number measurement unit,
21 register write access information generator,
22 data hazard detection and execution machine cycle number calculation unit,
31 register write access information storage unit,
32 execution machine cycle number information storage unit,
60 execution result,

Claims (13)

A simulation device for simulating the operation of a processor,
A plurality of instructions that can be executed on the processor, an instruction execution unit that executes each of the plurality of instructions and performs processing according to the instructions;
And type of said plurality of instructions, when each of the plurality of instructions are executed, a first execution machine cycles expended when data hazard does not occur, when the data hazard occurs a storage unit and a second execution machine cycles are stored spent,
A recording section;
When said instruction is Ru value in the register by executing is written, reading the number of the first and second execution machine cycle to the instruction from the storage unit, on the basis of their pipeline stalls as a read inhibition period, A register for generating a cycle number and identifying the register; a register write access time when a value is written to the register; and a pipeline stall cycle number stored in the recording unit; ,
When the instruction is executed to read the value of the register and the register is subject to the data hazard, the register write access time and the pipeline for the instruction stored in the recording unit Calculating an execution machine cycle number for the instruction based on the stall cycle number and the second execution machine cycle number for the instruction, and when the instruction is executed and the value of the register is not read, or When the instruction is executed, the value of the register is read, and when the register is not subject to the data hazard, the number of machine cycles executed without hazard for the instruction is read from the storage unit, and the data hazard is to and a calculation unit for generating a data hazard no information indicating that do not occur Simulation equipment. The second execution machine cycle number is equal to or greater than the first execution machine cycle number;
The generating unit, from the second execution machine cycles for the instruction, by subtracting the number of the first execution machine cycle for the instruction, according to claim 1 that generates the number of pipeline stall cycles Simulation device. When the number of pipeline stall cycles is greater than 0, the calculation unit stores the register write access time and the number of pipeline stall cycles stored in the recording unit, and the second execution for the instruction. simulation device according to claim 2 that to calculate the number of the execution machine cycles on the basis of the number of machine cycles. The calculating unit, when said register is the subject of the data hazards, calculates the number of execution wait cycle based on the register write access time and the number of pipeline stall cycles stored in the recording unit the simulation apparatus according to claim 1 wherein by adding the execution wait cycle number to the second number of execution machine cycles for the instruction that generates the number of the execution machine cycles. The calculation unit calculates the number of waiting cycles by adding the number of cycles indicating the register write access time and the number of pipeline stall cycles when the register is the target of the data hazard. the simulation apparatus according to claim 4 wherein by adding the execution wait cycle number to the second number of execution machine cycles for the instruction that generates the number of the execution machine cycles. The instruction execution unit, if the register is the subject of the data hazards, the data hazard data hazard presence information indicating that occurs, it outputs the execution result including said execution machine cycles claims Item 6. The simulation device according to any one of Items 1 to 5. A simulation method for simulating the operation of a processor using a computer,
A plurality of instructions executable on the processor are provided, and each of the plurality of instructions is executed to perform processing according to the instructions ;
If the instruction is Ru value to be executed register is written with respect to the instruction, a first execution machine cycles expended when data hazard does not occur, when the data hazard occurs to read out a second execution machine cycles spent from the storage unit, based on the first and second number of execution machine cycles, and generates a number of pipeline stall cycles as read prohibited period, identifying the register Storing a register identifier, a register write access time when a value is written to the register, and the number of pipeline stall cycles in a recording unit;
When the instruction is executed to read the value of the register and the register is subject to the data hazard, the register write access time stored in the recording unit and the pipeline stall Calculating an execution machine cycle number based on the cycle number and the second execution machine cycle number for the instruction;
When the instruction is executed and the value of the register is not read, or when the instruction is executed and the value of the register is read and the register is not subject to the data hazard, the instruction Reading out the number of machine cycles executed when no hazard is generated from the storage unit, and generating no-hazard information indicating that no data hazard occurs . The second execution machine cycle number is equal to or greater than the first execution machine cycle number;
The step of generating the pipeline stall cycle number subtracts the first execution machine cycle number for the instruction from the second execution machine cycle number for the instruction to obtain the pipeline stall cycle number. simulation method according to claim 7 that generates. The step of calculating the number of execution machine cycles is, when the number of pipeline stall cycles is greater than 0, the register write access time and the number of pipeline stall cycles stored in the recording unit, simulation method according to <br/> claim 8 that to calculate the number of the execution machine cycles on the basis of the second execution machine cycles for the instruction. The step of calculating the number of execution machine cycles includes:
When the instruction is executed to read the value of the register and the register is subject to the data hazard, the register write access time stored in the recording unit and the pipeline stall Generating a number of waiting cycles based on the number of cycles;
Simulation method according to any one of claims 7-9, further comprising the step of generating the execution number of waiting the execution machine cycles by adding the number of cycles of the number of the second execution machine cycle for the instruction. The step of generating the number of waiting cycles is
When the instruction is executed, the value of the register is read, and the register is subject to the data hazard, the number of cycles indicating the register write access time, the number of pipeline stall cycles, To generate the number of cycles waiting for execution,
The simulation method according to claim 10. When the instruction is executed and the value of the register is not read, or when the instruction is executed and the value of the register is read and the register is not subject to the data hazard, the data a data hazard presence information indicating that the hazard occurs, the simulation method according to any one of claims 7 to 11, further comprising the steps of outputting the execution result including said execution machine cycles.   The computer program which makes a computer perform each step of the simulation method in any one of Claims 7-12.

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