JP5115360B2 - AD conversion circuit and receiving circuit - Google Patents

Description

  The present invention is an AD (analog-digital) used in a high-speed transmission / reception system that performs signal transmission between a plurality of circuit blocks in a chip, signal transmission between LSI chips, signal transmission between boards or between cases. The present invention relates to a conversion circuit and a reception circuit including such an AD conversion circuit.

  High-speed AD conversion circuits are widely used. Although there are various types of AD conversion circuits, a flash type is generally used as one of AD conversion circuits that can be used for high-speed signal transmission of gigabit / second.

FIG. 1 is a diagram showing a basic configuration of a flash AD converter circuit. As shown in FIG. 1, the flash type AD converter circuit includes a resistor string (ladder resistance) between a high-side reference potential VrefH output from the VrefH generation circuit 11 and a low-side reference potential VrefL output from the VrefL generation circuit 12. 13 is provided to generate a plurality of reference voltages obtained by dividing the reference potential at the connection node of the resistors. The plurality of comparators 14 respectively compare the voltage (input voltage) Vi of the input signal and each reference voltage. If Vi is lower than a certain reference voltage, the output of the comparator on the higher side than the comparator 14 to be compared with the reference voltage is “0”, and the output of the lower side comparator including the comparator 14 is “1”. When the outputs of a plurality of comparators 14 are encoded by an encoder 15 in the form of a thermometer, binary-format output data corresponding to the level of Vi can be obtained. In the case of an N-bit AD converter circuit, 2 ^N -1 comparators are required. For example, a 5-bit AD converter circuit outputs a code representing 32 levels and requires 31 (2 ⁵ -1) comparators. In FIG. 1, the first and final reference voltages are the reference potentials output from VrefL12 and VrefH11. However, resistors are provided between VrefH11 and VrefL12 at both ends of the ladder resistor 13 to provide the first and final reference voltages. The reference voltage may be different from the reference potential output by VrefL12 and VrefH11. Although not shown, the comparator 49 includes an amplifier as will be described later. Non-Patent Document 1 describes the configuration of an encoder of an AD conversion circuit.

  FIG. 2 is a diagram showing an example of use of a high-speed flash AD conversion circuit, and shows a schematic configuration of a high-speed signal transmission system. As shown in FIG. 2, the signal transmission system includes a transmission circuit 51, a transmission line 52, and a reception circuit 53. In the transmission circuit 51, low-speed parallel data is converted to serial data by a multiplexer (MUX) 61, and serial data is output to the transmission line 52 by a driver (Driver) 62 having the same output impedance as the characteristic impedance of the transmission line 52. To do. The serial data is input to the receiving circuit 53 via the transmission line 52. The input reception waveform received by the reception circuit 53 is deteriorated due to the characteristics of the transmission line 52. Specifically, the high frequency component is lost and the waveform becomes dull.

  The data to be transmitted is binary data of “0” and “1”, and when the deterioration in the transmission line 52 is small, input to the serial data indicated by the columns of “0” and “1” on the lower side The received waveform is a signal waveform as shown in FIG. With this received signal waveform, the received data can be correctly reproduced by setting the threshold level to the level indicated by the broken line and determining with the comparator.

  However, when the transmission line 2 is long or when the frequency (data rate) of transmission data becomes very high, the deterioration in the transmission line 52 becomes large, and the rows of “0” and “1” are on the lower side. The input reception waveform for the serial data shown is a reception signal waveform as shown in FIG. In the case of such a received signal waveform, the received data cannot be correctly reproduced if it is determined by one comparator. Therefore, as shown in FIG. 3B, the signal level is detected according to the clock of the received data, and the data received therefrom is reproduced correctly.

  Therefore, as shown in FIG. 2, the receiving circuit 53 samples the received signal (analog waveform) by the AD conversion circuit (ADC) 71 arranged in the input portion and digitizes it. The equivalent circuit (EQ) 72 performs waveform shaping (equalization processing) on the output of the AD conversion circuit 71 so as to compensate for waveform deterioration due to the transmission line. The equalizer circuit is described in Patent Document 1 and the like. The shaped received data is determined to be 0/1, and the determination result is converted from serial data to parallel data by a latch (Decision Latch) and a demultiplexer (D / L DMUX) 73. A clock signal is required for sampling in the AD conversion circuit 71 and processing in the equalization circuit 72. A clock recovery circuit (CRU) 74 recovers a data clock from the received data output from the equalization circuit 72. Note that the CRU 74 is also provided in the receiving circuit described below, but the description and illustration are omitted for the sake of simplicity.

  In order for the equalization circuit 72 to perform equalization correctly, the AD conversion circuit 71 needs to have an appropriate input signal range (input quantization range), operation speed, and resolution (number of bits). . Therefore, a peak / bottom detection circuit for detecting the maximum value (peak value) and minimum value (bottom value) of the voltage of the signal waveform (analog signal) received by the reception circuit 53 is provided, and the AD conversion circuit VrefH generation circuit of FIG. 11 and the voltage generated by the VrefL generation circuit 12 are adjusted so that the entire voltage range of the input signal can be quantized.

  On the other hand, the operation speed and resolution of the AD converter circuit, in other words, the slew rate and the number of bits of the AD converter circuit are set according to the application. For example, in the application of the signal transmission system as shown in FIG. 2, the data rate is defined respectively, and it is common to design or select an AD conversion circuit having an optimum slew rate and number of bits for each application. . Specifically, considering the signal waveform of the transmission circuit, the frequency characteristics (impulse response characteristics) of the transmission line, the sensitivity of the AD converter circuit, the loss compensation performance (achieved SNR) of the equalization circuit, the data rate is determined by simulation. Generally, an AD conversion circuit having an appropriate slew rate and number of bits is selected based on a simulation result.

As shown in FIG. 1, the flash type AD converter circuit has a larger number of comparators than other types of AD converter circuits having the same number of bits, and if n bits are used, about 2 ⁿ -1 comparators are required. It is. For example, in the case of 5 bits, 31 comparators are required. The relationship between the number m of comparators and the number n of bits in the flash AD converter circuit is expressed by the following equation (1).

n = log (m + 1) / log2 (1)
In the conventional flash type AD converter circuit, the resolution of the corresponding number of bits is obtained by using the provided comparator to the maximum. That is, the number of comparators and the number of bits have a relationship represented by Expression (1).

  In addition, it is possible to obtain a resolution higher than the number of bits corresponding to the number of comparators by switching the range of reference voltages generated in the AD converter circuit at different times. In other words, the resolution is improved by time division. The number of bits n ′ obtained in this case is larger than the above n. That is, n '> n.

  Patent Document 2 describes an AD converter circuit that reduces the influence of noise by performing a plurality of determinations at different times and coding based on the determination results of a plurality of times. In other words, Patent Document 2 describes a method for improving resolution by time division.

  In Patent Document 3, multiple sets of load MOSFETs are provided at the drains of the differential MOSFETs constituting the comparator of the flash AD converter circuit, and the outputs of the front and rear comparators are applied to the gates of the multiple sets of load MOSFETs, thereby averaging. Describes an AD conversion circuit with higher performance. Patent Document 3 also describes that dummy comparators are provided on both sides of the comparator row. However, since the reference voltage outside the detection range is applied to the dummy comparator, the output is always constant and does not substantially operate as a comparator. . Therefore, in the flash type AD converter circuit described in Patent Document 3, the number of comparators that substantially operate as comparators excluding the dummy comparator and the number of bits of the AD converter circuit satisfy the above formula (1).

  Patent Document 4 describes an AD conversion circuit that can set the quantization width of each level from the outside.

Japanese Patent Laid-Open No. 2000-22240 Japanese Patent Laid-Open No. 6-112825 JP 2004-194138 A JP 2002-217733 A Syed Masood Ali, Rabin Raut, Mohamad Sawan "Digital Encoders for Gigh Speed Falsh-ADCs: Modeling and Coparison" 1-4244-0417-7 / 06 IEEE

  As described above, the number of bits n of output data and the number of comparators m of the n-bit flash AD converter circuit substantially satisfy the above formula (1).

  However, in recent years, the signal voltage has decreased, the number of bits of the AD converter circuit has increased, and the quantization width has become very small. For this reason, the requirements for the accuracy of the ladder resistor that generates the reference voltage and the accuracy of the comparator are becoming strict.

  In the flash type AD converter circuit of the embodiment, the number of the plurality of comparators is larger than the number obtained by subtracting 1 from the number of voltage levels represented by the output data, and the arithmetic circuit outputs at least a part of the voltage level of the signal. It is determined based on the comparison result of the comparator.

  In the flash type AD converter circuit of the embodiment, since there are more comparators than the number required to determine the number of voltage levels represented by the output data, at least some of the levels are set to each level. Judgment is made based on judgment results of a plurality of comparators. Thereby, the accuracy of determination for at least some levels can be improved, and the accuracy of AD conversion processing can be improved.

  Hereinafter, embodiments will be described with reference to the accompanying drawings.

  FIG. 4 is a diagram illustrating a configuration of the AD conversion circuit according to the first embodiment. The AD converter circuit of the first embodiment converts the voltage of the analog signal Vi into N-bit digital data. As is clear from the comparison with the conventional flash type AD converter circuit of FIG. 1, in the AD converter circuit of the first embodiment, the columns of the comparators 14 of the conventional example include comparator units 21-1,. The other parts (VrefH generation circuit 11, VrefL generation circuit 12, ladder resistor 13 and encoder 15) are the same as in the conventional example. Accordingly, the ladder resistor 13 generates m reference voltages.

  Each comparator unit 21 includes three comparators 22 and a level value determination circuit 23 that determines the level value from the determination results of the three comparators 22.

  The three comparators 22 compare the same reference voltage with the signal voltage Vi and output the comparison results. Therefore, in the comparator unit 21 whose reference voltage is sufficiently smaller than the signal voltage Vi, all the three comparators 22 output a logical value 0, and in the comparator unit 21 whose reference voltage is sufficiently larger than the signal voltage Vi, three comparators are output. 22 all output a logical value of 1. In the comparator unit 21 whose reference voltage is close to the signal voltage Vi, there may occur a case where the outputs of the three comparators 22 are different due to noise or a difference in characteristics of the three comparators 22.

  The level value determination circuit 23 selects the outputs of the three comparators 22 by majority logic. For example, if all the outputs of the three comparators 22 are 0, 0 is used. If all the outputs are 1, 1 is used. If 2 outputs are 0 and 1 output is 1, 2 is used. 1 is output and one output is 0, 1 is output. Therefore, in the comparator unit 21 whose reference voltage is sufficiently smaller than the signal voltage Vi, all the three comparators 22 output the logical value 0, and therefore the level value determination circuit 23 outputs 0. In the comparator unit 21 whose reference voltage is sufficiently larger than the signal voltage Vi, all the three comparators 22 output a logical value 1, so that the level value determination circuit 23 outputs 1. In the comparator unit 21 whose reference voltage is close to the signal voltage Vi, the outputs of the three comparators 22 may be different. In this case, the larger output is selected and output. For example, the level value determination circuit 23 adds the outputs of the three comparators as 2-bit “00” or “01” data, and then shifts and divides by 1 bit (the upper 1 bit of 2 bits is divided). (Selectable) circuit.

  For example, even when the determination result of one comparator 22 changes due to noise, the remaining two comparators 22 output correct determination results, so that correct determination results can be obtained. Even if the characteristics of one comparator 22 differ from the characteristics of the other two comparators 22 due to manufacturing errors or the like, the two comparators 22 output the correct determination results, so that the correct determination results can be obtained. it can. In other words, in this embodiment, the accuracy of the determination operation with respect to the reference voltage is improved by redundantly processing the determination results of the three comparators 22.

  Since the determination result output from each comparator unit 21 is 0 or 1 as in the conventional example, the encoder 15 of the conventional example as described in Non-Patent Document 1 can be used as the encoder 15.

  FIG. 5 is a diagram illustrating a configuration of the AD conversion circuit according to the second embodiment. The AD converter circuit according to the second embodiment includes three sets of determination units and level value determination circuits 23-1,..., 23-m-1, 23 that determine the determination results of each level output from the three sets of determination units. -M and the encoder 15. Each determination unit includes VrefH generation circuits 11-1, 11-2, and 11-3, VrefL generation circuits 12-1, 12-2, and 12-3, and ladder resistors 13-1, 13-2, and 13-3. And columns of comparators 14-1, 14-2, 14-3. In other words, each determination unit has a portion excluding the encoder 15 in the conventional AD conversion circuit of FIG. The level value determination circuit determines the determination result of each level output from the three comparators, and the determined result is encoded by the encoder 15. As in the first embodiment, the level value determination circuit according to the second embodiment selects the determination result of each level of the comparator by majority logic. The encoder 15 is the same as that of the conventional example and the first embodiment.

  In the first embodiment, a common reference voltage is supplied to the three comparators 22 of each comparator unit 21. Therefore, although the determination result of the comparator 22 is redundantly processed, the accuracy of AD conversion processing cannot be improved when noise occurs in the reference voltage or there is an error in the reference voltage. On the other hand, in the second embodiment, since the reference voltage is generated independently, the accuracy of AD conversion processing can be improved even when noise occurs in the reference voltage or there is an error in the reference voltage. .

  FIG. 6 is a diagram illustrating a configuration of the AD conversion circuit according to the third embodiment. The AD converter circuit of the third embodiment has four AD converter circuits (ADC) 31-1, 31-2, 31-3, 31-4 having the same configuration as the conventional AD converter circuit shown in FIG. A reference voltage VrefH1, VrefL1, VrefH2, VrefL2, VrefH3, VrefL3, VrefH4, and VrefL4 that generate reference reference voltages VrefH1, VrefL1, VrefH2, VrefH4, and VrefL4 to be supplied to the four ADCs. In this example, the ADCs 31-1, 31-2, 31-3, and 31-4 output 3-bit data indicating eight levels, and are described as having seven comparators inside. However, it is not limited to a 3-bit ADC.

  The VrefH generation circuit 11 and the VrefL generation circuit 12 of each ADC output the reference reference voltage supplied from the Vref generation circuit 32 to the ladder resistor as it is.

  The AD conversion circuit of the third embodiment has first to third states. In the first state, the reference reference voltages VrefH1, VrefL1, VrefH2, VrefL2, VrefH3, VrefL3, VrefH4, and VrefL4 supplied to the four ADCs are all different and supplied to 4 × 7 = 28 comparators of the four ADCs. It is determined whether the input signal voltage Vi is any of 29 levels by making all the reference voltages to be different. The output at this time identifies 29 levels, and performs a 4.7-bit ADC operation from the equation (1). In the second state, VrefH1 = VrefH2, VrefL1 = VrefL2, VrefH3 = VrefH4, VrefL3 = VrefL4, the same reference reference voltage is supplied to each of the two ADCs, and the reference voltage supplied to each of the 14 sets of comparators is different. Thus, it is determined whether the input signal voltage Vi is any of 15 levels. The output at this time identifies 15 levels, and performs a 3.9-bit ADC operation from the equation (1). In the third state, VrefH1 = VrefH2 = VrefH3 = VrefH4, VrefL1 = VrefL2 = VrefL3 = VrefL4, the same reference reference voltage is supplied to the four ADCs, and the reference voltages supplied to the seven sets of comparators are changed four by four. Then, it is determined whether the input signal voltage Vi is any of 8 levels. The output at this time identifies 8 levels, and performs a 3-bit ADC operation from the equation (1).

  FIG. 7 is a diagram showing the configuration of the arithmetic circuit 37. As illustrated, the arithmetic circuit 34 adds the 3-bit output data output from the three ADCs 31-1, 31-2, 31-3, 31-4, and outputs 5-bit data. And a divider 36 that divides the output data of the adder 35 by shifting by 1 bit or 2 bits, and a selector 37 that selects the output data of the adder 35 or the output data of the divider 36. The divider 36 selects whether to shift 1 bit or 2 bits according to the control signal from the control circuit 33. The selector 37 switches between selecting output data from the adder 35 and selecting output data from the divider 36 in accordance with a control signal from the control circuit 33.

  FIG. 8 is a diagram illustrating reference voltages generated in the Vref generation circuit 32 and each ADC in the third embodiment. In the first state (when 4.7-bit operation), levels 1, 2, 3, and 4 are supplied as VrefL1, VrefL2, VrefL3, and VrefL4, and levels 25, 26, 27, and 28 are supplied as VrefH1, VrefH2, VrefH3, and VrefH4. The The VrefH generation circuit 11, the VrefL generation circuit 12, and the ladder resistor 13 of each ADC generate a seven-level reference voltage by equally dividing the supplied high-side reference voltage and low-side reference voltage. Therefore, the first ADC 31-1 generates reference voltages of levels 1, 5, 9, 13, 17, 21, 25, and the second ADC 31-2 generates reference voltages of levels 2, 6, 10, 14, 18, 22, 26. The third ADC 31-3 generates reference voltages of levels 3, 7, 11, 15, 19, 23, and 27, and the fourth ADC 31-4 generates levels 4, 8, 12, 16, 20, 24, and 28. Generate a reference voltage.

  For example, if the signal voltage Vi is between levels 19 and 20, that is, the 20th level, the output of the encoder 15 of the first ADC 31-1 is “101” (“00101” if it is 5 bits), and the second ADC 31− The output of the second encoder 15 is “101”, the output of the encoder 15 of the third ADC 31-3 is “101”, and the output of the encoder 15 of the fourth ADC 31-4 is “100”. When the adder 35 of the arithmetic circuit 34 adds these four pieces of output data, the result is “10011”, which indicates the 20th level.

  In the second state (during 3.9 bit operation), level 1 is supplied as VrefL1 and VrefL2, level 3 is supplied as VrefL3 and VrefL4, level 25 is supplied as VrefH1 and VrefH2, and level 27 is supplied as VrefH3 and VrefH4. Therefore, the first ADC 31-1 and the second ADC 31-2 generate reference voltages of levels 1, 5, 9, 13, 17, 21, 25, and the third ADC 31-3 and the fourth ADC 31-4 have levels 3, 7, 11, Reference voltages 15, 19, 23, and 27 are generated.

  Similarly to the above, it is assumed that the signal voltage Vi is between levels 19 and 20, that is, the 20th level. This level is the 11th level in 15 levels represented by 3.9 bits. At this time, the output of the encoder 15 of the first ADC 31-1 and the second ADC 31-2 is "101", and the output of the encoder 15 of the third ADC 31-3 and the fourth ADC 31-4 is "101". When the adder 35 of the arithmetic circuit 34 adds these four output data, the result is “10100”, and when this is shifted by 1 bit, it becomes “1010”, indicating the eleventh level.

  In the third state (at the time of 3-bit operation), level 1 is supplied from VrefL1 to VrefL4, and level 25 is supplied from VrefH1 to VrefH4. Accordingly, the first ADC 31-1 to the fourth ADC 31-4 generate the reference voltages of levels 1, 5, 9, 13, 17, 21, 25.

  Similarly to the above, it is assumed that the signal voltage Vi is between levels 19 and 20, that is, the 20th level. This level is the sixth level in 8 levels represented by 3 bits. At this time, the output of the encoder 15 of the first ADC 31-1 to the fourth ADC 31-4 is "101". When the adder 35 of the arithmetic circuit 34 adds these four output data, the result is “10100”, and when this is shifted by 2 bits, it becomes “101”, indicating the sixth level.

  In the third state, since the 8 levels are determined by the determination results of the 28 comparators 22, the generation of the reference voltage and the determination operation of the comparators are redundantly processed, and the accuracy of AD conversion processing is improved.

  Even in the second state, since the 15th level is determined by the determination results of the 28 comparators 22, the generation of the reference voltage and the determination operation of the comparator are redundantly processed, and the accuracy of AD conversion processing is improved. Generally, when there are two determination results for one level, it cannot be determined by majority logic. However, as in the third embodiment, the determination can be made by adding the determination results by the adding circuit and dividing the addition results. In the second state, a redundancy effect can be obtained particularly when there is an error over two levels.

  The Vref generation circuit 34 of the third embodiment needs to supply a reference reference voltage as shown in FIG. 8 to each ADC according to the first to third states. FIG. 9 is a diagram showing a configuration of the Vref generation circuit 34 in the third embodiment.

  As shown in FIG. 9, the Vref generation circuit 34 includes a common VrefH generation circuit 41, a common VrefL generation circuit 42, a ladder resistor 43, and selection circuits 44-1 to 44-6. The ladder resistor 43 has nine resistors and generates ref1 to ref4 corresponding to the reference voltages of levels 1 to 4 and ref25 to ref28 corresponding to the reference voltages of levels 25 to 28. Since a resistor is provided between the generation location of ref1 and ref28 in the ladder resistor 43 and the output terminal of the common VrefL generation circuit 42 and the common VrefH generation circuit 41, the ref1 and ref28, the common VrefL generation circuit 42, and the common VrefH The output voltage of the generation circuit 41 is different. Therefore, the output voltages of the common VrefL generation circuit 42 and the common VrefH generation circuit 41 are set in consideration of the resistance values of the resistances at both ends of the ladder resistance. For example, the common VrefL generation circuit 42 is generally at the ground level.

  The selection circuit 44-1 selects ref2 in the first state, selects ref1 in the second and third states, and supplies the selected signal to the second ADC 31-2. The selection circuit 44-2 selects ref3 in the first and second states, selects ref1 in the third state, and supplies the selected signal to the third ADC 31-3. The selection circuit 44-3 selects ref4 in the first state, selects ref3 in the second state, selects ref1 in the third state, and supplies the selected signal to the second ADC 31-4.

  The selection circuit 44-4 selects ref26 in the first state, selects ref25 in the second and third states, and supplies the selected signal to the second ADC 31-2. The selection circuit 44-5 selects ref27 in the first and second states, selects ref25 in the third state, and supplies the selected signal to the third ADC 31-3. The selection circuit 44-6 selects ref28 in the first state, selects ref27 in the second state, selects ref25 in the third state, and supplies the selected signal to the second ADC 31-4.

  FIG. 10 shows a configuration example of the selection circuit 44-1. Ref1 is input as voltage 1 and ref2 is input as voltage 2, and a signal that becomes “0” in the first state and “1” in the second and third states is applied as a control signal. As a result, ref2 (voltage 2) is output in the first state, and ref1 is output in the second and third states. The other selection circuits have the same basic configuration, the input voltage and the control signal are different, and the selection circuits 44-3 and 44-6 have three inputs.

  As described above, in the third embodiment, four conventional general ADCs are used and can be switched to output data having a resolution of 4.7 bits, 3.9 bits, or 3 bits. When the number of bits is reduced, redundant processing is performed to improve the accuracy of AD conversion processing.

  In FIG. 6, the ADCs 31-1 to 31-4 are shown to be controlled by the control circuit 33. As will be described later, this is because the ADCs 31-1 to 31-4 are brought into an operation stop state by the control of the control circuit 33. In the third embodiment, the ADCs 31-1 to 31-4 are controlled. It is unnecessary.

  FIG. 11 is a diagram illustrating a configuration of an AD conversion circuit according to the fourth embodiment. The AD conversion circuit according to the fourth embodiment uses a 5-bit AD conversion circuit (ADC) having 31 comparators, performs a 5-bit AD conversion process for identifying 32 levels, and a 8-bit processing state. This is a circuit capable of switching a high-precision processing state in which 3-bit AD conversion processing for identifying a level is performed with high accuracy by redundant processing.

  As illustrated in FIG. 11, the AD conversion circuit according to the fourth embodiment includes an ADC 101, an arithmetic circuit 111, and a control circuit 118. The ADC 101 includes a comparator row 102 composed of 31 comparators, an adder 103 that adds the determination results of the 31 comparators, an encoder 104 that encodes the output of the adder 103, and a ref voltage generator that generates a reference voltage. Part 105. The comparator array 102 and the encoder 104 have the same configuration as that of the conventional example shown in FIG. 1, but the top three comparator arrays 102 are configured to output “0” in the high-precision processing state. The adder 103 calculates the number of comparators that output “1” by adding the values “0” or “1” output from each comparator of the comparator array 102.

  12A and 12B are diagrams showing the configuration of the ref voltage generator 105, where FIG. 12A shows the overall configuration, and FIG. 12B shows the configuration of the resistance segment. As shown in FIG. 12A, the ref voltage generation unit 105 includes seven reference voltages ref connected in series between a high-side voltage Vtop and a ground between a low-side voltage Vbottom and a high-side voltage Vtop. Resistance segments 121 and a ladder resistor 120 composed of four pieces (upper three pieces and one lower piece). Each resistance segment 121 includes four ladder resistors and three selectors 122. The voltage at the node of the first resistor is output to the first terminal. The first selector 122 selects the voltage at the first and second resistance nodes in the 5-bit processing state and outputs it to the second terminal, and selects the voltage at the first resistance node in the high-precision processing state. Output to the second terminal. The second selector 122 selects the voltage of the second and third resistance nodes in the 5-bit processing state and outputs them to the third terminal, and selects the voltage of the first resistance node in the high-precision processing state. Output to the third terminal. The third selector 122 selects the voltage of the third and fourth resistance nodes in the 5-bit processing state and outputs them to the fourth terminal, and selects the voltage of the first resistance node in the high-precision processing state. Output to the fourth terminal. Each output terminal of the resistor segment 121 supplies a reference voltage to a corresponding comparator in the comparator array 102.

  Accordingly, in the 5-bit processing state, 31 reference voltages ref1-ref31 having different voltages at equal intervals are supplied to the comparator array 102, and the same 5-bit AD conversion processing as in the conventional example is performed. In the high-precision processing state, seven reference voltages ref1, ref5, ref9, ref13, ref17, ref21, and ref25 are supplied to the first to 28th comparators so that the same reference voltage is provided four by four. In the high-precision processing state, the reference voltages ref29 to ref31 are supplied to the 29th to 31st comparators. However, in the high-precision processing state, the outputs of the 29th to 31st comparators are “0”. Since it is controlled, the reference voltage is not related to operation. In the high-precision processing state, eight levels are identified, and a redundant process is performed to identify the same level by combining four comparators.

  Note that the reference level to be selected in the high-precision processing state is not limited to the above example.

  The arithmetic circuit 111 includes a comparator row 112 having seven comparators, an encoder 114 that encodes the output of the comparator row 112, and a selector 117 that selects and outputs one of the output of the encoder 114 and the output of the ADC 101. And having. In each of the seven comparators in the comparator row 112, the data output from the ADC 101 is “00010” or more, “00110” or more, “01010” or more, or “01110” or more. Or “10010” or more, “10110” or more, or “11010” or more. The encoder 114 includes an adder 115 that adds the outputs of the seven comparators in the comparator row 112, and an encoder 116 that encodes the addition result of the adder 115.

  In the 5-bit processing state, the selector 117 selects the 5-bit output data of the ADC 101, and thus operates as a 5-bit ADC conversion circuit similar to the conventional example.

  In the high-precision processing state, the comparator array 112 outputs the level corresponding to the 5-bit output data of the ADC 101 in the form of 3 bits in the form of a thermometer code. Data is obtained and encoded and output.

  FIG. 13 is a diagram illustrating a configuration of an AD conversion circuit according to the fifth embodiment. The AD converter circuit according to the fifth embodiment is obtained by providing an arithmetic circuit provided outside the ADC 101 in the ADC 120 in the AD converter circuit according to the fourth embodiment, and a 5-bit AD conversion process for identifying 32 levels. This is a circuit that can be switched between a 5-bit processing state in which high-precision processing is performed and a high-precision processing state in which 3-bit AD conversion processing for identifying 8 levels is performed with high accuracy by redundant processing.

  As illustrated in FIG. 13, the AD conversion circuit 120 according to the fifth embodiment includes a comparator array 102 including 31 comparators, eight adders 121 that add four outputs of the 31 comparators, A comparator 122 that compares the outputs of the seven adders 121 with “010” or more; a selector 123 that selects one of the outputs of the lower seven adders 121 and the outputs of the comparator 122; An adder 124 that adds the output and the output of the highest-order adder 121, a ref voltage generation unit 125 that generates a reference voltage, and a control circuit 126 are included. The comparator array 102, the ref voltage generator 125, and the control circuit 126 are the same as those in the fourth embodiment.

  In the 5-bit processing state, the ref voltage generation unit 125 supplies 31 reference voltages ref <b> 1-ref <b> 31 having different voltages at equal intervals to the comparator array 102. The adder 121 adds four outputs from the 31 comparators and outputs the result. The highest-order adder 121 adds the outputs of the three comparators. Therefore, the outputs of the eight adders 121 indicate the number of “1” among the outputs of the four comparators. Since the selector 123 selects the output of the adder 121, the adder 124 receives 8 outputs obtained by adding 4 outputs of 31 comparators. That is, the adder 124 receives data indicating the number of “1” s from the outputs of the 31 comparators, adds them, and encodes them. In other words, 5-bit AD conversion processing is performed.

  In the high-precision processing state, the ref voltage generator 125 supplies the reference voltages ref1, ref5, ref9, ref13, ref17, ref21, and ref25 to the comparators in the comparator row 102 by four. The upper three comparators are controlled to output “0”. The adder 121 adds the determination results of the four comparators for the same reference voltage, that is, adds the number of outputs “1” out of the four, and outputs the result. The comparator 122 determines whether the output of each adder 121 is “10” or more and outputs a determination result. Therefore, when the determination result of two or more comparators is “1” for the same reference voltage, the output of the comparator 122 is “1”. In this way, the redundancy process is performed, and the determination accuracy is improved. Since the selector 123 selects the output of the comparator 122, the adder 124 receives the determination result of seven redundant processes. The adder 124 calculates and outputs the number “1” among the seven determination results. This is the result of 3-bit AD conversion processing.

  The AD converter circuits of the first to fifth embodiments described above can be used as the AD converter circuit (ADC) 71 of the receiving circuit of the signal transmission system shown in FIG.

  FIG. 14 is a diagram illustrating a configuration of a receiving circuit according to the sixth embodiment. The receiving circuit of the sixth embodiment has a configuration in which the AD converting circuit of the third to fifth embodiments is used as the ADC 71 as the AD converting circuit 71 of the receiving circuit 53. The ADC 71 of the receiving circuit according to the sixth embodiment includes an AD conversion circuit (ADC) 81, an arithmetic circuit 82, and a control circuit 85. For example, when the AD conversion circuit according to the third embodiment shown in FIG. 6 is applied, the ADC 81 is connected to the first to fourth ADCs 31-1 to 31-4 and the Vref generation circuit 32, and the arithmetic circuit 82 is connected to the arithmetic circuit 34. The control circuit 85 corresponds to the control circuit 33. When the AD conversion circuit of the fourth embodiment shown in FIG. 11 is applied, the ADC 81 corresponds to the ADC 101, the arithmetic circuit 82 corresponds to the arithmetic circuit 111, and the control circuit 85 corresponds to the control circuit 118. Furthermore, when the AD conversion circuit of the fifth embodiment shown in FIG. 13 is applied, the arithmetic circuit 82 is added to the adder 124, the control circuit 85 is set to the control circuit 126, and the ADC 81 is set to a portion other than the above in the ADC 120. Corresponding.

  As shown in FIG. 14, the control circuit 85 supplies different reference voltages to all of the comparators provided in the ADC 81 based on an external control signal from the outside (for example, a transmission circuit), and performs high-bit AD conversion processing. The ADC 81 and the arithmetic circuit 82 are controlled such that the same reference voltage is supplied to a plurality of comparators and the determination result is redundantly processed to perform high-precision AD conversion processing with improved processing accuracy. .

  For example, when transmitting data at a high bit rate, the transmission circuit generates an external control signal that instructs to perform AD conversion processing with a high number of bits, and the bit rate is low, but it is high due to noise and the like. When a highly accurate AD conversion process is required, an external control signal that instructs to perform a high precision AD conversion process is generated.

  FIG. 15 is a diagram illustrating a configuration of a receiving circuit according to the seventh embodiment. In the receiving circuit according to the sixth embodiment, the control circuit 85 performs control based on an external control signal, whereas in the receiving circuit according to the seventh embodiment, the control circuit 85 includes an error generated by the equalization circuit 72. The control is different based on the control signal generated according to the information, and the other parts are the same as in the sixth embodiment. The table 74 stores a control signal generated according to the error information. When the error information generated by the equalization circuit 72 is input, a corresponding control signal is generated.

  When affected by noise, the value of error information generated by the equalization circuit 72 increases. In such a case, the transmission circuit is instructed to reduce the bit rate, and a control signal that instructs to perform high-precision AD conversion processing is generated.

  In addition, the bit rate may be low and high-resolution AD conversion processing may not be required. In such a case, it is possible to reduce the power consumption by stopping the operation of a part of the comparator of the ADC 81. For example, when the ADC 81 has 31 comparators and can perform 5-bit AD conversion processing, the operation of the 24 comparators is stopped and the 3-bit AD conversion processing is performed. In addition, the bit rate may be a low-speed and 2-bit AD conversion process, but when the processing accuracy needs to be high, the operation of 19 comparators out of 31 is stopped, and 12 The four comparators are divided into three groups, and each level is determined by redundant processing with four comparators as described in the third to fifth embodiments.

  As described above, in order to stop the operation of the comparator, it is necessary to use a comparator capable of stopping the operation. As described above, the AD converter circuit according to the third embodiment illustrated in FIG. 6 is in a state where the four ADCs 31-1, 31-2, 31-3, and 31-4 are stopped from operation by the control circuit 33. To be able to. Therefore, if the AD converter circuit of the third embodiment is used, it is possible to put some of the comparators in an operation stop state. It is also possible to perform a redundancy process using a plurality of comparators among the remaining comparators with some of the comparators in an operation stop state. For example, when performing 3-bit AD conversion processing, one ADC is stopped, the same reference reference voltage is supplied to the remaining three ADCs, and each level is determined by three comparators. In this case, the redundant processing is performed.

  FIG. 16 is a diagram illustrating a configuration example of a comparator capable of stopping operation, where (A) is an overall diagram, (B) is a circuit diagram of an amplifier unit, and (C) is a circuit diagram of a comparator unit. .

  As shown in FIG. 16A, each comparator includes an amplifier unit 89 and a comparator 90. A predetermined number of such comparators are provided in the comparator array. The amplifier unit 89 and the comparator 90 operate in synchronization with the clock clk.

  As shown in FIG. 16B, each amplifier unit 89 inputs the signal voltage Vi and its inverted signal (for example, a signal inverted with respect to 1.5V) / Vi, the reference voltage ref and its inverted signal / ref as gate inputs. The differential signals a and / a are output. The difference signals a and / a are a </ a when Vi> ref, a> / a when Vi <ref, and the level relationship between a and / a is inverted with Vi = ref as a boundary.

  As shown in FIG. 16C, each comparator 90 receives the difference signals a and / a and generates an output corresponding to the level relationship between the difference signals a and / a.

  FIG. 17 is a diagram illustrating an example of a 4-bit encoder circuit described in Non-Patent Document 1 and suitable for use as an ADC encoder of a receiving circuit. This circuit counts and codes the number of “1” among the determination results of the 15 comparators. Detailed description of the circuit is omitted.

  FIG. 18 shows an amplifier unit 89 constituting each comparator, a clock buffer 93 for supplying the clock clk to the comparator unit 90, and a selector 94 for the signal voltage Vi to be supplied to the amplifier unit 89 in the comparator row. 93 shows a configuration in which the outputs of 93 and selector 94 can be fixed by a control signal ctrl. With such a configuration, each set of the amplifier unit 89 and the comparator unit 90 can be stopped.

  Although the embodiments have been described above, the described embodiments are merely examples, and it goes without saying that various modifications are possible. Each circuit element shown in the described embodiment can be applied to other embodiments, and various modifications can be made with respect to the number of bits, a reference voltage, a comparator, an adder (encoder), and the like.

  Regarding the above embodiment, the following additional notes are disclosed.

(Supplementary note 1) a reference voltage generating circuit for generating a plurality of reference voltages;
A plurality of comparators for comparing the voltage of the signal with any of the plurality of reference voltages;
An arithmetic circuit that calculates a comparison result of the plurality of comparators and generates output data indicating a voltage level of the signal,
The number of the plurality of comparators is greater than the number obtained by subtracting 1 from the number of voltage levels represented by the output data,
The AD converter circuit, wherein the arithmetic circuit determines at least part of the voltage level of the signal based on a comparison result of a first comparator and a second comparator of the plurality of comparators.
(Supplementary note 2) The AD converter circuit according to supplementary note 1, wherein the first comparator and the second comparator compare the voltage of the signal with a first reference voltage of the plurality of reference voltages.
(Supplementary Note 3) The AD conversion circuit according to Supplementary Note 2, wherein the arithmetic circuit includes a majority circuit that determines a comparison result of the first comparator and the second comparator by majority logic.
(Supplementary Note 4) The reference voltage generation circuit includes a switch circuit that switches the reference voltage supplied to the plurality of comparators,
The AD converter circuit according to appendix 1, wherein the number of voltage levels represented by the output data changes.
(Supplementary Note 5) The AD conversion circuit according to Supplementary Note 4, wherein the maximum value of the number of voltage levels represented by the output data is a number obtained by adding one to the number of the plurality of comparators.
(Supplementary note 6) The AD conversion circuit according to supplementary note 1, wherein a part of the plurality of comparators can be in an operation stop state.
(Supplementary note 7) The AD conversion circuit according to claim 1, wherein the AD conversion circuit according to claim 1, which receives a reception signal and outputs output data indicating a voltage level of the reception signal;
And an equalization circuit for equalizing the output of the AD conversion circuit.
(Supplementary Note 8) A control circuit is further provided for controlling the AD converter circuit so as to change the number of voltage levels represented by the output data.
8. The receiver circuit according to appendix 7, wherein the AD converter circuit changes the number of voltage levels represented by the output data to be output in accordance with the control of the control circuit.
(Supplementary note 9) The reception circuit according to supplementary note 8, wherein the control circuit controls the AD conversion circuit based on error information from the equalization circuit.

  The disclosed AD conversion circuit can be applied to any flash AD conversion circuit, and a reception circuit using the disclosed AD conversion circuit is a signal transmission system and a reception circuit used in such a signal transmission system. As long as it is applicable to anything.

It is a figure which shows the structure of a flash type AD converter circuit. It is a figure which shows schematic structure of a high-speed signal transmission system. It is a figure explaining deterioration of the received signal by transmission, and necessity of an AD converter. It is a figure which shows the structure of the AD converter circuit of 1st Embodiment. It is a figure which shows the structure of the AD converter circuit of 2nd Embodiment. It is a figure which shows the structure of the AD converter circuit of 3rd Embodiment. It is a figure which shows the structure of the arithmetic circuit of 3rd Embodiment. It is a figure explaining the reference voltage which generate | occur | produces in 3rd Embodiment. It is a figure which shows the structure of the ref voltage generation circuit which generates a reference voltage in 3rd Embodiment. It is a figure which shows the structure of the selection circuit provided in a ref voltage generation circuit. It is a figure which shows the structure of the AD converter circuit of 4th Embodiment. It is a figure which shows the structure of the ref voltage generation circuit which generates a reference voltage in 4th Embodiment. It is a figure which shows the structure of the AD converter circuit of 5th Embodiment. It is a figure which shows the structure of the receiver circuit of 6th Embodiment. It is a figure which shows the structure of the receiver circuit of 7th Embodiment. It is a figure which shows the structure of the comparator provided in AD conversion circuit (ADC) of a receiving circuit. It is a figure which shows the structure of the encoder used in 7th Embodiment. It is a figure which shows the structure of the comparator row | line | column which can be made into an operation stop state.

Explanation of symbols

11 VrefH generation circuit 12 VrefL generation circuit 13 Ladder resistance 14, 14-1, 14-2, 14-3 Comparator 15 Encoder 21-1, 21-m Comparator unit 31-1 to 31-4 AD conversion circuit 32 Vref generation circuit 33 control circuit 34 arithmetic circuit 35 adder 36 divider 37 selector 51 transmission circuit 52 transmission line 53 reception circuit 71 AD converter circuit (ADC)
72 Equalizer (EQ)

Claims (5)

A reference voltage generation circuit for generating a plurality of reference voltages;
A plurality of comparators for comparing the voltage of the signal with any of the plurality of reference voltages;
An arithmetic circuit that calculates a comparison result of the plurality of comparators and generates output data indicating a voltage level of the signal,
The number of the plurality of comparators is greater than the number obtained by subtracting 1 from the number of voltage levels represented by the output data,
The arithmetic circuit determines at least part of the voltage level of the signal based on a comparison result of a first comparator and a second comparator of the plurality of comparators ,
The reference voltage generation circuit includes a switch circuit that switches the reference voltage supplied to the plurality of comparators,
An AD conversion circuit characterized in that the number of voltage levels represented by the output data changes .   The AD converter circuit according to claim 1, wherein the first comparator and the second comparator compare the voltage of the signal with a first reference voltage of the plurality of reference voltages. The AD converter circuit according to claim 1, which receives a reception signal and outputs output data indicating a voltage level of the reception signal;
And an equalization circuit for equalizing the output of the AD conversion circuit. A control circuit for controlling the AD converter circuit so as to change the number of voltage levels represented by the output data;
The receiving circuit according to claim 3, wherein the AD conversion circuit changes the number of voltage levels represented by the output data to be output in accordance with control of the control circuit.   The receiving circuit according to claim 4, wherein the control circuit controls the AD conversion circuit based on error information from the equalization circuit.

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