JP5109420B2 - Liquid ejection head drive device and liquid ejection device - Google Patents

Description

  The present invention relates to a drive device for a liquid discharge head and a liquid discharge device.

  As a kind of ink jet recording system in which ink droplets ejected from nozzles of a recording head are attached to a recording medium to record images such as characters and photographs on the recording medium, a piezoelectric element associated with application of a drive signal voltage to the piezoelectric element A piezoelectric method is known in which displacement is transmitted to a pressure chamber filled with ink through a vibration plate so that ink droplets are ejected from a nozzle by pressure fluctuation in the pressure chamber.

  A driving apparatus for driving the piezoelectric recording head described above is an IC including an HV unit driven by a high voltage (for example, 40 V) to drive a piezoelectric element, and a logic unit including a logic circuit such as a shift register. However, the logic unit malfunctions due to the influence of noise generated by a logic power source (eg, 3.3 V) for driving the logic unit, or noise generated by the HV power source unit for driving the HV unit. The HV section may malfunction due to the influence of the above (latch-up).

  When the HV part is latched up, a large overcurrent flows through the HV part, so that the reference potential in the IC rises, resulting in a malfunction of the logic part. A malfunction of a logic unit including a logic circuit or the like such as a shift register interrupts or delays data transfer, leading to erroneous ink droplet ejection. Damage such as deterioration of the output image due to erroneous ejection of ink droplets must be minimized.

  In order to detect the malfunction of the recording head described above, Patent Document 1 loops back the output of the final stage of the shift register of the recording head driving device, and collates this with the signal input to the shift register. A technique for detecting a malfunction by determining whether or not both match is disclosed.

Patent Document 2 discloses a technique for detecting a malfunction by adding parity to print data recorded by a recording head and performing parity check on the output of a shift register.
Japanese Patent No. 3434410 JP-A-8-309974

  In recent years, the length of recording heads of inkjet printers has been increasing, and along with this, the number of ICs of driving devices mounted on the recording heads has also been increasing.

The present invention has been made in consideration of the above facts, and detects a malfunction at the time of data transfer of the drive device mounted on the recording head, and reliably detects errors with a simple configuration provided in the drive device. It is an object of the present invention to obtain a liquid ejection head drive device and a liquid ejection device capable of preventing ejection.

In order to achieve the above object, the invention according to claim 1 is a liquid ejection head drive for driving a liquid ejection head for ejecting recording droplets from a plurality of nozzles provided corresponding to each of the plurality of drive elements. A plurality of drive signal voltage generating means provided corresponding to each of the plurality of drive elements and generating a drive signal voltage applied to the corresponding drive element based on print data; and the plurality of drives A plurality of holding units corresponding to each of the signal voltage generating means are provided, the print data corresponding to the predetermined number of transfer data is transferred, and the print data corresponding to each of the plurality of holding units is held and held. transfer means for outputting the print data to the corresponding plurality of drive signal voltage generating unit has, in the transfer path end of said transfer means during the predetermined sampling period the print data after transfer Repeated cycles of view, wherein when the print data after transfer to the sampling period is zero whole, the malfunction of the transfer means is determined to have occurred all print data held in the plurality of holding portions And a signal output means for outputting a clear instruction signal for instructing a process to be cleared to the transfer means and restarting the next sampling period after outputting the clear instruction signal to the transfer means .

The invention according to claim 2 is the invention according to claim 1, wherein the transfer means is provided corresponding to each of the plurality of shift registers for transferring print data and the plurality of shift registers. And a plurality of latches for holding print data output from the shift register, wherein the signal output means outputs the clear instruction signal to both the plurality of shift registers and the plurality of latches. To do. According to a third aspect of the present invention, in the first or second aspect of the present invention, the signal output means starts counting when print data is input to the transfer means and is predetermined. The counter circuit is configured to end counting when the sampling period elapses. When the print data after transfer becomes 1 within the sampling period, the counter circuit is reset and starts the next counting operation. When the print data after transfer is all 0 within the sampling period, the clear instruction signal is output to the transfer means.

According to a fourth aspect of the present invention, there is provided a liquid discharge head that drives a liquid discharge head that discharges recording liquid droplets from a plurality of nozzles provided corresponding to each of the plurality of drive elements ; A liquid discharge apparatus comprising : the liquid discharge head driving device according to any one of the above items .

  According to the liquid ejection head drive device of the first aspect, the malfunction of the drive device mounted on the recording head at the time of data transfer is detected, and the simple configuration provided in the drive device ensures that the error is detected. There is an effect that discharge can be prevented.

Further, there is an effect that it is easy to re-drive the liquid discharge head after detecting the malfunction.

According to the liquid ejection device of the fourth aspect of the present invention, erroneous operation at the time of data transfer of the drive device mounted on the recording head is detected, and erroneous discharge is reliably prevented with a simple configuration provided in the drive device. There is an effect that can be.

  Hereinafter, an example of an embodiment of the present invention will be described in detail with reference to the drawings.

  FIG. 1 shows an internal structure of a liquid discharge head 10 of an ink jet printer apparatus according to the present invention. The liquid discharge head 10 is a long one provided with a number of nozzles, but the portions corresponding to the individual nozzles have the same structure, and FIG. 1 shows a single nozzle. Only the corresponding part is shown.

  As shown in FIG. 1, an ink tank 12 is provided in the liquid ejection head 10, and ink supplied through an ink supply path (not shown) is stored in the ink tank 12. The ink tank 12 is connected to the pressure chamber 16 via the supply path 14, and the pressure chamber 16 is filled with ink supplied from the ink tank 12 via the supply path 14. A part of the wall surface of the pressure chamber 16 is constituted by a diaphragm 16A, and a piezoelectric element 20 as a driving element according to the present invention is joined to the diaphragm 16A by bonding or the like.

  When a voltage (a driving signal voltage described later) is applied to the piezoelectric element 20, the diaphragm 16A vibrates due to the displacement of the piezoelectric element 20, and the vibration of the diaphragm 16A propagates in the pressure chamber 16 as a pressure wave. Thus, the ink in the pressure chamber 16 is ejected as ink droplets through the nozzle 18 that is in a continuous state with the pressure chamber 16.

  FIG. 2 shows a head drive unit 60 according to this embodiment. The head driving unit 60 is a part that drives a large number of piezoelectric elements provided in the liquid ejection head 10, and is built in the liquid ejection head 10. A large number of piezoelectric elements provided in the liquid ejection head 10 are driven by a plurality of head driving units 60 having the same configuration. That is, a large number of piezoelectric elements are divided into a predetermined number, and the predetermined number of piezoelectric elements are driven by one head driving unit 60.

  The head driving unit 60 includes a large number of driving signal voltage generation units 34 provided corresponding to the individual piezoelectric elements 20 of the liquid ejection head 10 and a large number of types of basic waveform data that generate a plurality of types of basic waveform data according to the amount of liquid droplets. Corresponding to basic waveform data generation / input circuit 62A for drops, basic waveform data generation / input circuit 62B for medium drops, basic waveform data generation / input circuit 62C for small drops, and basic waveform data generation / input circuit 62D for non-ejection Shift register groups 28A, 28B, 28C, and 28D that transfer a plurality of types of basic waveform data generated by the basic waveform data generation / input circuit to be supplied to each drive signal voltage generation unit 34, and input image data Based on this, the presence / absence of ink droplet ejection from each nozzle 18 and the amount of ink droplets to be ejected (large droplet / medium droplet / small droplet) are judged, and for large droplets, medium droplets, small droplets A selection data input circuit 66 for generating and outputting selection data for indicating which basic waveform data is to be selected from the basic waveform data for non-injection, and transferring the input selection data and individual drive signals Each voltage generation unit 34 includes a data transfer input unit 68 that holds corresponding selection data.

  In the present embodiment, the basic waveform data is data representing a basic waveform whose voltage level changes in two steps (a waveform that is a basis of the drive vibration voltage, see FIG. 3A as an example), and the corresponding basic waveform When the voltage level is low (eg, 0 (V)), the value is “0”, and when the voltage level is high (eg, VDD (V)), the value is “1”. The voltage level between the timing and the change timing is represented by binary values.

  Each basic waveform data generation / input circuit 62 stores the basic waveform data in the built-in memory, and reads and outputs the basic waveform data bit by bit from the built-in memory at a timing synchronized with a predetermined clock signal (for example, reading). If the bit value is “0”, the output voltage level is 0 (V), and if the bit value is “1”, the output voltage level is VDD (V)).

  In addition, two types of basic waveform data representing different basic waveforms are stored in the built-in memory of each basic waveform data generation / input circuit 62 (hereinafter, for convenience, one of the two types of basic waveform data is used as a basic waveform). Data A, the other is called basic waveform data B). As will be described later, two types of basic waveform data are respectively input to the individual drive signal voltage generation units 34, and the two types of basic waveform data are boosted to different voltage levels in the drive signal voltage generation unit 34, and after boosting By appropriately switching the basic waveform voltage that is selectively output as the drive signal voltage among the two types of basic waveform voltages, a drive signal voltage whose voltage level changes in three or more stages is generated. The waveform data represents different basic waveforms determined so as to obtain a drive signal voltage having a desired waveform (see FIGS. 3 (1) and 3 (2) as an example), and each basic waveform data is generated and input. The circuit 62 repeatedly reads and outputs the basic waveform data A and B stored in the built-in memory one bit at a time.

  The basic waveform data A and B are different from each other in each basic waveform data / input circuit 62. In the built-in memory of the large drop basic waveform data generation / input circuit 62A, a drive signal voltage having a waveform to be applied to the piezoelectric element 20 in order to eject ink drops (large drops) of a relatively large drop amount from the nozzles 18. Are stored as basic waveform data A and B for large droplets (see FIGS. 3A and 3B).

  In addition, in the built-in memory of the basic waveform data generation / input circuit 62B for medium droplets, driving of a waveform to be applied to the piezoelectric element 20 in order to eject ink droplets (medium droplets) having a medium droplet amount from the nozzle 18 is performed. The basic waveform data A and B for medium droplets (see FIGS. 3 (3) and (4)) for generating the signal voltage are stored and stored in the built-in memory of the basic waveform data generation / input circuit 62C for the small droplets. The basic waveform data A and B for droplets for generating a drive signal voltage having a waveform to be applied to the piezoelectric element 20 in order to eject a relatively small amount of ink droplet (small droplet) from the nozzle 18 (FIG. 3 (5), (6)) is stored.

  Further, in the built-in memory of the non-ejection basic waveform data generation / input circuit 62D, a drive signal voltage having a waveform to be applied to the piezoelectric element 20 in order to prevent ink sticking at the time of non-ejection when ink droplets are not ejected from the nozzle 18. Non-injection basic waveform data A and B (not shown) for generating

  Each drive signal voltage generator 34 corresponding to each piezoelectric element 20 is provided with selectors 64A and 64B. The input terminal of the booster circuit 36A is connected to the output terminal of the selector 64A and the input terminal of the booster circuit 36B. The ends are respectively connected to the output ends of the selector 64B.

  The basic waveform data A and B output from each basic waveform data generation / input circuit 62 are input to the shift register groups 28A to 28D, respectively. The shift register groups 28A to 28D include a shift register array A in which a large number of shift registers 30 provided corresponding to the individual drive signal voltage generation units 34 are connected in series, and individual drive signal voltage generation units. Each of the shift register arrays B is formed by connecting a large number of shift registers 32 corresponding to 34 in series. The basic waveform data A input to the shift register groups 28A to 28D bit by bit is input to the shift register array A, and the shift register array A is sequentially transferred in a cycle synchronized with a predetermined clock signal. Similarly, the basic waveform data B input bit by bit to the shift register group 28 is input to the shift register train B, and the shift register train B is sequentially transferred in a cycle synchronized with a predetermined clock signal.

  The output terminals of the individual shift registers 30 of the shift register array A are connected to the input terminals of the selectors 64A of the corresponding drive signal voltage generators 34, and the outputs of the individual shift registers 32 of the shift register array B are output. The ends are respectively connected to the input ends of the selectors 64B of the corresponding drive signal voltage generators 34. Accordingly, the basic waveform data A and B are respectively input to the individual drive signal voltage generators 34 at a timing shifted by one cycle of a predetermined clock signal.

  The booster circuit 36A generates the basic waveform voltage A by boosting the input basic waveform data A to a predetermined voltage level (voltage level 1). The booster circuit 36B generates the basic waveform voltage B by boosting the input basic waveform data B to a voltage level (voltage level 2) different from that of the booster circuit 36A. The output terminals of the booster circuits 36A and 36B are connected to the input terminal of the driver circuit 38, and the basic waveform voltages A and B generated by the booster circuits 36A and 36B are input to the driver circuit 38, respectively.

  The driver circuit 38 generates a drive signal voltage whose voltage level changes in three steps based on the input basic waveform voltages A and B, and applies the drive signal voltage to the piezoelectric element 20 (for example, FIGS. 3 (19) to (21)). See).

  The head drive unit 60 is provided with a selection data input circuit 66. Image data representing an image to be formed on the recording medium by ejecting ink droplets from each nozzle 18 of the liquid ejection head 10 is input to the selection data input circuit 66. The selection data input circuit 66 determines the presence / absence of ink droplet ejection from each nozzle 18 and the amount of ink droplets to be ejected (large droplet / medium droplet / small droplet) based on the input image data, Based on the result of the determination, any of the basic waveform data for large droplets, medium droplets, small droplets, and non-injection input to the selectors 64A and 64B for each drive signal voltage generator 34 is selected. Selection data for instructing whether to select basic waveform data (used for driving the piezoelectric element 20) is generated, and the generated selection data is sequentially selected in units of selection data corresponding to a single drive signal voltage generator 34. Output.

  A data transfer input unit 68 is connected to the output terminal of the selection data input circuit 66. The data transfer input unit 68 includes a large number of shift registers 70 provided corresponding to the individual drive signal voltage generation units 34 connected in series, and selection data (printing) sequentially output from the selection data input circuit 66. Data) according to the transfer clock, and connected to the output terminal of each shift register 70 of the shift register string, holds selection data output from the shift register 70, and controls the selectors 64A and 64B. It consists of a number of latches 72 that are input to the input terminals.

  In addition, the head drive unit 60 includes a malfunction detection unit 80 that monitors print data and detects the occurrence of malfunctions in the data transfer input unit 68. The input end of the malfunction detection unit 80 is connected to the output end of the data transfer input unit 68. Accordingly, the malfunction detection unit 80 is sequentially transferred with the data transfer input unit 68 and the print data output from the data transfer input unit 68. The malfunction detection unit 80 receives the print data delayed by the number of clocks corresponding to the number of registers (bit storage number) in the shift register row of the data transfer input unit 68 after the print data is input to the data transfer input unit 68. Is entered.

  An output terminal of the malfunction detection unit 80 is connected to a reset terminal of each of the plurality of shift registers 70 constituting the data transfer input unit 68, and resets a latch 72 that holds selection data output from each shift register 70. Connected to the terminal. Therefore, the malfunction detection unit 80 constantly monitors the print data. When the malfunction is detected in the data transfer input unit 68, a reset signal is output and the shift register 70 constituting the data transfer input unit 68 is output. A reset signal is input to each of the reset terminal and the reset terminal of the latch 72. As a result, the data held by the shift register 70 and the latch 72 is reset, and all the nozzles of the liquid ejection head 10 are in an ink non-ejection (non-ejection) state.

  The malfunction detection unit 80 includes a counter circuit 86 as shown in FIG. The counter circuit 86 is supplied with a print clock signal, a counter clock signal, and a print data signal indicating whether or not execution of the print cycle is permitted, and a carry-out (CO) signal. The print data is output from the selection data input circuit 66 within a period when the print clock is at a high level, that is, printing is permitted, transferred to the data transfer input unit 68, and input to the counter circuit 86. The carry-out signal output from the counter circuit 86 is a “reset signal” used for resetting data held by the shift register 70 and the latch 72.

  When the printing clock becomes high level, the counter circuit 86 starts counting in synchronization with the counter clock signal and counts up to a predetermined value. When the count up to the predetermined value is completed, the next count operation is started. Hereinafter, the period from the count start to the count end is referred to as a “sampling period”. In the counter circuit 86, when the print data signal becomes high level (= 1) during the sampling period, the counter is reset even during the sampling period, and the next counting operation is started.

  On the other hand, if the print data signal is always at the low level (= 0) during the sampling period, the carry-out (CO) signal is at the high level, and the reset signal is output to the data transfer input unit 68. Here, if the counter circuit 86 functions like a timer and the print data signal never becomes high (= 1) during the sampling period, a reset signal is output to the data transfer input unit 68.

  That is, the fact that the print data signal becomes high level during the sampling period is evidence that the data transfer input unit 68 is operating normally, and the counter is reset many times and the next counting operation is started. The Therefore, the printing operation is continued as it is. On the other hand, if the print data signal is always at a low level during the sampling period, there is a high possibility that the data transfer input unit 68 is not operating normally. The data is output to the data transfer input unit 68. As a result, all the nozzles of the liquid discharge head 10 are in an ink non-discharge (non-ejection) state.

  Even if the data transfer input unit 68 is operating normally, the print data signal may always be at a low level during the sampling period. In this case, the data held by the shift register 70 and the latch 72 Is reset, there is no change in the logic in which all the nozzles of the liquid discharge head 10 are in a non-ejection (non-ejection) state, so no problem occurs.

  FIG. 4B is a schematic diagram illustrating an example of the counter circuit 86. The counter circuit 86 includes a 512-bit counter that uses the output of the ring oscillation circuit 82 as a counter clock. The 512 BIT counter is provided with a reset terminal (reset terminal) to which print data is input, an output terminal (CO terminal), and a clock terminal (clk terminal) to which a counter clock signal is input. The reset terminal is connected to the end of the data transfer input unit 68, and the CO terminal is connected to the shift register 70 for transferring print data and the reset terminal of the latch 72. The clk terminal is connected to the ring oscillation circuit 82.

  The ring oscillation circuit 82 is a circuit in which a plurality of inverters 84 are connected in an odd number of stages, and uses the gate delay time of the inverter 84 to generate a rectangular wave serving as a counter clock signal. For example, if the transfer clock of the print data transfer shift register is 10 MHZ, the counter clock can have a rectangular waveform of 5 MHZ that is slower than the transfer clock. Further, for example, if the reset terminal is fixed at the low level, the 512BIT counter ends counting at 5MHZ × 512≈1 KHZ, and enters the next counting operation while setting the output signal of the CO terminal to the high level. That is, the sampling period is set to about 1 KHZ, and the reset signal is output once every about 1 KHZ.

  Next, the operation of this embodiment will be described. First, driving control of the liquid ejection head 10 by the head driving unit 60 will be described.

  In the head driving unit 60 according to the present embodiment, prior to ejection of ink droplets from the liquid ejection head 10, selection data is generated based on image data by the selection data input circuit 66 and sequentially output. The selection data sequentially output from the selection data input circuit 66 is transferred by the shift register string of the data transfer input unit 68 and held in the latch 72, whereby the selectors 64A and 64B of the corresponding drive signal voltage generation unit 34 are stored. Respectively.

  Further, the basic waveform data generation / input circuits 62A to 62D have the basic waveform data A and B (for large drops, for medium drops, for small drops, stored in the built-in memory at a timing synchronized with a predetermined clock signal. Any one of non-injection) is read out bit by bit and output sequentially. The basic waveform data A for large droplets, medium droplets, small droplets, and non-injections output from the basic waveform data generation / input circuits 62A to 62D are transferred by the shift register array A of the shift register groups 28A to 28D, respectively. Then, the signals are input to the selectors 64A of the individual drive signal voltage generators 34 at timings shifted by one cycle of a predetermined clock signal. The basic waveform data B for large droplets, medium droplets, small droplets, and non-injection output from the basic waveform data generation / input circuits 62A to 62D is transferred by the shift register row B of the shift register groups 28A to 28D. Each is transferred and inputted to the selector 64B of each drive signal voltage generator 34 at a timing shifted by one cycle of a predetermined clock signal.

  The selectors 64A and 64B respectively receive the basic waveform data for large drops, medium drops, small drops, and non-injections inputted from the basic waveform data generation / input circuits 62A to 62D via the shift register groups 28A to 28D. Among them, the basic waveform data instructed to be selected by the selection data input to the control signal input terminal from the selection data input circuit 66 via the data transfer input unit 68 is output to the booster circuits 36A and 36B.

  As a result, as shown in FIGS. 3 (19) to (21) as an example, based on the basic waveform data output from the selectors 64A and 64B, the signals are output via the booster circuits 36A and 36B and the driver circuit 38. The drive signal voltage applied to the piezoelectric element 20 has a waveform corresponding to the type of basic waveform data (large drop / medium drop / small drop / non-jet) output from the selectors 64A and 64B. The waveform of the drive signal voltage applied to each of the piezoelectric elements 20 depends on the selection data input to the selectors 64A and 64B of the individual drive signal voltage generators 34 corresponding to the individual piezoelectric elements 20. It is controlled independently every 20th. 3 (19) to 3 (21), for the piezoelectric element 1, the drive signal voltage of the waveform for the large droplet is generated and applied by selecting the basic waveform data for the large droplet, and the piezoelectric element 1 For the element 2, the basic waveform data for the medium droplet is selected and a drive signal voltage having the waveform for the medium droplet is generated and applied. For the piezoelectric element 3, the basic waveform data for the small droplet is generated. This shows a case where a drive signal voltage having a waveform for a droplet is generated and applied by selecting.

  Whether or not ink droplets are ejected from the individual nozzles 18 of the liquid ejection head 10 and the amount of ink droplets ejected depend on the waveform of the drive signal voltage applied to the corresponding piezoelectric element 20, and the individual nozzles 18. Since the size of the dots formed on the recording medium by the ink droplets ejected from the ink droplets depends on the droplet amount of the ink droplets ejected from the individual nozzles 18, the head driving unit 60 according to the present embodiment The size of dots formed on the recording medium by the ink droplets ejected from the individual nozzles 18 should be formed on the recording medium by switching the amount of ink droplets ejected from the individual nozzles 18. It is possible to realize dot diameter modulation that switches for each individual nozzle 18 (individual piezoelectric element) according to the image, and this dot diameter modulation improves the image quality of the image formed on the recording medium. It can be realized.

  Next, malfunction detection control by the head drive unit 60 will be described.

  As shown in FIG. 5, when the print clock becomes high level, a print cycle is started, and input of image data to the selection data input circuit 66 is started. The selection data input circuit 66 generates selection data, that is, print data based on the input image data, and sequentially outputs it to the data transfer input unit 68. The print data sequentially output from the selection data input circuit 66 is transferred bit by bit in synchronization with a transfer clock (not shown) by the shift register array of the data transfer input unit 68, and the counter circuit of the malfunction detection unit 80. 86.

  When the input of print data for the number of registers in the shift register row of the data transfer input unit 68 is completed, the print clock becomes low level and the print cycle is completed. Similarly, the print cycle 2 is started, and the next print data is output from the selection data input circuit 66, sequentially transferred by the data transfer input unit 68, and input to the counter circuit 86 of the malfunction detection unit 80.

  When the printing clock becomes high level, the counter circuit 86 starts counting in synchronization with the counter clock signal. As shown in FIG. 5, when a sampling period that is about twice as long as the print cycle is set, the counter circuit 86 causes a halfway through the sampling period when the print data signal becomes high level (= 1) during the sampling period. However, the counter is reset and the next counting operation is started. As shown in the figure, when the print data signal is always at the low level (= 0) during the sampling period, the carry-out (CO) signal is output. Becomes a high level, and a reset signal is output to the data transfer input unit 68. The same applies to the print cycles 3 and thereafter.

  In the above embodiment, the example in which the output of the ring oscillation circuit is used as the counter clock has been described. However, for generation of the counter clock signal, for example, another rectangular wave oscillation circuit such as an RC oscillation circuit can be used. In addition, a transfer clock can be used.

  In the above embodiment, the printing cycle and the sampling period are asynchronous. However, the printing cycle and the sampling period may be synchronized, for example, the sampling period is an integral multiple of the printing cycle.

  In the above-described embodiment, as a stop signal for stopping the output of print data, a clear instruction signal (reset signal) for instructing to execute a process of clearing (resetting) all the registers in the head driving unit 60. Although an example of outputting an error is described, an error occurrence signal indicating that an error has occurred is output to a control device on the main body side of an inkjet printer device (not shown), and a power supply device (not shown) that supplies power to the head driving unit 60 Output of print data can also be stopped by a process of outputting a power stop signal instructing stop of power supply.

It is sectional drawing which shows the internal structure of a liquid discharge head. It is a block diagram which shows schematic structure of a head drive part. It is a timing chart of the data (voltage) which flows through each part of a head drive part. It is a block diagram which shows schematic structure of a calculating part. 4 is a timing chart of a print clock signal, a counter clock signal, print data, and a carry-out signal.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Liquid discharge head 20 Piezoelectric element 28A, 28B, 28C, 28D Shift register group 30, 32 Shift register 34 Drive signal voltage generation part 36A, 36B Booster circuit 38 Driver circuit 60 Head drive part 62A Basic waveform data generation / input for large droplets Circuit 62B Basic waveform data generation / input circuit 62C for medium droplets Basic waveform data generation / input circuit 62D for small droplets Non-injection basic waveform data generation / input circuits 64A, 64B Selector 66 Selection data input circuit 68 Data transfer input unit 70 Shift Register 72 Latch 80 Malfunction detection unit 82 Ring oscillation circuit 84 Inverter 86 Counter circuit

Claims (4)

A liquid ejection head drive device for driving a liquid ejection head for ejecting recording droplets from a plurality of nozzles provided corresponding to each of a plurality of drive elements,
A plurality of drive signal voltage generating means provided corresponding to each of the plurality of drive elements and generating a drive signal voltage to be applied to the corresponding drive element based on print data;
A plurality of holding units corresponding to each of the plurality of drive signal voltage generating means are provided, print data corresponding to a predetermined number of transfer data is transferred, and print data corresponding to each of the plurality of holding units is held. Transfer means for outputting the held print data to the corresponding drive signal voltage generation means; and
In the transfer path end of said transfer means, when repeated cycles of monitoring during a predetermined sampling period the print data after transfer, the print data after transfer within the sampling period is zero whole, the transfer means A clear instruction signal for instructing a process of clearing all the print data held in the plurality of holding units is output to the transfer means, and the clear instruction signal is output to the transfer means. Signal output means for restarting the next sampling period later ;
A liquid ejection head drive device comprising: The transfer means includes a plurality of shift registers for transferring print data, and a plurality of latches provided corresponding to each of the plurality of shift registers and holding the print data output from the corresponding shift registers. ,
The signal output means outputs the clear instruction signal to both the plurality of shift registers and the plurality of latches;
The drive device of the liquid discharge head according to claim 1. The signal output means includes a counter circuit that starts counting when print data is input to the transfer means and ends counting when a predetermined sampling period elapses, and the counter circuit includes the sampling period. When the print data after transfer becomes 1, the counter is reset and starts the next counting operation. When the print data after transfer is all 0 within the sampling period, the clear instruction signal The liquid ejection head driving device according to claim 1, wherein the liquid ejection head is output to the transfer unit. A liquid discharge head for driving a liquid discharge head for discharging recording droplets from a plurality of nozzles provided corresponding to each of the plurality of drive elements ;
A drive device for a liquid discharge head according to any one of claims 1 to 3 ,
A liquid ejection device comprising:

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