JP5107395B2 - Display device - Google Patents

Description

  The present invention relates to a memory device. More specifically, the present invention relates to a memory element suitable for pixel driving of an active matrix display device. The present invention also relates to an active matrix display device in which such a memory element is formed in each pixel.

  An active matrix display device includes a row-like gate line, a column-like data line, and pixels arranged at a portion where the two intersect. Each pixel is formed with an electro-optical element typified by a liquid crystal cell and an active element such as a thin film transistor for driving the element. The thin film transistor has a gate connected to the gate line, a source connected to the data line, and a drain connected to the electro-optic element. An active matrix display device scans gate lines line-sequentially, and supplies an image signal (data) to a column-shaped data line accordingly, thereby displaying an image corresponding to the image signal on a pixel array. .

  In an active matrix display device, gate lines are scanned in sequence for each field, and video signals are supplied to data lines in accordance with the scanning. In the case of moving image display, since the screen is switched for each field, the data line needs to repeat charging / discharging of the video signal for each field. When driving a panel of an active matrix display device, most of the power consumption is spent on charging / discharging data lines.

  In order to suppress this amount of power consumption, it is effective to lower the image rewriting frequency (field frequency). However, it is well known that when the field frequency is lowered to 30 to 60 Hz or less, flicker called flicker occurs on the screen and the display characteristics deteriorate. Therefore, conventionally, as a means for saving power consumption without lowering the field frequency, a method of reducing the number of times of charging / discharging by providing a memory function in each pixel has been proposed. For example, there are descriptions in Patent Document 1 and Non-Patent Document 1 below.

Japanese Patent Laid-Open No. 11-52416

M.Senda et. Al. "Ultra low power polysilicon AMLCD with full integration" SID2002p790 SQ Liu, NJ Wu, and A. Ignatieva, Space Vacuum Epitaxy Center and Texas Center for Superconductivity, University of Houston, Houston, Texas 77204-5507 "Electric-pulse-induced reversible resistance change effect in magnetoresistive films", APPLIED PHYSICS LETTERS, VOLUME 76, NUMBER 19, 8 MAY 2000 Akihito SAWA, Takeshi FUJII1, Masashi KAWASAKI and Yoshinori TOKURA, "Colossal Electro-Resistance Memory Effect at Metal / La2CuO4 Interfaces" Japanese Journal of Applied Physics, Vol. 44, No. 40, 2005, pp. L1241-L1243

  When the input video signal does not change, such as when a still image is displayed, the data held in the memory function in the pixel continues to be displayed, reducing the number of times the data line is charged and discharged and reducing power consumption. Research is progressing.

  For example, in order to incorporate a memory function in a pixel of a liquid crystal panel, a method has been proposed in which SRAM memory elements are integrated in each pixel. However, SRAM memory devices use at least 6 transistors per bit. Therefore, in order to display 64 gradations of 6 bits per pixel, it is necessary to integrally form 6 × 6 = 36 transistors per pixel, and the effective opening area of the pixel is pressed accordingly. Since the pixel aperture area through which the backlight light necessary for display can pass is reduced, a bright screen cannot be obtained. Therefore, if a conventional memory element is incorporated in a pixel as it is, it is difficult to increase the number of bits, and restrictions are imposed on high-definition multi-gradation display, which is a problem to be solved.

  In Patent Document 1, an example using a ferroelectric is described as a method for realizing a memory function incorporated in a pixel. Since it is not necessary to form a circuit element such as a transistor in each pixel, there is no fear of squeezing the opening area, but a material suitable for a ferroelectric having a memory function is scarce and has not reached a practical level. When data is rewritten repeatedly, ferroelectric characteristics and insulation are likely to change, and it is said that it is difficult to ensure the reliability of the memory function.

In view of the problems of the prior art described above, the present invention aims to provide a display device of active matrix type elaborate viewing set ultra small memory device that can be incorporated into the pixel. In order to achieve this purpose, the following measures were taken. That is, a display device according to the present invention includes a row-shaped gate line, a column-shaped data line, and a pixel arranged at a portion where the two intersect, and the pixel includes an electro-optic element and a plurality of memory elements. The plurality of memory elements are provided corresponding to each bit of the multi-gradation data, and each memory element stores data corresponding to each bit of the multi-gradation data supplied from the data line and from the gate line. Data is read according to the supplied signal, the electro-optical element exhibits luminance according to the multi-gradation data read from the plurality of memory elements, and the memory element is electrically connected to the thin film transistor and the resistance change element. The thin film transistor includes a semiconductor thin film in which a channel region, an input end, and an output end are formed, and a gate electrode that overlaps the channel region through an insulating film. One conductive layer electrically connected to the end side, the other conductive layer electrically connected to the output end side, and between one conductive layer and the other conductive layer, applied to the input end A read time for reading data in response to a signal supplied from a gate line by a plurality of memory elements having at least one oxide film layer made of a material that changes between a low resistance state and a high resistance state according to a voltage is Each of the plurality of memory elements is different for each bit of the corresponding multi-gradation data, and the oxide film layer constituting the memory element is made of SiO _x , and one of the one conductive layer and the other conductive layer Is made of Si doped with impurities .

According to the present invention, the memory element comprises a parallel connection of a thin film transistor (TFT) and a resistance change element (ReRAM). Compared with the conventional SRAM, the circuit scale is greatly simplified and the size is reduced. Further, the life of the memory element can be extended by using the oxide film layer as SIO _x and one of the conductive layers as doped Si. A plurality of such miniaturized memory elements can be easily incorporated in a pixel, and a multi-bit memory can be incorporated in a pixel with a small area. Therefore, an active matrix display device capable of multi-gradation display with a practical pixel size can be realized.

  Since a multi-bit memory can be built in a pixel, it is possible to reduce power consumption required for charging / discharging data lines that occupy most of the panel power consumption other than the backlight. Accordingly, an active matrix liquid crystal display device panel that can be driven with low power consumption can be realized. By incorporating such a liquid crystal panel in a monitor of a portable device, not only can the battery charging interval be extended, but the battery volume can be reduced, and the portable device can be further miniaturized.

1 is a schematic circuit diagram showing a configuration of a first embodiment of a memory element and a display device according to the present invention. It is a schematic diagram which shows the structure and operation | movement of a resistance change element integrated in the memory element concerning 1st embodiment. It is process drawing which shows the manufacturing method of the display apparatus concerning 1st embodiment. It is process drawing which similarly shows a manufacturing method. It is process drawing which similarly shows a manufacturing method. It is process drawing which shows the manufacturing method of the display apparatus concerning 2nd embodiment. It is process drawing which similarly shows a manufacturing method. It is process drawing which similarly shows a manufacturing method. It is a graph which shows the relationship between the number of pixels and power consumption. It is a perspective view which shows the television set provided with the display apparatus concerning this invention. It is a perspective view which shows the digital still camera provided with the display apparatus concerning this invention. 1 is a perspective view illustrating a notebook personal computer including a display device according to the present invention. It is a schematic diagram which shows the portable terminal device provided with the display apparatus concerning this invention. It is a perspective view which shows the video camera provided with the display apparatus concerning this invention. It is a schematic diagram which shows the other structural example of the resistance change element integrated in a memory element. It is a schematic diagram which shows the structure of the resistance change element integrated in the memory element concerning 3rd embodiment. It is typical sectional drawing which shows the structure of the memory element concerning 3rd embodiment.

The best mode for carrying out the invention (referred to as embodiment) will be described below with reference to the drawings. The description will be given in the following order.
First embodiment
Second embodiment
Application form
Third embodiment

<First embodiment>
[overall structure]
FIG. 1 is a schematic view showing an embodiment of a memory element and a display device according to the present invention. This schematic diagram is a circuit diagram showing one pixel of an active matrix display device. The pixel 10 includes the memory element 1.

  As shown in the figure, the memory element 1 is composed of a thin film transistor (TFT) and a resistance change element (ReRAM) connected in parallel. The TFT has a semiconductor thin film in which a channel region and input and output ends (source and drain) located on both sides thereof are formed, and a gate electrode that overlaps the channel region via an insulating film and serves as a control end. The ReRAM includes one conductive layer connected to the input end side of the TFT, the other conductive layer connected to the output end side of the TFT, and at least one oxide film layer disposed between the two conductive layers. . When the TFT is in the OFF state according to the voltage applied to the control terminal (gate electrode), the ReRAM is switched between the low resistance state (LRS) and the high resistance state (HRS) according to the voltage applied from the input terminal. And the corresponding binary data is written. In the illustrated example, parallel connection of TFT and ReRAM is connected in series in a plurality of stages (1) to (6), and the voltage applied to the control terminal of each stage TFT is controlled to be written in the ReRAM in each stage. Read binary data.

  Next, the configuration of the display device will be described. The active matrix display device includes a row-like gate line GATE and a column-like data line SIG, and pixels 10 arranged at a portion where the two intersect. The figure shows only one pixel 10. The pixel 10 includes a memory element 1 and an electro-optical element. In the illustrated example, the electro-optical element is a liquid crystal cell LC. The liquid crystal cell LC is composed of a pixel electrode, a counter electrode, and a liquid crystal layer held between both electrodes. The counter electrode is connected to a common counter potential VCOM in all pixels, while the pixel electrode is connected to the memory element 1.

  The memory element 1 stores data supplied from the data line SIG and reads data in accordance with a signal supplied from the gate line GATE. The liquid crystal cell LC, which is an electro-optical element, exhibits a luminance corresponding to the stored data.

  As described above, the memory element 1 includes a parallel connection of a TFT and a ReRAM. The TFT has a semiconductor thin film in which a channel region and input and output ends (source and drain) located on both sides thereof are formed, and a gate electrode that overlaps with the channel region and serves as a control end through an insulating film. The ReRAM includes one conductive layer connected to the input end side of the TFT, the other conductive layer connected to the output end side of the TFT, and at least one oxide film layer disposed between the two conductive layers. . When the TFT is in an OFF state in accordance with a signal applied from the gate line GATE to the control terminal (gate electrode), the ReRAM has a high resistance state LRS and a high resistance in response to data applied from the data line SIG to the input terminal. It changes depending on the resistance state HRS, and this data is stored.

  In the present embodiment, the pixel 10 includes a plurality of memory elements (1) to (6) connected in series between the data line SIG and the liquid crystal cell LC. The memory elements (1) to (6) are time-divisionally controlled by a plurality of gate lines GATE1 to GATE6 corresponding to the memory elements (1) to (6), and multi-bit data corresponding to multiple gradations is written. . Further, the liquid crystal cell LC is driven in a time-sharing manner according to the written multi-bit data, thereby controlling the luminance of the liquid crystal cell LC in multiple gradations.

  With continued reference to FIG. 1, the operation of the display device will be described. The operation of the pixel 10 is roughly divided into a multi-bit data write operation and a multi-bit data read operation. In order to perform a writing operation, the pixel 10 includes a switch SW. This switch SW is also formed of a thin film transistor (TFT), and one current end is connected to the series connection of the memory elements 1, while a predetermined reference potential Vref is applied to the other current end. A control line Reset for writing is connected to the control end (gate electrode) of the switch SW.

  The pixel 10 uses a 6-bit memory in which six memory elements 1 are connected. Specifically, six ReRAMs are connected in parallel to each of the six TFTs. Each bit data is stored by switching each ReRAM between the high resistance state HRS and the low resistance state LRS. First, all ReRAMs are initialized to, for example, a high resistance state (HRS), and then bit data is written to the first memory element (1). Specifically, the gate line GATE1 is set to a low level (Lo) to close the TFT, while the gate lines GATE2 to GATE6 of the other memory elements (2) to (6) are all set to a high level (Hi). Turn on. Further, the write control line Reset is also set to the high level to turn on the switch SW. As a result, the ReRAM of the first memory element (1) is applied with bit data from the data line SIG on the input end side, and the reference potential Vref is applied to the output end via the subsequent TFT and SW in the on state. ing. When the bit data applied from the data line SIG is at a high level with respect to the reference potential Vref (in other words, when a positive signal voltage is applied), the ReRAM changes from the high resistance state HRS to the low resistance state LRS. Thereby, the bit data 1 is written into the memory element (1). Conversely, when a negative data voltage is supplied from the data line SIG, the ReRAM of the memory element (1) maintains the high resistance state HRS as it is. That is, when a negative signal voltage is applied, bit data 0 is written in the memory element (1).

  Subsequently, when writing bit data to the second memory element (2), the TFT of the memory element (2) is turned off, while the TFTs and SW of the remaining memory elements are all turned on. In this state, when a positive signal voltage (bit data 1) is applied from the data line SIG to the reference potential Vref, the ReRAM of the memory element (2) becomes LRS and the bit data 1 is written. Conversely, when the signal voltage supplied from the data line SIG is negative with respect to Vref (that is, when bit data 0 is supplied), the ReRAM of the memory element (2) maintains HRS and bit data 0 is written. That's right. In this manner, the bit lines corresponding to the memory elements (3) to (6) are sequentially written to the memory elements (3) to (6) by time-division control of the gate line GATE and the control line Reset. In this manner, by turning off the TFT of the memory element to which bit data is to be written while turning on the TFTs of the remaining memory elements, the bit data can be written to the target memory element.

  Next, a multi-bit data read operation (that is, a lighting operation of the pixel 10) will be described. In the read operation, the write switch SW is turned off. Thereby, the pixel 10 includes six memory elements (1) to (6) connected in series between the data line SIG and the liquid crystal cell LC. The memory elements (1) to (6) are controlled in a time-sharing manner by a plurality of gate lines GATE1 to GATE6 corresponding to the memory elements (1) to (6), and multi-bit data is read out accordingly. The liquid crystal cell is driven, and thus the luminance of the liquid crystal cell LC is controlled in multiple gradations. In the case of this embodiment, since six one-bit memory elements 1 are used, the luminance of the liquid crystal cell LC can be controlled to 2 6 = 64 gradations.

  Specifically, assuming that the read time of the first memory element (1) is one unit, the read time of the next memory element (2) is set to double. The read time of the third memory element (3) is four times that of the first memory element (1). In this way, the read time is sequentially doubled, and the read time of the last memory element (6) is 32 times that of the first memory element (1). Here, if binary data 1 is written in all of the memory elements (1) to (6), a driving current is supplied from the data line SIG side to the liquid crystal cell LC over the entire reading time, and the liquid crystal cell LC is turned on. I'm left. Conversely, when binary data 0 is written in all the memory elements (1) to (6), the driving current does not flow, and the liquid crystal cell LC is turned off. Between the all-lit state and the all-off state, the liquid crystal cell LC is divided into the on-state and the off-state for the time represented by the other bit data according to the multi-bit data written in the memory elements (1) to (6). It is done. In this way, the active matrix type display device drives the liquid crystal cell LC in a time-sharing manner according to the multi-bit data written in the memories (1) to (6) of each pixel 10, and thereby the liquid crystal cell LC. Can be controlled in multiple gradations.

  In order to explain the read operation of the memory element 1, a truth table is referred to. As shown in the figure, this truth table has the level of the gate line GATE in the horizontal column and the state of the ReRAM in the vertical column. When the signal applied to the gate line GATE is at the high level Hi, the TFT is in the on state. Therefore, regardless of the ReRAM state, the memory element 1 is in the conductive state and can supply the drive current. On the other hand, when the control signal of the gate line GATE is at the low level Lo, the TFT is in the off state. At this time, the conduction / non-conduction of the memory element 1 depends on the state of the ReRAM. That is, when the ReRAM is in the HRS, since the TFT and ReRAM connected in parallel are in a high resistance state (high impedance), the memory element 1 is turned off as a whole. Conversely, if the ReRAM is LRS, even if the TFT is off, the current flows through the low impedance ReRAM, so that the memory element 1 is on. From this, the memory element 1 reads the state written in the memory element 1 as the form of the driving current for the liquid crystal cell LC by setting the gate potential of the corresponding TFT to the low level (Lo). For example, when reading the bit data of the memory element (1), the gate line GATE1 is set to the low level Lo, while the remaining gate lines GATE2 to GATE6 are set to the high level Hi. In this way, depending on the OFF / ON state of the memory element (1), the current path between the liquid crystal cell LC and the data line SIG can be switched OFF / ON.

[Configuration example 1 of variable resistance element]
FIG. 2 is a schematic diagram illustrating a specific configuration example of the ReRAM. The low resistance state LRS of ReRAM is shown on the left and the high resistance state HRS is shown on the right. As shown in the figure, the resistance change element ReRAM includes a pair of conductive layers and at least one oxide film layer disposed therebetween. In the illustrated example, each of the pair of conductive layers is made of metal Pt, and two layers of metal oxide films PCMO and YBCO are formed therebetween. That is, in this example, the oxide film layer is made of a metal oxide. When a positive voltage of, for example, + 18V is applied to the upper Pt layer with reference to the lower Pt layer, the ReRAM becomes LRS. Conversely, when a negative voltage is applied to the upper Pt layer with reference to the lower Pt layer, the ReRAM switches from LRS to HRS.

  The lower side of FIG. 2 shows the electrical characteristics of ReRAM. In this graph, the horizontal axis represents the number of applied pulses, and the vertical axis represents electric resistance. This is a result of measuring electrical resistance appearing at both ends of a pair of Pt layers when a pulse having an amplitude of 18 V is applied while switching the polarity. As is apparent from the graph, the ReRAM switches between a low resistance state and a high resistance state depending on the polarity of the applied pulse. Moreover, the low resistance state and the high resistance state are maintained as they are even when the applied voltage is released. For example, when a positive pulse is applied and the ReRAM becomes LRS, the ReRAM maintains the LRS even after the applied pulse is released thereafter. Thereafter, when a negative pulse is applied, the ReRAM is switched from LRS to HRS for the first time. Thereafter, even if the applied pulse is released, the ReRAM holds the HRS.

  The ReRAM layer structure is not limited to the example shown in FIG. Thin film laminated resistance change elements include Pt / TiO / Pt, Pt / NiO / Pt, Pt / NiO / TiO / Pt, W / GdO / CuTe / W, Ag / PCMO / Pt, TiN / CuO / Cu, etc. Is mentioned.

[Manufacturing process]
A method for manufacturing a memory device according to the present invention will be described in detail with reference to FIGS. FIG. 3A is a manufacturing process diagram of a memory element, where a TFT manufacturing process is shown on the left side and a ReRAM manufacturing process is shown on the right side. TFTs and ReRAMs are integrated and formed simultaneously on the substrate 101 using a thin film process. In the present embodiment, the TFT has a bottom gate structure.

  First, in the first step A, a metal film 102 is formed on an insulating substrate 101 such as glass by a sputtering method, for example, by 90 nm. The metal film 102 is patterned into a predetermined shape and becomes a gate electrode of the TFT. Further, the metal film 102 is also secured on the ReRAM side so as to serve as a connection wiring. An insulating film 103 is formed so as to cover the patterned metal film 102. This insulating film 103 becomes a gate insulating film on the TFT side. The insulating film 103 has, for example, a two-layer structure of a silicon nitride film 50 nm and a silicon oxide film 50 nm, and is formed by CVD. Further, a semiconductor thin film 104 made of amorphous silicon is formed thereon by a plasma CVD method with a thickness of 50 nm. The gate insulating film 103 and the semiconductor thin film 104 are continuously formed by a plasma CVD method.

  Proceeding to Step B, the excimer laser is irradiated to convert the amorphous silicon thin film 104 into the polysilicon thin film 104.

  Proceeding to step C, an impurity is implanted into the polysilicon film 105 at a predetermined concentration to form a source region S and a drain region D. This impurity implantation is performed selectively, so that the impurity is not implanted into the portion of the polysilicon film 105 located immediately above the gate electrode to become the channel region CH. A low concentration impurity region (LDD) is formed between the channel region CH and the source region S. Similarly, an LDD is also formed between the channel region CH and the drain region D. Further, the implanted impurities are activated using an RTA apparatus. Subsequently, the polysilicon film 105 is patterned into an island shape to form a TFT element region. At this time, since the polysilicon film is unnecessary on the ReRAM side, it is completely removed. An interlayer insulating film 106 is formed over the entire surface so as to cover the bottom-gate TFT formed in this way. For example, a two-layer insulating film 106 made of a silicon oxide film 300 nm and a silicon nitride film 300 nm is formed by, for example, a plasma CVD method. Further, annealing at about 400 ° C. is performed to hydrogenate the polysilicon film 105.

  Subsequently, the process proceeds to step E in FIG. 3B, and the substrate 101 is entirely covered with the photoresist 110. The photoresist 110 is patterned by photolithography. The insulating films 103 and 106 are dry-etched through the patterned photoresist 110 to provide an opening on the ReRAM side. Further, while leaving the photoresist 110, metal, metal oxide, and metal are sequentially deposited to form a ReRAM 107 having a multilayer thin film structure in the opening. As is apparent from the drawing, the lower conductor film of the ReRAM is in contact with the metal wiring 102. The ReRAM 107 has a four-layer structure of Pt / PCMO / YBCO / Pt, for example, as shown in FIG.

  Proceeding to step F, the used photoresist 110 is removed. As a result, the stack of metal and metal oxide is lifted off from the substrate 101, and the ReRAM 107 remains only in the contact opened in the insulating film 106.

  Proceeding to step G, the insulating films 103 and 106 are again dry-etched using another photoresist to provide contact holes. On the TFT side, a contact hole communicating with the source region S and a contact hole communicating with the drain region D are opened in the interlayer insulating film 106. On the ReRAM side, an additional contact hole communicating with the metal wiring 102 is formed in the insulating films 106 and 103.

  Proceeding to Step H in FIG. 3C, a three-layer metal film to be a metal wiring is formed on the interlayer insulating film 106. This three-layer metal film has a structure of, for example, lower titanium 50 nm, middle aluminum 500 nm, and upper titanium 50 nm. This metal film is patterned into a predetermined shape to form wiring 108. On the TFT side, a wiring 108 connected to the source region S and a wiring 108 contacting the drain region D are formed. On the other hand, on the ReRAM side, a metal wiring 108 that contacts the upper conductive layer and a metal wiring 108 that connects to the lower conductive layer via the metal wiring 102 are formed. Here, the upper conductive layer of the ReRAM 107 is connected to a wiring 108 on the source S side of the TFT through a metal wiring 108. On the other hand, the lower conductive layer of the ReRAM is connected to the metal wiring 108 on the drain D side of the TFT via the metal wirings 102 and 108. In this way, the TFT and ReRAM are connected in parallel with each other. At that time, the TFT and the ReRAM are connected to each other via the wiring 102 in the same layer as the gate electrode. In other words, in this embodiment, the ReRAM and the TFT are electrically connected to each other on the same insulating substrate 101 by using a metal layer serving as a gate electrode for a part of wiring.

  Although not shown, after step H, an organic planarizing film is formed so as to cover the TFT and ReRAM. A contact communicating with the drain region D of the TFT is opened in the organic planarizing film. Thereafter, a transparent conductive film ITO is formed on the organic flattening film and processed into a predetermined shape to form a pixel electrode. This pixel electrode is connected to the drain D side of the TFT through a contact opened in the organic planarization film. In this manner, an active matrix display device in which a memory element composed of a parallel connection of TFT and ReRAM is incorporated in a pixel can be produced.

<Second embodiment>
[Manufacturing process]
A second embodiment of the method for manufacturing a display device according to the present invention will be described with reference to FIGS. In the present embodiment, a memory element is formed on the pixel side, and a memory element is also formed on the peripheral circuit side for driving the pixel. In the process diagrams of FIGS. 4A to 4C, the pixel part forming process is shown on the left side, and the peripheral circuit part creating process is shown on the right side. However, the pixel portion and the peripheral circuit portion are simultaneously formed on the insulating substrate using a semiconductor process. Unlike the previous embodiment shown in FIGS. 3-1 to 3-3, in this embodiment, a TFT having a top gate structure is formed.

  As shown in FIG. 4A, in the first step A, first, a buffer layer 202 and an amorphous silicon layer 203 are continuously formed on the insulating substrate 201 by plasma CVD. The amorphous silicon film 203 has a thickness of 50 nm, for example. The amorphous silicon film 203 is irradiated with an excimer laser to be converted into a polysilicon film 203.

  Proceeding to Step B, the polysilicon film 203 is covered with the gate insulating film 204. The gate insulating film 204 is made of, for example, a silicon oxide film or a silicon nitride film.

  Proceeding to Step C, a conductive film 205 is formed on the gate insulating film 204. The conductive film 205 is made of a refractory metal material or a conductive polysilicon film.

  Proceeding to step D, the conductive film 205 is patterned into a predetermined shape and processed into a gate electrode. As illustrated, the gate electrode 205 is formed in both the pixel region and the peripheral circuit region. Note that the left side of the insulating substrate 201 is a region where pixels are formed, and the right side is a region where peripheral circuits are formed. In order to clarify this, the center of the insulating substrate 201 is divided by a boundary line.

  Proceeding to step E in FIG. 4B, impurities are selectively implanted into the polysilicon film 203 through the insulating film 204 using the gate electrode 205 as a mask. Thereby, the source region S and the drain region D are formed in the polysilicon film 203. A channel region CH into which no impurity is implanted is formed immediately below the gate electrode 205. In addition, an LDD region into which impurities are implanted at a low concentration is provided between the channel region CH and the source region S. An LDD region is also provided between the channel region CH and the drain region D. In this manner, the TFTs having the top gate structure are integrally formed on the element region side and the peripheral circuit region side of the insulating substrate 201. The polysilicon film 203 is patterned into an island shape in accordance with the shape of the element region of each TFT.

  Proceeding to Step F, the TFT is covered with the interlayer insulating film 206. The interlayer insulating film 206 is formed of, for example, a laminate of a silicon oxide film 300 nm and a silicon nitride film 300 nm, and is formed by a plasma CVD method. Subsequently, annealing is performed at about 400 ° C. to hydrogenate the polysilicon film 203.

  Proceeding to Step G, a photoresist 210 is applied on the interlayer insulating film 206 and patterned into a predetermined shape by photolithography. The interlayer insulating film 206 is dry-etched using the patterned photoresist 210 as a mask to open a contact hole. This contact hole communicates with the drain region D of the TFT. Further, a ReRAM 207 is formed in the contact hole by continuously forming a stack of a metal film and a metal oxide film with the photoresist 210 left. As shown in the drawing, the lower conductive layer of the ReRAM 207 is in contact with the drain region D of the TFT 205. The ReRAM 207 formed in the process G includes, for example, Pt / TiO / Pt, Pt / NiO / Pt, Pt / NiO / TiO / Pt, W / GdO / CuTe / W, Ag / PCMO / Pt, TiN / CuO / Cu. Etc.

  Proceeding to Step H, after removing the used photoresist 210, a new photoresist 210 'is applied. The photoresist 210 'is patterned by photolithography. Using the patterned photoresist 210 'as a mask, the interlayer insulating film 206 and the gate insulating film 204 are again dry etched to open a contact hole communicating with the source region S of the TFT.

  Proceeding to Step I in FIG. 4C, the used photoresist 210 ′ is removed, and then a metal film 208 is laminated on the interlayer insulating film 206. The metal film 208 has a laminated structure of, for example, a lower layer titanium 50 nm, a middle layer aluminum 500 nm, and an upper layer titanium 50 nm. This metal film is patterned into a predetermined shape to form a metal wiring 208. As shown in the figure, the upper conductive layer of the ReRAM is connected to the source region S of the TFT by the metal wiring 208. On the other hand, the lower conductive layer of the ReRAM 207 is in direct contact with the drain region D of the TFT. As described above, in this embodiment, the TFT and the ReRAM are connected to each other via the wiring (that is, the drain region D) in the same layer as the semiconductor thin film 203 in which the channel region CH is formed.

  On the same substrate 201, a memory element composed of a parallel connection of TFT and ReRAM is formed in the pixel area, and a memory element composed of a parallel connection of TFT and ReRAM is also formed in the peripheral circuit area. This peripheral circuit includes a drive circuit for driving a gate line and a data line formed on the pixel side. This drive circuit includes a memory element composed of the above-described TFT and ReRAM connected in parallel as a circuit element. This memory element is used, for example, for holding gradation data in the drive circuit.

  FIG. 5 is a graph showing the effect of the present invention. The horizontal axis represents the number of pixels, and the vertical axis represents power consumption. In the case of a panel having 120 × 60 pixels, the power consumption is about 20 mW if the pixel memory is not used. When a pixel memory is incorporated in this panel according to the present invention, the power consumption is 0.1 mW or less, and a large reduction in power consumption can be achieved, which is suitable for applications such as displays for portable devices. Similarly, even in a panel of 170 × 220 pixels, the power saving due to the use of the pixel memory is very large, and this is the same in the panel of the QVGA standard.

<Application form>
FIG. 6 shows a television to which the present invention is applied, which includes a video display screen 11 composed of a front panel 12, a filter glass 13, and the like, and is produced by using the display device of the present invention for the video display screen 11. .

  FIG. 7 shows a digital camera to which the present invention is applied, in which the top is a front view and the bottom is a rear view. This digital camera includes an imaging lens, a light emitting unit 15 for flash, a display unit 16, a control switch, a menu switch, a shutter 19, and the like, and is manufactured by using the display device of the present invention for the display unit 16.

  FIG. 8 shows a notebook personal computer to which the present invention is applied. The main body 20 includes a keyboard 21 operated when inputting characters and the like, and the main body cover includes a display unit 22 for displaying an image. This display device is used for the display portion 22.

  FIG. 9 shows a portable terminal device to which the present invention is applied. The left side shows an open state and the right side shows a closed state. The portable terminal device includes an upper housing 23, a lower housing 24, a connecting portion (here, a hinge portion) 25, a display 26, a sub-display 27, a picture light 28, a camera 29, and the like, and includes the display device of the present invention. The display 26 and the sub-display 27 are used. Since the display device of the present invention can incorporate a multi-bit memory in a pixel, it is possible to reduce power consumption required for charging / discharging data lines that occupy most of panel power consumption other than the backlight. Accordingly, an active matrix liquid crystal display device panel that can be driven with low power consumption can be realized. By incorporating such a liquid crystal panel in the monitor of the mobile terminal device, not only the battery charging interval can be extended but also the battery volume can be reduced, and the mobile terminal device can be further downsized.

  FIG. 10 shows a video camera to which the present invention is applied. The video camera includes a main body 30, a lens 34 for photographing a subject, a start / stop switch 35 at the time of photographing, a monitor 36, etc. on the side facing forward. It is manufactured by using the device for its monitor 36.

<Third embodiment>
[Configuration example 2 of variable resistance element]
FIG. 11A is a schematic diagram illustrating another configuration example of the variable resistance element ReRAM. As shown in the figure, the resistance change element ReRAM includes a pair of conductive layers and at least one oxide film layer disposed therebetween. In this example, the upper conductive layer has a four-layer structure of Ti / Al / Ti / CuTe. Of these, the third layer of Ti / Al / Ti is a composite metal film frequently used as a wiring layer in an ordinary thin film semiconductor device or the like, and the fourth CuTe alloy layer is a functional layer of the resistance change element.

  On the other hand, the lower conductive layer (electrode layer) is made of metal Mo. Mo, which is a refractory metal, is often used as a gate electrode or a gate wiring in a normal thin film transistor manufacturing process. Note that the distinction between the upper electrode and the lower electrode is for convenience, and the vertical relationship is not limited to the illustrated example in the actual structure.

The intermediate oxide film layer sandwiched between the upper and lower conductive layers is made of GdO _x . This metal oxide is an unfamiliar material in a normal thin film semiconductor process. With this configuration, as shown in the figure, when a positive set voltage E is applied to the upper conductive layer with reference to the lower conductive layer, the ReRAM is set to the low resistance state LRS. That is, Cu atoms contained in the conductive layer CuTe move to the oxide film layer GdO _x in accordance with the set voltage, thereby forming a fine current path (filament). As a result, the electrical resistance of the oxide film layer GdO _x is lowered to the low resistance state LRS.

On the other hand, when the polarity of the voltage applied to the upper and lower conductive layers is reversed, the Cu atoms moved into the oxide film layer GdO _x return to the conductive layer CuTe, and the fine current path is eliminated. By applying this negative reset voltage, the variable resistance element ReRAM is reset to a high resistance state HRS. However, in reality, application of the reset voltage causes metal Mo atoms to diffuse into the oxide film layer GdO _x from the lower conductive layer and lower its electrical resistance. This migration of the metal Mo proceeds by repeating the set / reset operation, and eventually the reset from the LRS to the HRS becomes impossible and the life ends. In addition, the oxide GdO _x has poor consistency with other materials in a normal thin film semiconductor process, and has difficulty in workability.

[Configuration Example 3 of Resistance Change Element]
FIG. 11B is a schematic diagram illustrating another configuration example of the variable resistance element ReRAM. Basically, it is similar to the example shown in FIG. 11A, but the structure of the intermediate oxide film layer and the lower conductive layer is different. In this example, the intermediate oxide film layer uses SiO _x instead of GdO _x . SiO _x is widely used as a gate insulating film or a passivation film of the thin film transistor TFT. The lower conductive layer is made of silicon Si (doped Si) doped with impurities at a high concentration to give conductivity instead of the refractory metal Mo. Doped Si is widely used as a source / drain electrode and wiring material of TFT.

In this example, the life of the ReRAM is extended by using SiO _{x as the} oxide film layer and doped Si as the lower conductive layer. In the configuration of this example, migration from the lower conductive layer to the intermediate oxide film layer hardly occurs. Even if Si atoms diffuse into the oxide film layer SiO _x , the resistance of the oxide film layer is hardly lowered. Thereby, a lifetime can be made longer than the example shown to FIGS.

[Configuration of memory element]
FIG. 11C is a schematic cross-sectional view showing the third embodiment of the memory element according to the present invention. Basically, it is similar to the second embodiment shown in FIG. The difference is the configuration of the resistance change element 207. In the present embodiment, the configuration shown in FIG. That is, the resistance change element 207 is a laminate in which a metal film 208 having a three-layer structure of Ti / Al / Ti and an alloy layer of CuTe are stacked as an upper conductive layer. Here, the metal film 208 having a three-layer structure of Ti / Al / Ti is used as the wiring of the TFT 205 and is frequently used in the TFT process.

  On the other hand, the lower conductive layer is formed of a polysilicon film 203. This polysilicon film 203 is doped with impurities at a high concentration to provide conductivity. In this example, the lower conductive layer corresponds to an extended portion of the polysilicon film 203 constituting the drain region of the TFT. Thus, by sharing the TFT drain electrode with the ReRAM electrode layer, the integration density of the memory elements can be increased.

The intermediate oxide film layer is made of SiO _x . This SiO _x is obtained, for example, by thermally oxidizing the surface of the polysilicon film 203. Alternatively, it is formed on the polysilicon film 203 by PECVD (plasma chemical vapor deposition) or sputtering. These film forming methods are widely used in TFT processes. As is clear from the above description, all the materials except CuTe are widely used in the normal TFT process for the variable resistance element of the present embodiment, and the memory element composed of a combination of TFT and ReRAM is integrated and formed. It is a suitable material.

  DESCRIPTION OF SYMBOLS 1 ... Memory element, 10 ... Pixel, TFT ... Thin-film transistor, ReRAM ... Resistance change element, LC ... Liquid crystal cell

Claims (6)

A row-shaped gate line, a column-shaped data line, and a pixel arranged at a portion where both intersect,
The pixel includes an electro-optic element and a plurality of memory elements,
Said plurality of memory elements is provided corresponding to each bit of the multi-tone data, each memory element may store data corresponding to each bit of the multi-tone data supplied from the data line, wherein Read the data according to the signal supplied from the gate line,
The electro-optic element exhibits luminance according to the multi-gradation data read from the plurality of memory elements ,
The memory element comprises an electrically parallel connection of a thin film transistor and a resistance change element,
The thin film transistor includes a semiconductor thin film in which a channel region, an input end, and an output end are formed, and a gate electrode that overlaps the channel region through an insulating film,
The variable resistance element includes one conductive layer electrically connected to the input end side, the other conductive layer electrically connected to the output end side, and the one conductive layer and the other conductive layer. disposed between, having at least one layer of oxide film layer made of varying materials and the low resistance state and high resistance state in response to a voltage applied to said input terminal,
Said plurality of memory elements, before reading time for reading the data in accordance with a signal supplied from Kige over preparative lines for each bit of the multi-tone data each memory element of said plurality of memory elements corresponding Differently
The oxide film layer constituting the memory element is made of SiO _x , and one of the one conductive layer and the other conductive layer is made of Si doped with impurities,
Display device. The display device according to claim 1, wherein the plurality of memory elements are electrically connected in series between the data line and the electro-optical element. 2. The display device according to claim 1, wherein the data read time is sequentially doubled for each memory element constituting the plurality of memory elements, and the electro-optic element is time-division driven in accordance with the read time. . Any one of the one conductive layer and the other conductive layer constituting the variable resistance element is doped with the impurity,
  4. The display device according to claim 1, wherein an impurity concentration of the conductive layer doped with the impurity is higher than an impurity concentration of the oxide film layer. 5. 5. The display device according to claim 4, wherein one of the one conductive layer and the other conductive layer constituting the variable resistance element is shared as a drain electrode of the thin film transistor. The display device according to claim 1, wherein the thin film transistor and the variable resistance element are connected to each other through a wiring in the same layer as the gate electrode.

Images