JP5105721B2 - Method with three masks to construct the final hard mask used to etch the fin fin silicon fins - Google Patents

Description

  The present disclosure uses a three-mask method to build a silicon mesa for a non-FinFET device such as a final hard mask, source / drain silicon regions, and resistors, diodes, and capacitors used to etch silicon fins. A method of manufacturing a fin field effect transistor (FinFET) is presented.

  Because of the continuing need to reduce transistor size, new small types of transistors have been created. One recent advance in transistor technology is the introduction of fin-type field effect transistors known as FinFETs. (US Pat. No. 6,069,069 to Hue et al.) Incorporated herein by reference (hereinafter “Hu”) includes a central fin having a channel along the center and a FinFET having a source and drain at the ends of the fin structure. A structure is disclosed. A gate conductor covers the channel portion.

US Pat. No. 6,413,802

  Although FinFET structures reduce the size of transistor-based devices, it is important to continue to improve FinFETs and methods of manufacturing the FinFETs. The present invention described below includes a final hard mask used to etch silicon fins, a FinFET source / drain silicon region, and three masks for building non-FinFET silicon mesas such as resistors, diodes, and capacitors. The method according to is used.

  The present disclosure presents a method for manufacturing a fin-type field effect transistor (FinFET) that begins by forming a mandrel on a laminated structure. The stacked structure includes a substrate, a silicon layer on the substrate, and a hard mask on the silicon layer. The present invention then forms a sidewall spacer around the mandrel and then removes the mandrel, leaving the free-standing sidewall spacer in place. The present invention then uses several patterned masks to remove all selected segments of the sidewall spacer.

  Next, the present invention uses a photomask to form a box-shaped structure on the remaining sidewall spacer portion, and the remaining sidewall spacer segments connect the box-shaped structure to form a modified H-shape. A structure is generated on the hard mask. This step of forming the box-shaped structure includes forming alignment marks in the laminated structure separately from the modified H-shaped structure.

  Next, the present invention transfers the pattern of the modified H-shaped structure to the hard mask, and later removes the modified H-shaped structure. Following this, the present invention uses a hard mask to transfer the pattern of the modified H-shaped structure to the silicon layer, and two opposing box-shaped structures, some of which are connected by fins A modified H-shaped structure including a body is obtained.

  Next, the present invention grows a sacrificial oxide on the modified H-shaped structure of the silicon layer and implants impurities into the fin of the silicon layer to adjust the threshold voltage value in the channel region. The sacrificial oxide is then removed and a gate oxide is formed / grown over the silicon layer fins.

  Thereafter, the present invention forms a gate conductor between the box-shaped structures of the silicon layer. The gate conductor intersects the fin. This step of forming the gate conductor involves using the alignment marks generated by the same photomask as used to generate the box-shaped structure, and then aligning the gate conductor to the modified H-shaped structure. Align. Next, the present invention forms gate sidewall spacers on the gate conductor. The gate sidewall spacer is present only on the gate conductor and not on the modified H-shaped structure of the silicon layer. The method of the present invention then grows additional silicon on the modified H-shaped structure of the silicon layer. After the additional silicon growth step, the present invention implants impurities into the modified H-shaped structure of the silicon layer to form the source / drain and extension and halo. The structure is then completed using known processing techniques to form various isolators / insulators, contacts, and the like.

  These and other aspects and objects of the invention will be better appreciated and understood when considered in conjunction with the following description and the accompanying drawings. However, it is to be understood that the following description illustrates preferred embodiments of the invention and numerous specific details thereof, but is for the purpose of illustration only and not limitation. Many changes and modifications may be made within the scope of the present invention without departing from the spirit thereof, and the invention includes all such modifications.

  The invention will be better understood from the following detailed description with reference to the drawings.

  The details of the invention and its various features and advantages are more fully described by reference to the non-limiting embodiments that are illustrated in the accompanying drawings and detailed in the following description. The features shown in the drawings are not necessarily to scale. Well-known components and processing techniques have been omitted to the extent that the present invention is not unnecessarily obscured. The examples used herein are intended only to assist in understanding the manner in which the present invention may be implemented and to further enable those skilled in the art to practice the present invention. Accordingly, these examples should not be construed as limiting the scope of the invention.

  The present invention provides a three-mask method for building the final hardmask used to etch silicon fins, the FinFET source / drain silicon regions, and the silicon mesa of non-FinFET devices such as resistors, diodes, and capacitors. provide. An alignment tree and process that retains most of the layout found in a typical CMOS process is described below.

  The present disclosure presents a method of manufacturing a fin field effect transistor (FinFET), which begins by forming a mandrel 100 on a stacked structure (FIGS. 1A, 1B). The mandrel 100 can be composed of any of patterned materials such as photoresist, silicon nitride, silicon dioxide, polysilicon. In the figure, the “A” view represents a plan view or a horizontal sectional view of the structure, and the “B” view represents either the line II ′ or II-II ′ of the structure shown in the “A” view. FIG. The stacked structure includes a substrate 108, a silicon layer 106 on the substrate 108, and a hard mask 104 (eg, silicon dioxide, silicon nitride) on the silicon layer 106.

  The present invention then forms a sidewall spacer 102 around the sides of the mandrel 100 and then removes the mandrel, leaving the freestanding sidewall spacer 102 in place (FIGS. 2A, 2B). The sidewall spacer can be constructed of any formed spacer material such as silicon dioxide, silicon nitride, polysilicon. As shown in FIGS. 3A and 3B, the present invention then uses a patterned mask 300 to remove all selected segments of the sidewall spacers 110, 112, 116. Element 300 represents the mask and element 302 represents the opening of the mask, and the etching process removes the spacer 110 through the opening. The mask 300 can be composed of any of patterned materials such as photoresist, silicon nitride, silicon dioxide. Thus, as shown in FIGS. 4A and 4B (showing the structure after the mask 300 has been removed), the U-shaped or C-shaped freestanding structure (when viewed from above) is a hard mask. 104 is formed.

  Next, as shown in FIGS. 5A and 5B, the present invention forms a box-shaped structure 500 on the remaining opposing sidewall spacers 112, 116 after removing the first sidewall spacer 110, The remaining sidewall spacers 114 connect the box-shaped structure 500 so that a modified H-shaped structure 504 is generated on the hard mask 104. The mask 500 can be comprised of any of patterned materials such as photoresist, silicon nitride, silicon dioxide. This structure is referred to as a “modified” H-shaped structure 504 because the remaining fins 114 are not in the longitudinal center position of the opposing box-shaped structure 500. This step of forming the box-shaped structure 500 includes forming alignment marks 502 in the stacked structure separately from the modified H-shaped structure 504. The alignment mark 502 has a shape defined by a mask used for defining the box-shaped structure 500. These marks 502 are transferred to the hard mask material 104 and later used to pattern the silicon region 106. These marks 502 are used in subsequent steps to align an optical exposure tool for patterning the gate conductors, thereby providing an optimal overlay (minimum overlay) of the gate to the box-shaped structure. Ensure that alignment errors are achieved. The mark 502 is not shown in the “B” view because it is very far from the H-shaped structure 500.

  Next, as shown in FIGS. 6A and 6B, the present invention transfers the modified H-shaped structure pattern 504 to the hard mask 104 (by etching or similar well-known material removal process). The modified H-shaped structure in the hard mask 104 is displayed as element 604 in the figure. The modified H-shaped structure 604 further includes an opposing box-shaped structure 600 and a connecting fin 602. Thereafter, the present invention removes the modified H-shaped structure 504.

  Thus, as indicated above, the present invention includes the final hard mask 604 used to etch silicon fins, the FinFET source / drain silicon regions, and the silicon mesas of non-FinFET devices such as resistors, diodes, and capacitors. A method with three masks to build is provided. More specifically, a first mask is used to generate the mandrel 100, a second mask 300 is used to pattern the sidewall spacers 102, and a third mask 500 is used to form the box-shaped structure 600. Used to form a pattern. The advantages derived from this method include the precise formation of very narrow fins and minimizing the spacing of the gate conductors relative to the box-shaped structure, which results in low extrinsic resistance, high speed, It becomes possible to manufacture a FinFET having a very short gate length.

  Following this, the present invention uses the patterned hard mask 104 (again using etching or a similar selective material removal method) to pattern the modified H-shaped structure pattern 604 into the silicon. Transfer to layer 106 so that a portion of silicon layer 106 obtains a modified H-shaped structure pattern 604 as shown in FIGS. 7A and 7B. The modified H-shaped structure in the silicon layer 106 also includes two opposing box-shaped structures 700 connected by fins 702, as shown in FIG. 7B. The present invention then grows a sacrificial oxide (not shown) on the modified H-shaped structure of the silicon layer 106, and impurities (boron, arsenic, phosphorus, indium, etc.) are deposited on the fin 702 of the silicon layer 106. Then, the threshold voltage of the channel region is adjusted by injecting into the box-shaped structure 700. Using a mask (not shown), the p-type FET and the n-type FET can be separately ion-implanted with different impurities to generate various threshold voltage values. The sacrificial oxide is then removed and a gate oxide is formed / grown on the fin 702 of the silicon layer 106.

  The present invention then forms a gate conductor 800 between the box-shaped structures of the silicon layer 106, as shown in FIGS. 8A and 8B. The gate conductor 800 can be made of, for example, polysilicon, metal, metal alloy, or the like that is patterned using a normal masking process (not shown). The gate conductor 800 intersects the fin 702 and is separated from the fin 702 by a gate oxide or other gate insulator such as a so-called high-k material (eg, hafnium silicate or hafnium dioxide). This step of forming the gate conductor 800 uses the alignment mark 502 generated by the same photomask used to generate the box-shaped structure to make the gate conductor 800 a modified H-shaped structure. And align. By using the same alignment mark 502 to pattern the box-shaped structure 600, 700 and the gate conductor 800, the present invention substantially eliminates the position between the gate conductor 800 and the box-shaped structure 700. Increase the accuracy of alignment and spacing. The alignment for the active silicon channel, i.e. the fin, which is usually preferred in planar FETs, is now replaced by the alignment for the shape defining the source and drain regions (box-shaped structures 600, 700). In the planar case, the exact overlay to the channel determines the alignment to the channel, but in the case of the FinFET of the present invention, the narrow nature of the fins provides additional overlap space for the channel. In addition, the alignment of the gate conductor with respect to the box-shaped structure, unlike the planar FET, results in reduced extrinsic resistance and a faster FET.

  Next, as shown in FIGS. 9A and 9B, the present invention forms a gate sidewall spacer 900 on the gate conductor 800. The gate sidewall spacer 900 can include any grown or formed material including silicon dioxide, silicon nitride, and the like. The gate sidewall spacer 900 exists only on the gate conductor 800 and does not exist on the modified H-shaped structure of the silicon layer 106. The gate sidewall spacer 900 may be formed by performing a directional etch (eg, reactive ion etching) followed by a conformal stratification of a material such as chemical vapor deposition (CVD) of silicon nitride. Directional etching only etches the vertical surface and can therefore continue until all of the spacer material is removed from the fin sidewalls. The gate conductor is higher than the fin, so the spacer 900 will still remain in the lower portion of the gate conductor 800.

  Then, as shown in FIGS. 10A and 10B, the method of the present invention grows additional silicon 902 on the modified H-shaped structure of the silicon layer 106. This selective silicon growth extends the exposed fin thickness beyond the gate conductor and spacer, thereby allowing for a reduction in extrinsic resistance at the source and drain. After the step of growing additional silicon 902, the present invention implants impurities into the modified H-shaped structure of silicon layer 106 to form source / drain extensions. In addition, halo implantation can be performed at this point to further reduce short channel effects in the FinFET. The structure is then completed using known processing techniques to form various isolators / insulators, contacts, and the like.

  FIG. 11 illustrates the present invention in flowchart form. More particularly, the method of the present invention begins 1100 by forming a mandrel on a laminated structure. The stacked structure includes a substrate, a silicon layer on the substrate, and a hard mask on the silicon layer. The present invention then forms 1102 sidewall spacers around the mandrels and then removes the mandrels 1104 leaving the freestanding sidewall spacers in place. The present invention then uses a number of patterned masks to remove 1106 the sidewall spacer segments. This forms a self-supporting structure on the hard mask that is U-shaped laterally or C-shaped rearward (when viewed from above). Next, the present invention forms a box-shaped structure on the remaining opposing sidewall spacers after removing the first sidewall spacers 1108, the sidewall spacers connecting the box-shaped structures, A modified H-shaped structure is generated on the hard mask. This step of forming the box-shaped structure 1108 uses a photomask that is also used to define the box-shaped structure 1108 to place alignment marks separately from the modified H-shaped structure 1108 in the stacked structure. Forming.

  The present invention then transfers 1110 the pattern of the modified H-shaped structure to a hard mask, and then 1112 removes the modified H-shaped structure. Following this, the present invention uses a hard mask to transfer the pattern of the modified H-shaped structure to the silicon layer 1114, two opposing box shapes in which a portion of the silicon layer is connected by fins. A modified H-shaped structure including the structure is obtained.

  Next, the present invention grows a sacrificial oxide on the modified H-shaped structure of the silicon layer 1116 and implants impurities into the fin and box-shaped structures of the silicon layer 1118, channel regions and source / drains. Form a region. The sacrificial oxide is then removed 1120 and a gate oxide is formed / grown 1122 over the fin of the silicon layer.

  Thereafter, the present invention forms a gate conductor between the box-shaped structures of the silicon layer 1124. The gate conductor intersects the fin. This step 1124 of forming a gate conductor involves positioning the gate conductor in a modified H-shaped structure using alignment marks formed by the same photomask used to generate the box-shaped structure. Match. Next, the present invention forms 1126 gate sidewall spacers on the gate conductor. The gate sidewall spacer is present only on the gate conductor and not on the modified H-shaped structure of the silicon layer. The method of the present invention then grows 1128 additional silicon on the modified H-shaped structure of the silicon layer. After the step of growing additional silicon, the present invention implants impurities into the modified H-shaped structure of the silicon layer to form 1130 source / drains and extensions and halos. The structure is then completed 1132 using known processing techniques to form various isolators / insulators, contacts, and the like.

  Thus, as indicated above, the present invention includes the final hard mask 604 used to etch silicon fins, the FinFET source / drain silicon regions, and the silicon mesas of non-FinFET devices such as resistors, diodes, and capacitors. A method with three masks to build is provided. More specifically, a first mask is used to generate the mandrel 100, a second mask 300 is used to pattern the sidewall spacers 102, and a third mask 500 is used to form the box-shaped structure 600. Used to form a pattern. The advantages derived from this method include the precise formation of very narrow fins and minimizing the spacing of the gate conductors relative to the box-shaped structure, which results in low extrinsic resistance, high speed, It is possible to manufacture a FinFET having a short gate length.

  The present invention provides the advantages of low gate-to-drain capacitance and low extrinsic resistance FinFETs. Furthermore, FinFETs formed according to the present invention can be switched very quickly as a result of these advantages. Increased circuit density and reduced power consumption are also brought about by the combination of elements provided herein. Thus, high-speed and / or low-power CMOS circuits and products in microprocessor, memory, digital signal processor, and analog applications can provide the advantages of increased power efficiency, lower cost, and higher speed.

  While the invention has been described in terms of preferred embodiments, those skilled in the art will recognize that the invention can be practiced with modification within the spirit and scope of the claims.

FIG. 3 is a schematic diagram of a partially completed finFET structure. FIG. 3 is a schematic diagram of a partially completed finFET structure. FIG. 3 is a schematic diagram of a partially completed finFET structure. FIG. 3 is a schematic diagram of a partially completed finFET structure. FIG. 3 is a schematic diagram of a partially completed finFET structure. FIG. 3 is a schematic diagram of a partially completed finFET structure. FIG. 3 is a schematic diagram of a partially completed finFET structure. FIG. 3 is a schematic diagram of a partially completed finFET structure. FIG. 3 is a schematic diagram of a partially completed finFET structure. FIG. 3 is a schematic diagram of a partially completed finFET structure. FIG. 3 is a schematic diagram of a partially completed finFET structure. FIG. 3 is a schematic diagram of a partially completed finFET structure. FIG. 3 is a schematic diagram of a partially completed finFET structure. FIG. 3 is a schematic diagram of a partially completed finFET structure. FIG. 3 is a schematic diagram of a partially completed finFET structure. FIG. 3 is a schematic diagram of a partially completed finFET structure. FIG. 3 is a schematic diagram of a partially completed finFET structure. FIG. 3 is a schematic diagram of a partially completed finFET structure. FIG. 3 is a schematic diagram of a partially completed finFET structure. FIG. 3 is a schematic diagram of a partially completed finFET structure. FIG. 3 is a flow diagram illustrating a preferred method of the present invention.

Explanation of symbols

100: mandrel 102: sidewall spacer 104: hard mask 106: silicon layer 108: substrate 800: gate conductor 900: gate sidewall spacer 902: additional silicon

Claims (12)

A method of manufacturing a fin-type field effect transistor (FinFET) comprising:
Forming a modified H-shaped structure on the silicon layer structure, comprising forming an alignment mark on the silicon layer structure separately from the modified H-shaped structure;
A modified H-shape including a pattern of the modified H-shaped structure transferred to a silicon layer of the silicon layer structure, wherein two portions of the silicon layer are connected by fins. Having a structure; and
Forming a gate conductor intersecting the fin between the box-shaped structures of the silicon layer, wherein the gate conductor is aligned with the modified H-shaped structure using the alignment marks; And steps to
Forming a gate sidewall spacer on the gate conductor that is only on the gate conductor and not on the modified H-shaped structure of the silicon layer;
Growing additional silicon on the modified H-shaped structure of the silicon layer;
Only including,
Forming the modified H-shaped structure,
Forming a mandrel on the silicon layer structure;
Forming a sidewall spacer around the mandrel;
Removing the mandrel and leaving the sidewall spacers in place;
Removing a portion of the sidewall spacer such that the sidewall spacer comprises two opposing portions and a portion connecting the two opposing portions;
Forming a mask over the two opposing portions of the sidewall spacer, the connecting portion of the sidewall spacer connecting the mask to produce the modified H-shaped structure;
Including a method. The method of claim 1, wherein the connecting portion of the sidewall spacer is perpendicular to the opposed portions of the front SL side wall spacer.   The method of claim 1, further comprising implanting impurities into the modified H-shaped structure of the silicon layer after the step of growing the additional silicon. Before forming the gate conductor,
Growing a sacrificial oxide on the modified H-shaped structure of the silicon layer;
Implanting impurities into the fins and the box-shaped structure of the silicon layer;
Removing the sacrificial oxide;
The method of claim 1 further comprising:   The method of claim 1, further comprising forming a gate insulator on the fin of the silicon layer prior to forming the gate conductor.   The method according to claim 1, wherein in the modified H-shaped structure, the fin is not located at a longitudinal center position of the opposing box-shaped structure. A method of manufacturing a fin-type field effect transistor (FinFET) comprising:
Forming a modified H-shaped structure on a laminated structure including a substrate, a silicon layer on the substrate, and a hard mask on the silicon layer, the modified H-shaped structure Forming alignment marks in the laminated structure separately from the body;
Transferring the pattern of the modified H-shaped structure to the hard mask;
Removing the modified H-shaped structure;
Using the hard mask, the pattern of the modified H-shaped structure is transferred to the silicon layer, and a portion of the silicon layer includes two opposing box-shaped structures connected by fins. Having a shape structure;
Forming a gate conductor intersecting the fin between the box-shaped structures of the silicon layer, wherein the gate conductor is aligned with the modified H-shaped structure using the alignment marks; And steps to
Forming a gate sidewall spacer on the gate conductor that is only on the gate conductor and not on the modified H-shaped structure of the silicon layer;
Growing additional silicon on the modified H-shaped structure of the silicon layer;
Only including,
Forming the modified H-shaped structure,
Forming a mandrel on the hard mask;
Forming a sidewall spacer around the mandrel;
Removing the mandrel and leaving the sidewall spacers in place;
Removing selected segments of the sidewall spacer such that the sidewall spacer comprises two opposing segments and a segment connecting the two opposing segments;
A box-shaped structure is formed on the two opposing segments of the sidewall spacer, and the connecting segment of the sidewall spacer connects the box-shaped structure to produce the modified H-shaped structure. Steps to do
Including a method. Segment the coupling of said sidewall spacers, the method of claim 7, perpendicular to the opposing segments of the front SL side wall spacer. 8. The method of claim 7 , further comprising implanting impurities into the modified H-shaped structure of the silicon layer after the additional silicon growth step. Before forming the gate conductor,
Growing a sacrificial oxide on the modified H-shaped structure of the silicon layer;
Implanting impurities into the fins and the box-shaped structure of the silicon layer;
Removing the sacrificial oxide;
The method of claim 7 further comprising: The method of claim 7 , further comprising forming a gate oxide on the fin of the silicon layer prior to forming the gate conductor. The method according to claim 7 , wherein in the modified H-shaped structure, the fin is not located at a longitudinal center position of the opposing box-shaped structure.

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