JP5105111B2 - Packet relay apparatus and packet relay method - Google Patents

Description

  The present invention relates to a packet relay apparatus and a packet relay method having a circuit that absorbs additional information (overhead).

  There is a router as a packet relay device. The router is generally configured as shown in FIG. The router of FIG. 5 assumes a router configuration with a data transmission rate of 1 Gbps. The router is a device that relays between the lower network and the upper network, that is, transmits and receives IP (Internet Protocol) packets.

  Between the layer 2 processing unit 103 and the layer 3 processing unit 104, GMII (Gigabit Media Independent Interface), RGMII (Reduced Gigabit Media Independent Interface), SGMII (Serial Gigabit Media Independent Interface), which are standardized by IEEE 802.3z. In general, they are connected by MAC (Media Access Controller) 101, 102) having a clock synchronous interface. In patent document 1, it connects by the RGMII circuit.

  In a conventional router, an IP packet is transmitted through the following route. When transmitting from the lower network to the upper network, the IP packets received by the input / output unit 105 are stored in the buffer 107 and then transmitted from the layer 2 processing unit 103 to the layer 3 processing unit 104. Next, the IP packet is stored in the buffer 108 and then transmitted to the input / output unit 106. On the other hand, when transmitting an IP packet from the upper network to the lower network, the IP packet received by the input / output unit 106 is stored in the buffer 108 and then transmitted from the layer 3 processing unit 104 to the layer 2 processing unit 103. Next, the data is stored in the buffer 107 and then transmitted to the input / output unit 105.

JP 2009-188479 A

  In the conventional router, when an IP packet is transmitted from the upper network to the lower network at a maximum transmission rate of 1 Gbps, the IP packet is once stored in the buffer 108. At this time, the layer 3 processing unit 104 may add additional information to the processed IP packet and transmit it to the layer 2 processing unit 103. If additional information is added to the IP packet to be transmitted, the data size is originally larger than the IP packet size passing through the interface between the layer 3 processing unit 104 and the layer 2 processing unit 103. Here, since there is only 1 Gbps transmission capability between the layer 2 processing unit 103 and the layer 3 processing unit 104, the layer 3 processing unit 104 stores the increased amount of data in the buffer 108. When the IP packet overflows in the buffer 108, the IP packet is discarded and the throughput decreases between the upper network and the lower network.

  As a solution to the problem of reduced throughput, it is conceivable to speed up the interface between the layer 2 processing unit 103 and the layer 3 processing unit 104. However, when IP packets are stored in the buffer 107 and the buffer 107 overflows, the layer 2 processing unit 103 is forced to discard the IP packets coming later.

  Until now, flow control defined as an optional function of IEEE802.3x has been used to eliminate discarding of IP packets. The flow control is control for transmitting a pause (PAUSE) frame to a transmission source device and stopping transmission (in this case, transmission from the higher level network to the input / output unit 106). When flow control is used, when an IP packet (for example, Video on demand, Voice Over Internet Protocol, etc.) that requires real-time performance is transmitted from the upper network to the lower network, the IP packet processed by the layer 3 processing unit 104 is transmitted. By transmitting additional information, the IP packet overflows in the buffer 107 and is discarded and the quality deteriorates, or flow control is performed to prevent the discard of the IP packet, delay occurs, and real-time performance Is damaged.

  In the network processor of Patent Document 1, in order to improve the processing speed, a transmission control circuit including a FIFO buffer is added between the RGMII circuit and the PHY circuit, and between the RGMII circuit and the switch circuit. The transmission speed between the transmission control circuit and the RGMII circuit is controlled. In this network processor, the transmission control circuit and the PHY circuit (or from the transmission control circuit to the switch) are connected by an RGMII circuit (transmission speed 1 Gbps). However, when additional information is added to an IP packet in a CPU or switch circuit that is a layer processing unit, the required maximum transmission rate is 1 Gbps + α (because α transmits additional information). Therefore, this network processor absorbs additional information between the CPU and the switch circuit when transmitting a packet at the maximum transmission speed (1 Gbps) between the WAN and the LAN or between the PHY circuit and the switch circuit. I can't do that.

  A main problem of the present invention is to solve a decrease in the throughput of an IP packet between a lower network and an upper network when additional information is added, and a packet relay device that realizes priority processing of the IP packet at this time, and It is to provide a packet relay method.

In the first aspect of the present invention, the packet relay apparatus processes the layer 2 data in the packet and adds or deletes additional information to the packet, and the layer 3 processing unit in the packet. A layer 3 processing unit that processes data and has a function of adding or deleting additional information to the packet; and a transmission path between the layer 2 processing unit and the layer 3 processing unit, and the layer An interface in which the transmission rate or the number of ports from the 2 processing unit side to the layer 3 processing unit side is fixed and the transmission rate or the number of ports from the layer 3 processing unit side to the layer 2 processing unit side can be switched When, wherein the interface, along with being communicatively connected to the layer 2 processing section, a clock synchronous type Intafu And a second media access controller that is communicably connected to the layer 3 processing unit and that has a clock synchronous interface, from the first media access controller to the first media access controller. The transmission rate to the second media access controller is fixed, the transmission rate from the second media access controller to the first media access controller is variable, and packets processed by the layer 2 processing unit are stored. A possible first buffer; a second buffer capable of storing packets to be processed by the layer 3 processing unit; and a usage state or a free state of the first buffer to monitor the usage state or A buffer monitoring circuit that outputs a control signal according to an empty state; And the second media access controller switches the transmission clock frequency based on the control signal from the buffer monitoring circuit, thereby transferring the transmission speed from the second media access controller to the first media access controller. It is characterized by switching .

  In the packet relay device of the present invention, the buffer monitoring circuit validates the control signal when the capacity of the first buffer becomes equal to or greater than a first set value, and the capacity of the first buffer is set to the first setting. The control signal is invalidated when the value becomes equal to or smaller than a second set value smaller than the value, and the control signal is set when the capacity of the first buffer exceeds the second set value and less than the first set value. Maintaining the previous state, the second media access controller sets the transmission rate from the second media access controller to the first media access controller as the first transmission rate when the control signal is invalid, and the control signal Is effective, the transmission rate from the second media access controller to the first media access controller is lower than the first transmission rate. It is preferable to switch to the second transmission rate.

In the second aspect of the present invention, the layer 2 data in the packet is processed, the layer 2 processing unit having a function of adding or deleting additional information to the packet, and the layer 3 data in the packet are processed. And a layer 3 processing unit having a function of adding or deleting additional information to the packet, and a transmission path between the layer 2 processing unit and the layer 3 processing unit, and from the layer 2 processing unit side An interface that fixes the transmission rate or the number of ports to the layer 3 processing unit side, and that can switch the transmission rate or the number of ports from the layer 3 processing unit side to the layer 2 processing unit side, The interface is connected to the layer 2 processing unit in a communicable manner and has a first interface having a clock synchronous interface. And a second interface control circuit having a clock synchronous interface and communicably connected to the layer 3 processing unit, from the first interface control circuit to the second interface control circuit number of ports is fixed, the second number of ports from the interface control circuit to the first interface control circuit Ri variable der, the first that can keep accumulate packets processed by the layer 2 processing section A buffer, a second buffer capable of storing packets processed by the layer 3 processing unit, and a use state or a free state of the first buffer, thereby monitoring the use state or the free state. A buffer monitoring circuit for outputting a control signal, wherein the second interface control circuit includes the buffer monitoring circuit. Based on the control signals from, and also changes a number of ports to the first interface control circuit from said second interface control circuit.

  In the packet relay device of the present invention, the buffer monitoring circuit validates the control signal when the capacity of the first buffer becomes equal to or greater than a first set value, and the capacity of the first buffer is set to the first setting. The control signal is invalidated when the value becomes equal to or smaller than a second set value smaller than the value, and the control signal is set when the capacity of the first buffer exceeds the second set value and less than the first set value. Maintaining the previous state, the second interface control circuit sets the number of ports from the second interface control circuit to the first interface control circuit as the first port number when the control signal is invalid; Is switched so that the number of ports from the second interface control circuit to the first interface control circuit is the second number of ports smaller than the first number of ports. Rukoto is preferable.

  According to the present invention, packets are transmitted and received between the layer 3 processing unit and the layer 2 processing unit at a transmission rate faster than the transmission rate of the input / output unit, so the layer 2 processing unit or the layer 3 processing unit side adds Even if information is attached to a packet, the packet can be transmitted and received between the lower network and the upper network at the maximum transmission rate of the input / output unit. Also, the transmission rate or port of the interface from the layer 3 processing unit to the layer 2 processing unit according to the free state of the first buffer by the buffer monitoring circuit that monitors the use state or free state of the first buffer of the layer 2 processing unit By switching the number, it is possible to prevent packets from being discarded in the layer 2 processing unit and to transmit packets from the upper network to the lower network by not stopping transmission from the layer 3 processing unit to the layer 2 processing unit. The layer 3 processing unit can perform priority control, and can guarantee the quality of a packet that requires real-time performance.

It is the block diagram which showed typically the circuit structure of the packet relay apparatus which concerns on Example 1 of this invention. It is the flowchart which showed typically the operation | movement of the packet relay apparatus which concerns on Example 1 of this invention. It is the block diagram which showed typically the circuit structure of the packet relay apparatus which concerns on Example 2 of this invention. It is the flowchart which showed typically the operation | movement of the packet relay apparatus which concerns on Example 2 of this invention. It is the block diagram which showed typically the circuit structure of the router which concerns on a prior art example.

In the packet relay apparatus according to the first embodiment of the present invention, a layer 2 processing unit (13 in FIG. 1 and 3 in FIG. 3) has a function of processing layer 2 data in a packet and adding or deleting additional information to the packet. 23), a layer 3 processing unit (14 in FIG. 1, 24 in FIG. 3) having a function of processing layer 3 data in the packet and adding or deleting additional information to the packet, and the layer 2 processing unit And the layer 3 processing unit, the transmission rate or the number of ports from the layer 2 processing unit side to the layer 3 processing unit side is fixed, and the layer 3 processing unit side interface that enables switching the transmission rate or the number of ports to the layer 2 processing section side from (11, 12 in FIG. 1, 21 and 22 in FIG. 3) provided with the said Intafe Is connected to the layer 2 processing unit in a communicable manner and has a clock synchronous interface, and is connected to the layer 3 processing unit in a communicable manner and has a clock synchronous interface. A second media access controller, wherein a transmission rate from the first media access controller to the second media access controller is fixed, and a transmission rate from the second media access controller to the first media access controller is variable. A first buffer capable of storing packets processed by the layer 2 processing unit, a second buffer capable of storing packets processed by the layer 3 processing unit, and Monitors the usage status or free status of the first buffer And a buffer monitoring circuit that outputs a control signal according to the use state or the empty state, and the second media access controller uses a frequency of a transmission clock based on the control signal from the buffer monitoring circuit. Is switched to switch the transmission rate from the second media access controller to the first media access controller.

In the packet relay apparatus according to the second embodiment of the present invention, the layer 2 processing unit (13 in FIG. 1 and FIG. 3) has a function of processing layer 2 data in the packet and adding or deleting additional information to the packet. 23), a layer 3 processing unit (14 in FIG. 1, 24 in FIG. 3) having a function of processing layer 3 data in the packet and adding or deleting additional information to the packet, and the layer 2 processing unit And the layer 3 processing unit, the transmission rate or the number of ports from the layer 2 processing unit side to the layer 3 processing unit side is fixed, and the layer 3 processing unit side An interface (11, 12 in FIG. 1, 21 and 22 in FIG. 3) capable of switching the transmission rate or the number of ports from the layer 2 to the layer 2 processing unit. Is connected to the layer 2 processing unit so as to be communicable, and has a first interface control circuit having a clock synchronous interface, and is communicably connected to the layer 3 processing unit, and has a clock synchronous interface. A second interface control circuit, the number of ports from the first interface control circuit to the second interface control circuit is fixed, and the number of ports from the second interface control circuit to the first interface control circuit is variable A first buffer capable of storing packets processed by the layer 2 processing unit, a second buffer capable of storing packets processed by the layer 3 processing unit, and By monitoring the use state or free state of the first buffer, the use state or free state A buffer monitoring circuit that outputs a control signal in accordance with the control signal from the second interface control circuit to the first interface control circuit based on the control signal from the buffer monitoring circuit. Switch the number of ports.

  A packet relay apparatus according to Embodiment 1 of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram schematically showing a circuit configuration of the packet relay apparatus according to the first embodiment of the present invention.

  FIG. 1 illustrates a circuit configuration of a router used in a broadband communication device as a packet relay device. The packet relay device is arranged on a path between the lower network and the upper network. The packet relay apparatus has a common part with the circuit configuration of the conventional router (see FIG. 5), MAC (Media Access Control; MAC11, MAC12), layer 2 processing unit 13, layer 3 processing unit 14, and input / output Section 15, input / output section 16, and buffers 17 and 18. In addition, the packet relay device is connected to the MAC 12 to the MAC 11 through an interface having a variable transmission speed, and the transmission speed from the MAC 11 to the MAC 12 is fixed to a transmission speed exceeding 1 Gbps as a part different from the circuit configuration of the conventional router. And a buffer monitoring circuit 19 is further added.

  The MACs 11 and 12 are media access controllers having a clock synchronous interface. The MAC 11 and the MAC 12 perform a connection based on RGMII (Reduced Gigabit Media Independent Interface) in FIG. Only the transmission rate from the MAC 12 to the MAC 11 can be switched to more than 1 Gbps / 1 Gbps or less, and the transmission rate from the MAC 11 to the MAC 12 is connected at a fixed transmission rate exceeding 1 Gbps. Specifically, the signal line between the MAC 11 and the MAC 12 includes four transmission signal lines, one transmission clock signal line, four reception signal lines, and one reception clock signal line. With regard to the transmission speed, in this embodiment, 1 Gbps or less is set to 0.8 Gbps, and more than 1 Gbps is set to 1.2 Gbps. The transmission speed from the MAC 12 to the MAC 11 is switched by the MAC 12 receiving the control signal from the buffer monitoring circuit 19 and switching the clock signal frequency of the transmission circuit in the MAC 12 so that 0.8 Gbps (transmission clock 100 MHz) and 1.2 Gbps. Switching to (transmission clock 150 MHz) is performed. The MAC 11 is connected to be able to communicate with the layer 2 processing unit 13. The MAC 12 is communicably connected to the layer 3 processing unit 14.

  The layer 2 processing unit 13 is a functional unit that processes layer 2 data in an IP packet. The layer 2 processing unit 13 performs data transfer processing of the data link layer (layer 2) in the OSI (Open Systems Interconnection) reference model, that is, data between communication devices connected directly (adjacent). Deliver. The layer 2 processing unit 13 has a function of adding or deleting additional information to the IP packet when transferring. The layer 2 processing unit 13 is communicably connected to the input / output unit 15, is communicably connected to the buffer 17, and is communicably connected to the MAC 11.

  The layer 3 processing unit 14 is a functional unit that processes layer 3 data in an IP packet. The layer 3 processing unit 14 performs data transfer processing of the network layer (layer 3) in the OSI reference model, that is, selects (routes) a communication path in the network and relays data. The layer 3 processing unit 14 has a function of adding or deleting additional information to the IP packet when transferring. The layer 3 processing unit 14 performs a discarding process when an IP packet accumulates in the buffer 18 and overflows, but has a function of performing an advanced analysis of the IP packet so as not to discard an IP packet that requires real-time performance. Has priority control function. The layer 3 processing unit 14 is communicably connected to the input / output unit 16, is communicably connected to the buffer 18, and is communicably connected to the MAC 12.

  The input / output units 15 and 16 are functional units for inputting / outputting IP packets. The input / output units 15 and 16 are connected by an interface conforming to IEEE802.3-1000BASE-T. The input / output unit 15 is communicably connected to the layer 2 processing unit 13 through four ports and is communicably connected to a lower network. The input / output unit 16 is communicably connected to the layer 3 processing unit 14 through one port and is communicably connected to the upper network.

  The buffer 17 is a functional unit capable of storing packets processed by the layer 2 processing unit 13. The buffer 17 stores the IP packet received by the input / output unit 15 or the IP packet transmitted from the layer 3 processing unit 14 to the layer 2 processing unit 13. The buffer 17 may be built in the layer 2 processing unit 13.

  The buffer 18 is a functional unit capable of storing packets processed by the layer 3 processing unit 14. The buffer 18 is a functional unit that stores IP packets received by the input / output unit 16 or IP packets transmitted from the layer 2 processing unit 13 to the layer 3 processing unit 14. The buffer 18 may be built in the layer 3 processing unit 14.

  The buffer monitoring circuit 19 monitors the empty state of the buffer 17 and controls the transmission clock of the MAC 12. That is, the buffer monitoring circuit 19 sends a control signal to the MAC 12 to switch the transmission clock in the MAC 12 and control the transmission speed. The buffer monitoring circuit 19 may be built in the layer 2 processing unit 13.

  Next, the operation of the packet relay apparatus according to the first embodiment of the present invention will be described with reference to the drawings. FIG. 2 is a flowchart schematically showing the operation of the packet relay apparatus according to the first embodiment of the present invention. Refer to FIG. 1 for the components in the packet relay apparatus.

  The transmission speed control operation by the buffer monitoring circuit 19 will be described.

  First, in the buffer monitoring circuit 19, the control signal is invalid in the initial state (step A1). Note that the buffer monitoring circuit 19 constantly monitors the free state (or use state) of the buffer 17. At this time, IP packets are transmitted and received between the MAC 12 and the MAC 11 at an initial value (1.2 Gbps).

  Next, the buffer monitoring circuit 19 determines the usage state of the buffer 17 (step A2). In the determination of the use state of the buffer 17, whether the detection value related to the buffer capacity is equal to or higher than the threshold value 1 (for example, 80% of the buffer capacity), or lower than the threshold value 0 (for example, 50% of the buffer capacity), It is determined whether it is less than 1 (for example, 80% of the buffer capacity) and exceeds the threshold value 0 (for example, 50% of the buffer capacity). When the threshold value is 1 or more (80% or more of step A2), the process proceeds to step A3. When the threshold is 0 or less (50% or less of step A2), the process proceeds to step A5. When it is less than the threshold value 1 and more than the threshold value 0 (more than 50% of step A2 and less than 80%), the process proceeds to step A7.

  When the usage state of the buffer 17 is equal to or greater than the threshold value 1 (80% or more of step A2), the buffer monitoring circuit 19 validates the control signal to the MAC 12 (step A3). After step A3, the MAC 12 receives the control signal in the valid state, sets the transmission clock to 100 MHz, fixes the transmission speed to 1 Gbps or less (0.8 Gbps), and transmits the IP packet to the MAC 13 ( Step A4). After step A4, the process returns to step A2.

  When the use state of the buffer 17 is less than or equal to the threshold value 0 (50% or less of step A2), the buffer monitoring circuit 19 invalidates the control signal to the MAC 12 (step A5). After step A5, the MAC 12 receives the control signal in an invalid state, sets the transmission clock frequency to 150 MHz, fixes the transmission speed to over 1 Gbps (1.2 Gbps), and transmits the IP packet to the MAC 13 (Step A6). After step A6, the process returns to step A2.

  When the usage state of the buffer 17 is less than the threshold value 1 and more than the threshold value 0 (more than 50% and less than 80% in Step A2), the buffer monitoring circuit 19 maintains the control signal in the previous state (Step A7). After step A7, the process returns to step A2. The MAC 12 receives the same control signal as in the previous state after step A7, thereby maintaining the transmission clock in the previous state, maintaining the transmission speed in the previous state, and directing the IP packet to the MAC 13 Will be sent.

  Next, details of the operation of the packet relay apparatus when transmitting an IP packet from the upper network side to the lower network side in FIG. 1 will be described.

  In the initial state (step A1 in FIG. 2), the buffer monitoring circuit 19 invalidates the control signal. At this time, IP packets are transmitted and received between the MAC 12 and the MAC 11 at a transmission rate of an initial value of 1.2 Gbps. The IP packet enters from the host network at 1 Gbps and is stored in the buffer 18. Then, the layer 3 processing unit 14 sometimes adds additional information to the IP packet. Since the transmission rate of 1.2 Gbps from the MAC 12 to the MAC 11 is sufficient to absorb the overhead, the overhead due to the additional information of the layer 3 processing unit 14 can be absorbed.

  Subsequently, the layer 2 processing unit 13 stores the IP packet sent from the MAC 12 at 1.2 Gbps in the buffer 17, takes additional information attached after the processing of the layer 3 processing unit 14, and receives it from the upper network side. The IP packet is transmitted to the input / output unit 15 at a transmission rate of 1 Gbps with the same size as the data size. Although 1.2 Gbps is a capacity sufficient to absorb overhead, it exceeds the transmission rate of IEEE 802.3-1000BASE-T, so that IP packets are accumulated in the buffer 17. When an IP packet is stored in the buffer 17 and the packet overflows in the buffer 17, the buffer monitoring circuit 19 detects the use state of the buffer 17 and switches the transmission speed of the MAC 12 in order not to discard the IP packet that comes later.

  Specifically, when the MAC 12 continues to transmit IP packets at 1.2 Gbps, the IP packets are accumulated in the buffer 17, and the use state of the buffer 17 is a threshold 0 (for example, as shown in step A2 in FIG. 2). 50% of the buffer capacity) and less than the threshold value 1 (for example, 80% of the buffer capacity), and as shown in step A7 in FIG.

  Further, when IP packets whose usage state of the buffer 17 is greater than or equal to the threshold value 1 (for example, 80% of the buffer capacity) are accumulated, the buffer monitoring circuit 19 validates the control signal as shown in step A3 of FIG. Thereafter, as shown in step A4 of FIG. 2, the MAC 12 reduces the transmission rate from 1.2 Gbps to 0.8 Gbps. When the MAC 12 transmits IP packets at 0.8 Gbps, the number of IP packets stored in the buffer 17 decreases, and the usage state of the buffer 17 is less than a threshold value 1 (for example, 80% of the buffer capacity) and a threshold value 0 (a buffer capacity of 50). 2), the buffer monitoring circuit 19 does not change the control signal while being valid, as indicated by step A7 in FIG.

  When the use state of the buffer 17 becomes the threshold value 0 (50% of the buffer capacity) or less, the buffer monitoring circuit 19 invalidates the control signal as shown in step A5 in FIG. Thereafter, as shown in Step A6 of FIG. 2, the MAC 12 increases the transmission rate from 0.8 Gbps to 1.2 Gbps and transmits the IP packet. The series of operations described above prevents IP packets from overflowing in the buffer 17 and realizes priority control of IP packets in the layer 3 processing unit 14.

  The above operation is premised on not performing flow control using a PAUSE frame.

  Next, details of the operation of the packet relay apparatus when an IP packet is transmitted in the direction opposite to the above transmission direction, that is, when the IP packet is transmitted from the lower network side to the upper network side in FIG.

  An IP packet entering from the lower network is temporarily stored in the buffer 17. When the layer 2 processing unit 13 attaches additional information to the IP packet, the MAC 11 transmits the IP packet to the MAC 12 at a transmission rate of 1.2 Gbps, so that the overhead is absorbed. The layer 3 processing unit 14 stores the IP packet transmitted from the MAC 11 at a transmission rate of 1.2 Gbps in the buffer 18, and then takes additional information added after the processing by the layer 2 processing unit 13, and sends it to the input / output unit 16 side. Transmit at a transmission rate of 1 Gbps. At this time, IP packets are accumulated in the buffer 18.

  When the IP packet accumulates in the buffer 18 and overflows, the layer 3 processing unit 14 discards the IP packet. The layer 3 processing unit 14 has a function of performing an advanced analysis of the IP packet. Therefore, it is possible to protect IP packets having high real-time characteristics from being discarded by preferentially transmitting IP packets that require real-time characteristics.

  According to the first embodiment, the following effects can be obtained.

  The first effect is that the IP packet transmission / reception is performed between the layer 3 processing unit 14 and the layer 2 processing unit 13 at a transmission rate faster than the transmission rates of the input / output units 15 and 16. Alternatively, even if the layer 3 processing unit 14 attaches additional information to the IP packet, the IP packet can be transmitted and received at the maximum transmission rate of the input / output units 15 and 16 between the lower network and the upper network, so that overhead can be absorbed and the IP packet However, the throughput is not lowered and the processing capability can be improved as compared with the prior art.

  The second effect is that a buffer monitoring circuit for monitoring the buffer 17 connected to the layer 2 processing unit 13 (which may be built-in) is added, and the layer 3 processing unit 14 changes the layer 2 according to the free state of the buffer 17. By switching the transmission rate of the interface to the processing unit 13, the layer 2 processing unit 13 prevents IP packets from being discarded, and does not stop transmission from the layer 3 processing unit 14 to the layer 2 processing unit 13. Even when an IP packet is transmitted from the upper network to the lower network, priority control can be performed by the layer 3 processing unit 14 to guarantee the quality of the IP packet that requires real-time performance.

  The third effect is that since only the buffer monitoring circuit is added to obtain the first and second effects, the additional circuit scale can be minimized as compared with the prior art.

  A packet relay apparatus according to Embodiment 2 of the present invention will be described with reference to the drawings. FIG. 3 is a block diagram schematically illustrating a circuit configuration of the packet relay apparatus according to the second embodiment of the present invention.

  The second embodiment is a modification of the first embodiment, and further devise the interface between the layer 2 processing unit 23 and the layer 3 processing unit 24.

  Instead of using the MAC (11, 12 in FIG. 1) as an interface between the layer 2 processing unit 23 and the layer 3 processing unit 24, SGMII control circuits 21, 22 are used. The SGMII control circuit 21 and the SGMII control circuit 22 are connected by two independent SGMII ports. That is, here, transmission is performed with two pairs of transmission signal lines, two pairs of transmission clock signal lines, two pairs of reception signal lines, and two pairs of reception clock signal lines (all signals are differential signals). Transmission / reception is performed at a speed of 2 Gbps (1 Gbps × 2).

  The SGMII control circuit 21 is communicably connected to the layer 2 processing unit 23 via an internal bus. The SGMII control circuit 22 is connected to the layer 3 processing unit 24 through an internal bus so as to be communicable.

  The SGMII control circuit 21 and the SGMII control circuit 22 have a function of assigning continuous IP packets to two independent SGMII ports and a function of receiving IP packets from the two SGMII ports. The SGMII control circuit 22 is configured to be able to control whether to transmit an IP packet in the 1-port mode or to transmit an IP packet in the 2-port mode in response to a control signal from the buffer monitoring circuit 29.

  Other configurations are the same as those of the first embodiment.

  Next, the operation of the packet relay apparatus according to the second embodiment of the present invention will be described with reference to the drawings. FIG. 4 is a flowchart schematically showing the operation of the packet relay apparatus according to the second embodiment of the present invention. Refer to FIG. 3 for the components in the packet relay apparatus.

  The transmission speed control operation by the buffer monitoring circuit 29 will be described.

  First, in the buffer monitoring circuit 29, the control signal is invalid in the initial state (step B1). Note that the buffer monitoring circuit 29 constantly monitors the free state (or use state) of the buffer 27. At this time, IP packets are transmitted and received between the SGMII control circuit 21 and the SGMII control circuit 22 using two SGMII ports.

  Next, the buffer monitoring circuit 29 determines the usage state of the buffer 27 (step B2). In the determination of the use state of the buffer 27, whether the detection value related to the buffer capacity is equal to or higher than the threshold value 1 (for example, 80% of the buffer capacity), or lower than the threshold value 0 (for example, 50% of the buffer capacity). It is determined whether it is less than 1 (for example, 80% of the buffer capacity) and exceeds the threshold value 0 (for example, 50% of the buffer capacity). When the threshold value is 1 or more (80% or more of step B2), the process proceeds to step B3. When the threshold is 0 or less (50% or less of step B2), the process proceeds to step B5. If it is less than the threshold value 1 and more than the threshold value 0 (more than 50% and less than 80% of step B2), the process proceeds to step B7.

  When the usage state of the buffer 27 is equal to or greater than the threshold value 1 (80% or more of step B2), the buffer monitoring circuit 29 validates the control signal to the SGMII control circuit 22 (step B3). After step A3, the SGMII control circuit 22 receives the control signal in the valid state, and transmits an IP packet to the SGMII control circuit 22 using one SGMII port (step B4). After step B4, the process returns to step B2.

  When the usage state of the buffer 27 is equal to or less than the threshold value 0 (50% or less of step B2), the buffer monitoring circuit 29 invalidates the control signal to the SGMII control circuit 22 (step B5). After step B5, the SGMII control circuit 22 receives the control signal in the invalid state and transmits an IP packet to the SGMII control circuit 22 using the two SGMII ports (step B6). After step B6, the process returns to step B2.

  When the usage state of the buffer 27 is less than the threshold value 1 and more than the threshold value 0 (more than 50% and less than 80% of Step B2), the buffer monitoring circuit 29 maintains the control signal in the previous state (Step B7). After step B7, the process returns to step B2. The SGMII control circuit 22 receives the same control signal as in the previous state after step B7, maintains the number of SGMII ports in the previous state, and transmits the IP packet to the SGMII control circuit 22. It will be.

  Next, details of the operation of the packet relay apparatus when transmitting IP packets from the upper network side to the lower network side in FIG. 3 will be described.

  When transmitting an IP packet at a maximum transmission rate of 1 Gbps from an upper network (input / output unit 26) to a lower network (input / output unit 25), the layer 3 processing unit 24 that has received the IP packet sends the IP packet to the buffer 28. Store. At this time, in an initial state (step B1 in FIG. 4), the control signal is invalid, and the SGMII control circuit 22 transmits using two SGMII ports.

  When the SGMII control circuit 22 transmits through two SGMII ports, IP packets are accumulated in the buffer 27, and the use state of the buffer 27 is set to a threshold value 0 (for example, 50% of the buffer capacity) as shown in step B2 of FIG. When the threshold value is exceeded and less than the threshold value 1 (for example, 80% of one buffer capacity), the buffer monitoring circuit 29 does not change the control signal while being invalid as shown in Step B7 of FIG.

  Further, when the usage state of the buffer 27 becomes equal to or more than the threshold value 1 (for example, 80% of the buffer capacity), the buffer monitoring circuit 29 validates the control signal as shown in Step B3 of FIG. Thereafter, as shown in step B4 of FIG. 4, the SGMII control circuit 22 switches to transmit an IP packet only to one of the two SGMII ports (transmission speed 1 Gbps) when transmitting.

  When the SGMII control circuit 22 transmits only with one SGMII port, the data size larger than the IP packet size entered from the original upper network to the layer 3 processing unit 24 is added by the additional information attached to the IP packet by the layer 3 processing unit 24. Become. However, since one SGMII has only 1 Gbps, it cannot be transmitted as the data size increases, and an IP packet entered from the upper network reaches the buffer 27 at less than 1 Gbps.

  Further, the layer 2 processing unit 23 takes the additional information added by the layer 3 processing unit 24, and transmits the IP packet (the IP packet received from the upper network itself) to the input / output unit 25 at a transmission rate of 1 Gbps. The IP packets in the buffer 27 are decreased.

  When the use state of the buffer 27 is less than the threshold value 1 (for example, 80% of the buffer capacity) and exceeds the threshold value 0 (for example, 50% of the buffer capacity), the buffer monitoring circuit 29 controls as shown in step B7 of FIG. The signal remains valid and remains unchanged.

  When the use state of the buffer 27 becomes a threshold value 0 (for example, 50% of the buffer capacity) or less, the buffer monitoring circuit 29 invalidates the control signal as shown in step B5 of FIG. Thereafter, as shown in step B6 of FIG. 4, the SGMII control circuit 22 switches to transmit to the SGMII control circuit 21 using two SGMII ports.

  The above operation is premised on not performing flow control using a PAUSE frame.

  Next, details of the operation of the packet relay apparatus when an IP packet is transmitted in the direction opposite to the above transmission direction, that is, when the IP packet is transmitted from the lower network side to the upper network side in FIG.

  When an IP packet is transmitted from the lower network side to the upper network, the IP packet is fixedly transmitted to two SGMII ports (2 Gbps). Specifically, the layer 2 processing unit 23 stores the IP packet received by the input / output unit 25 in the buffer 27 and then transmits the IP packet to the SGMII control circuit 21. The SGMII control circuit 21 allocates continuous IP packets to the two SGMII ports and transmits them.

  The SGMII control circuit 22 transmits the IP packet received from the two SGMII ports to the layer 3 processing unit 24. The layer 3 processing unit 24 stores the IP packet in the buffer 28 and then transmits the IP packet to the input / output unit 46.

  When the layer 2 processing unit 23 continuously transmits IP packets at a transmission rate of 2 Gbps, the IP packets are accumulated in the buffer 28. When the IP packet accumulates in the buffer 28 and overflows, the layer 3 processing unit 24 performs the discarding process. However, since the layer 3 processing unit 24 has a priority control function, the IP packet that requires real-time property is discarded. It is possible to protect against such.

  According to the second embodiment, since two SGMII ports are used between the layer 3 processing unit 24 and the layer 2 processing unit 23, transmission between the layer 3 processing unit 24 and the layer 2 processing unit 23 is performed. The speed is doubled. Thereby, the overhead is absorbed between the lower network and the upper network, and the throughput is maintained. Also, priority control can be performed in the transmission direction from the upper network to the lower network.

  In the configuration of the second embodiment, the layer 2 processing unit 23 and the layer 3 processing unit 24 may be configured with an interface of 2 ports or more (for example, 3 ports or more). Also, the interface connecting the layer 2 processing unit 23 and the layer 3 processing unit 24 is not limited to SGMII, and other interfaces (for example, RGMII, GMII) can be used.

11, 12, 101, 102 MAC (first and second media access controllers)
13, 23, 103 Layer 2 processing unit 14, 24, 104 Layer 3 processing unit 15, 25, 105 Input / output unit 16, 26, 106 Input / output unit 17, 27, 107 Buffer (first buffer)
18, 28, 108 buffer (second buffer)
19, 29 Buffer monitoring circuit 21, 22 SGMII control circuit (first and second interface control circuit)

Claims (4)

A layer 2 processing unit that processes layer 2 data in the packet and has a function of adding or deleting additional information to the packet;
A layer 3 processing unit having a function of processing layer 3 data in a packet and adding or deleting additional information to the packet;
The transmission line or the number of ports from the layer 2 processing unit side to the layer 3 processing unit side is fixed while being arranged in a transmission path between the layer 2 processing unit and the layer 3 processing unit, and An interface capable of switching the transmission rate or the number of ports from the layer 3 processing unit side to the layer 2 processing unit side;
Equipped with a,
The interface is
A first media access controller that is communicably connected to the layer 2 processing unit and has a clock synchronous interface;
A second media access controller that is communicably connected to the layer 3 processing unit and has a clock synchronous interface;
With
A transmission rate from the first media access controller to the second media access controller is fixed;
A transmission rate from the second media access controller to the first media access controller is variable;
A first buffer capable of storing packets processed by the layer 2 processing unit;
A second buffer capable of storing packets processed by the layer 3 processing unit;
A buffer monitoring circuit that outputs a control signal according to the use state or the free state by monitoring the use state or the free state of the first buffer;
With
The second media access controller switches a transmission rate from the second media access controller to the first media access controller by switching a frequency of a transmission clock based on the control signal from the buffer monitoring circuit. A packet relay device. The buffer monitoring circuit validates the control signal when the capacity of the first buffer becomes equal to or greater than a first set value, and the capacity of the first buffer is equal to or less than a second set value that is smaller than the first set value. The control signal is invalidated when the first buffer capacity is exceeded, and the control signal is maintained in the previous state when the capacity of the first buffer exceeds the second set value and less than the first set value,
The second media access controller sets the transmission rate from the second media access controller to the first media access controller as the first transmission rate when the control signal is invalid, and the second media access controller when the control signal is valid. 2 medium access packet relay apparatus according to claim 1, wherein the switch to the slower second transmission speed than the transmission speed of the first transmission rate from the controller to the first media access controller. A layer 2 processing unit that processes layer 2 data in the packet and has a function of adding or deleting additional information to the packet;
A layer 3 processing unit having a function of processing layer 3 data in a packet and adding or deleting additional information to the packet;
The transmission line or the number of ports from the layer 2 processing unit side to the layer 3 processing unit side is fixed while being arranged in a transmission path between the layer 2 processing unit and the layer 3 processing unit, and An interface capable of switching the transmission rate or the number of ports from the layer 3 processing unit side to the layer 2 processing unit side;
With
The interface is
A first interface control circuit that is communicably connected to the layer 2 processing unit and has a clock synchronous interface;
A second interface control circuit that is communicably connected to the layer 3 processing unit and has a clock synchronous interface;
With
The number of ports from the first interface control circuit to the second interface control circuit is fixed,
Ri ports variable der from the second interface control circuit to the first interface control circuit,
A first buffer capable of storing packets processed by the layer 2 processing unit;
A second buffer capable of storing packets processed by the layer 3 processing unit;
A buffer monitoring circuit that outputs a control signal according to the use state or the free state by monitoring the use state or the free state of the first buffer;
With
Said second interface control circuit, said buffer based on the control signal from the monitoring circuit, the second interface control features and to Rupa packet relay apparatus that switches the number of ports from the circuit to the first interface control circuit . The buffer monitoring circuit validates the control signal when the capacity of the first buffer becomes equal to or greater than a first set value, and the capacity of the first buffer is equal to or less than a second set value that is smaller than the first set value. The control signal is invalidated when the first buffer capacity is exceeded, and the control signal is maintained in the previous state when the capacity of the first buffer exceeds the second set value and less than the first set value,
The second interface control circuit sets the number of ports from the second interface control circuit to the first interface control circuit as the first port number when the control signal is invalid, and the second interface control circuit when the control signal is valid. 4. The packet relay apparatus according to claim 3 , wherein the number of ports from the two-interface control circuit to the first interface control circuit is switched so as to be a second port number smaller than the first port number.

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