JP5104139B2 - Cash system - Google Patents

Description

  The present invention relates to a cache system.

  In general, in a computer system, a small-capacity and high-speed cache memory is provided separately from the main memory. By copying a part of the information stored in the main memory to the cache, when accessing this information, it is possible to read the information at a high speed by reading from the cache instead of the main memory.

  The cache includes a plurality of cache lines, and information is copied from the main memory to the cache in units of cache lines. The memory space of the main memory is divided in units of cache lines, and the divided memory areas are sequentially assigned to the cache lines. Since the capacity of the cache is smaller than the capacity of the main memory, the memory area of the main memory is repeatedly assigned to the same cache line.

  When the first access is executed to an address in the memory space, the information (data or program) at that address is copied to the corresponding cache line in the cache. When executing the next access to the same address, information is read directly from the cache. Generally, out of all bits of the address, a predetermined number of lower bits serve as a cache index, and the remaining bits positioned higher than that serve as a cache tag.

  When accessing the data, the tag of the corresponding index in the cache is read using the index portion in the address indicating the access destination. It is determined whether or not the read tag matches the bit pattern of the tag portion in the address. If they do not match, a cache miss occurs. If they match, a cache hit occurs, and the cache data corresponding to the index (data of a predetermined number of bits for one cache line) is accessed.

  A cache configuration in which only one tag is provided for each cache line is called a direct mapping method. A cache configuration in which N tags are provided for each cache line is called an N-way set associative. The direct mapping method can be regarded as a one-way set associative.

  In order to reduce the penalty for accessing the main memory when a cache miss occurs, a system in which the cache memory is hierarchized is used. For example, by providing a secondary cache that can be accessed faster than the main memory between the primary cache and the main memory, the frequency at which access to the main memory is required when a cache miss occurs in the primary cache. Can be reduced to reduce the cache miss penalty.

  Conventionally, in a processor, the processing speed has been improved by improving the operating frequency and improving the architecture. However, in recent years, a technical limit has begun to appear when the frequency is further increased, and there is a strong movement toward improving the processing speed by a multiprocessor configuration using a plurality of processors.

  A system having a plurality of processors can be realized by providing a plurality of existing single processor cores each having a cache and simply connecting them. Such a configuration can keep the design cost low, but there are problems with cache usage efficiency and cache consistency.

  In Patent Document 1 below, each of a plurality of processor elements connected to each other via a network stores a processing device, an instruction sequence executed by the processing device, and data used in the instruction sequence A transmitting unit for transmitting data to other processor elements via the network, a receiving unit for receiving data transferred from other processor elements via the network, and a local unit requested by the processing device. A first cache memory for temporarily holding data held in the memory or data to be stored in the local memory, and data received by the receiving unit and stored in the local memory temporarily The second cache memory for holding the data and the receiving unit In response to this, the data is written to the second cache memory, and in response to a read request for data in the local memory from the processing device, the first and second cache memories are It is detected whether or not there is data subject to the request in either one of them, and when there is the data in either one, it has a cache access control means for reading the data from the one cache memory The calculator is listed.

  Patent Document 2 below discloses one or more processor modules having a processor and a cache memory, a memory module having a main memory shared by the processor modules, the one or more processor modules, and the memory. In a multiprocessor system comprising coupling means for interconnecting modules, a line size as a unit of data in cache coherency control for maintaining data coherency between cache memories in the processor module is the coupling means. N times the transfer size (n is an integer equal to or greater than 2), which is a unit of data when transferring data in the main memory via the processor, and the processor module sets the value of the line size to the value of the cache coherency control. Data unit Cache processor for controlling the cache memory, and when the data request issued by the processor in the processor module causes a cache miss in its own cache memory, the processor module and the memory module A data request issuing control means for issuing a coherent read request for requesting data and issuing a non-coherent read request for requesting data only to the memory module only (n-1) times; A multiprocessor system characterized by having a multiprocessor system is described.

  Patent Document 3 below discloses a shared bus that transfers data, a shared memory that is connected to the shared bus and holds data, a data holding unit that is connected to the shared bus and holds data, and A plurality of cache memories having a tag holding unit for holding information of data held in the data holding unit, and one cache memory of the plurality of cache memories, and necessary data is stored in the cache memory. In a method for controlling a multiprocessor including a plurality of processors (PE) that perform predetermined processing upon request, a predetermined cache memory of the plurality of cache memories is in a shared state with another cache memory. When the data updated to the shared memory is replaced, the other cache sharing the data is replaced. A tag holding unit of one cache memory in the cache memory holds information indicating that the shared memory has been updated, and the updated data is not written back to the shared memory. A multiprocessor control method is described.

JP-A-6-103244 Japanese Patent Laid-Open No. 2003-30048 JP-A-9-185547

  An object of the present invention is to provide a cache system capable of efficiently transferring data between a plurality of caches when a plurality of caches are connected to a plurality of processing devices on a one-to-one basis.

The cache system of the present invention includes a plurality of processing devices, a plurality of caches connected to the plurality of processing devices on a one-to-one basis, and a network connected to the plurality of caches and performing data communication between the plurality of caches. A plurality of buffers provided for each cache, wherein the cache has a plurality of buffers for data communication with the network, and when the data requested by the processing device misses in one cache, the plurality of buffers Depending on the state of the cache, when the cache performs data communication via the network and the data requested by the processing device misses in one cache and hits in another cache, There is no predetermined amount of data in the buffer for transmitting data to the one cache, and the previous There is a predetermined amount of data in the buffer for transmitting data from one cache to the other hit cache, and the one cache is not the least recently used among the plurality of caches And when there is no predetermined amount of data in the buffer for transmitting data from the one cache to the least recently used cache among the plurality of caches, the entry of the one cache is changed to the most recent The cache entry that is not used is overwritten, and the entry in the other cache that has been hit is overwritten in the entry in the one cache.

  Data can be efficiently transferred between a plurality of caches according to the state of the buffer, and an increase in traffic can be prevented.

  FIG. 1 is a diagram illustrating a configuration example of a shared distributed cache system. This shared distributed cache system has three cores (processors: processing devices) 101 to 103, three three-way primary caches 111 to 113 corresponding to the three cores 101 to 103, and caches 111 to 113. And an inter-cache connection controller (ICC) 120 connected to the main memory (or secondary cache) 130. Each of the cores 101 to 103 can access a cache (own core cache) directly connected to itself as an upper layer cache. This shared distributed cache system is further configured so that a cache of another core (another core cache) can be accessed as a lower hierarchy cache. That is, for example, when viewed from the core 101, the cache 111 can be accessed as an upper hierarchy cache, and the other core caches 112 and 113 can be accessed as lower hierarchy caches. A path for accessing such a lower hierarchy cache is provided via the inter-cache connection controller 120.

  The inter-cache connection controller 120 includes an information memory that stores the first LRU information 121 to 123 and the second LRU information 129. The information memory may be outside the inter-cache connection controller 120. The first LRU information 121 indicates the oldest order of the entries a, b, and c of the cache 111 and the group x of the other core caches 112 and 113, with “0” indicating the oldest and “2” indicating the latest. That is, the first LRU information 121 is LRU information obtained by adding n (= 1) other core cache groups x to the three entries a, b, and c of the own cache 111.

  FIG. 2 is a diagram showing details of the first LRU information 121 to 123 and the second LRU information 129 of FIG. Similar to the first LRU information 121, the first LRU information 122 indicates the oldest order of the entries a, b, and c of the cache 112 and the group x of the other core caches 111 and 113. Similarly to the first LRU information 121, the first LRU information 123 also indicates the oldest order of the entries a, b, and c of the cache 113 and the group x of the other core caches 111 and 112. When the first LRU information 121 to 123 is encoded by the binary relation method, each becomes 6 bits.

  The core 101 is the core A, and the cache 111 is the cache A. The core 102 is the core B, and the cache 112 is the cache B. The core 103 is the core C, and the cache 113 is the cache C.

  The second LRU information 129 indicates the usage order of the caches 111 to 113 among the three cores 101 to 103, A is the LRU information of the cache A (111), and B is the cache B (112). LRU information, and C is the LRU information of the cache C (113). When the second LRU information 129 is encoded by the binary relation method, it becomes 3 bits. Therefore, the sum of the LRU information 121 to 123 and 129 is 6 + 6 + 6 + 3 = 21 bits, which is smaller than the number of bits of the system of FIG. The information memory of the first LRU information 121 to 123 holds the first LRU information 121 to 123 for each cache on the assumption that the other core cache group is increased by one way in the local LRU information of each of the caches 111 to 113. To do.

  FIG. 3 is a diagram illustrating another configuration example of the shared distributed cache system. Hereinafter, the points of FIG. 3 different from FIG. 1 will be described. The shared distributed cache system includes six cores 101 to 106, six primary caches 111 to 116 corresponding to the six cores 101 to 106, and an inter-cache connection controller connected to the caches 111 to 116. (ICC) 120 and main memory (or secondary cache) 130 are included. The caches 111 to 114 and 116 are 3 ways, and the cache 115 is 2 ways. Each of the cores 101 to 106 can access the own core caches 111 to 116 as an upper hierarchy cache. This shared distributed cache system is further configured so that the other core cache can be accessed as a lower hierarchy cache. That is, for example, when viewed from the core 101, the cache 111 can be accessed as a higher-level cache, and the group x of the other core caches 112 and 113, the group y of the other core caches 114 and 115, and the other core cache 116 The group z is configured to be accessible as a lower hierarchy cache.

  The inter-cache connection controller 120 includes an information memory that stores the first LRU information 121 to 126 and the second LRU information 129. The first LRU information 121 indicates the earliest order of the entries a, b, and c of the cache 111, the group x of the other core caches 112 and 113, the group y of the other core caches 114 and 115, and the other core cache 116 group z. , “0” indicates the oldest and “5” indicates the latest. That is, the first LRU information 121 is LRU information obtained by adding n (= 3) other core cache groups x, y, and z to the three entries a, b, and c of the own cache 111. .

  FIG. 4 is a diagram showing details of the first LRU information 121 to 126 and the second LRU information 129 of FIG. Similarly to the first LRU information 121, the first LRU information 122 includes the entries a, b, c, n (= 3) of the other core caches 111 and 113 of the cache 112, the group x of the other core caches 114, and the other core cache 114. , 115 of group y, and the oldest order of group z of other core cache 116. The first LRU information 123 includes entries a, b, c and n (= 3) of the cache 113, the group x of the other core caches 111 and 112, the group y of the other core caches 114 and 115, and the other core cache 116. Indicates the oldest order of group z. The first LRU information 124 includes the entries a, b, c and n (= 2) of the cache 114, the group x of the other core caches 111 and 112, and the oldest group y of the other core caches 113, 115 and 116. Indicates the order. The first LRU information 125 includes two entries a and b in the cache 115, group x of n (= 3) other core caches 111 and 112, group y of other core caches 113 and 114, and other core caches. 116 shows the oldest order of 116 groups z. The first LRU information 126 includes entries a, b, c and n (= 3) of the cache 116, the group x of the other core caches 111 and 112, the group y of the other core caches 113 and 114, and the other core cache 115. Indicates the oldest order of group z. The combination of groups can be determined arbitrarily.

  When the first LRU information 121 to 123, 126 is encoded by the binary relation method, each becomes 15 bits. Since the first LRU information 124 includes information on two other core cache groups x and y, the first LRU information 124 becomes 10 bits when encoded by the binary relational method. Since the first LRU information 125 includes information on two entries a and b in the cache 115, the first LRU information 125 becomes 10 bits when encoded by the binary relation method.

  The core 101 is the core A, and the cache 111 is the cache A. The core 102 is the core B, and the cache 112 is the cache B. The core 103 is the core C, and the cache 113 is the cache C. The core 104 is the core D, and the cache 114 is the cache D. The core 105 is the core E, and the cache 115 is the cache E. The core 106 is the core F, and the cache 116 is the cache F.

  The second LRU information 129 indicates the used order of the caches 111 to 116 among the six cores 101 to 106, A is the LRU information of the cache A (111), and B is the cache B (112). LRU information of the cache C (113), D is LRU information of the cache D (114), E is LRU information of the cache E (115), and F is LRU information of the cache F (116). When the second LRU information 129 is encoded by the binary relation method, it becomes 15 bits. Therefore, the sum of the LRU information 121 to 126, 129 is 15 + 15 + 15 + 10 + 10 + 15 + 15 = 95 bits, and when the number of cores is large, the effect of reducing the number of bits is great.

  FIG. 5 is a flowchart showing a data load access operation in the shared distributed cache system. Hereinafter, the system of FIG. 1 will be described as an example. In step S1, first, any one of the plurality of cores 101 to 103 issues a load request to a cache (own core cache) directly connected to itself.

  In step S2, the cache that has received the load request determines whether or not the requested data exists in the cache, that is, whether or not it is a cache hit. If it is a cache hit, in step S3, the requested data is read from the own core cache, and the data is returned to the core that issued the load request.

  If there is a cache miss in step S2, the process proceeds to step S4. In step S4, it is determined whether or not a lower hierarchy cache exists under the cache in which a cache miss is detected. For example, when a cache miss is detected in step S2 and the process proceeds to step S4, the cache in which the cache miss is detected is any one of the caches 111 to 113. In this case, the other two caches are in the lower level. It exists as a hierarchical cache. If a lower hierarchy cache exists, the process proceeds to step S5.

  In step S5, the cache hierarchy accesses the other core cache one level below. In step S6, the cache that has received the access request determines whether or not the requested data exists in the cache, that is, whether or not it is a cache hit. If it is a cache miss, the process returns to step S4 and the above processing is repeated.

  If it is a cache hit in step S6, the process proceeds to step S7. In step S7, cache data exchange processing is performed. That is, the cache line to be accessed (data to be accessed) is moved from the cache hit to the own core cache, and the data is returned to the core. At this time, as the cache line moves to the own core cache, the cache line evicted from the own core cache is moved to another core. Details of step S7 will be described later with reference to FIG.

  If it is determined in step S4 that there is no lower hierarchy cache, the process proceeds to step S8. For example, when a cache miss is detected in step S6 and the process proceeds to step S4, if the cache in which this cache miss is detected is already the lowermost cache, only the main memory 130 exists in the lower layer. In such a case, in step S8, the requested data is read from the main memory 130, allocated to the own core cache (the requested data for one cache line is copied to the own core cache), and a load request is issued. Return data to the issued core. Further, the cache line evicted from the own core cache as a result of this operation is moved to, for example, a lower hierarchy cache. Details of step S8 will be described later with reference to FIG.

  In the above operation flow, step S7 is an operation related to data transfer between the cache and the cache, and step S8 is an operation related to data transfer between the main memory 130 and the cache.

  FIG. 6 is a flowchart showing the exchange process in step S7 of FIG. First, in step A1, it is determined that another core cache that can be used as a lower hierarchy cache has been hit by the determination in step S6 of FIG.

  Next, in step A2, the inter-cache connection controller 120 performs a determination process. That is, whether or not the condition that the first LRU information of the own core local of the group to which the hit other core belongs is the latest and the entry of the first LRU information of the hit other core cache is not the latest is satisfied Determine whether. If the condition is satisfied, the process proceeds to step A4. If the condition is not satisfied, the process proceeds to step A7.

  In step A4, the inter-cache connection controller 120 performs exchange processing between the own core cache and the other core cache. That is, the oldest entry in the own core cache and the hit entry in the other core cache are exchanged.

  Next, in step A5, the inter-cache connection controller 120 performs LRU update processing. That is, for the first LRU information of the own core, the exchanged entry of the own core cache is updated to the latest, and for the first LRU information of the other core, the exchanged entry of the other core cache is updated the oldest. The second LRU information is updated so that the own core cache becomes the latest. Then, it progresses to step A6 and complete | finishes a process.

  In step A7, the self-core performs a reference process via the inter-cache connection controller 120. That is, it directly refers to (reads out) the entry hit in the other core cache.

  Next, in step A3, the inter-cache connection controller 120 performs LRU update processing. That is, for the first LRU information of the own core, the group to which the hit other core cache belongs is updated to the latest, and for the first LRU information of the other core, 2 if the entry of the hit other core cache is the latest. The second LRU information is updated so that the hit other core cache becomes the latest. Then, it progresses to step A6 and complete | finishes a process.

  7 to 9 are diagrams illustrating an example of the exchange process of FIG. 6 in the system of FIGS. 1 and 2. FIG. 7 shows an initial state. The first LRU information 121 to 123 and the second LRU information 129 indicate that 0 is the oldest and newer as the value increases.

  First, the case where the entry c of the cache B (112) of the other core B (102) is hit from the own core A (101) in step A1 will be described.

  Next, in step A2, the first LRU information 121 of the own core local of the group x to which the hit other core cache B (112) belongs is 1 and is not the latest, so the process proceeds to step A7. In step A7, the entry c hit in the other core cache B (112) is directly referenced.

  Next, in step A3, as shown in FIG. 8, for the first LRU information 121 of the own core A (101), the group x to which the hit other core cache B (112) belongs is updated (value “3”). ), The entry c of the other core cache B (112) that has been hit is the latest (value “3” in FIG. 7) for the first LRU information 122 of the other core B (102). The new entry x is updated to be exchanged, and the second LRU information 129 is updated so that the hit other core cache B (112) becomes the latest. Then, it progresses to step A6 and complete | finishes a process.

  Next, the case where the entry c of the cache B (112) of the other core B (102) is hit again from the own core A (101) in step A1 will be described.

  Next, in Step A2, the first LRU information 121 of the own core local of the group x to which the hit other core cache B (112) belongs is the latest (value “3”), and the hit other core cache Since the entry c of the first LRU information 122 of B (112) is not the latest (value “2”), the process proceeds to step A4. In step A4, the oldest entry b in the own core cache A (111) and the hit entry c in the other core cache B (112) are exchanged.

  Next, in step A5, as shown in FIG. 9, for the first LRU information 121 of the own core A (101), the exchanged entry b of the own core cache A (111) is updated to the latest, and the other cores For the first LRU information 122 of B (102), the exchanged entry c of the other core cache B (112) is updated to the oldest, and for the second LRU information 129, the own core cache A (111) is the latest Update to be Then, it progresses to step A6 and complete | finishes a process.

  As described above, when the entry c of the other core cache B is hit at the first time, the replacement process is not performed, and when the entry c of the other core cache B is hit at the second time, the replacement process is performed. , Useless exchange processing can be eliminated and traffic can be reduced. In other words, efficient exchange processing can be performed by exchanging only the entry c that is continuously accessed by the own core A and that is currently not frequently used in the hit other core cache B.

  FIG. 10 is a flowchart showing the eviction process in step S8 of FIG. First, in step B1, it is determined that all other core caches that can be used as the lower hierarchy cache have missed by the determination in step S4 of FIG.

  Next, in step B2, the inter-cache connection controller 120 performs a determination process. That is, referring to the second LRU information, it is determined whether or not the self-core satisfies the condition that it is not the most recently used core of the index. If the condition is satisfied, the process proceeds to step B4. If the condition is not satisfied, the process proceeds to step B7.

  In step B4, the inter-cache connection controller 120 performs an eviction process from the own core cache to another core cache. That is, the oldest entry of the own core cache (the oldest entry among those not including the other core group entry) is moved to the oldest entry of the other core cache that has not been used most recently.

  Next, in step B5, the inter-cache connection controller 120 performs LRU update processing. That is, the oldest entry of the own core cache is updated to the latest for the first LRU information of the own core, and the oldest entry of the other core cache to be evicted is updated to the latest for the first LRU information of the other core. The second LRU information is updated so that its own core cache is the latest and the other core cache of the eviction destination is the second most recent. Then, it progresses to step B6.

  In step B7, the inter-cache connection controller 120 performs a discard process. That is, the oldest entry in the own core cache is discarded. Specifically, nothing is processed in this step, and the oldest entry in the own core cache is discarded by the overwrite process in the subsequent step B6.

  Next, in step B3, the inter-cache connection controller 120 performs LRU update processing. That is, for the first LRU information of the own core, the oldest entry in the own core cache is updated to the latest, and the second LRU information is updated to be the latest. Then, it progresses to step B6.

  In Step B6, the inter-cache connection controller 120 overwrites the data read from the main memory 130 on the oldest entry (the latest entry after the LRU information update) of the own core cache, and the own core acquires the data. Thus, the process ends.

  11 to 13 are diagrams illustrating an example of the eviction process of FIG. 10 in the system of FIGS. 1 and 2. FIG. 11 shows an initial state. The first LRU information 121 to 123 and the second LRU information 129 indicate that 0 is the oldest and newer as the value increases.

  First, in step B1, the case where the access of the own core A (101) misses in all other core caches will be described.

  Next, in step B2, when referring to the second LRU information 129, since the own core cache A (111) has not been used most recently, the process proceeds to step B3 via step B7.

  In step B3, as shown in FIG. 12, for the first LRU information 121 of the own core A (101), the oldest entry b of the own core cache A (111) is updated to the latest, and the second LRU information 129 is updated. Is updated so that its own core cache A becomes the latest.

  Next, in step B6, the data read from the main memory 130 is overwritten on the oldest entry (latest entry after updating the LRU information) b of the own core cache A (111). The process ends here.

  Next, the case where the access of the own core A (101) misses in all other core caches again in step B1 will be described.

  Next, in step B2, referring to the second LRU information 129, the other core cache C (113) has not been used most recently, so the process proceeds to step B4.

  In step B4, the oldest entry b of the own core cache A (111) is included in the oldest entry b of the other core cache C (113) that has not been used most recently (the oldest entry among those not including the other core group entry). Move a.

  Next, in step B5, as shown in FIG. 13, for the first LRU information 121 of the own core A (101), the oldest entry a of the own core cache A (111) is updated to the latest, and the other core C For the first LRU information 123 of (103), the oldest entry b of the other core cache C (113) to be evicted is updated to the latest, and for the second LRU information 129, the own core cache A (111) is the latest Then, the other core cache C (113) of the eviction destination is updated so as to be the second newest.

  Next, in step B6, the data read from the main memory 130 is overwritten on the oldest entry (latest entry after updating the LRU information) a of the own core cache A (111). The process ends here.

  As described above, if all other core caches miss in the first time, the eviction process is not performed, and if the other core cache misses in the second time, the eviction process is performed, so that unnecessary eviction is performed. Processing can be eliminated and traffic can be reduced. In other words, efficient eviction processing can be performed by performing eviction processing only when the own core A continuously misses the cache and the other core cache is the oldest.

  The second LRU information 129 holds only the latest access, but may hold the complete oldest order. The reason for retaining only the latest access is to reduce the number of bits. In addition, when the second LRU information 129 is updated, the eviction destination core is updated to the second most recent one, and the eviction destination is carried around, so that it is possible to suppress the performance degradation compared to the case where the complete oldest order is maintained. .

  FIG. 14 is a diagram showing a configuration example of the shared distributed cache system according to the embodiment of the present invention. Hereinafter, the points of FIG. 14 different from FIG. 1 will be described. The information memory 1421, the determination circuit 1424, and the inter-cache connection network (ICN) 1425 correspond to the inter-cache connection controller 120 of FIG. The information memory 1421 stores LRU information 1422 and transmission / reception buffer information 1423. The LRU information 1422 corresponds to the LRU information 121 to 123 and 129 in FIG. The inter-cache connection network 1425 is connected to the main memory 130 and the caches 111 to 113. The determination circuit 1424 controls communication of the inter-cache connection network 1425 according to the LRU information 1422 or the transmission / reception buffer information 1423 in the information memory 1421.

  The transmission buffer A (1401) and the reception buffer A (1411) are provided in the cache A (111). The transmission buffer 1401 is a buffer for transmitting data in the cache 111 to the cache 112 or 113 via the inter-cache connection network 1425. The reception buffer 1411 is a buffer for receiving data in the cache 112 or 113 to the cache 111 via the inter-cache connection network 1425.

  The transmission buffer B (1402) and the reception buffer B (1412) are provided in the cache B (112). The transmission buffer 1402 is a buffer for transmitting data in the cache 112 to the cache 111 or 113 via the inter-cache connection network 1425. The reception buffer 1412 is a buffer for receiving data in the cache 111 or 113 to the cache 112 via the inter-cache connection network 1425.

  The transmission buffer C (1403) and the reception buffer C (1413) are provided in the cache C (113). The transmission buffer 1403 is a buffer for transmitting data in the cache 113 to the cache 111 or 112 via the inter-cache connection network 1425. The reception buffer 1413 is a buffer for receiving data in the cache 111 or 112 to the cache 113 via the inter-cache connection network 1425.

  The transmission / reception buffer information 1423 is usage amount information indicating whether each of the transmission buffer 1401, the reception buffer 1411, the transmission buffer 1402, the reception buffer 1412, the transmission buffer 1403, and the reception buffer 1413 is filled beyond a threshold.

  FIG. 15 is a flowchart showing the exchange process of step S7 of FIG. 5 in the cache system of FIG. 14, FIG. 16 is a diagram showing an example of the ball hitting process of step C13 of FIG. 15, and FIG. 17 is step C11 of FIG. It is a figure which shows the example of this movement process.

  First, in step C1, it is determined that another core cache that can be used as a lower hierarchy cache has been hit by the determination in step S6 of FIG.

  Next, in step C2, as in step A2 of FIG. 6, the determination circuit 1424 performs LRU determination processing. That is, whether or not the condition that the first LRU information of the own core local of the group to which the hit other core belongs is the latest and the entry of the first LRU information of the hit other core cache is not the latest is satisfied Determine whether. If the condition is satisfied, the process proceeds to step C8. If the condition is not satisfied, the process proceeds to step C7.

  In step C8, the determination circuit 1424 performs a first buffer determination process. That is, it is determined whether or not the buffer from the hit other core cache to the own core cache is filled beyond the threshold. For example, in order to perform data transfer from the hit other core buffer 112 to the own core buffer 111, the transmission / reception buffer information 1423 is referred to, and the transmission buffer 1402 of the other core buffer 112 or the reception buffer 1411 of the own core buffer 111 exceeds the threshold. To determine whether it is buried. If at least one of the transmission buffer 1402 or the reception buffer 1411 is filled, the process proceeds to Step C7, and if both the transmission buffer 1402 and the reception buffer 1411 are not filled, the process proceeds to Step C9.

  In step C7, the own core performs a reference process via the inter-cache connection network 1425 as in step A7 of FIG. That is, it directly refers to (reads out) the entry hit in the other core cache.

  Next, in step C3, the cache system performs LRU update processing as in step A3 of FIG. That is, for the first LRU information of the own core, the group to which the hit other core belongs is updated to the latest, and for the first LRU information of the other core, the second is the second if the entry of the hit other core is the latest. The second LRU information is updated so that it is replaced with a new one, and the other core cache that has been hit is updated so as to be the latest. Then, it progresses to step C6 and complete | finishes a process.

  In step C9, the determination circuit 1424 performs a second buffer determination process. That is, it is determined whether or not the buffer to the other core cache hit from the own core cache is filled beyond the threshold. For example, in order to perform data transfer from the own core buffer 111 to the other core buffer 112 hit, the transmission / reception buffer information 1423 is referred to, and the transmission buffer 1401 of the own core buffer 111 or the reception buffer 1412 of the other core buffer 112 exceeds the threshold. To determine whether it is buried. If at least one of the transmission buffer 1401 and the reception buffer 1412 is filled, the exchange process cannot be performed, so the process proceeds to Step C10. If both the transmission buffer 1401 and the reception buffer 1412 are not filled, the exchange process is possible, and therefore, the process proceeds to Step C4. .

  In step C4, as in step A4 of FIG. 6, the cache system performs an exchange process between the own core cache and the other core cache. For example, as shown in FIGS. 16 and 17, the oldest entry b in the own core cache 111 and the hit entry c in the other core cache 112 are exchanged. In other words, the data of the hit entry c in the other core cache 112 is moved to the oldest entry b of the own core cache 111 by the data transfer process 1611, and the data of the oldest entry b of the own core cache 111 is moved by the data transfer process 1612. It is moved to hit entry c in the other core cache 112.

  Next, in step C5, as in step A5 of FIG. 6, the cache system performs LRU update processing. That is, for the first LRU information of the own core, the exchanged entry of the own core is updated to the latest, for the first LRU information of the other core, the exchanged entry of the other core is updated to the oldest, The LRU information of 2 is updated so that the own core cache becomes the latest. Then, it progresses to step C6 and complete | finishes a process.

  In step C10, the determination circuit 1424 performs a third buffer determination process. That is, by referring to the LRU information 1422 and the transmission / reception buffer information 1423, whether the buffer of the own core is the oldest or the transmission / reception buffer from the buffer of the own core to the buffer of the oldest core is filled beyond the threshold. Determine whether or not. When the buffer of the own core is the oldest, it is not necessary to perform the ball hitting process (step C13), and the process proceeds to step C11. When the transmission / reception buffer from the buffer of the own core to the buffer of the oldest core is filled beyond the threshold, the ball hitting process (step C13) cannot be performed, and the process proceeds to step C11. When the buffer of the own core is not the oldest and the transmission / reception buffer from the buffer of the own core to the buffer of the oldest core is not filled beyond the threshold, the process proceeds to step C13 to perform a ball hitting process.

  In step C13, the cache system performs a ball hitting process. That is, as shown in FIG. 16, the data transfer process 1613 overwrites the oldest entry c of the cache 111 of the own core 101 with the oldest entry c of the cache 113 of the oldest core 103, and the data transfer process 1611 The oldest entry b of the cache 111 of the core 101 is overwritten with the hit entry c of the cache 112 of the other core 102, and the hit entry c of the cache 112 of the other core 102 is invalidated. The oldest core can be determined based on the second LRU information 129, and the oldest entry can be determined based on the first LRU information 121-123.

  As shown in FIG. 16, the transmission buffer 1402 and the reception buffer 1411 of the communication path 1601 from the hit other core cache 112 to the own core cache 111 are not filled beyond the threshold value, and the own core cache 111 is hit. The transmission buffer 1401 and the reception buffer 1412 of the communication path 1602 to the other core cache 112 are filled beyond the threshold, and the transmission buffer 1401 and the reception buffer of the communication path 1603 from the own core cache 111 to the oldest core cache 113 When 1413 is not filled exceeding the threshold value, the replacement process (step C4) 1611 and 1612 cannot be performed, so the above-described ball hitting processes (step C13) 1611 and 1613 are performed.

  Next, in step C14, the cache system performs LRU update processing. That is, the oldest entry of the own core cache is updated to the latest for the first LRU information of the own core, the oldest entry is updated to the latest for the first LRU information of the oldest other core, and the second The LRU information is updated so that the own core cache is the latest and the oldest other core is the second most recent. Then, it progresses to step C6 and complete | finishes a process.

  In step C11, the cache system performs migration processing. That is, as shown in FIG. 17, the data transfer process 1611 overwrites the entry c hit in the cache 112 of the other core 102 with the oldest entry b of the cache 111 of the own core 101, and The hit entry c is invalidated. By the overwriting, the original cache line of the oldest entry b in the own core cache 111 is discarded 1614.

  As described above, the transmission buffer 1402 and the reception buffer 1411 of the communication path 1601 from the hit other core cache 112 to the own core cache 111 are not filled beyond the threshold and the other core hit from the own core cache 111 The transmission buffer 1401 and the reception buffer 1412 of the communication path 1602 to the cache 112 are filled beyond the threshold, and the transmission buffer 1401 and the reception buffer 1413 of the communication path 1603 from the own core cache 111 to the oldest core cache 113 are Since the replacement process (step C4) 1611 and 1612 and the ball hitting process (step C13) cannot be performed when the threshold is exceeded, the movement processes (step C11) 1611 and 1614 are performed.

  Next, in step C12, the cache system performs LRU update processing. That is, the oldest entry of the own core cache is updated to the latest for the first LRU information of the own core, and the cache of the own core is updated to the latest order for the second LRU information. Then, it progresses to step C6 and complete | finishes a process.

  In step C10, if it is determined that the own core cache is not the oldest and the transmission / reception buffer from the own core cache to the oldest core cache is filled beyond the threshold, 2 from the own core cache. It may be determined whether the transmission / reception buffer for the second oldest cache is filled beyond the threshold. If not, the oldest entry in the own core cache is overwritten with the oldest entry in the second oldest core cache, the oldest entry in the own core cache is overwritten with the hit entry in the other core cache, Invalidate hit entries in other core caches. If it is filled, it is further determined whether the transmission / reception buffer from the own core cache to the third oldest cache is filled beyond the threshold, and the third, fourth,... Old core caches may be sequentially subjected to the ball hitting process.

  As described above, according to the present embodiment, when performing the exchange process, in addition to the LRU determination process (step C2), the transmission / reception buffer determination process (steps C8 to C10) is performed. In FIG. 15, a ball hitting process (step C13) and a moving process (step C11) are added to FIG. When the process proceeds to step C8 in the LRU determination process (step C2), the reference process (step C7), the exchange process (step C4), and the ball hitting process (step S4) are performed depending on how the transmission / reception buffers (for example, the transmission buffer 1401 and the reception buffer 1412) are filled. Step C13) or movement processing (step C11) is performed. Thereby, traffic can be reduced.

  18 is a flowchart showing the eviction process in step S8 of FIG. 5 in the cache system of FIG. 14, and FIG. 19 is a diagram showing an example of the eviction process to the next candidate in step D10 of FIG.

  First, in step D1, it is determined that all other core caches that can be used as the lower hierarchy cache have missed by the determination in step S4 of FIG.

  Next, in step D2, as in step B2 of FIG. 10, the determination circuit 1424 performs LRU determination processing. That is, referring to the second LRU information, it is determined whether or not the self-core satisfies the condition that it is not the most recently used core of the index. If the condition is satisfied, the process proceeds to step D8. If the condition is not satisfied, the process proceeds to step D7.

  In step D8, the determination circuit 1424 performs a first buffer determination process. That is, it is determined whether the transmission / reception buffer from the buffer of the own core to the buffer of the oldest core is filled beyond the threshold. For example, in FIG. 19, it is determined whether or not the transmission buffer 1401 or the reception buffer 1412 of the communication path 1901 from the buffer 111 of the own core 101 to the buffer 112 of the oldest core 102 is filled beyond the threshold. When the transmission buffer 1401 or the reception buffer 1412 is filled beyond the threshold, the process proceeds to step D9. When the transmission buffer 1401 and the reception buffer 1412 are not filled beyond the threshold, the process proceeds to step D4.

  In step D4, as in step B4 of FIG. 10, the cache system performs eviction processing from its own core cache to another core cache. That is, as shown in FIG. 19, the data transfer processing 1912 causes the oldest entry c of the other core cache 112 that has not been used most recently to be the oldest entry of the own core cache 111 (not including the entry for the other core group). To move the oldest entry b).

  Next, in step D5, the cache system performs LRU update processing as in step B5 of FIG. That is, the oldest entry of the own core cache is updated to the latest for the first LRU information of the own core, and the oldest entry of the other core cache to be evicted is updated to the latest for the first LRU information of the other core. The second LRU information is updated so that the own core cache is in the latest order and the other core cache in the eviction destination is in the second most recent order. Thereafter, the process proceeds to Step D6.

  In step D9, the determination circuit 1424 performs a second buffer determination process. That is, it is determined whether the transmission / reception buffer from the cache of the own core to the cache of the second oldest core is filled beyond the threshold. For example, in FIG. 19, it is determined whether the transmission buffer 1401 or the reception buffer 1413 of the communication path 1902 from the cache 111 of the own core 101 to the cache 113 of the second oldest core 103 is filled beyond the threshold. When the transmission buffer 1401 or the reception buffer 1413 is filled beyond the threshold, the process proceeds to step D7. When the transmission buffer 1401 and the reception buffer 1413 are not filled beyond the threshold, the process proceeds to step D10.

  In step D7, as in step B7 of FIG. 10, the cache system performs a discard process. That is, the oldest entry in the own core cache is discarded. Specifically, nothing is processed in this step, and the oldest entry in the own core cache is discarded by the overwrite process in the subsequent step D6.

  Next, in step D3, the cache system performs LRU update processing as in step B3 of FIG. That is, for the first LRU information of the own core, the oldest entry in the own core cache is updated to the latest, and the second LRU information is updated to be the latest. Thereafter, the process proceeds to Step D6.

  In step D10, the cache system performs an eviction process for the next candidate. That is, as shown in FIG. 19, the data transfer process 1913 causes the oldest entry c of the own core cache 111 to be the oldest entry (not including the entry for other core groups) in the oldest entry c of the second oldest core cache 113. ) Move b.

  Next, in step D11, the cache system performs LRU update processing. That is, the oldest entry of the own core cache is updated to the latest for the first LRU information of the own core, and the oldest entry is updated to the latest for the first LRU information of the second oldest core (ejecting destination core). For the second LRU information, the local core cache is updated to the latest, and the second oldest core (ejecting destination core) is updated to the second newest. Thereafter, the process proceeds to Step D6.

  In step D6, as in step B6 of FIG. 10, as shown in FIG. 19, the own core 101 sets the oldest entry (latest entry after updating the LRU information) b in the own core cache 111 by the data read processing 1911. The data read from the main memory (or secondary cache) 130 is overwritten and the data is acquired. Thus, the process ends.

  When it is determined in step D9 that the transmission / reception buffer from the own core cache to the second oldest core cache is filled beyond the threshold, the transmission / reception buffer from the own core cache to the third oldest core cache is determined. It may be determined whether or not is buried beyond the threshold. If it is not filled, the oldest entry in the own core cache is overwritten with the oldest entry in the third oldest core cache, the oldest entry in the own core cache is overwritten with the hit entry in the other core cache, Invalidate hit entries in other core caches. If it is filled, it is further determined whether or not the transmission / reception buffer from the own core cache to the fourth oldest core cache exceeds the threshold, and the fourth, fifth,... Alternatively, older core caches may be sequentially targeted for eviction processing.

  As described above, in the present embodiment, when the eviction process is performed, the transmission / reception buffer determination process (steps D8 and D9) is performed in addition to the LRU determination process (step D2). In FIG. 18, a process of evicting to the next candidate (step D10) is added to FIG. When the process proceeds to step D8 in the LRU determination process (step D2), the discard process (step D7), the eviction process (step D4), or the next candidate is selected depending on how the transmission / reception buffers (for example, the transmission buffer 1401 and the reception buffer 1412) are filled. The eviction process (step D10) is performed. Thereby, traffic can be reduced.

  FIG. 20 is a diagram showing a configuration example of a shared distributed cache system according to another embodiment of the present invention. Hereinafter, the points of FIG. 20 different from FIG. 14 will be described. In FIG. 14, the LRU information 1422 and the transmission / reception buffer information 1423 of all the caches 111 to 113 are stored in one common information memory 1421. The information memories 1421a, 1421b, 1421c, LRU information 1422a, 1422b, 1422c, and transmission / reception buffers 1423a, 1423b, 1423c in FIG. 20 are obtained by distributing the information memory 1421, LRU information 1422, and transmission / reception buffer 1423 in FIG. is there.

  The information memory 1421a is provided in the cache 111, and stores LRU information 1422a and transmission / reception buffer information 1423a. The LRU information 1422a corresponds to the first LRU information 121 of FIG. The transmission / reception buffer information 1423a is information indicating whether each of the transmission buffer 1401 and the reception buffer 1411 is filled beyond a threshold.

  The information memory 1421b is provided in the cache 112, and stores LRU information 1422b and transmission / reception buffer information 1423b. The LRU information 1422b corresponds to the first LRU information 122 in FIG. The transmission / reception buffer information 1423b is information indicating whether or not each of the transmission buffer 1402 and the reception buffer 1412 is filled beyond a threshold.

  The information memory 1421c is provided in the cache 113, and stores LRU information 1422c and transmission / reception buffer information 1423c. The LRU information 1422c corresponds to the first LRU information 123 of FIG. The transmission / reception buffer information 1423c is information indicating whether each of the transmission buffer 1403 and the reception buffer 1413 is filled beyond a threshold.

  The second LRU information 129 of FIG. 1 may be stored in the determination circuit 1424, or may be stored in the caches 111 to 113. The operation of the cache system of FIG. 20 is the same as that of the cache system of FIG.

  As described above, in this embodiment, the determination of entry (cache line) movement is performed by performing entry movement determination based on transmission / reception buffer information that can directly know the traffic state in addition to LRU information. It can be reduced directly.

  In the present embodiment, a plurality of processing devices (cores) 101 to 103, a plurality of caches 111 to 113 connected to the plurality of processing devices 101 to 103 on a one-to-one basis, and a plurality of caches 111 to 113 are connected. , A network 1425 that performs data communication between the plurality of caches 111 to 113, and a plurality of buffers 1401 that are provided for each of the caches 111 to 113 and that allow the caches 111 to 113 to perform data communication with the network 1425. 1403, 1411-1413. When the data requested by the processing device misses in one cache, the cache performs data communication via the network according to the plurality of buffer states (transmission / reception buffer information) 1423.

  When the data requested by the processing device misses in one cache (step S2 in FIG. 5) and hits in another cache (step S6 in FIG. 5), the one cache is transferred from the other hit cache. There is no predetermined amount of data in the buffer for transmitting data to (step C8 in FIG. 15), and the predetermined amount of data in the buffer for transmitting data from the one cache to the other hit cache When there is no data (step C9 in FIG. 15), the entry in the one cache and the entry in the other hit cache are exchanged (step C4 in FIG. 15).

  In addition, when the data requested by the processing device misses in one cache (step S2 in FIG. 5) and hits in another cache (step S6 in FIG. 5), the data from the other cache hit becomes the one. When a predetermined amount of data exists in the buffer for transmitting data to the cache (step C8 in FIG. 15), the requested processing device refers to the data in the other cache hit (in FIG. 15). Step C7).

  In addition, when the data requested by the processing device misses in one cache (step S2 in FIG. 5) and hits in another cache (step S6 in FIG. 5), the data from the other cache hit becomes the one. There is no predetermined amount of data in the buffer for transmitting data to the cache (step C8 in FIG. 15), and the buffer for transmitting data from the one cache to the other cache hit. When a predetermined amount of data exists (step C9 in FIG. 15) and the one cache is least recently used among the plurality of caches (step C10 in FIG. 15), the other hits The cache entry is overwritten with the one cache entry (step C11 in FIG. 15).

  In addition, when the data requested by the processing device misses in one cache (step S2 in FIG. 5) and hits in another cache (step S6 in FIG. 5), the data from the other cache hit becomes the one. There is no predetermined amount of data in the buffer for transmitting data to the cache (step C8 in FIG. 15), and the buffer for transmitting data from the one cache to the other cache hit. There is a predetermined amount of data (step C9 in FIG. 15), and the one of the plurality of caches is not the least recently used (step C10 in FIG. 15). A predetermined amount of data is stored in the buffer for transmitting data from the cache to the least recently used cache of the plurality of caches. Is not present (step C10 in FIG. 15), the entry of the one cache is overwritten with the entry of the least recently used cache, and the entry of the other cache hit is the entry of the one cache. (Step C13 in FIG. 15).

  In addition, when the data requested by the processing device misses in one cache (step S2 in FIG. 5) and hits in another cache (step S6 in FIG. 5), the data from the other cache hit becomes the one. There is no predetermined amount of data in the buffer for transmitting data to the cache (step C8 in FIG. 15), and the buffer for transmitting data from the one cache to the other cache hit. There is a predetermined amount of data (step C9 in FIG. 15), and the one of the plurality of caches is not the least recently used (step C10 in FIG. 15). A predetermined amount of data is stored in the buffer for transmitting data from the cache to the least recently used cache of the plurality of caches. When but present in (step C10 in FIG. 15) overwrites the entry of other caches that the hit entry of said one cache (step C11 in FIG. 15).

  In addition, when the data requested by the processing device misses in one cache (step S2 in FIG. 5) and hits in another cache (step S6 in FIG. 5), the data from the other cache hit becomes the one. There is no predetermined amount of data in the buffer for transmitting data to the cache (step C8 in FIG. 15), and the buffer for transmitting data from the one cache to the other cache hit. There is a predetermined amount of data (step C9 in FIG. 15), and the one of the plurality of caches is not the least recently used (step C10 in FIG. 15). A predetermined amount of data is stored in the buffer for transmitting data from the cache to the least recently used cache of the plurality of caches. (Step C10 in FIG. 15), and there is no predetermined amount of data in the buffer for transmitting data from the one cache to the second least recently used cache among the plurality of caches Sometimes, the one cache entry is overwritten with the second least recently used cache entry, and the other cache entry with the hit is overwritten with the one cache entry.

  In addition, when the data requested by the processing device misses in all of the plurality of caches (steps S2, S4, and S6 in FIG. 5), from one cache of the requested processing device to the plurality of caches. When the predetermined amount of data does not exist in the buffer for transmitting data to the least recently used cache (step D8 in FIG. 18), the entry of the one cache is stored in the least recently used cache. Move to the entry (step D4 in FIG. 18), and overwrite the data read from the main storage device (main memory) or the cache (secondary cache) 130 lower than the plurality of caches on the entry of the moved one cache. (Step D6 in FIG. 18).

  In addition, when the data requested by the processing device misses in all of the plurality of caches (steps S2, S4, and S6 in FIG. 5), from one cache of the requested processing device to the plurality of caches. A predetermined amount of data exists in the buffer for transmitting data to the least recently used cache (step D8 in FIG. 18), and the second most recently used from the one cache to the plurality of caches When a predetermined amount of data does not exist in the buffer for transmitting data to a cache that has not been processed (step D9 in FIG. 18), the cache entry that has not been used the second most recently is entered. (Step D10 in FIG. 18) and read from the main storage device or a cache lower than the plurality of caches. Overwrite out data to the entry of one cache and the moved (step D6 in Fig. 18).

  In addition, when the data requested by the processing device misses in all of the plurality of caches (steps S2, S4, and S6 in FIG. 5), from one cache of the requested processing device to the plurality of caches. A predetermined amount of data exists in the buffer for transmitting data to the least recently used cache (step D8 in FIG. 18), and the second most recently used from the one cache to the plurality of caches When there is a predetermined amount of data in the buffer for transmitting data to a cache that has not been processed (step D9 in FIG. 18), the data read from the main storage device or a cache in a lower hierarchy than the plurality of caches is stored in the buffer. The entry in one cache is overwritten (step D6 in FIG. 18).

  In addition, when the data requested by the processing device misses in all of the plurality of caches (steps S2, S4, and S6 in FIG. 5), from one cache of the requested processing device to the plurality of caches. A predetermined amount of data exists in the buffer for transmitting data to the least recently used cache (step D8 in FIG. 18), and the second most recently used from the one cache to the plurality of caches There is a predetermined amount of data in the buffer for sending data to a cache that has not been performed (step D9 in FIG. 18), and the third most recently used from the one cache to the plurality of caches When there is no predetermined amount of data in the buffer for sending data to the cache, the entry in the one cache is Go to the entry of the cache serial third not recently used, overwrites the data read from the cache of the lower hierarchical than the main storage device or the plurality of cache entries of one cache that the mobile.

  The cache system shown in FIG. 14 has one information memory 1421 for storing the states (transmission / reception buffer information) 1423 of the plurality of buffers 111 to 113 in a centralized manner. On the other hand, the cache system of FIG. 20 includes a plurality of information memories 1421a, 1421b, and 1421c that store the states 1423a, 1423b, and 1423c of the plurality of buffers 111 to 113 in a distributed manner for each buffer.

  The above-described embodiments are merely examples of implementation in carrying out the present invention, and the technical scope of the present invention should not be construed in a limited manner. That is, the present invention can be implemented in various forms without departing from the technical idea or the main features thereof.

  The embodiment of the present invention can be applied in various ways as follows, for example.

(Appendix 1)
A plurality of processing devices;
A plurality of caches connected one-to-one to the plurality of processing devices;
A network connected to the plurality of caches and performing data communication between the plurality of caches;
A plurality of buffers provided for each cache, the cache having data communication with the network;
When the data requested by the processing device misses in one cache, the cache performs data communication via the network according to the states of the plurality of buffers.
(Appendix 2)
When the data requested by the processing device misses in one cache and hits in another cache, a predetermined amount of data is stored in the buffer for transmitting data from the hit other cache to the one cache. When there is no predetermined amount of data in the buffer for transmitting data from the one cache to the other hit cache, the one cache entry and the other hit cache entry The cache system according to supplementary note 1, characterized in that:
(Appendix 3)
When the data requested by the processing device misses in one cache and hits in another cache, a predetermined amount of data is stored in the buffer for transmitting data from the hit other cache to the one cache. 2. The cache system according to claim 1, wherein when the request exists, the requested processing device refers to the data of the other hit cache.
(Appendix 4)
When the data requested by the processing device misses in one cache and hits in another cache, a predetermined amount of data is stored in the buffer for transmitting data from the hit other cache to the one cache. Does not exist, and a predetermined amount of data exists in the buffer for transmitting data from the one cache to the other hit cache, and the one cache is the most recent among the plurality of caches The cache system according to claim 1, wherein when the cache is not used, the entry of the other cache hit is overwritten on the entry of the one cache.
(Appendix 5)
When the data requested by the processing device misses in one cache and hits in another cache, a predetermined amount of data is stored in the buffer for transmitting data from the hit other cache to the one cache. Does not exist, and a predetermined amount of data exists in the buffer for transmitting data from the one cache to the other hit cache, and the one cache is the most recent among the plurality of caches When the predetermined amount of data does not exist in the buffer for transmitting data from the one cache to the least recently used cache among the plurality of caches when not being used, Overwrite cache entry with the least recently used cache entry and hit Cache system according to Supplementary Note 1, wherein the overwriting entries in other cache entries of the one caches.
(Appendix 6)
When the data requested by the processing device misses in one cache and hits in another cache, a predetermined amount of data is stored in the buffer for transmitting data from the hit other cache to the one cache. Does not exist, and a predetermined amount of data exists in the buffer for transmitting data from the one cache to the other hit cache, and the one cache is the most recent among the plurality of caches The hit is found when there is a predetermined amount of data in the buffer for transmitting data from the one cache to the least recently used cache among the plurality of caches that are not used Supplementary note 1 overwriting another cache entry with the one cache entry Mounting cache system.
(Appendix 7)
When the data requested by the processing device misses in one cache and hits in another cache, a predetermined amount of data is stored in the buffer for transmitting data from the hit other cache to the one cache. Does not exist, and a predetermined amount of data exists in the buffer for transmitting data from the one cache to the other hit cache, and the one cache is the most recent among the plurality of caches A predetermined amount of data exists in the buffer for transmitting data from the one cache to the least recently used cache among the plurality of caches, and is not used, and the one cache Sending data from one cache to the second least recently used cache among the plurality of caches When a predetermined amount of data does not exist in the buffer, the one cache entry is overwritten with the second least recently used cache entry, and the hit other cache entry is overwritten with the one cache entry. The cache system according to appendix 1, wherein the cache system is overwritten.
(Appendix 8)
When data requested by the processing device misses in all of the plurality of caches, the data is transmitted from one cache of the requested processing device to the least recently used cache among the plurality of caches. When a predetermined amount of data does not exist in the buffer, the entry of the one cache is moved to the entry of the least recently used cache, and the data read from the main storage device or a cache lower than the plurality of caches 2. The cache system according to appendix 1, wherein the entry of the moved one cache is overwritten.
(Appendix 9)
When data requested by the processing device misses in all of the plurality of caches, the data is transmitted from one cache of the requested processing device to the least recently used cache among the plurality of caches. There is a predetermined amount of data in the buffer, and there is no predetermined amount of data in the buffer for transmitting data from the one cache to the second least recently used cache among the plurality of caches. Sometimes the entry of the one cache is moved to the entry of the second least recently used cache, and the data read from the main storage device or the cache lower than the plurality of caches is moved to the cache of the moved one cache. The cache system according to appendix 1, wherein the entry is overwritten.
(Appendix 10)
When data requested by the processing device misses in all of the plurality of caches, the data is transmitted from one cache of the requested processing device to the least recently used cache among the plurality of caches. There is a predetermined amount of data in the buffer, and there is a predetermined amount of data in the buffer for transmitting data from the one cache to the second least recently used cache among the plurality of caches. 2. The cache system according to appendix 1, wherein data read from a main storage device or a cache lower than the plurality of caches is overwritten on an entry of the one cache.
(Appendix 11)
When data requested by the processing device misses in all of the plurality of caches, the data is transmitted from one cache of the requested processing device to the least recently used cache among the plurality of caches. A predetermined amount of data exists in the buffer, and there is a predetermined amount of data in the buffer for transmitting data from the one cache to the second least recently used cache among the plurality of caches. And when there is no predetermined amount of data in the buffer for transmitting data from the one cache to the third least recently used cache among the plurality of caches, the entry of the one cache is Move to the third least recently used cache entry and either main storage or the caches Cache system according to Supplementary Note 1, wherein the overwriting data read from the cache of the lower hierarchy than the Interview entry of one cache that the mobile.
(Appendix 12)
The cache system according to appendix 1, further comprising one information memory for storing the states of the plurality of buffers in a concentrated manner.
(Appendix 13)
The cache system according to appendix 1, further comprising a plurality of information memories for storing the states of the plurality of buffers in a distributed manner for each of the buffers.

It is a figure which shows the structural example of a shared distributed cache system. It is a figure which shows the detail of the 1st LRU information and 2nd LRU information of FIG. It is a figure which shows the other structural example of a shared distributed cache system. It is a figure which shows the detail of the 1st LRU information and 2nd LRU information of FIG. It is a flowchart which shows the data load access operation | movement in a shared distributed cache system. It is a flowchart which shows the exchange process of FIG.5 S7. It is a figure which shows the example of the exchange process of FIG. 6 in the system of FIG.1 and FIG.2. It is a figure which shows the example of the exchange process of FIG. 6 in the system of FIG.1 and FIG.2. It is a figure which shows the example of the exchange process of FIG. 6 in the system of FIG.1 and FIG.2. It is a flowchart which shows the eviction process of step S8 of FIG. It is a figure which shows the example of the eviction process of FIG. 10 in the system of FIG.1 and FIG.2. It is a figure which shows the example of the eviction process of FIG. 10 in the system of FIG.1 and FIG.2. It is a figure which shows the example of the eviction process of FIG. 10 in the system of FIG.1 and FIG.2. It is a figure which shows the structural example of the shared distributed cache system by embodiment of this invention. It is a flowchart which shows the exchange process of FIG.5 S7 in the cache system of FIG. It is a figure which shows the example of the ball hit process of step C13 of FIG. It is a figure which shows the example of the movement process of step C11 of FIG. FIG. 15 is a flowchart showing eviction processing in step S8 of FIG. 5 in the cache system of FIG. It is a figure which shows the example of the eviction process to the next candidate of step D10 of FIG. It is a figure which shows the structural example of the shared distributed cache system by other embodiment of this invention.

Explanation of symbols

101-103 core (processing equipment)
111 to 113 cache 130 main memory 1401 to 1403 transmission buffer 1411 to 1413 reception buffer 1421 information memory 1422 LRU information 1423 transmission / reception buffer information 1424 determination circuit 1425 inter-cache connection network

Claims (4)

A plurality of processing devices;
A plurality of caches connected one-to-one to the plurality of processing devices;
A network connected to the plurality of caches and performing data communication between the plurality of caches;
A plurality of buffers provided for each cache, the cache having data communication with the network;
When the data requested by the processing device misses in one cache, the cache performs data communication via the network according to the state of the plurality of buffers,
When the data requested by the processing device misses in one cache and hits in another cache, a predetermined amount of data is stored in the buffer for transmitting data from the hit other cache to the one cache. Does not exist, and a predetermined amount of data exists in the buffer for transmitting data from the one cache to the other hit cache, and the one cache is the most recent among the plurality of caches When the predetermined amount of data does not exist in the buffer for transmitting data from the one cache to the least recently used cache among the plurality of caches when not being used, Overwrite cache entry with the least recently used cache entry and hit Features and to Ruki catcher Tsu shoe system to overwrite the entry of another cache entry of the one of the cache. A plurality of processing devices;
A plurality of caches connected one-to-one to the plurality of processing devices;
A network connected to the plurality of caches and performing data communication between the plurality of caches;
A plurality of buffers provided for each cache, the cache having data communication with the network;
When the data requested by the processing device misses in one cache, the cache performs data communication via the network according to the state of the plurality of buffers,
When data requested by the processing device misses in all of the plurality of caches, the data is transmitted from one cache of the requested processing device to the least recently used cache among the plurality of caches. There is a predetermined amount of data in the buffer, and there is no predetermined amount of data in the buffer for transmitting data from the one cache to the second least recently used cache among the plurality of caches. Sometimes the entry of the one cache is moved to the entry of the second least recently used cache, and the data read from the main storage device or the cache lower than the plurality of caches is moved to the cache of the moved one cache. features and be Ruki turbocharger Tsu Gerhard system to overwrite the entry. When the data requested by the processing device misses in one cache and hits in another cache, a predetermined amount of data is stored in the buffer for transmitting data from the hit other cache to the one cache. When there is no predetermined amount of data in the buffer for transmitting data from the one cache to the other hit cache, the one cache entry and the other hit cache entry cache system according to claim 1 or 2, wherein the exchanging.   When data requested by the processing device misses in all of the plurality of caches, the data is transmitted from one cache of the requested processing device to the least recently used cache among the plurality of caches. When the predetermined amount of data does not exist in the buffer, the entry of the one cache is moved to the entry of the least recently used cache, and the data read from the main storage device or the cache at a lower hierarchy than the plurality of caches The cache system according to any one of claims 1 to 3, wherein an entry of the moved one cache is overwritten.

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