JP5100806B2 - Thin film magnetic memory device - Google Patents

Description

  The present invention relates to a thin film magnetic memory device, and more particularly to a random access memory including a memory cell having a magnetic tunnel junction (MTJ).

  An MRAM (Magnetic Random Access Memory) device has attracted attention as a storage device that can store nonvolatile data with low power consumption. An MRAM device is a storage device that performs non-volatile data storage using a plurality of thin film magnetic bodies formed in a semiconductor integrated circuit and allows random access to each of the thin film magnetic bodies.

  In particular, in recent years, it has been announced that the performance of an MRAM device is dramatically improved by using a thin film magnetic material using a magnetic tunnel junction (MTJ) as a memory cell. For MRAM devices with memory cells with magnetic tunnel junctions, see “A 10ns Read and Write Non-Volatile Memory Array Using a Magnetic Tunnel Junction and FET Switch in each Cell”, ISSCC Digest of Technical Papers, TA7.2, Feb 2000. and “Nonvolatile RAM based on Magnetic Tunnel Junction Elements”, ISSCC Digest of Technical Papers, TA7.3, Feb. 2000.

  FIG. 42 is a schematic diagram showing the configuration of a memory cell having a magnetic tunnel junction (hereinafter also simply referred to as an MTJ memory cell).

  Referring to FIG. 42, the MTJ memory cell includes a magnetic tunnel junction MTJ whose resistance value changes according to the data level of stored data, and an access transistor ATR. Access transistor ATR is formed of a field effect transistor, and is coupled between magnetic tunnel junction MTJ and ground voltage Vss.

  For MTJ memory cells, write word line WWL for instructing data writing, read word line RWL for instructing data reading, and the level of stored data at the time of data reading and data writing A bit line BL which is a data line for transmitting the electrical signal is disposed.

FIG. 43 is a conceptual diagram illustrating a data read operation from the MTJ memory cell.
Referring to FIG. 43, magnetic tunnel junction MTJ includes a magnetic layer (hereinafter also simply referred to as a fixed magnetic layer) FL having a fixed magnetic field in a fixed direction and a magnetic layer (hereinafter simply referred to as free magnetic field) having a free magnetic field. VL). A tunnel barrier TB formed of an insulator film is disposed between the fixed magnetic layer FL and the free magnetic layer VL. In the free magnetic layer VL, either one of the magnetic field in the same direction as that of the fixed magnetic layer FL and the magnetic field in a direction different from that of the fixed magnetic layer FL is nonvolatilely written in accordance with the level of stored data.

  At the time of data reading, access transistor ATR is turned on in response to activation of read word line RWL. As a result, a sense current Is supplied as a constant current from a control circuit (not shown) flows through a current path from the bit line BL to the magnetic tunnel junction MTJ to the access transistor ATR to the ground voltage Vss.

  The resistance value of the magnetic tunnel junction MTJ changes according to the relative relationship in the magnetic field direction between the fixed magnetic layer FL and the free magnetic layer VL. Specifically, when the magnetic field direction of the pinned magnetic layer FL and the magnetic field direction written in the free magnetic layer VL are the same, the resistance of the magnetic tunnel junction MTJ is greater than when both magnetic field directions are different. The value becomes smaller.

  Therefore, at the time of data reading, the voltage drop generated at the magnetic tunnel junction MTJ by the sense current Is differs depending on the magnetic field direction stored in the free magnetic layer VL. Thus, if the supply of the sense current Is is started after the bit line BL is once precharged to a high voltage, the level of the data stored in the MTJ memory cell is read by monitoring the voltage level change of the bit line BL. Can do.

FIG. 44 is a conceptual diagram illustrating a data write operation for the MTJ memory cell.
Referring to FIG. 44, at the time of data writing, read word line RWL is inactivated and access transistor ATR is turned off. In this state, a data write current for writing a magnetic field in free magnetic layer VL is supplied to write word line WWL and bit line BL. The magnetic field direction of free magnetic layer VL is determined by a combination of directions of data write currents flowing through write word line WWL and bit line BL, respectively.

  FIG. 45 is a conceptual diagram illustrating the relationship between the direction of the data write current and the magnetic field direction during data writing.

  Referring to FIG. 45, magnetic field Hx indicated by the horizontal axis indicates the direction of magnetic field H (WWL) generated by the data write current flowing through write word line WWL. On the other hand, the magnetic field Hy indicated on the vertical axis indicates the direction of the magnetic field H (BL) generated by the data write current flowing through the bit line BL.

  The magnetic field direction stored in the free magnetic layer VL is newly written only when the sum of the magnetic fields H (WWL) and H (BL) reaches the region outside the asteroid characteristic line shown in the figure. . That is, when a magnetic field corresponding to the region inside the asteroid characteristic line is applied, the magnetic field direction stored in the free magnetic layer VL is not updated.

  Therefore, in order to update the data stored in the magnetic tunnel junction MTJ by the write operation, it is necessary to pass a current through both the write word line WWL and the bit line BL. The magnetic field direction once stored in the magnetic tunnel junction MTJ, that is, the stored data is held in a nonvolatile manner until new data writing is executed.

  Even during the data read operation, sense current Is flows through bit line BL. However, since the sense current Is is generally set to be about 1 to 2 digits smaller than the data write current described above, the stored data in the MTJ memory cell is erroneously read at the time of data reading due to the influence of the sense current Is. The possibility of rewriting is small.

  The above-described technical literature discloses a technique for constructing an MRAM device that is a random access memory by integrating such MTJ memory cells on a semiconductor substrate.

“A 10ns Read and Write Non-Volatile Memory Array Using a Magnetic Tunnel Junction and FET Switch in each Cell”, ISSCC Digest of Technical Papers, TA7.2, Feb. 2000. and “Nonvolatile RAM based on Magnetic Tunnel Junction Elements”, ISSCC Digest of Technical Papers, TA7.3, Feb. 2000.

FIG. 46 is a conceptual diagram showing MTJ memory cells integrated and arranged in a matrix.
Referring to FIG. 46, a highly integrated MRAM device can be realized by arranging MTJ memory cells in a matrix on a semiconductor substrate. FIG. 46 shows a case where MTJ memory cells are arranged in n rows × m columns (n, m: natural numbers).

  As already described, it is necessary to arrange the bit line BL, the write word line WWL, and the read word line RWL for each MTJ memory cell. Therefore, n write word lines WWL1 to WWLn and read word lines RWL1 to RWLn and m bit lines BL1 to BLn are arranged for n × m MTJ memory cells arranged in a matrix. There is a need.

  As described above, an MTJ memory cell is generally provided with an independent word line corresponding to each of the read operation and the write operation.

FIG. 47 is a structural diagram of an MTJ memory cell arranged on a semiconductor substrate.
47, access transistor ATR is formed in p type region PAR on semiconductor main substrate SUB. Access transistor ATR has source / drain regions 110 and 120 which are n-type regions, and a gate 130. Source / drain region 110 is coupled to ground voltage Vss through a metal wiring formed in first metal wiring layer M1. For the write word line WWL, a metal wiring formed in the second metal wiring layer M2 is used. The bit line BL is provided in the third metal wiring layer M3.

  The magnetic tunnel junction MTJ is disposed between the second metal wiring layer M2 provided with the write word line WWL and the third metal wiring layer M3 provided with the bit line BL. Source / drain region 120 of access transistor ATR is connected to magnetic tunnel junction MTJ through metal film 150 formed in the contact hole, first and second metal wiring layers M1 and M2, and barrier metal 140. Electrically coupled. The barrier metal 140 is a cushioning material provided to electrically couple the magnetic tunnel junction MTJ and the metal wiring.

  As already described, in the MTJ memory cell, the read word line RWL is provided as a wiring independent of the write word line WWL. The write word line WWL and the bit line BL need to pass a data write current for generating a magnetic field having a magnitude greater than a predetermined value at the time of data writing. Therefore, the bit line BL and the write word line WWL are formed using metal wiring.

  On the other hand, the read word line RWL is provided to control the gate voltage of the access transistor ATR, and it is not necessary to actively flow a current. Therefore, from the viewpoint of increasing the degree of integration, the read word line RWL is formed using a polysilicon layer or a polycide structure in the same wiring layer as the gate 130 without newly providing an independent metal wiring layer. .

  With such a configuration, the number of metal wiring layers can be suppressed and the MTJ memory cells can be integrated and arranged on the semiconductor substrate. However, since the read word line RWL is formed of a polysilicon layer or the like, the resistance value becomes relatively large. As a result, the signal propagation delay in the read word line RWL is increased during data reading, which hinders the speeding up of the data reading operation.

  As a structure of an MTJ memory cell that can be further integrated as compared with the MTJ memory cell shown in FIG. 42, a configuration using a PN junction diode as an access element instead of an access transistor is known.

FIG. 48 is a schematic diagram showing a configuration of an MTJ memory cell using a diode.
Referring to FIG. 48, an MTJ memory cell MCDD using a diode includes a magnetic tunnel junction MTJ and an access diode DM. Access diode DM is coupled between the two, with the direction from magnetic tunnel junction MTJ to word line WL as the forward direction. Bit line BL is provided in a direction crossing word line WL, and is coupled to magnetic tunnel junction MTJ.

  Data writing to the MTJ memory cell MCDD is performed by supplying a data write current to the word line WL and the bit line BL. The direction of the data write current is set according to the data level of the write data, as in the case of the memory cell using the access transistor.

  On the other hand, at the time of data reading, word line WL corresponding to the selected memory cell is set to a low voltage (for example, ground voltage Vss) state. At this time, by precharging the bit line BL to a high voltage (for example, power supply voltage Vcc) state, the access diode DM becomes conductive and the sense current Is can flow to the magnetic tunnel junction MTJ. On the other hand, since the word line WL corresponding to the non-selected memory cell is set to the high voltage state, the corresponding access diode DM maintains the off state, and the sense current Is does not flow.

  In this manner, data reading and data writing can be executed also in an MTJ memory cell using an access diode.

  FIG. 49 is a structural diagram when the MTJ memory cell shown in FIG. 48 is arranged on a semiconductor substrate.

  Referring to FIG. 49, an access diode DM is formed by N-type region NWL on semiconductor main substrate SUB and P-type region PAR provided on N-type region NWL. FIG. 49 shows an N-type well as an example of forming the N-type region.

  N-type region NWL corresponding to the cathode of access diode DM is coupled to word line WL arranged in metal interconnection layer M1. P-type region PAR corresponding to the anode of access diode DM is electrically coupled to magnetic tunnel junction MTJ through barrier metal 140 and metal film 150. Bit line BL is arranged in metal interconnection layer M2 and coupled to magnetic tunnel junction MTJ. In this way, by using an access diode instead of an access transistor, an MTJ memory cell advantageous for high integration can be configured.

  However, since data write current flows through word line WL and bit line BL at the time of data writing, a voltage drop due to the data write current occurs in these wirings. As a result of such a voltage drop, depending on the voltage distribution on the word line WL and the bit line BL, the PN junction of the access diode DM is turned on in a part of the MTJ memory cell not subjected to data writing. There is a risk that. As a result, an unexpected current may flow through the MTJ memory cell, which may cause erroneous data writing.

  As described above, the conventional MTJ memory cell using the access diode is advantageous for high integration, but has a problem that the data writing operation becomes unstable.

  The present invention has been made to solve such problems, and an object of the present invention is to speed up and stabilize a data read operation in an MRAM device having MTJ memory cells. .

  The thin film magnetic memory device according to claim 1 includes a memory array having a plurality of magnetic memory cells arranged in a matrix, each of the plurality of magnetic memory cells including a first data write and a second data write Including a storage unit whose resistance value changes in accordance with the level of stored data to be written when the data write magnetic field applied by the current is larger than a predetermined magnetic field, each provided corresponding to a row of magnetic memory cells, A plurality of write word lines formed of wiring having a first resistivity are further provided, and each of the plurality of write word lines corresponds to a row selection result in both data writing and data reading. A current path of a first data write current is selectively activated and activated for at least one of the plurality of write word lines in each of data writing and data reading. A word line current control circuit for forming and blocking each, a plurality of data lines provided corresponding to the columns of the magnetic memory cells, and a second in each of data writing and data reading A read / write control circuit for causing each of the data write current and the data read current to flow through one of the plurality of data lines corresponding to the selected column, and a row of the magnetic memory cell A plurality of read word lines each formed by a wiring having a second resistivity higher than the first resistivity, and each read word line corresponds to a row selection result in data reading. It is selectively activated together with the corresponding write word line.

  The thin film magnetic memory device according to claim 2 is the thin film magnetic memory device according to claim 1, wherein the memory array is divided into a plurality of regions along the column direction, and the plurality of read word lines include a plurality of read word lines. Each of the plurality of write word lines is arranged in common in the plurality of regions, and the thin film magnetic memory device includes a plurality of read word lines provided corresponding to the plurality of read word lines, respectively. A read word line driver is further provided, and each of the plurality of read word line drivers includes a plurality of read word lines in response to activation of a corresponding one of the plurality of write word lines during data reading. Activate the corresponding one of.

  The thin film magnetic memory device according to claim 3 is the thin film magnetic memory device according to claim 1, wherein the word line drive for selectively activating a plurality of write word lines in accordance with a row selection result. The word line drive circuit further includes a first data write current for each of data write and data read for at least one of the plurality of write word lines activated. And a charging current are respectively supplied, and a magnetic field generated by the charging current is smaller than a predetermined magnetic field.

  The thin film magnetic memory device according to claim 4 is the thin film magnetic memory device according to claim 3, wherein the word line drive circuit includes a plurality of first and second word lines provided corresponding to a plurality of write word lines, respectively. Each of the plurality of first current supply circuits includes a second current supply circuit, and corresponds to the first data write current when the corresponding write word line is activated during data writing. Each of the plurality of second current supply circuits supplies a charging current to the corresponding write word line when the corresponding write word line is activated during data reading. To do.

  The thin film magnetic memory device according to claim 5 is the thin film magnetic memory device according to claim 3, wherein the word line drive circuit has a first data write current corresponding to a first data write current during data write. A first current supply transistor for supplying an operating current, a second current supply transistor for supplying a second operating current corresponding to a charging current during data reading, and a plurality of write word lines are provided. Each of the plurality of current supply circuits is supplied from one of the first and second current supply transistors when the corresponding write word line is activated. One of the first and second operating currents is supplied to the corresponding write word line.

  The thin film magnetic memory device according to claim 6 is the thin film magnetic memory device according to claim 1, wherein the data write magnetic field is formed by a sum of magnetic fields respectively generated by the first and second data write currents. The direction of the first data write current is constant regardless of the level of the stored data to be written, and the direction of the second data write current varies depending on the level of the stored data to be written. Set to

  The thin film magnetic memory device according to claim 7 is the thin film magnetic memory device according to claim 6, wherein the word line current control circuit is lower than the voltages of the plurality of write word lines in the activated state. A plurality of switch circuits provided between a power supply node for supplying a voltage and a plurality of write word lines are included, and the plurality of switch circuits are turned on at the time of data writing.

  The thin-film magnetic memory device according to claim 8 is the thin-film magnetic memory device according to claim 1, wherein the first and second word lines for activating each of the plurality of write word lines and the read word lines at the time of data reading are provided. The plurality of write word lines and the plurality of read word lines are arranged so that the first and second magnetic fields generated in the storage unit are canceled by the second charging current, respectively.

  The thin-film magnetic memory device according to claim 9 is the thin-film magnetic memory device according to claim 8, wherein the plurality of write word lines and the plurality of read word lines are formed on the semiconductor substrate. Are arranged so as to be sandwiched in the height direction.

  The thin film magnetic memory device according to claim 10 is the thin film magnetic memory device according to claim 2, wherein each of the plurality of read word line drivers is selected from a plurality of regions selected in accordance with a column selection result. In one of the above, activation of a plurality of read word lines at the time of data reading is executed.

  The thin film magnetic memory device according to an eleventh aspect is the thin film magnetic memory device according to the tenth aspect, wherein the read / write control circuit is divided for each of a plurality of regions.

  The thin film magnetic memory device according to claim 12 is the thin film magnetic memory device according to claim 1, wherein each of the plurality of read word lines corresponds to the plurality of write word lines at at least one node. Electrically coupled to one.

  The thin film magnetic memory device according to claim 13 is the thin film magnetic memory device according to claim 12, wherein the current flowing through the plurality of storage units and the plurality of data lines is forced during data writing. And a current interrupt circuit for interrupting.

  The thin film magnetic memory device according to claim 14 is the thin film magnetic memory device according to claim 12, wherein each magnetic memory cell is further formed of a field effect transistor formed on a semiconductor substrate. The access transistor includes a first source / drain region coupled to a read reference voltage, a second source / drain region electrically coupled to the storage unit, and a plurality of read word lines And a plurality of write word lines are formed on one of the first and second metal wiring layers disposed above the access transistor, close to the access transistor. Each data line is formed on the other of the first and second metal wiring layers.

  The thin film magnetic memory device according to claim 15 is the thin film magnetic memory device according to claim 12, wherein each magnetic memory cell is further activated by a corresponding one of the plurality of read word lines. In response to, an access transistor for electrically coupling the memory portion between a corresponding one of the plurality of data lines and the read reference voltage, each of the plurality of data lines prior to data reading. The read / write control circuit applies a voltage different from the read reference voltage to only one of the plurality of data lines corresponding to the selected column of the magnetic memory cells during data reading. Combine with.

  The thin film magnetic memory device according to claim 16 is the thin film magnetic memory device according to claim 1, and is provided along the same direction as the plurality of data lines corresponding to the columns, each of which is a read reference. A plurality of source lines for supplying a voltage are further provided, and the sum of the wiring resistances of the portions included in the path of the data read current of the source line and the data line corresponding to the selected column is selected during data reading. The plurality of source lines and the plurality of data lines are arranged so as to be substantially constant without depending on the formed rows.

  The thin film magnetic memory device according to claim 17 is the thin film magnetic memory device according to claim 16, wherein each source line is coupled to a read reference voltage at one end of the memory array, and each data line is connected to the memory Connected to the read / write control circuit at the other end of the array and supplied with a data read current, each source line and data line are designed to have the same wiring resistance per unit length.

  The thin-film magnetic memory device according to claim 18 is the thin-film magnetic memory device according to claim 1, and corresponds to each of the rows along the same direction as the plurality of read word lines and the plurality of write word lines. A plurality of source lines, and a plurality of source lines and a read reference voltage, which are electrically coupled to each other, each of which activates and deactivates a corresponding one of a plurality of write word lines And a plurality of current cut-off switches that are turned on and off, respectively.

  The thin-film magnetic memory device according to claim 19 is the thin-film magnetic memory device according to claim 1, wherein the thin-film magnetic memory device corresponds to each row along the same direction as the plurality of read word lines and the plurality of write word lines. And a plurality of source lines each supplying a read reference voltage. The read / write control circuit is provided between a global data line provided along the same direction as the plurality of source lines and between the global data line and the plurality of data lines, and each is turned on according to the column selection result. A plurality of column selection gates and a data read circuit for supplying a data read current to the global data line at the time of data reading are included. At the time of data reading, the sum of the wiring resistances of the portion included in the data read current path between the source line corresponding to the selected row and the global data line does not depend on the column of the selected magnetic memory cell. A plurality of source lines and global data lines are arranged so as to be substantially constant.

  The thin film magnetic memory device according to claim 20 is the thin film magnetic memory device according to claim 19, wherein each source line is coupled to a read reference voltage at one end of the memory array, and the global data line is connected to the memory The other end of the array is connected to the read / write control circuit, and the wiring resistance per unit length of the global data line and each source line is designed to be the same value.

  The thin film magnetic memory device according to claim 21 is the thin film magnetic memory device according to claim 1, wherein the thin film magnetic memory device is in the same direction as the plurality of read word lines and the plurality of write word lines corresponding to each row. A plurality of source lines each for supplying a read reference voltage and a common for the magnetic memory cells along the same direction as the plurality of data lines, the read reference voltage and the plurality of source lines And a dummy data line that is electrically coupled to each other. At the time of data reading, the sum of the wiring resistances of the data line corresponding to the selected column and the dummy data line in the portion included in the path of the data read current is substantially constant regardless of the selected row. In addition, a plurality of data lines and dummy data lines are arranged.

  The thin film magnetic memory device according to claim 22 is the thin film magnetic memory device according to claim 21, wherein the dummy data line is coupled to a read reference voltage at one end of the memory array, and each data line is connected to the memory On the other end side of the array, connected to a read / write control circuit and supplied with a data read current, the wiring resistance per unit length of each data line and dummy data line is designed to be the same value.

  The thin-film magnetic memory device according to claim 23 is the thin-film magnetic memory device according to claim 1, wherein the thin-film magnetic memory device corresponds to each row along the same direction as the plurality of read word lines and the plurality of write word lines. A plurality of source lines each supplying a read reference voltage and dummy data provided along the same direction as the plurality of data lines and electrically coupled to each of the read reference voltage and the plurality of source lines And a line. At the time of data reading, the sum of the wiring resistances of the portion included in the data read current path between the source line corresponding to the selected row and the global data line is substantially constant regardless of the selected column. In addition, a plurality of source lines and global data lines are arranged, and at the time of data reading, the sum of the wiring resistances of the portions included in the data read current path between the data line corresponding to the selected column and the dummy data line is The plurality of data lines and the dummy data lines are arranged so as to be substantially constant without depending on the selected row.

  A thin film magnetic memory device according to claim 24 is the thin film magnetic memory device according to any one of claims 16 to 23, wherein each magnetic memory cell further activates a corresponding read word line. A memory cell select gate for conducting data read current through the memory portion in response to the memory portion; the memory cell select gate including a diode element coupled between the memory portion and a corresponding read word line; .

  26. The thin film magnetic memory device according to claim 25, comprising a memory array having a plurality of magnetic memory cells arranged in rows and columns, wherein each of the plurality of magnetic memory cells has first and second data writing. A storage unit whose resistance value changes according to the level of stored data to be written when the data write magnetic field applied by the current is larger than a predetermined magnetic field, and a data read current is passed through the storage unit during data reading A plurality of write word lines, each of which is provided corresponding to a row of the magnetic memory cell and constitutes a write word line pair for each of the two rows. The two write word lines constituting the word line pair are electrically coupled at one end of the memory array at least at the time of data writing and arranged at the other end of the memory array. In order to cause the first data write current to flow, each of the two write word lines constituting the write word line pair corresponding to the selected row is set to one of the first and second voltages. Word line drive circuit for setting, a plurality of data lines provided corresponding to the columns of magnetic memory cells, and a data line corresponding to the selected column in each of data writing and data reading In contrast, a read / write control circuit for supplying a second data write current and a data read current, and a magnetic memory cell, respectively, are provided corresponding to the rows of the magnetic memory cells. A plurality of read word lines for conducting the corresponding memory cell selection gate according to the row selection result are further provided.

  The thin-film magnetic memory device according to claim 26 is the thin-film magnetic memory device according to claim 25, wherein each write word line is formed of a wiring having a first resistivity, and each read word line is , Formed of wiring having a second resistivity higher than the first resistivity, and arranged at one end side of the memory array in correspondence with the write word line pair, respectively, for data writing and data Each of the read word lines further includes a plurality of short-circuit switch circuits for electrically coupling and disconnecting between two corresponding write word lines at the time of reading, and each read word line has a row selection result at the time of data reading. Are selectively activated together with the corresponding write word line.

  The thin film magnetic memory device according to claim 27 is the thin film magnetic memory device according to claim 26, wherein each read word line includes one line corresponding to the same row of a plurality of write word lines. Electrically coupled.

  The thin film magnetic memory device according to claim 28 is the thin film magnetic memory device according to claim 26, wherein the memory array is divided into a plurality of regions along the column direction, and the plurality of read word lines are divided into a plurality of read word lines. Each of the plurality of write word lines is arranged in common in the plurality of regions, and the thin film magnetic memory device includes a plurality of read word lines provided corresponding to the plurality of read word lines, respectively. A read word line driver is further provided, and the word line drive circuit activates a write word line corresponding to the selected row during data reading, and each of the plurality of read word line drivers includes a plurality of read word line drivers during data reading. In response to activation of the corresponding one of the write word lines, the corresponding one of the plurality of read word lines is activated.

  A thin-film magnetic memory device according to claim 29 is the thin-film magnetic memory device according to claim 25, wherein two write lines constituting a write word line pair corresponding to a selected row in the memory array are provided. A combination of the first data write current that flows through the word line as a round-trip current and the second data write current that flows through the data line corresponding to the selected column causes one magnetic memory cell to A plurality of magnetic memory cells are arranged so that data writing is performed.

  30. The thin film magnetic memory device according to claim 30, comprising a memory array having a plurality of magnetic memory cells arranged in rows and columns, wherein each of the plurality of magnetic memory cells has first and second data writing. A storage unit whose resistance value changes according to the level of stored data to be written when the data write magnetic field applied by the current is larger than a predetermined magnetic field, and a data read current is passed through the storage unit during data reading A plurality of write word lines provided corresponding to the rows of magnetic memory cells, each of which is shared by two rows, and a plurality of write word lines. Word line current control for forming and blocking the current path of the first data write current in each of data writing and data reading with respect to at least one activated , A word line drive circuit for activating a write word line corresponding to a selected row in each of data reading and data writing, and a column corresponding to a column of magnetic memory cells, respectively. Read for supplying a second data write current and a data read current to the data lines corresponding to the selected column at the time of data writing and data reading, respectively, A write control circuit and a plurality of read word lines each provided corresponding to a row of magnetic memory cells, each for conducting a corresponding memory cell selection gate in accordance with a row selection result in data reading With. Each read word line is selectively activated together with a corresponding write word line in accordance with a row selection result at the time of data reading.

  The thin film magnetic memory device according to claim 31 is the thin film magnetic memory device according to claim 30, wherein each write word line is formed of a wiring having a first resistivity, and each read word line is A first data write current formed by a wiring having a second resistivity higher than the first resistivity and flowing in a write word corresponding to a selected row in the memory array, The plurality of magnetic memory cells are arranged such that data writing is performed on one magnetic memory cell by a combination with the second data write current that is passed through the data line corresponding to the column. .

  The thin film magnetic memory device according to claim 32 is the thin film magnetic memory device according to claim 30, wherein each read word line is electrically coupled to a corresponding one of the plurality of write word lines. Is done.

  The thin film magnetic memory device according to claim 33 is the thin film magnetic memory device according to claim 30, wherein the memory array is divided into a plurality of regions along the column direction, and the plurality of read word lines are divided into a plurality of read word lines. Each of the plurality of write word lines is shared by adjacent rows and is commonly disposed in the plurality of regions. The thin film magnetic memory device includes a plurality of read word lines. And a plurality of read word line drivers provided corresponding to each of the plurality of read word line drivers, each of the plurality of read word line drivers including information indicating whether an even-numbered row or an odd-numbered row is selected during data reading; The corresponding read word line is activated in response to activation of the corresponding one of the write word lines.

  The thin film magnetic memory device according to claim 34 is the thin film magnetic memory device according to any one of claims 25 to 33, wherein the memory cell selection gate is provided between the memory portion and the corresponding read word line. Including diode elements to be coupled.

  The thin film magnetic memory device according to claim 35 includes a memory array having a plurality of magnetic memory cells arranged in a matrix, the memory array being divided into a plurality of regions along the column direction, Each of the body memory cells includes a storage unit whose resistance value changes according to the level of stored data to be written when the data write magnetic field applied by the first and second data write currents is larger than a predetermined magnetic field. Including a plurality of write word lines each provided corresponding to a row of magnetic memory cells and formed with a wiring having a first resistivity. A plurality of embedded word lines are selectively activated according to the row selection result to flow the first data write current during data writing, and are provided corresponding to the columns of the magnetic memory cells, respectively. Data line and Read data for flowing each of second data write current and data read current to one corresponding to the selected column of the plurality of data lines in each of data writing and data reading Control circuit, a plurality of main read word lines that are provided in common to a plurality of regions and formed of wiring having a second resistivity, and each region corresponds to a row of magnetic memory cells And a plurality of read word lines formed by wiring having a third resistivity higher than the first and second resistivity, and each of the plurality of read word lines includes a plurality of main lines. A plurality of read word line drivers corresponding to any one of the read word lines and provided corresponding to the plurality of read word lines, respectively, are further provided. There are, in response to a corresponding one of the activation of a plurality of main read word line, and activates the corresponding one of the plurality of read word lines.

  The thin film magnetic memory device according to claim 36 is the thin film magnetic memory device according to claim 35, wherein the thin film magnetic memory device is formed on a semiconductor substrate, and each of the plurality of main read word lines is formed in a plurality of rows of the magnetic memory cells. The plurality of main read word lines are formed on the same metal line layer as the plurality of write word lines.

  A thin-film magnetic memory device according to claim 37 is the thin-film magnetic memory device according to claim 35, wherein the thin-film magnetic memory device is formed on a semiconductor substrate, and each of the plurality of main read word lines includes a plurality of rows of magnetic memory cells. Each of the magnetic memory cells has an access transistor for allowing a data read current to pass through the storage portion at the time of data reading, and the plurality of main read word lines are arranged on a plurality of layers above the access transistor. Of the metal wiring layers, the first metal wiring layer closest to the access transistor is formed.

  39. The thin film magnetic memory device according to claim 38, comprising a memory array having a plurality of magnetic memory cells arranged in a matrix, wherein each of the plurality of magnetic memory cells has first and second data writing. A plurality of storage units each having a resistance value that changes in accordance with the level of stored data to be written when the data write magnetic field applied by the current is larger than a predetermined magnetic field, each provided corresponding to a column of magnetic memory cells. Each of the second data write current and the data read current is set to one corresponding to the selected column of the plurality of data lines in each of the data lines and at the time of data writing and data reading. A read / write control circuit for flowing and a plurality of word lines provided corresponding to the rows of the magnetic memory cells, respectively, and corresponding one voltage among the plurality of word lines According to the level, a first current path including a plurality of corresponding storage units and a plurality of data lines is formed, and a second current path for flowing the first data write current at the time of data writing Is formed on a plurality of word lines, and at the time of data reading, the word line current control circuit cuts off the second current path in the plurality of word lines.

  The thin film magnetic memory device according to claim 39 is the thin film magnetic memory device according to claim 38, wherein the access transistor is a field effect transistor formed on a semiconductor substrate, and the gate of the access transistor is A plurality of word lines are formed in the same layer as the gate.

  The thin film magnetic memory device according to claim 40 is the thin film magnetic memory device according to claim 38, further comprising a current interrupt circuit for forcibly interrupting the first current path during data writing. .

  The thin film magnetic memory device according to the first, second, and twelfth aspects can reduce the signal propagation delay of the read word line and speed up the data read operation.

  The thin film magnetic memory device according to any one of claims 3 to 5 has a sufficient amount of current for data writing at the time of data writing in addition to the effect exhibited by the thin film magnetic memory device according to claim 1. In addition, the data stored in the magnetic memory cell can be prevented from being destroyed by the current flowing through the write word line during data reading.

  The thin film magnetic memory device according to the sixth and seventh aspects can simplify the configuration of the word line current control circuit in addition to the effect exhibited by the thin film magnetic memory device according to the first aspect.

  The thin film magnetic memory device according to claims 8 and 9 has a charging current transiently generated in the write word line and the read word line at the time of data reading in addition to the effect exhibited by the thin film magnetic memory device according to claim 1. Therefore, it is possible to prevent the data stored in the magnetic memory cell from being destroyed.

  The thin film magnetic memory device according to claim 10 performs the data read operation only in the region including the magnetic memory cell to be accessed for data in addition to the effect exhibited by the thin film magnetic memory device according to claim 2. Therefore, low power consumption can be achieved.

  The thin film magnetic memory device according to claim 11 can execute independent data reading and data writing operations in each of the plurality of regions, in addition to the effect exhibited by the thin film magnetic memory device according to claim 10. .

  The thin-film magnetic memory device according to claim 13 has the effect produced by the thin-film magnetic memory device according to claim 12 and prevents unnecessary leakage current from being generated in the magnetic memory cell during data writing. , Low power consumption can be achieved.

  The thin film magnetic memory device according to claim 14 has a simple vertical structure using two metal wiring layers, in addition to the effect exhibited by the thin film magnetic memory device according to claim 12. The cell can be formed on a semiconductor substrate.

  The thin-film magnetic memory device according to claim 15 needs to charge only the data line corresponding to the selected column in addition to the effect exhibited by the thin-film magnetic memory device according to claim 12, and corresponds to the other columns. This eliminates the need to supply a charging current for precharging the data line to be read each time data is read. As a result, power consumption in the memory array can be reduced.

  The thin film magnetic memory device according to the sixteenth, seventeenth, nineteenth and twentieth aspects of the present invention has the effect of the data read current regardless of the selected memory cell row in addition to the effect exhibited by the thin film magnetic memory device according to the first aspect. Since the sum of the resistance values of the data line and the source line included in the current path can be maintained substantially constant, it is possible to prevent the data read current from fluctuating depending on the position of the selected memory cell row. As a result, the operation margin at the time of data reading in the memory array can be kept uniform, and the operation margin of the entire thin film magnetic memory device can be sufficiently secured.

  The thin film magnetic memory device according to claim 18 shares the voltage of the write word line or the row decode signal with the control signal of the current cut-off switch in addition to the effect exhibited by the thin film magnetic memory device according to claim 1. Can do. As a result, the configuration of the peripheral circuit can be simplified.

  The thin film magnetic memory device according to claims 21 and 22 is included in the current path of the data read current regardless of the selected memory cell column, in addition to the effect exhibited by the thin film magnetic memory device according to claim 1. Since the sum of the resistance values of the source line and the global data line can be maintained almost constant, it is possible to prevent the data read current from fluctuating depending on the position of the selected memory cell column. As a result, the operation margin at the time of data reading in the memory array can be kept uniform, and the operation margin of the entire thin film magnetic memory device can be sufficiently secured.

  The thin film magnetic memory device according to claim 23 has a data read current substantially equal to the row and column to which the selected magnetic memory cell belongs in addition to the effect exhibited by the thin film magnetic memory device according to claim 1. Can be kept constant. As a result, the operation margin at the time of data reading in the memory array can be kept uniform, and the operation margin of the entire thin film magnetic memory device can be sufficiently secured.

  The thin film magnetic memory device according to a twenty-fourth aspect of the present invention can be arranged with higher integration of the magnetic memory cells in addition to the effects exhibited by the thin film magnetic memory device according to the sixteenth to twenty-third aspects.

  In the thin film magnetic memory device according to the 25th and 29th aspects, a reciprocal current path is formed by the write word line pair corresponding to the selected memory cell row to flow the data write current. As a result, the configuration of the word line drive circuit can be simplified because row selection may be performed by selecting write word line pairs that are half the number of write word lines. Further, the magnetic field generated around the magnetic memory cell acts in a direction to cancel each other by the data write currents flowing through the two write word lines constituting the write word line pair corresponding to the selected memory cell row. Therefore, magnetic field noise with respect to the periphery of the memory cell can be reduced.

  In the thin film magnetic memory device according to the twenty-sixth, twenty-seventh and twenty-eighth aspects, it is possible to reduce the signal propagation delay of the read word line having a relatively large resistance value and to speed up the data read operation.

  The thin film magnetic memory device according to any one of claims 30 to 33 reduces the signal propagation delay of the read word line, speeds up the data read operation, and shares the write word line WWL to reduce the wiring pitch. It is possible to secure the cross-sectional area easily. For this reason, by reducing the current density of the write word line, the occurrence of electromigration can be suppressed and the operation reliability can be improved.

  A thin film magnetic memory device according to a thirty-fourth aspect of the present invention can be provided with higher integration of magnetic memory cells in addition to the effects exhibited by the thin film magnetic memory device according to the twenty-fifth to thirty-third aspects.

  The thin film magnetic memory device according to claim 35 reduces the signal propagation delay by hierarchizing the read word lines. As a result, the data read operation can be speeded up by independently controlling the read word line and the write word line.

  The thin film magnetic memory device according to claims 36 and 37 is provided with a new metal wiring layer by suppressing the number of main read word lines in addition to the effect exhibited by the thin film magnetic memory device according to claim 35. The main read word line can be formed on the semiconductor substrate without any problem.

  In the thin film magnetic memory device according to the thirty-eighth aspect, since the word line can be shared both at the time of data reading and at the time of data writing, the number of wirings can be reduced and the data reading operation can be speeded up.

  The thin-film magnetic memory device according to claim 39 has an efficient layout on the semiconductor substrate because the word line can be arranged in the gate region of the access transistor in addition to the effect exhibited by the thin-film magnetic memory device according to claim 38. Can be formed.

  The thin film magnetic memory device according to claim 40 has the effect produced by the thin film magnetic memory device according to claim 38 and prevents unnecessary leakage current from being generated in the magnetic memory cell during data writing. , Low power consumption can be achieved.

It is a schematic block diagram which shows the whole structure of the MRAM device 1 according to Embodiment 1 of this invention. 2 is a diagram for illustrating in detail the configuration of memory array 10 according to the first embodiment. FIG. 6 is a timing chart illustrating data reading and data writing operations for memory array 10 according to the first embodiment. It is a conceptual diagram explaining the direction of the magnetic field produced in the data write current and MTJ memory cell at the time of data writing. 3 is a circuit diagram illustrating a configuration example of a word line driver 30. FIG. FIG. 6 is a circuit diagram showing another configuration example of the word line driver 30. 2 is a structural diagram of an MTJ memory cell formed on a semiconductor substrate. FIG. FIG. 10 is a diagram for illustrating a configuration of a memory array 10 according to a first modification of the first embodiment. FIG. 10 is a diagram for illustrating a configuration of a memory array 10 according to a second modification of the first embodiment. FIG. 7 is a diagram for illustrating a configuration of a memory array 10 according to the second embodiment. FIG. 6 is a structural diagram illustrating a first example of the arrangement of main read word lines MRWL. FIG. 10 is a structural diagram illustrating a second example of the arrangement of main read word lines MRWL. FIG. 10 is a structural diagram illustrating a third example of the arrangement of main read word lines MRWL. It is a figure for demonstrating the structure of the memory array 10 according to Embodiment 3. FIG. FIG. 11 is a structural diagram showing an arrangement of word lines according to a third embodiment. 14 is a timing chart illustrating data reading and data writing operations for memory array 10 according to the third embodiment. FIG. 11 is a diagram for illustrating a configuration of a memory array 10 according to a first modification of the third embodiment. 12 is a timing chart illustrating data reading and data writing operations for memory array 10 according to the first modification of the third embodiment. FIG. 11 is a diagram for illustrating a configuration of a memory array 10 according to a second modification of the third embodiment. FIG. 16 is a timing chart illustrating data reading and data writing operations for memory array 10 according to a second modification of the third embodiment. FIG. 11 is a structural diagram of an MTJ memory cell according to modification examples 1 and 2 of the third embodiment arranged on a semiconductor substrate. FIG. 11 is a diagram for illustrating a configuration of a memory array 10 according to a third modification of the third embodiment. FIG. 14 is a diagram for illustrating a configuration related to data reading of memory array 10 and its peripheral circuits according to a fourth embodiment of the present invention. FIG. 14 is a timing chart illustrating data reading and data writing operations for memory array 10 according to the fourth embodiment. FIG. 14 is a structural diagram showing an arrangement example of source lines SL according to the fourth embodiment. FIG. 17 is a diagram for illustrating a configuration related to data reading of memory array 10 and its peripheral circuits according to a first modification of the fourth embodiment of the present invention. FIG. 17 is a diagram for illustrating a configuration related to data reading of memory array 10 and its peripheral circuits according to a second modification of the fourth embodiment of the present invention. FIG. 16 is a conceptual diagram illustrating the arrangement of write word lines WWL according to the fifth embodiment. FIG. 16 is a diagram for illustrating a configuration of a memory array 10 and its peripheral circuits according to a first modification of the fifth embodiment. FIG. 16 is a diagram for illustrating a configuration of a memory array 10 and its peripheral circuits according to a second modification of the fifth embodiment. FIG. 29 is a timing chart for describing a row selection operation in the memory array according to the second modification of the fifth embodiment. It is a figure for demonstrating the structure of the memory array 10 according to the modification 3 of Embodiment 5, and its peripheral circuit. It is a figure for demonstrating the structure of the memory array 10 according to the modification 4 of Embodiment 5, and its peripheral circuit. FIG. 29 is a timing chart for illustrating a row selection operation in the memory array according to the fourth modification of the fifth embodiment. FIG. 11 shows a structure of an MTJ memory cell according to a sixth embodiment. FIG. 3 is a structural diagram when an MTJ memory cell MCD is arranged on a semiconductor substrate. 5 is a timing chart for explaining a read operation and a write operation with respect to an MTJ memory cell MCD. It is a figure for demonstrating the structure of the memory array 10 according to Embodiment 6, and its peripheral circuit. FIG. 22 is a diagram for describing a configuration of a memory array 10 and its peripheral circuits according to a first modification of the sixth embodiment. It is a figure for demonstrating the structure of the memory array 10 according to the modification 2 of Embodiment 6, and its peripheral circuit. It is a figure for demonstrating the structure of the memory array 10 according to the modification 3 of Embodiment 6, and its peripheral circuit. It is the schematic which shows the structure of the memory cell which has a magnetic tunnel junction part. It is a conceptual diagram explaining the data read-out operation | movement from an MTJ memory cell. It is a conceptual diagram explaining the data write-in operation | movement with respect to an MTJ memory cell. It is a conceptual diagram explaining the relationship between the direction of a data write current at the time of data writing, and a magnetic field direction. It is a conceptual diagram which shows the MTJ memory cell integratedly arranged by the matrix form. 2 is a structural diagram of an MTJ memory cell disposed on a semiconductor substrate. FIG. It is the schematic which shows the structure of the MTJ memory cell using a diode. FIG. 49 is a structural diagram when the MTJ memory cell shown in FIG. 48 is arranged on a semiconductor substrate.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[Embodiment 1]
FIG. 1 is a schematic block diagram showing an overall configuration of an MRAM device 1 according to the first embodiment of the present invention.

  Referring to FIG. 1, MRAM device 1 performs random access in response to external control signal CMD and address signal ADD, and executes input of write data DIN and output of read data DOUT.

  The MRAM device 1 includes a control circuit 5 that controls the overall operation of the MRAM device 1 in response to a control signal CMD, and a memory array 10 having a plurality of MTJ memory cells arranged in a matrix of n rows × m columns. Prepare. Although the configuration of the memory array 10 will be described in detail later, a plurality of write word lines WWL and read word lines RWL are arranged corresponding to the respective MTJ memory cell rows, and a plurality of write word lines WWL are arranged corresponding to the respective MTJ memory cell columns. Bit line BL is arranged.

  The MRAM device 1 further includes a row decoder 20 that performs row selection in the memory array 10 in accordance with the row address RA indicated by the address signal ADD, and a memory in the memory array 10 in accordance with the column address CA indicated by the address signal ADD. A column decoder 25 for performing column selection, a word line driver 30 for selectively activating the read word line RWL and the write word line WWL based on the row selection result of the row decoder 20, and writing at the time of data writing Word line current control circuit 40 for flowing data write current to word line WWL, and read / write control circuits 50 and 60 for flowing data write current and sense current during data reading and data writing With.

  Read / write control circuits 50 and 60 control the voltage level of bit line BL at both ends of memory array 10, and bit data write current and sense current for executing data write and data read, respectively. Flow on line BL.

FIG. 2 is a diagram for explaining the configuration of the memory array 10 in detail.
Referring to FIG. 2, memory array 10 is configured by MTJ memory cells MC having the configuration shown in FIG. 22 arranged in n rows × m columns. Memory array 10 is divided into two areas AR1 and AR2 along the column direction.

  Read word line RWL is provided independently in each of regions AR1 and AR2. For example, the read word line provided corresponding to the first row of memory cells is divided and arranged into a read word line RWL11 corresponding to the area AR1 and a read word line RWL21 provided corresponding to the area AR2. Similarly, the read word lines arranged corresponding to the other rows are also divided and arranged in the areas AR1 and AR2, respectively.

  Note that dividing the memory array 10 into two is merely an example, and the application of the present invention is not limited to such a case. Of the embodiments of the present invention that will be described below, the one that targets the divided memory array 10 can be similarly applied when the memory array is divided into an arbitrary plurality.

  On the other hand, write word line WWL is provided corresponding to each row of memory cells in common to regions AR1 and AR2. Therefore, in the entire memory array 10, write word lines WWL1 to WWLn are arranged. Read word lines RWL1 to RWLn and write word lines WWL1 to WWLn are arranged along the row direction.

  Bit line BL is arranged along the column direction corresponding to each column of memory cells. Therefore, bit lines BL1 to BLm are arranged in the entire memory array 10.

  In the following description, when the write word line, the read word line, and the bit line are collectively expressed, they are represented using the symbols WWL, RWL, and BL, respectively, and the specific write word line, read word line, When a bit line is indicated, a subscript is added to these codes and expressed as RWL11, RWL21.

  The word line current control circuit 40 includes current control transistors 41-1 to 41-n provided corresponding to the write word lines WWL1 to WWLn, respectively. Current control transistors 41-1 to 41-n are turned on in response to control signal WE activated at the time of data writing, and are electrically coupled to corresponding write word line WWL and ground voltage Vss. As a result, a data write current can be passed through the write word line activated in the selected state (high voltage state: H level).

  On the other hand, the current control transistors 41-1 to 41-n are turned off since the control signal WE is deactivated except during data writing. Therefore, no current flows even in the activated write word line WWL.

  Sub-drivers RSD11-RSD1n, RSD21-RSD2n are provided corresponding to read word lines RWL11-RWL1n, RWL21-RWL2n, respectively. A common control signal SD is given to these sub-drivers. Each sub-driver activates the corresponding read word line RWL to a selected state (high voltage state: H level) according to the signal level of the control signal SD and the voltage of the corresponding write word line WWL.

  As already described, write word lines WWL1 to WWLn need to pass a relatively large data write current (about several mA per write word line) in order to generate a magnetic field necessary for data writing. Formed on the metal wiring layer. The metal wiring layer desirably has a wiring structure having a low resistance value and high electromigration resistance. Therefore, it is desirable that the wiring layer in which the write word line WWL is arranged is formed with a wiring thickness thicker than that of other metal wiring layers or a metal material having a lower resistance than other metal wiring layers. For example, when the other metal wiring layer is formed of an aluminum alloy, the metal wiring layer on which the write word line WWL is formed may be formed of a Cu (copper) wiring.

  On the other hand, read word line RWL is formed of polysilicon or polycide structure in the same wiring layer as the gate of access transistor ATR in order to realize high integration of memory cells. In the first embodiment, read word lines RWL having high electrical resistance are divided and arranged to shorten the wiring length, and the activation of read word lines RWL according to the row selection result by hierarchizing with write word lines WWL. As a result, the signal propagation delay in the read word line RWL is reduced without particularly increasing the number of wiring layers and the number of wirings. Thereby, it is possible to further increase the speed of the data read operation while realizing high integration of the memory cells.

  FIG. 3 is a timing chart for explaining data reading and data writing operations with respect to the memory array 10.

First, the operation at the time of data writing will be described.
The word line driver 30 drives the voltage of the write word line WWL corresponding to the selected row to the selected state (H level) according to the row selection result of the row decoder 20. In the non-selected row, the voltage level of the write word line WWL remains in the non-selected state (L level: ground voltage Vss).

  At the time of data writing, since control signal WE is activated to H level, data writing is performed on write word line WWL corresponding to the selected row in accordance with turn-on of current control transistors 41-1 to 41-n. A current Ip flows. On the other hand, since the control signal SD remains inactivated to the L level, even if the write word line WWL is selectively driven to the H level, each read word line RWL is not activated.

  Read / write control circuits 50 and 60 generate a data write current in a direction corresponding to the data level of the write data by controlling the voltage of bit line BL at both ends of memory array 10. For example, when writing storage data of “1”, the bit line voltage on the read / write control circuit 60 side is set to a high voltage state (power supply voltage Vcc), and the read / write control circuit 50 on the opposite side is set. The bit line voltage on the side is set to a low voltage state (ground voltage Vss). As a result, data write current + Iw flows through bit line BL in the direction from read / write control circuit 60 toward 50. On the other hand, when the stored data of “0” is written, the bit line voltages on the read / write control circuit 50 side and 60 side are set to the high voltage state (power supply voltage Vcc) and the low voltage state (ground voltage Vss), respectively. Data write current -Iw flows through bit line BL in the direction from read / write control circuit 50 to 60.

  At this time, it is not necessary to pass the data write current ± Iw to each bit line, and the read / write control circuits 50 and 60 can select a part corresponding to the selected column according to the column selection result of the column decoder 25. The voltage of the bit line BL described above may be controlled so that the data write current ± Iw is selectively supplied to the bit line.

  FIG. 4 is a conceptual diagram illustrating the data write current and the direction of the magnetic field generated in the MTJ memory cell during data write.

  Referring to FIG. 4, at the time of data writing, data write current Ip for generating magnetic field H (WWL) in the + Hx direction is supplied to write word line WWL. On the other hand, a data write current + Iw or −Iw for causing a magnetic field H (BL) in the + Hy direction or the −Hy direction corresponding to the data level to be written flows through the bit line BL.

  As a result, a magnetic field corresponding to the outer region of the asteroid characteristic line is generated by a combination of the magnetic field H (WWL) and the magnetic field H (BL), and the direction of the magnetic field according to the data level can be freely set in the MTJ memory cell. The magnetic layer VL can be written.

  As described above, at the time of data writing, either one of the data write currents + Iw and −Iw in the reverse direction is selected according to the data levels “1” and “0”, and the data write of the write word line WWL is performed. By fixing the current Ip in a fixed direction regardless of the data level, the word line current control circuit 40 can be simply configured with only the current control transistors 41-1 to 41-n as shown in FIG. . Although not shown in detail, since the voltage setting of the write word line corresponding to the selected row can be made constant regardless of the data level, the word line driver 30 can also be configured easily.

Next, the operation at the time of data reading will be described.
Referring to FIG. 3 again, even at the time of data reading, word line driver 30 drives write word line WWL corresponding to the selected row to the selected state (H level) according to the row selection result of row decoder 20. . In the non-selected row, the voltage level of the write word line WWL remains in the non-selected state (L level: ground voltage Vss).

  At the time of data reading, since control signal WE remains inactive at L level, current control transistors 41-1 to 41-n maintain the off state. Accordingly, no current flows through the write word line WWL even in the selected row. On the other hand, since the control signal SD is activated to the H level, the sub-drivers RSD11 to RSD2n activate the corresponding read word line RWL to the selected state (H level) in the selected row.

  Before the data read operation, bit line BL is precharged to, for example, a high voltage state (power supply voltage Vcc). When read word line RWL is activated to H level in the selected row, corresponding access transistor ATR is turned on. Accordingly, in the MTJ memory cell, a current path of the sense current Is is formed between the bit line BL and the ground voltage Vss via the access transistor ATR.

  Read / write control circuit 50 supplies a constant sense current Is to bit line BL during the data read operation. Generally, the sense current Is is a current that is about two orders of magnitude smaller than the bit line current ± Iw at the time of data writing. For example, the data write current ± Iw at the time of data writing is a current of the order of 10 mA, while the sense current Is is a current of the order of 0.1 mA. Therefore, in the configuration of the first embodiment, even when data is read, write word line WWL corresponding to the selected row is activated to H level, but current does not flow to read word line RWL but flows to the bit line. The sense current Is is also small. Therefore, there is a low possibility that erroneous data writing is executed at the time of data reading and the stored data in the MTJ memory cell is destroyed.

  Due to such a sense current Is, a different voltage drop occurs in the bit line BL depending on the data level of the storage data of the MTJ memory cell. In FIG. 3, as an example, when the stored data level is “1” and the magnetic field directions in the fixed magnetic layer FL and the free magnetic layer VL are aligned, the stored data is “1”. In addition, the voltage drop ΔV1 of the bit line BL is small, and the voltage drop ΔV2 of the bit line BL when the stored data is “0” is larger than ΔV1. By detecting the difference between these voltage drops ΔV1 and ΔV2, data can be read from the MTJ memory cell at high speed.

FIG. 5 is a circuit diagram showing a configuration example of the word line driver 30.
The word line driver 30 has an inverter 31 and an inverter 32 provided corresponding to each of the write word lines WWL1 to WWLn. Each inverter 31 operates in response to the control signal WE. On the other hand, inverter 32 operates in response to / WE, which is an inverted signal of control signal WE. That is, inverter 31 operates at the time of data writing, and each inverter 32 operates at the time of data reading.

  Row decoder 20 activates one of row decode signals RD1-RDn corresponding to the selected row to L level in response to row address RA. The row decoder 20 further generates a control signal SD transmitted to the sub driver.

  Row decode signals RD1 to RDn are transmitted to word line driver 30. In word line driver 30, each of inverter 31 and inverter 32 receives a row decode signal for a corresponding memory cell row. For example, each of inverter 31 and inverter 32 provided corresponding to write word line WWL1 receives row decode signal RD1. Inverter 31 and inverter 32 activate corresponding write word line WWL to a selected state (H level) when the transmitted row decode signal is activated to L level.

  In both data reading and data writing, write word line WWL corresponding to the selected row is activated to a selected state (H level). Therefore, a transient charging current flows through the write word line WWL in the process of activating the write word line WWL from the non-selected state (L level) to the selected state (H level) even during data reading. If the transient charging current generates a magnetic field in a region exceeding the asteroid characteristic curve shown in FIG. 4, an erroneous data write operation is executed and the stored data in the MTJ memory cell is destroyed. On the other hand, at the time of data writing, it is necessary to pass a relatively large data write current Ip through write word line WWL.

  Therefore, word line driver 30 includes an inverter 31 for supplying current to the corresponding write word line WWL at the time of data writing and an inverter 32 for charging the corresponding write word line WWL at the time of data reading. Provide independently. The current drive capability of inverter 31 is set larger than the current drive capability of inverter 32 in accordance with the amount of data write current Ip. On the other hand, the current drive capability of the inverter 32 is suppressed so that the generated magnetic field is in the inner region of the asteroid characteristic line of FIG.

  The current drive capability can be adjusted by designing the transistor size of the MOS transistors constituting inverters 31 and 32, for example. This can further prevent destruction of data stored in the MTJ memory cell during data reading.

FIG. 6 is a circuit diagram showing another configuration example of the word line driver 30.
Referring to FIG. 6, word line driver 30 includes an inverter 31 provided corresponding to each of write word lines WWL1 to WWLn, and P-type MOS transistors 33 and 34 for supplying an operating current of inverter 31. Have. Transistors 33 and 34 are arranged in parallel between inverter 33 and power supply voltage Vcc. A control signal WE is input to the gate of the transistor 33, and an inverted signal / WE of the control signal WE is input to the gate of the transistor 34. Therefore, transistor 33 is turned on at the time of data writing, and transistor 34 is turned on correspondingly at the time of data reading.

  The current drive capability of the transistor 33 is set similarly to the inverter 31 in FIG. On the other hand, the current drive capability of the transistor 34 is set similarly to the inverter 32 in FIG. Even with such a configuration, as in the case of the word line driver 30 shown in FIG. 5, destruction of data stored in the MTJ memory cell at the time of data reading can be prevented more reliably. Furthermore, the word line driver 30 shown in FIG. 6 can be configured with a smaller number of transistor elements than the word line driver 30 shown in FIG.

Next, the structure of the MTJ memory cell according to the first embodiment will be described.
The MTJ memory cell in the memory array 10 can also be formed on a semiconductor substrate based on the same structure as FIG. 47 described in the prior art. However, in the following, the structure of an MTJ memory cell suitable for the configuration of the first embodiment for activating the write word line WWL to increase the data reading speed even during data reading will be described.

  FIG. 7 is a diagram illustrating a structure according to the first embodiment of an MTJ memory cell formed on a semiconductor substrate.

  Referring to FIG. 7, based on the same structure as that of FIG. 47, access transistor ATR is formed on semiconductor main substrate SUB and coupled to ground voltage Vss. Read word line RWL is also formed of polysilicon or a polycide structure on the same wiring layer as gate 130 of access transistor ATR, based on the same structure as in FIG.

  On the other hand, unlike the structure shown in FIG. 47, the magnetic tunnel junction MTJ is formed between the metal wiring layers M1 and M2. A bit line BL is formed in the metal wiring layer M2, and a write word line WWL is formed in the metal wiring layer M3. With this structure, the magnetic tunnel junction MTJ is disposed so as to be sandwiched between the read word line RWL and the write word line WWL in the height direction.

  As a result, at the time of data reading, the magnetic tunnel junction is generated by charging currents I (WWL) and I (RWL) transiently generated to drive write word line WWL and read word line RWL to the selected state (H level). The directions of the magnetic fields H (WWL) and H (RWL) generated in the MTJ can be set to cancel each other. As a result, it is possible to more reliably prevent the stored data from being destroyed in the transient state at the time of data reading from the configuration of the MTJ memory cell.

[Variation 1 of Embodiment 1]
FIG. 8 is a diagram for describing a configuration of memory array 10 according to the first modification of the first embodiment.

  Referring to FIG. 8, in the first modification of the first embodiment, independent control signals SD1 and SD2 are generated corresponding to regions AR1 and AR2 where read word line RWL is independently arranged. The

  The sub-drivers RSD11 to RSD1n in the area AR1 operate in response to the control signal SD1, and activate the corresponding read word lines RWL11 to RWL1n according to the activation of the write word lines WWL1 to WWn. Similarly, the sub-drivers RSD21 to RSD2n in the area AR2 operate in response to the control signal SD2, and activate the corresponding read word lines RWL21 to RWL2n according to the activation of the write word lines WWL1 to WWn. Since the configuration and operation of other parts are the same as those in the first embodiment, description thereof will not be repeated.

  Thereby, memory cell access can be performed independently for each region where read word line RWL is divided and arranged. As a result, it is not necessary to access an unnecessary memory cell at the time of data reading, so that the current consumption at the time of data reading operation can be reduced and the power consumption can be reduced. In the first modification of the first embodiment, it is necessary to reflect the column selection result of the column decoder 25 in the generation of the control signals SD1 and SD2. Therefore, the column selection result may be transmitted to the row decoder 20, or the control signals SD1 and SD2 may be directly generated by the column decoder 25.

[Modification 2 of Embodiment 1]
FIG. 9 is a diagram for describing a configuration of memory array 10 according to the second modification of the first embodiment.

  Referring to FIG. 9, in the second modification of the first embodiment, read / write control circuits 50 and 60 are divided and arranged for each of areas AR1 and AR2. Specifically, read / write control circuits 50a and 60a are arranged corresponding to area AR1, and read / write control circuits 50b and 60b are arranged corresponding to area AR2. Since the configuration and operation of other parts are the same as in Modification 1 of Embodiment 1, description thereof will not be repeated.

  Thus, by arranging the read / write control circuit for each region where independent read word line RWL is provided, data read and data write operations can be performed independently in each of these regions. For example, a data read operation can be executed in area AR1, and a data write operation can be executed in area AR2 in parallel with this. As a result, the total memory access time can be further reduced when memory access is continuously executed.

[Embodiment 2]
FIG. 10 shows a configuration of memory array 10 according to the second embodiment of the present invention.

  Referring to FIG. 10, in the second embodiment, read word line RWL is hierarchically arranged with main read word line MRWL. Read word line RWL is arranged for each memory cell row independently of regions AR1 and AR2, as in the first embodiment. Therefore, in the entire memory array 10, read word lines RWL11 to RWL1n, RWL21 to RWL2n are arranged. Corresponding to each read word line, sub-drivers RSD11 to RSD1n, RSD21 to RSD2n are provided.

  Main read word line MRWL is provided along the column direction in common to regions AR1 and AR2. The main read word line MRWL is arranged for every L (L: natural number) memory cell rows. Thus, each read word line RWL is associated with one of the main read word lines MRWL1 to MRWLj (j = n / L is a natural number).

  FIG. 9 shows, as an example, a configuration in which L = 4, that is, one main read word line MRWL is arranged for every four memory cell rows. In this way, by arranging the main read word line MRWL for each of a plurality of memory cell rows, the number of main read word lines MRWL is reduced to 1 / L of the write word line WWL arranged for each memory cell row. can do. As a result, the main read word line MRWL can be formed on the semiconductor substrate as a low resistance wiring by sharing the existing metal wiring layer without providing a new metal wiring layer.

  The operation of selecting one of the four memory cell rows associated with one main read word line MRWL is executed by 4-bit control signals SD1 to SD4. The control signals SD1 to SD4 are generated by the row decoder 20, for example, based on the row address RA. Control signals SD1 to SD4 are transmitted to sub-drivers RSD11 to RSD1n and RSD21 to RSD2n, respectively. When the corresponding main read word line MRWL is activated in the selected state, each sub-driver drives one of the corresponding four (L) read word lines RWL in response to the control signals SD1 to SD4. Activate selectively.

  In this way, the read word line RWL is divided into short wiring lines and hierarchized with the main read word line MRWL having a small resistance value formed of a metal wiring, so that the read word line RWL is the same as in the first embodiment. Can reduce the signal propagation delay and speed up data reading.

  In the configuration of the second embodiment, activation control of read word line RWL and write word line WWL can be performed independently of each other during data reading and data writing. As a result, in the word line current control circuit 40, each of the write word lines WWL1 to WWLn has only to be coupled to the ground voltage Vss, and the current control transistors 41-1 to 41-n as shown in the first embodiment are connected. There is no need to provide it. In the configuration according to the second embodiment, write word line WWL is not activated at the time of data reading, but is activated only at the time of data writing. Therefore, when write word line WWL is activated, data write current Ip can always flow, and it is not necessary to control formation / cutoff of a current path through which data write current Ip flows. Thus, the configuration of the word line current control circuit 40 can be simplified.

  11, 12 and 13 are structural diagrams illustrating first, second and third examples of the arrangement of main read word lines MRWL, respectively.

  Referring to FIG. 11, access transistor ATR, bit line BL, write word line WWL, and read word line RWL are arranged in the same structure as in FIG. The main read word line MRWL is arranged in the same metal wiring layer M2 as the write word line WWL.

  Referring to FIG. 12, access transistor ATR, bit line BL, write word line WWL, and read word line RWL are arranged in the same structure as in FIG. The main read word line MRWL is arranged in the same metal wiring layer M3 as the write word line WWL.

  As shown in FIGS. 11 and 12, since the number of main read word lines MRWL arranged for each of the plurality of memory cell rows is small, they can be arranged on the same metal wiring layer as that of write word line WWL. Thereby, the main read word line MRWL can be formed on the semiconductor substrate while sharing the existing metal wiring layer without providing a new metal wiring layer.

  Referring to FIG. 13, since the number of main read word lines MRWL is small, they can be arranged in metal wiring layer M1 used for interlayer coupling in the MTJ memory cell. Even with such a structure, the main read word line MRWL can be arranged without providing a new metal wiring layer.

[Embodiment 3]
FIG. 14 is a diagram for illustrating a configuration of memory array 10 according to the third embodiment.

  Referring to FIG. 14, in the third embodiment, in the memory array 10, the read word line and the write word line are formed by a common word line RWWL. That is, in memory array 10 according to the third embodiment, word lines RWWL1 to RWWLn are arranged for each memory cell row, and word line RWWL is shared for data reading and data writing. The word line current control circuit 40 includes current control transistors 41-1 to 41-n corresponding to the word lines RWWL1 to RWWLn, respectively.

FIG. 15 is a structural diagram showing an arrangement of word lines according to the third embodiment.
Referring to FIG. 15, word line RWWL is arranged as a metal wiring in the same layer as gate 130 of access transistor ATR formed of a low resistance material. As a low resistance material for forming the gate of access transistor ATR, for example, a metal material such as tungsten can be used. Thereby, compared with the structure of the conventional MTJ memory cell, the metal wiring layer (metal wiring layer M2 in FIG. 47) in which the write word line WWL is conventionally arranged can be omitted. Thereby, the number of metal wiring layers can be reduced.

  FIG. 16 is a timing chart illustrating data reading and data writing operations for memory array 10 according to the third embodiment.

  Referring to FIG. 16, in both the data write operation and the data read operation, the voltage of word line RWWL corresponding to the selected row is activated to the selected state (H level). However, since current control transistors 41-1 to 41-n are operated in response to control signal WE, a current can be supplied to word line RWWL only during data writing.

  Thus, the voltage waveform at the time of data writing of word line RWWL in FIG. 16 is equal to the voltage waveform of write word line WWL at the time of data writing shown in FIG. 3, and the voltage waveform at the time of data reading is shown in FIG. Is equal to the voltage waveform of the read word line RWL shown in FIG. The current waveform of the word line RWWL is equal to the current waveform of the write word line WWL shown in FIG. Thus, data reading and data writing similar to those in the first embodiment can be performed on memory array 10 formed of MTJ memory cells using word line RWWL.

  Since the word line RWWL is a metal wiring, its resistance value is small. Therefore, data write current Ip can be ensured during data writing. In addition, the signal propagation delay is also small since the data is charged at high speed and changes to the selected state (H level) during data reading.

  In this way, the gate of the access transistor ATR is formed of a low resistance material, and the word line shared as the read word line RWL and the write word line WWL is provided as a low resistance metal wiring in the same layer, thereby enabling a data read operation. Along with speeding up, the degree of integration can be improved by reducing the number of metal wiring layers.

[Modification 1 of Embodiment 3]
FIG. 17 is a diagram for describing a configuration of memory array 10 according to the first modification of the third embodiment.

  Referring to FIG. 17, in memory array 10 according to the first modification of the third embodiment, the read word line is not hierarchized even when the gate of access transistor ATR is formed without using a low-resistance material. 2 shows a configuration capable of speeding up data reading operation.

  Referring to FIG. 17, a read word line RWL and a write word line WWL are arranged along the row direction corresponding to each memory cell row. In the entire memory array 10, read word lines RWL1 to RWLn and write word lines WWL1 to WWLn are arranged.

  In the first modification of the third embodiment, it is assumed that the gate of access transistor ATR is formed of polysilicon or the like as in the first and second embodiments. Accordingly, read word line RWL is formed of polysilicon or the like on the same wiring layer as the gate of access transistor ATR. On the other hand, write word line WWL is formed in the metal wiring layer by a low resistance material such as copper or aluminum alloy in order to flow a data write current Ip sufficient to generate a magnetic field necessary for data writing.

A set of read word line RWL and write word line WWL corresponding to each memory cell row is electrically coupled at at least one connection node. For example, the read word line RWL1 is coupled to the write word line WWL1 in at least one node including the connection node Nc. Accordingly, even when the read word line RWL is activated, the write word line RWL1 is formed of a low resistance material. By shunting with the word line WWL, the effective wiring resistance of the read word line RWL can be reduced. That is, when the read word line RWL is activated from the non-selected state (L level) to the selected state (H level), the entire word line in which the read word line RWL and the write word line WWL are connected in parallel is charged. Therefore, the effective wiring resistance of the read word line RWL can be reduced. As a result, the signal propagation delay in the read word line RWL can be suppressed, and the data read speed can be increased.

  FIG. 18 is a timing chart illustrating a data read operation and a data write operation in the first modification of the third embodiment.

  Referring to FIG. 18, the voltage waveforms of electrically coupled read word line RWL and write word line WWL are equal in both the data write operation and the data read operation. Since the voltage waveform of these word lines is equal to the voltage waveform of word line RWWL described with reference to FIG. 16, description thereof will not be repeated.

  In addition, since the resistance value of the read word line RWL is considerably larger than the resistance value of the write word line WWL, the current of the write word line WWL can be set in substantially the same manner as in FIG. The data write current Ip at the time of loading can be secured. Similarly, current Ip ′ generated in read word line RWL at the time of data writing has a considerably smaller value than data write current Ip, so that current Ip ′ does not adversely affect data writing.

  On the other hand, at the time of data reading, current control transistors 41-1 to 41-n are turned off in response to control signal WE. Therefore, for both write word line WW and read word line RWL, word line RWWL in FIG. As with, no current flows.

  As a result, the same data read operation and data write operation as described in the first, second and third embodiments can be performed on memory array 10 formed of MTJ memory cells.

[Modification 2 of Embodiment 3]
FIG. 19 is a diagram for describing the configuration of memory array 10 according to the second modification of the third embodiment.

  Referring to FIG. 19, in the second modification of the third embodiment, a leakage current cutoff circuit 70 is further arranged as compared with the configuration of FIG. Leakage current cut-off circuit 70 is different in that it further includes current cut-off transistors 71-1 to 71-m provided corresponding to m memory cell columns, respectively. Each of current cut-off transistors 71-1 to 71-m is coupled between the source of access transistor ATR in the MTJ memory cell belonging to the corresponding memory cell column and ground potential Vss. Control signals WC1 to WCm are input to the gates of the current cutoff transistors 71-1 to 71-m, respectively. In the following, when these current cut-off transistors are generically referred to, they are simply indicated by reference numeral 71.

  Referring to FIG. 17 again, under the configuration according to the first modification of the third embodiment, read word line RWL and write word line WWL are electrically coupled, so that even when data is written, MTJ memory The access transistor ATR in the cell MC is turned on. Since the source terminal of access transistor ATR is coupled to ground voltage Vss, at the time of data writing, bit line BL (data write current ± Iw) to magnetic tunnel junction MTJ to access transistor ATR to ground voltage Vss A leakage current path is formed. The leakage current causes unnecessary power consumption.

  Referring again to FIG. 19, leak current cut-off circuit 70 is connected to the memory cell column to be subjected to data writing among current cut-off transistors 71-1 to 71-n provided corresponding to the respective bit lines. Turn off the corresponding part. Thereby, the leakage current path at the time of data writing described with reference to FIG. 17 is cut off, and unnecessary power consumption can be avoided. Note that even if the current cut-off transistors 71-1 to 71-n are turned off, the current flowing through the bit line BL and the write word line WWL is not affected, so that the data write operation can be performed normally.

  FIG. 20 is a timing chart illustrating data reading and data writing operations for memory array 10 according to the second modification of the third embodiment.

  Referring to FIG. 20, when control signals WC1 to WCm are generically indicated by WC, control signal WC is set at the L level corresponding to the memory cell column to which data is to be written during the data write operation. Is done. In response to this, the corresponding current cut-off transistor is turned off to disconnect the source of the access transistor ATR from the ground voltage Vss. As a result, it is possible to avoid occurrence of unnecessary leakage current in the MTJ memory cell that is the target of data writing.

  On the other hand, except at the time of data writing, control signal WC is set to H level corresponding to each current cutoff transistor. Thus, at the time of data reading, the source voltage of access transistor ATR in each MTJ memory cell is set to ground voltage Vss. As a result, data reading from the memory array 10 composed of MTJ memory cells can be executed normally as described in the first to third embodiments.

  Next, the structure of the MTJ memory cell having the read word line RWL shunted by the write word line WWL will be described.

  FIG. 21 is a structural diagram of an MTJ memory cell according to the first and second modifications of the third embodiment arranged on a semiconductor substrate.

  Referring to FIG. 21, an n-type region corresponding to source / drain region 110 of access transistor ATR formed on semiconductor main substrate SUB is directly coupled to ground voltage Vss. For example, for MTJ memory cells belonging to the same memory cell row or memory cell column, n-type regions corresponding to the source / drain regions 110 are electrically coupled to each other and collectively coupled to the ground voltage Vss. Arrangement is realized.

  Write word line WWL and bit line BL are arranged in first and second metal interconnection layers M1 and M2, respectively. Bit line BL is electrically coupled to magnetic tunnel junction MTJ. Magnetic tunnel junction MTJ is electrically coupled to source / drain region 120 of access transistor ATR via barrier metal 140 and metal film 150.

  Write word line WWL is electrically coupled to read word line RWL provided in the same layer as gate 130 of access transistor ATR by metal film 155 formed in the contact hole at at least one connection node.

  As described above, an MTJ memory cell capable of reading data at high speed by shunting a high-resistance read word line RWL with a write word line WWL formed of a low-resistance material is a simple configuration using two metal wiring layers. A vertical structure can be used to form a semiconductor substrate.

[Modification 3 of Embodiment 3]
In FIG. 19, in memory array 10 according to the first modification of the third embodiment, a configuration is shown in which generation of unnecessary leakage current at the time of data writing is avoided, but similar leakage current is caused by common word line RWWL. This also occurs in memory array 10 according to the third embodiment having the following.

  FIG. 22 is a diagram for describing the configuration of memory array 10 according to the third modification of the third embodiment.

  Referring to FIG. 22, in addition to the configuration of memory array 10 in which word line RWWL is arranged corresponding to each row of memory cells according to the third embodiment shown in FIG. 15, leakage current similar to FIG. A blocking circuit 70 is further arranged. Leakage current cut-off circuit 70 includes current cut-off transistors 71-1 to 71-m provided corresponding to m memory cell columns, respectively. Control signals WC1 to WCm are input to the gates of the current cutoff transistors 71-1 to 71-m, respectively. Setting of control signals WC1 to WCm has already been described with reference to FIG. 20, and therefore description thereof will not be repeated.

  Even in the configuration in which word line RWWL is arranged, access transistor ATR is turned on at the time of data writing. Therefore, when a leakage current path from bit line BL to magnetic tunnel junction MTJ to access transistor ATR to ground voltage Vss is formed, Useless current is consumed.

  Therefore, in the same manner as described in the second modification of the third embodiment, a portion corresponding to a memory cell column to be subjected to data writing among current cutoff transistors 71-1 to 71-m at the time of data writing. To turn off. Thus, similarly, the leakage current path at the time of data writing can be cut off, and unnecessary power consumption can be avoided.

[Embodiment 4]
FIG. 23 is a diagram for describing a configuration related to data reading of memory array 10 and its peripheral circuits according to the fourth embodiment of the present invention.

  Referring to FIG. 23, the configuration according to the fourth embodiment is provided in common to bit lines BL1 to BLm in addition to the configuration of memory array 10 according to the second modification of the third embodiment shown in FIG. A data bus DB and a data read circuit 51 are further arranged. Data read circuit 51 supplies sense current Is to data bus DB during data read.

  Further, column selection gates are arranged between one ends of the bit lines BL1 to BLm and the data bus DB, respectively. Column selection gates CSG1, CSG2,... Are turned on / off in response to a column selection result by the column decoder 25. In the following, the column selection gates CSG, CSG2,... Are collectively referred to simply as column selection gates CSG.

  Therefore, in the memory cell column corresponding to the column selection result, corresponding bit line BL and data bus DB are electrically coupled via column selection gate CSG.

  Since the structure of the other parts is the same as that of memory array 10 according to the second modification of the third embodiment shown in FIG. 19, detailed description will not be repeated.

  In each memory cell column, the wiring electrically coupled to the source of access transistor ATR is generically referred to as source line SL. That is, in the entire memory array 10, source lines SL1 to SLm that are electrically coupled to the ground voltage Vss through the current blocking transistors 71-1 to 71-m are provided corresponding to the memory cell columns, respectively. Provided.

  FIG. 24 is a timing chart illustrating data reading and data writing operations for memory array 10 according to the fourth embodiment.

  Referring to FIG. 24, the voltages and currents of bit line BL, write word line WWL and read word line at the time of data writing are set such that the voltage level of bit line BL at other than the time of data writing is not power supply voltage Vcc. Except for the fact that it is set to the ground voltage Vss, it is the same as FIG. 20, and therefore detailed description will not be repeated.

  In FIG. 23, only the circuit related to data reading, that is, supply of the sense current Is by the data bus DB and the data reading circuit 51 is shown, but the other ends of the bit lines BL1 to BLm are paired with the data bus DB. In the first to third embodiments, the voltage levels of data buses DB and / DB are set to one of a high voltage state (Vcc) and a low voltage state (Vss). The same data write operation can be executed by flowing the described data write current ± Iw in the same manner.

  Further, the setting of signal levels of control signals WE and WC at the time of data writing and data reading is the same as in FIG.

Next, the operation at the time of data reading will be described.
Prior to data reading, each bit line BL is precharged to the ground voltage Vss.

  At the time of data reading, bit line BL corresponding to the selected memory cell column is coupled to data bus DB via corresponding column selection gate CSG. Data read circuit 51 couples data bus DB to a voltage different from ground voltage Vss, for example, pulls up by power supply voltage Vcc and supplies sense current Is for reading data.

  As a result, for the selected memory cell, data read circuit 51-data bus DB-column select gate CSG-bit line BL-magnetic tunnel junction MTJ-access transistor ATR-source line SL-current cutoff transistor 71-ground. A current path of the voltage Vss is formed, and the sense current Is flows.

  As a result, a voltage change corresponding to the resistance value of the magnetic tunnel junction MTJ, which varies depending on the level of stored data, occurs in the bit line BL and the data bus DB.

  Data read circuit 51 sets the level of read data DOUT according to the voltage level of data bus DB. Thus, the difference in resistance value of the magnetic tunnel junction MTJ corresponding to the stored data level can be converted into a voltage difference and read.

  At the time of data reading, in response to the row selection result, the corresponding write word line WWL is selectively activated to the H level, and the read word line RWL electrically coupled to the write word line WWL is similarly used. Activated to H level. Thus, since the read word line RWL shunted by the write word line WWL formed of a low resistance material is activated, the effective word line resistance of the read word line RWL is reduced and the read word line RWL is reduced. RWL signal propagation delay can be suppressed.

  As described above, by setting the precharge voltage of the bit line BL to the ground voltage Vss, only the bit line corresponding to the selected memory cell column needs to be charged to the power supply voltage Vcc. That is, in the other memory cell columns, it is not necessary to supply a charging current for precharging the bit line BL to the power supply voltage Vcc every time data is read. As a result, power consumption in the memory array 10 can be reduced.

  In addition, since the voltage level of the bit line BL after the completion of data writing is aligned with the precharge level (ground voltage Vss), it is not necessary to perform a new precharge operation at the time of data reading, and data reading can be performed. The speed can be increased.

  Referring to FIG. 23 again, as already described, sense current Is flows through the path of data bus DB, bit line BL, memory cell MC, source line SL, and ground voltage Vss, so that the selected memory cell row Depending on the position, the resistance value of the sense current path may change, and the value of the sense current may fluctuate.

  As described above, when the sense current varies depending on the position of the selected memory cell, the operation margin at the time of data reading cannot be kept uniform in the memory array, and the operation margin of the entire MRAM device is sufficiently secured. It becomes difficult. As a result, there is a possibility that a malfunction may occur in a severe case, resulting in a decrease in yield.

FIG. 25 is a structural diagram showing an arrangement example of the source lines SL according to the fourth embodiment.
Referring to FIG. 25, source line SL is arranged with the same shape and the same material in the same wiring layer (M2) as bit line BL. Thereby, the resistance values per unit length of the source line SL and the bit line BL are designed to be similar values.

  As shown in FIG. 24, the source lines SL and the bit lines BL are arranged in this way, and as shown in FIG. 24, at each of the one end side and the opposite side of the memory array, the coupling points ( In other words, by providing the current cut-off transistor 71) and the coupling portion (that is, the column selection gate CSG) between the data bus DB to which the sense current Is is supplied and each bit line BL, regardless of the position of the selected memory cell row. The sum of the resistance values of the bit line BL and the source line SL included in the current path of the sense current Is can be maintained almost constant.

  As a result, the current value of the sense current Is can be prevented from changing depending on the selected memory cell row. As a result, the operation margin at the time of data reading can be kept uniform in the memory array, and the operation margin of the entire MRAM device can be sufficiently secured.

  Note that the source line SL needs to be designed so that the resistance value per unit length is the same as that of the bit line BL. As long as this condition is satisfied, each wiring is provided in a different metal wiring layer. Is also possible.

[Modification 1 of Embodiment 4]
FIG. 26 is a diagram for illustrating a configuration related to data reading of memory array 10 and its peripheral circuits according to the first modification of the fourth embodiment of the present invention.

  Referring to FIG. 26, in the configuration according to the first modification of the fourth embodiment, source line SL is arranged in parallel with read word line RWL and write word line WWL. In the entire memory array 10, source lines SL1 to SLn are provided corresponding to the respective memory cell rows.

  Current cutoff transistors 71 are arranged between source lines SL1 to SLn and ground voltage Vss, respectively. In FIG. 25, current cutoff transistors 71-1 to 71-3, 71- (n-1) and 71-n corresponding to the first to third, (n-1) th and nth rows are shown.

  With this configuration, the coupling / non-coupling between the source line SL and the ground voltage Vss is controlled in order to cut off the leakage current path during data writing and avoid unnecessary power consumption. The write word line voltage or the row decode signal can be shared for the control signal of the current cutoff transistor 71 to be used. As a result, it is not necessary to generate the control signals WE1 to WEm in FIG. 19, so that the configuration of the peripheral circuit can be simplified.

  Since the configuration of the other parts is the same as that of memory array 10 according to the fourth embodiment shown in FIG. 23, detailed description will not be repeated. Further, data reading and data writing with respect to each memory cell MC arranged in memory array 10 can be performed in the same manner as in the fourth embodiment, and therefore detailed description will not be repeated.

  Further, like the bit line BL and the source line SL in the fourth embodiment, the wiring resistance per unit length of each source line SL and the data bus DB is designed to have the same value, and is shown in FIG. As described above, at each of the one end side and the opposite side of the memory array, the coupling point between each source line SL and the ground voltage Vss (that is, the current cutoff transistor 71) and the coupling point between the data bus DB and the data read circuit 51 are provided. Therefore, the sum of the resistance values of the bit line BL and the source line SL included in the current path of the sense current Is can be maintained almost constant regardless of the position of the selected memory cell column.

  As a result, the current value of the sense current Is can be prevented from fluctuating depending on the selected memory cell column. Therefore, the operation margin at the time of data reading can be kept uniform in the memory array, and the operation margin of the entire MRAM device can be sufficiently secured.

  As described in the fourth embodiment, each source line SL and data bus DB needs to be designed so that the resistance resistance per unit length has the same value. It is also possible to provide each wiring on a different metal wiring layer as long as it is satisfied.

[Modification 2 of Embodiment 4]
FIG. 27 is a diagram for illustrating a configuration related to data reading of memory array 10 and its peripheral circuits according to the second modification of the fourth embodiment of the present invention.

  Referring to FIG. 27, in the configuration according to the second modification of the fourth embodiment, dummy bit line DMBL arranged along the column direction and coupled to ground voltage Vss is newly provided. Each of source lines SL1 to SLn is electrically coupled to dummy bit line DMBL via current blocking transistors 71-1 to 71-n.

  Since the configuration of the other parts is the same as that of memory array 10 according to modification 1 of the fourth embodiment shown in FIG. 26, detailed description will not be repeated. Further, data reading and data writing with respect to each memory cell MC arranged in memory array 10 can be performed in the same manner as in the fourth embodiment, and therefore detailed description will not be repeated.

  In the configuration according to the first modification of the fourth embodiment shown in FIG. 26, the source line SL and the data bus DB are appropriately arranged to suppress the variation in the sense current depending on the selected memory cell column. Thus, the operation margin at the time of data reading can be made uniform in the memory array.

  However, in the configuration of FIG. 26, the wiring length of the bit line BL included in the sense current path changes depending on the position of the selected memory cell row. The current value may also fluctuate.

  Therefore, in the configuration according to the second modification of the fourth embodiment, data bus DB and source line SL are arranged in the same manner as in the first modification of the fourth embodiment, and between dummy bit line DMBL and each bit line BL. Also, the wiring resistance value per unit length is designed to be the same. Further, as shown in FIG. 27, the coupling point between the dummy word line DMBL and the ground voltage Vss, the data bus DB to which the sense current Is is supplied, and each of the one end side and the opposite side of the memory array, respectively. By providing the coupling point with the bit line BL (that is, the column selection gate CSG), the wiring of the bit line BL and the dummy bit line DMBL included in the current path of the sense current Is regardless of the position of the selected memory cell column. The sum of the resistances can be maintained at a substantially constant value. As a result, the sense current Is can be prevented from fluctuating depending on the selected memory cell row.

  By arranging the bit line BL, the dummy bit line DMBL, the source line SL, and the data bus DB as described above, it is possible to sense without depending on the position of the selected memory cell row and memory cell column, that is, the selected memory cell. The total wiring resistance of the current path can be set to a substantially constant value. As a result, the operation margin at the time of data reading of the MRAM device can be secured more stably.

[Embodiment 5]
FIG. 28 is a conceptual diagram illustrating the arrangement of write word lines WWL according to the fifth embodiment.

  Referring to FIG. 28, in the configuration according to the fifth embodiment, write word line WWL arranged corresponding to each memory cell row forms a write word line pair for every two pairs.

  For example, adjacent write word lines WWL1 and WWL2 form a write word line pair WWLP1. Write word line WWL2 functions as a complementary write word line / WWL1 through which a data write current flows in the direction opposite to that of write word line WWL1 during data writing. Write word line WWL1 is electrically coupled to power supply voltage Vcc through transistor QD1. On the other hand, write word line WWL2 (/ WWL1) is electrically coupled to ground voltage Vss.

  In the subsequent memory cell rows, the write word line WWL is similarly arranged. The write word line pair WWLP2 is formed by the write word line WWL3 and the write word line WWL4 (/ WWL3) electrically coupled to the power supply voltage Vcc through the transistor QD2, and every two memory cell rows In addition, write word line WWL corresponding to the odd-numbered row is electrically coupled to power supply voltage Vcc through a driver transistor. On the other hand, write word line WWL corresponding to an even-numbered row is electrically coupled to ground voltage Vss.

  Each driver transistor is activated in response to the row selection result. For example, when the first or second memory cell row is selected, driver transistor QD1 is turned on. In response, data write currents are caused to flow in opposite directions to write word lines WWL1 and WWL2 (/ WWL1) constituting write word line pair WWLP1. Thus, in the configuration according to the fifth embodiment, the selection of the memory cell row is executed for each write word line pair formed for every two memory cell rows.

  In the following, when a write word line pair and a driver transistor are collectively referred to, they are simply expressed using the symbols WWLP and QD, respectively, and when a specific write word line and a driver transistor are indicated, a suffix is added. It is expressed as WWLP1 and QD1. Also, one of the write word lines constituting the write word line pair WWLP, that is, the write word line corresponding to the odd-numbered memory cell row is generally indicated by WWL, and the other of the write word lines constituting the write word line pair. That is, the write word line corresponding to the even-numbered memory cell row is generically expressed as / WWL.

  Write word lines WWL and / WWL forming the same write word line pair are electrically coupled in a region opposite to the region where driver transistor QD is provided across memory array 10. As a result, data write current Ip flows as a round-trip current to WWL and / WWL that form a write word line pair corresponding to the selected memory cell row.

  When a data write magnetic field is applied from both of the data write currents Ip and ± Iw, which flows according to the column selection result, the MTJ memory cell has a single magnetic memory cell as a data write target. In other words, every other memory cell row is arranged every other column so that a plurality of memory cells are not subjected to data writing at the same time.

  Thus, by forming a round-trip current path with the write word line pair, the driver transistors QD need only be provided for every two rows, so that the configuration of the word line driver 30 can be simplified.

  Further, the peripheral magnetic field caused by the data write current + Ip flowing through the write word line WWL corresponding to the selected memory cell row and the peripheral magnetic field caused by the data write current −Ip flowing through the write word line / WWL cancel each other. Since it acts in the direction, magnetic field noise on the periphery of the memory cell can be reduced.

[Modification 1 of Embodiment 5]
FIG. 29 is a diagram for describing the configuration of memory array 10 and its peripheral circuits according to the first modification of the fifth embodiment.

  Referring to FIG. 29, in the configuration according to the first modification of the fifth embodiment, write word line WWL is shared between adjacent memory cell rows. For example, one write word line WWL1 is shared by the first and second memory cell rows. The write word line WWL is similarly arranged for the subsequent memory cell rows. Write word lines WWL1 to WWLN (N: a natural number represented by n / 2) are coupled to ground voltage Vss through current control transistors 41-1 to 41-N, respectively.

  Each write word line WWL is electrically coupled to corresponding read word lines RWL for two rows. For example, read word lines RWL1 and RWL2 corresponding to the first and second memory cell rows are electrically coupled to write word line WWL1. Thereby, the substantial resistance value of read word line RWL at the time of data reading is reduced by the shunt, and the propagation delay in read word line RWL can be reduced to increase the speed of data reading.

  Furthermore, by sharing the write word line WWL, the number of write word lines WWL arranged in the entire memory array 10 can be reduced. As a result, since the write word line WWL can be arranged using the layout area for two rows, a sufficient cross-sectional area can be ensured by securing a sufficient wiring width, for example.

  As a result, in the write word line WWL in which a relatively large data write current needs to flow, the current density is reduced to avoid dangers such as a short circuit between wires and a wire disconnection due to electromigration, thereby stabilizing the operation. Can be achieved.

[Modification 2 of Embodiment 5]
FIG. 30 is a diagram for describing the configuration of memory array 10 and its peripheral circuits according to the second modification of the fifth embodiment.

  Referring to FIG. 30, in the configuration according to the second modification of the fifth embodiment, each read word line RWL is electrically coupled to write word line WWL. As a result, each read word line RWL can be shunted by the write word line WWL to reduce propagation delay during data reading.

  As already described, in such a configuration, the write word line WWL is selectively driven by the word line driver 30.

  In the configuration of FIG. 30, one set is formed for every two memory cell rows, and one write word line pair WWLP is formed by two write word lines WWL. For example, the write word line pair WWLP1 is formed by the write word lines WWL1 and WWL2 (/ WWL1) corresponding to the first row and the second row, respectively.

  Two write word lines WWL and / WWL forming the same write word line pair WWLP are electrically coupled via a short-circuit transistor 42. That is, the short-circuit transistor 42 is arranged corresponding to each write word line pair WWLP. Each short-circuit transistor 42 is turned on in response to a control signal WE that is activated to H level during data writing. Note that the short-circuit transistors are also represented simply by using the reference numeral 42 when generically referred to, and are denoted as 42-1 with a suffix when indicating a specific short-circuit transistor.

  In FIG. 30, short-circuit transistor 42-1 typically arranged corresponding to the first and second memory cell rows, and arranged corresponding to the third and fourth memory cell rows. A shorting transistor 42-2 is shown.

  FIG. 31 is a timing chart illustrating row selection operations at the time of data reading and data writing in the memory array having the configuration shown in FIG.

  Read row decode signal RRDi corresponding to the i-th (i: odd-numbered natural number from 1 to n) memory cell row is activated to H level when the i-th memory cell row is selected as a data read target. It becomes. Similarly, write row decode signal WRDi is activated to H level when the i-th memory cell row is selected as a data write target during data write. The read row decode signal / RRDi is an inverted signal of the read row decode signal RRDi, and the write row decode signal / WRDi is an inverted signal of the write row decode signal WRDi.

  The write word line WWLi is set to the H level when data is written when any of the i-th and (i + 1) -th memory cell rows corresponding to the same write word line pair WWLP is selected. Activated. Each of the other write word line / WWLi constituting the same write word line pair and the write word line WWL corresponding to the non-selected memory cell row is set to L level (ground voltage Vss).

  Further, since each short-circuit transistor 42 is turned on at the time of data writing, data write current Ip is set by write word lines WWL and / WWL forming write word line pair WWLP corresponding to the selected memory cell row. It can flow as a reciprocating current.

  That is, at the time of data writing, it is necessary to set each of write word lines WWL and / WWL forming a write word line pair corresponding to the selected memory cell row to power supply voltage Vcc and ground voltage Vss.

  On the other hand, since read word line RWLi is electrically coupled to write word line WWLi, its voltage level is set similarly to write word line WWLi.

  Therefore, at the time of data reading, it is necessary to independently activate (H level) each write word line WWL. Therefore, it is necessary to turn off each short-circuit transistor 42 and selectively set only the write word line WWL corresponding to the selected memory cell row to the power supply voltage Vcc (H level voltage).

  Thus, it is necessary to provide word drivers having different configurations for the write word lines WWL corresponding to the odd and even rows, respectively.

  In FIG. 30, the configuration of write word driver WDa1 provided corresponding to write word line WWL1 and the configuration of write word driver / WDa1 provided corresponding to write word line WWL2 (/ WWL1) will be representatively described. .

  Referring to FIG. 30 again, write word driver WDa1 outputs a logic gate LG11 that outputs a logical sum (OR) operation result of write row decode signals WRD1 and WRD2, an output signal of logic gate LG11, and read row decode signal RRD1. P-type MOS transistor Q11 and N-type MOS transistor Q12 that are electrically coupled to logic gate LG13 that outputs a NOR operation result between the power supply voltage Vcc, ground voltage Vss, and write word line WWL1, respectively. And have. The output signal of logic gate LG13 is input to the gates of transistors Q11 and Q12.

  By adopting such a configuration, write word driver WDa1 can write L of the output signal of logic gate LG13 when one of write row decode signals WRD1 and WRD2 is activated to H level during data writing. In response to the change to the level, write word line WWL1 and power supply voltage Vcc are electrically coupled. When both the write row decode signals WRD1 and WRD2 are inactivated to the L level, the output signal of the logic gate LG13 is set to the L level, so that the write word driver WDa1 sets the write word line WWL1 to Electrically coupled to the ground voltage Vss.

  On the other hand, write word driver / WDa1 provided for write word line WWL2 (/ WWL1) is P-type MOS transistor Q13 electrically coupled between power supply voltage Vcc, ground voltage Vss and write word line WWL2. And an N-type MOS transistor Q14. Read row decode signal / RRD2 is applied to the gates of transistors Q13 and Q14.

  At the time of data writing, the read row decode signal / RRD2 is set to the H level regardless of the row selection result. Therefore, the write word driver / WDa1 connects the write word line WWL2 (/ WWL1) to the ground voltage Vss. Join.

  At the time of data writing, since the short-circuit transistor 42-1 is turned on in response to the activation (H level) of the control signal WE, the first or second memory cell row is selected and the write word line When WWL1 is set at power supply voltage Vcc, a round trip path is formed by write word lines WWL1 and WWL2 (/ WWL1), and data write current Ip flows.

  On the other hand, at the time of data reading, both write row decode signals WRD1 and WRD2 are deactivated to L level, so that write word driver WDa1 is in the case where read row decode signal RRD1 is activated to H level. In response to the change of the output signal of logic gate LG13 to L level, write word line WWL1 and power supply voltage Vcc are electrically coupled. As a result, read word line RWL1 electrically coupled to write word line WWL1 is also activated to H level.

  Similarly, write word driver / WDa1 electrically couples write word line WWL2 to power supply voltage Vss through transistor Q13 in response to activation (L level) of read row decode signal / RRD2.

  At the time of data reading, since short-circuit transistor 42-1 is turned off, each of write word lines WWL1 and WWL2 is independently activated to the H level. In response, each of read word lines RWL1 and RWL2 is also independently activated to the H level (power supply voltage Vcc) according to the row selection result.

  For the subsequent memory cell rows, a write word driver having the same configuration as that of write word driver WDa1 is provided for odd-numbered write word lines, and for write word lines / WWL corresponding to even-numbered rows. Thus, a write word driver having the same configuration as that of the write word driver / WDa1 is arranged.

  With this configuration, the read word line RWL is shunted by the write word line WWL having a low wiring resistance to increase the speed of data reading, and the data write current Ip during data writing forms a reciprocal path. Therefore, magnetic noise to the outside of the memory cell can be reduced.

[Modification 3 of Embodiment 5]
FIG. 32 is a diagram for describing the configuration of memory array 10 and its peripheral circuits according to the third modification of the fifth embodiment.

  Referring to FIG. 32, in the configuration according to the third modification of the fifth embodiment, the read word lines are arranged hierarchically, similarly to the configuration according to the second embodiment shown in FIG. Further, as in the case of the fourth embodiment, write word line WWL is shared by adjacent memory cell rows.

  Similarly to FIG. 8, sub word drivers RSD11 to RSD1n and RSD21 to RSD2n are arranged in regions AR1 and AR2 where read word lines RWL are independently arranged. The sub word drivers respectively corresponding to two memory cell rows sharing the same write word line WWL activate the corresponding read word line RWL in response to the activation of the common write word line WWL.

  However, the sub-word driver corresponding to the odd-numbered memory cell row operates in response to the activation of the control signal SD1. Similarly, the sub word driver corresponding to the even-numbered memory cell row operates in response to the activation of the control signal SD2. The control signal SD1 is activated when an odd-numbered memory cell row is selected. On the other hand, the control signal SD2 is activated when an even-numbered memory cell row is selected.

  Therefore, the write word line WWL can be shared between adjacent memory cells, and the read word line RWL can be hierarchically divided and shortened without newly providing a main read word line.

Since the configuration of other parts is the same as that of FIG. 8, detailed description will not be repeated.
As a result, the wiring resistance of each read word line RWL is reduced to increase the speed of data reading, and by sharing the write word line WWL, the wiring pitch is secured and the cross-sectional area is easily secured. Can do. For this reason, it is possible to further reduce the possibility of electromigration in the write word line WWL and improve the operation reliability.

  In addition, the read word line RWL is hierarchized, and the write word line WWL can be shared in the configuration of FIG. 9 for independently executing the data read and data write operations in each of the areas AR1 and AR2. is there.

[Modification 4 of Embodiment 5]
FIG. 33 is a diagram for describing a configuration of memory array 10 and its peripheral circuits according to the fourth modification of the fifth embodiment.

  In the configuration according to the fourth modification of the fifth embodiment, the read word line RWL is hierarchized and, similarly to the configuration shown in FIG. 30, a pair of write words formed for every two memory cell rows Data write current Ip is caused to flow in a round trip path formed by line pair WWLP.

  Referring to FIG. 33, sub-word drivers RSI11-RSI1n and RSI21-RSI2n each formed of an inverter are arranged in regions AR1 and AR2 where read word lines RWL are independently arranged. Each of subword drivers RSI11-RSI1n and RSI21-RSI2n operates in response to activation of control signal SD. When the control signal SD is in an inactive state, each read word line RWL is maintained in an inactive state regardless of the voltage of the corresponding write word line WWL.

  Each of sub word drivers RSI11-RSI1n and RSI21-RSI2n, unlike sub word drivers RSD11-RSD1n and RSD21-RSD2n, inverts the voltage level of the corresponding write word line WWL to drive the corresponding read word line RWL.

  FIG. 34 is a timing chart illustrating row selection operations at the time of data reading and data writing in the memory array having the configuration shown in FIG.

  Read row decode signals RRDi and / RRDi and write row decode signals WRDi and / WRD are set similarly to FIG.

  At the time of data reading, in order to set read word line RWL corresponding to the non-selected row to ground voltage Vss, in the configuration according to FIG. 33, the voltage of the write word line corresponding to the non-selected row needs to be power supply voltage Vcc. There is.

  Therefore, at the time of data reading, write word line WWL corresponding to the selected memory cell row is activated to L level. Similarly to the case of FIG. 30, since each short-circuit transistor 42 is turned off at the time of data reading, the voltage of the write word line WWL can be set independently for each memory cell row.

  Further, at the time of data reading, control signal SD is activated (H level), and therefore read word line RWL is activated to H level (power supply voltage Vcc) in the selected memory cell row. Thus, one read word line RWL corresponding to the row selection result can be selectively activated.

  At the time of data writing, when any of the i-th and (i + 1) -th memory cell rows corresponding to the same write word line pair WWLP is selected, the write word line WWLi is at L level (grounded) Voltage Vss). Each of the other write word line / WWLi constituting the same write word line pair and the write word line WWL corresponding to the non-selected memory cell row is set to the H level (power supply voltage Vss).

  As in the case of FIG. 30, short circuit transistor 42 is turned on during data writing, so that data is written by write word lines WWL and / WWL forming write word line pair WWLP corresponding to the selected memory cell row. The write current Ip can be passed as a reciprocating current.

  On the other hand, at the time of data writing, control signal SD is inactivated (L level), so that each read word line RWL is set to an inactive state (L level: power supply voltage Vcc).

  Therefore, as in the case of FIG. 30, it is necessary to provide word drivers having different configurations for the write word lines WWL corresponding to the odd and even rows, respectively. In FIG. 33, the configuration of write word driver WDb1 provided corresponding to write word line WWL1 and the configuration of write word driver / WDb1 provided corresponding to write word line WWL2 (/ WWL1) will be described representatively. .

  Referring again to FIG. 33, write word driver WDb1 outputs logic gate LG21 that outputs the logical product (AND) operation result of write row decode signals / WRD1 and / WRD2, and the output signal and read row decode of logic gate LG21. P type MOS transistor Q21 and N type electrically coupled to logic gate LG23 outputting the NAND operation result between signal / RRD1 and power supply voltage Vcc, ground voltage Vss and write word line WWL1, respectively. MOS transistor Q22. The output signal of logic gate LG23 is input to the gates of transistors Q21 and Q22.

  With such a configuration, write word driver WDb1 outputs an output signal of logic gate LG23 when either of write row decode signals / WRD1 and / WRD2 is activated to L level during data writing. In response to the change to H level, write word line WWL1 and ground voltage Vss are electrically coupled. When both of the write row decode signals / WRD1 and / WRD2 are inactivated to the H level, the output signal of the logic gate LG23 is set to the L level, so that the write word driver WDb1 WWL1 is electrically coupled to power supply voltage Vcc.

  On the other hand, write word driver / WDb1 provided for write word line WWL2 (/ WWL1) has P-type MOS transistor Q23 electrically coupled between power supply voltage Vcc, ground voltage Vss, and write word line WWL2. And an N-type MOS transistor Q24. Read row decode signal RRD2 is input to the gates of transistors Q23 and Q24.

  At the time of data writing, read row decode signal RRD2 is inactivated to L level regardless of the row selection result, so that write word driver / WDb1 uses write word line WWL2 (/ WWL1) as power supply voltage Vcc. Connect electrically.

  At the time of data writing, short-circuit transistor 42-1 is turned on in response to activation of control signal WE (H level), so that, for example, the first or second memory cell row is selected and the write word When line WWL1 is set to ground voltage Vss, a reciprocal path is formed in write word lines WWL1 and WWL2 (/ WWL1), and data write current Ip flows.

  At the time of data reading, both write row decode signals / WRD1 and / WRD2 are set to H level. Therefore, write word driver WDb1 is activated when read row decode signal / RRD1 is activated to L level. In response to the change of the output signal of logic gate GL22 to the H level, write word line WWL1 and ground voltage Vss are electrically coupled. Thereby, read word line RWL1 electrically coupled to write word line WWL1 is activated to H level by corresponding sub word driver RSI11 or RSI21.

  At the time of data reading, write word driver / WDb1 electrically couples write word line WWL2 to ground voltage Vss through transistor Q23 in response to activation (H level) of read row decode signal / RRD2. To do.

  At the time of data reading, since short-circuit transistor 42-1 is turned off, each of write word lines WWL1 and WWL2 is independently activated to L level according to the row selection result. In response, each of read word lines RWL1 and RWL2 is also activated to the H level (power supply voltage Vcc) by the corresponding sub word driver.

  For the subsequent memory cell rows, a write word driver having the same configuration as that of the write word driver WDb1 is provided for the odd-numbered write word lines, and the write word lines / WWL corresponding to the even-numbered rows are provided. Thus, a write word driver having the same configuration as that of the write word driver / WDb1 is arranged.

  With such a configuration, it is possible to realize high-speed data reading by hierarchizing the read word line RWL and reduce magnetic noise by making the data write current Ip a reciprocal path.

[Embodiment 6]
FIG. 35 shows a structure of an MTJ memory cell according to the sixth embodiment.

  Referring to FIG. 35, MTJ memory cell MCD according to the sixth embodiment includes magnetic tunnel junction MTJ and access diode DM, similarly to the configuration shown in FIG. The MTJ memory cell MCD is different from the configuration shown in FIG. 48 in that the read word line RWL and the write word line WWL are separately arranged. Bit line BL is arranged in a direction crossing write word line WWL and read word line RWL, and is electrically coupled to magnetic tunnel junction MTJ.

  Access diode DM is coupled between the two, with the direction from magnetic tunnel junction MTJ toward read word line RWL as the forward direction. The write word line WWL is provided close to the magnetic tunnel junction MTJ without being connected to other wiring.

FIG. 36 is a structural diagram when the MTJ memory cell MCD is arranged on a semiconductor substrate.
Referring to FIG. 36, N type region NWL formed on semiconductor main substrate SUB corresponds to the cathode of access diode DM. In the case where MTJ memory cells are arranged in a matrix on a semiconductor substrate, for example, the read word line RWL is connected to the MTJ memory cells belonging to the same row by electrically coupling the N-type regions NWL to each other. Without providing, the coupling relationship between the access diode DM and the read word line RWL shown in FIG. 25 can be realized. FIG. 36 shows an example in which an N-type well is formed as an N-type region, but an n + diffusion region having a smaller resistance value may be used instead of the N-type well.

  P-type region PAR provided on N-type region NWL corresponds to the anode of access diode DM. P-type region PAR is electrically coupled to magnetic tunnel junction MTJ through barrier metal 140 and metal film 150.

  Write word line WWL and bit line BL are arranged in metal interconnection layer M1 and metal interconnection layer M2, respectively. Bit line BL is arranged to be coupled to magnetic tunnel junction MTJ.

  Since the distance between the bit line BL and the magnetic tunnel junction MTJ is smaller than the distance between the write word line WWL and the magnetic tunnel junction MTJ, the bit line BL flows even when the same amount of current flows. The magnetic field generated by the data write current is larger than the magnetic field generated by the data write current flowing through the write word line WWL.

  Therefore, in order to apply a data write magnetic field having substantially the same strength to the magnetic tunnel junction MTJ, it is necessary to pass a data write current larger than that of the bit line BL to the write word line WWL. Bit line BL and write word line WWL are formed in a metal wiring layer in order to reduce the wiring resistance value. However, if the current density flowing in the wiring becomes excessive, a disconnection or a short circuit between wirings due to the electromigration phenomenon may occur, which may hinder operation reliability. For this reason, it is desirable to suppress the current density of the wiring through which the data write current flows.

  Therefore, when the MTJ memory cell MCD according to the sixth embodiment is arranged on a semiconductor substrate, the cross sectional area of the write word line WWL is made larger than that of the bit line BL closer to the magnetic tunnel junction MTJ, thereby increasing the The reliability of the MRAM device can be improved by suppressing the current density of the write word line WWL in which the data write current needs to flow.

  Further, the metal wiring (the write word line WWL in FIG. 36) that has a large distance from the magnetic tunnel junction MTJ and needs to flow a larger data write current may be formed of a material having high electromigration resistance. Effective in improving reliability. For example, when other metal wiring is formed of an aluminum alloy (Al alloy), the metal wiring that needs to be considered for electromigration resistance may be formed of copper (Cu).

  FIG. 37 is a timing chart illustrating a read operation and a write operation for MTJ memory cell MCD.

  Referring to FIG. 37, at the time of data writing, the voltage of read word line RWL, that is, N-type region NWL is set to the H level (power supply voltage Vcc). In data reading, no current flows through read word line RWL.

  A power supply voltage Vcc is applied to write word line WWL corresponding to the selected memory cell, and data write current Ip flows. For bit line BL, data corresponding to the data level of the write data is set by setting one of both ends of bit line BL to power supply voltage Vcc and ground voltage Vss according to the data level of the write data. The write current ± Iw can be supplied to the bit line BL.

  Data writing to the MTJ memory cell is executed by the data write currents Ip and ± Iw that flow in this way. In this case, since read word line RWL is set to power supply voltage Vcc, access diode DM is surely turned off during data writing. Therefore, the data write operation can be stabilized as compared with the MTJ memory cell shown in FIG.

Next, the operation at the time of data reading will be described.
Before data reading, the bit line BL is precharged to the ground voltage Vss.

  Read word line RWL corresponding to memory cell MCD to be read is driven to an active state (L level: ground voltage Vss) at the time of data reading. Accordingly, access diode DM is forward-biased, so that data read is performed by passing sense current Is through the path from bit line BL to magnetic tunnel junction MTJ to access diode DM to RWL (ground voltage Vss). be able to.

  Specifically, the data stored in the magnetic tunnel junction MTJ can be read by amplifying the voltage change generated in the bit line BL by the sense current Is.

  FIG. 38 is a diagram for describing the configuration of memory array 10 and its peripheral circuits according to the sixth embodiment.

  Referring to FIG. 38, in the configuration of memory array 10 according to the sixth embodiment, memory cells MCD having the configuration shown in FIG. 35 arranged in a matrix are arranged. A write word line WWL and a read word line RWL are arranged corresponding to each row of memory cells MCD. A current control transistor is arranged between each write word line WWL and the ground voltage Vss. Each current control transistor is turned on in response to activation of the control signal WE.

  In FIG. 38, read word lines RWL1 to RWL4, write word lines WWL1 to WWL4, and current control transistors 41-1 to 41-4 corresponding to the first to fourth memory cell rows are representatively shown. .

  Each read word line RWL is electrically coupled to a write word line WWL corresponding to the same memory cell row. As a result, the read word line RWL formed in the N-type region and having a relatively high resistance value is shunted by the write word line WWL formed of a metal wiring having a low resistance value. By combining the two at a plurality of nodes, the time constant can be further reduced. Thereby, the signal propagation delay in read word line RWL can be reduced, and the data read operation can be speeded up.

  The word line driver 30 has a word driver provided in response to each write word line WWL. In FIG. 38, word drivers WD1 to WD4 corresponding to the first to fourth memory cell rows are representatively shown. When these word drivers are collectively referred to, the code WD is simply used.

  Each word driver WD receives supply of power supply voltage Vcc and ground voltage Vss from the power supply node and the ground node. In particular, the supply of the ground voltage Vss is performed via a dummy bit line DMBL provided in the same direction as the bit line BL.

  Each word driver WD couples the corresponding write word line WWL to the power supply voltage Vcc when the corresponding memory cell row is selected in both data reading and data writing. When not selected, the corresponding write word line WWL is coupled to the ground voltage Vss.

  With such a configuration, data write current Ip can be supplied to write word line WWL corresponding to the selected memory cell row during data writing.

  Although illustration of a circuit configuration for supplying the data write current ± Iw to the bit line BL is omitted, as in the case of the first embodiment, by controlling the voltage across the bit line BL, the data A write current ± Iw can flow.

  The sense current Is at the time of data reading is supplied by the data reading circuit 51 as in the fourth embodiment. The sense current Is is supplied via the data bus DB and the column selection gate CSG arranged between the data bus DB and the bit line BL.

  At the time of data reading, read word line RWL corresponding to the non-selected row is set to a high voltage state (H level), and read word line RWL corresponding to the selected row is activated to ground voltage Vss. Thereby, in the selected row, the PN junction of the access diode DM is forward-biased, and the sense current Is is changed from the data bus DB to the column selection gate CSG to the bit line BL to the magnetic tunnel junction MTJ to the access diode DM to the read word line RWL. -Word driver WD-Dummy bit line DMBL-Ground voltage Vss is passed through the current path.

  Therefore, by arranging the data bus DB and the read word line RWL in the same manner as the source line SL and the data bus DB in FIG. 26, the resistance of the sense current path regardless of the position of the selected memory cell column. The value can be kept almost constant.

  Further, by arranging the dummy bit line DMBL and the bit line BL in the same manner as in FIG. 27, the sense is performed regardless of the position of the selected memory cell row as in the fourth embodiment and its modification. The sum total of the resistance values of the current path can be kept substantially constant.

  As described above, even in the memory array in which the MTJ memory cells MCD suitable for high integration are arranged, the fluctuation in the sense current depending on the position of the selected memory cell is suppressed, and the operation margin at the time of data reading of the MRAM device is suppressed. Can be secured stably.

[Modification 1 of Embodiment 6]
FIG. 39 is a diagram for describing the configuration of memory array 10 and its peripheral circuits according to the first modification of the sixth embodiment.

  Referring to FIG. 39, in the configuration according to the first modification of the sixth embodiment, as in the fifth embodiment and the second and fourth modifications, data writing is performed using a write word line pair that forms a round-trip current path. Current flows.

  Each read word line RWL is provided independently in each of the regions AR1 and AR2, as in FIG. Each read word line RWL is driven by a drive inverter that inverts the voltage state of the write word line WWL corresponding to the same memory cell row. Drive inverters are arranged corresponding to the read word lines RWL, respectively. Write word line WWL is provided in common to regions AR1 and AR2. Thereby, since the wiring resistance of the read word line RWL can be reduced by shortening the line, data reading can be performed at high speed.

  In addition, when the write word line WWL is set to the non-selected state (L level), the voltage of the corresponding read word line RWL is set to the H level, so that the reverse bias state of the access diode DM is ensured. Secured. Each drive inverter is supplied with ground voltage Vss by dummy bit lines DMBL1 and DMBL2 provided corresponding to regions AR1 and AR2, respectively, as in FIG.

  In FIG. 39, read word lines RWL11 to RWL13, RWL21 to RWL23, write word lines WWL11 to WWL13, WWL21 to WWL23, and drive inverters DIV11 to DIV13, DIV21 to corresponding to the first to third memory cell rows. DIV23 is typically shown. Write word lines WWL1 and WWL2 (/ WWL1) form a write word line pair WWLP1, and a short-circuit transistor 42-1 is arranged between them. The read word line, the write word line, and the drive inverter are similarly arranged for the subsequent memory cell rows.

  A write word driver having the same configuration as that of write word driver WDb1 shown in FIG. 33 is arranged for write word line WWL corresponding to the odd-numbered memory cell row. Similarly, a write word driver having a configuration similar to that of write word driver / WDb1 shown in FIG. 33 is arranged for write word line WWL corresponding to an even-numbered memory cell row.

  Although illustration of a circuit configuration for supplying the data write current ± Iw to the bit line BL is omitted, as in the case of the first embodiment, by controlling the voltage across the bit line BL, the data A write current ± Iw can flow.

  With such a configuration, at the time of data writing, a data write current Ip can be made to flow by forming a round trip current path by the write word line pair WWLP corresponding to the selected memory cell row. Thereby, simplification of a peripheral circuit and reduction of magnetic field noise can be achieved.

  In addition, by arranging the arrangement of data bus DB and read word line RWL in the same manner as source line SL and data bus DB in FIG. 26, the memory cell column selected in each of regions AR1 and AR2 is designed. Regardless of the position, the resistance value of the sense current path can be kept substantially constant.

  Further, the layout of dummy bit lines DMBL1 and DMBL2 and bit line BL is designed in the same manner as described with reference to FIG. 27, whereby the position of the selected memory cell row in each of regions AR1 and AR2. Regardless of this, the total sum of the resistance values of the sense current path can be kept substantially constant.

  Although not shown, if the data bus DB and the data read circuit 51 are arranged for each area where the read word line RWL is independently arranged, sensing is performed in the memory array 10 regardless of the position of the selected memory cell. The sum total of the resistance values of the current path can be kept substantially constant.

  As described above, the memory array in which the MTJ memory cells MCD suitable for high integration are arranged is selected even when the data write current is supplied to the write word line WWL by forming a reciprocal current path. The fluctuation of the sense current depending on the position of the memory cell can be suppressed, and the operation margin when reading data from the MRAM device can be stably secured.

[Modification 2 of Embodiment 6]
FIG. 40 is a diagram for describing the configuration of memory array 10 and its peripheral circuits according to the second modification of the sixth embodiment.

  Referring to FIG. 40, in the configuration according to the second modification of the sixth embodiment, sharing of the write word line WWL is achieved as in the first and third modifications of the fifth embodiment. Write word line WWL is shared by every two adjacent memory cell rows.

  Similarly to FIG. 39, read word line RWL is arranged independently in each of regions AR1 and AR2, and write word line WWL is provided in common to regions AR1 and AR2. The read word line RWL is arranged hierarchically with the write word line WWL. Thereby, since the wiring resistance of the read word line RWL can be reduced by shortening the line, data reading can be performed at high speed.

  Each read word line RWL is driven by a drive inverter that inverts the voltage state of the corresponding write word line WWL. Drive inverters are arranged corresponding to the read word lines RWL, respectively. Each drive inverter is supplied with the ground voltage Vss by dummy bit lines DMBL1 and DMBL2 arranged in the same manner as in FIG.

  A drive inverter corresponding to each of two memory cell rows sharing the same write word line WWL has a corresponding read word line when the common write word line WWL is set to a non-selected state (L level). The voltage of RWL is set to H level. Therefore, each of the access diodes DM corresponding to the non-selected memory cell rows can be reliably reverse-biased.

  A current control transistor is arranged between each write word line WWL and the ground voltage Vss. Each current control transistor is turned on in response to activation of the control signal WE.

  In FIG. 40, read word lines RWL11-RWL14, RWL21-RWL24, drive inverters DIV11-DIV14, DIV21-DIV24, write word lines WWL1, WWL2 and current control corresponding to the first to fourth memory cell rows. Transistors 41-1 and 41-2 are representatively shown. The write word line WWL1 is shared by the first and second memory cell rows, and the write word line WWL2 is shared by the third and fourth memory cell rows. The read word line, the write word line, and the drive inverter are similarly arranged for the subsequent memory cell rows.

  Although illustration of a circuit configuration for supplying the data write current ± Iw to the bit line BL is omitted, as in the case of the first embodiment, by controlling the voltage across the bit line BL, the data A write current ± Iw can flow.

  With this configuration, the number of write word lines WWL in the entire memory array 10 can be reduced by sharing the write word line WWL. As a result, since the write word line WWL can be arranged using the layout area for two rows, a sufficient cross-sectional area can be ensured by securing a sufficient wiring width, for example.

  As a result, in the write word line WWL in which a relatively large data write current needs to flow, the current density is reduced to avoid dangers such as a short circuit between wires and a wire disconnection due to electromigration. It is possible to stabilize the operation.

  In addition, by arranging the arrangement of data bus DB and read word line RWL in the same manner as source line SL and data bus DB in FIG. 26, the memory cell column selected in each of regions AR1 and AR2 is designed. Regardless of the position, the resistance value of the sense current path can be kept substantially constant.

  Further, the arrangement of dummy bit lines DMBL1, DMBL2 and bit line BL is designed in the same manner as described with reference to FIG. 27, so that the position of the selected memory cell row is determined in each of areas AR1 and AR2. In other words, the total resistance value of the sense current path can be kept substantially constant.

  Although not shown, if the data bus DB and the data read circuit 51 are arranged for each area where the read word line RWL is independently arranged, sensing is performed in the memory array 10 regardless of the position of the selected memory cell. The sum total of the resistance values of the current path can be kept substantially constant.

  In this manner, even in a memory array in which MTJ memory cells MCD suitable for high integration are arranged, even when the write word line WWL is shared between adjacent memory cells, the memory cell is positioned at the position of the selected memory cell. The fluctuation of the dependent sense current can be suppressed, and the operation margin at the time of data reading of the MRAM device can be stably secured.

[Modification 3 of Embodiment 6]
FIG. 41 is a diagram for describing the configuration of memory array 10 and its peripheral circuits according to the third modification of the sixth embodiment.

  Referring to FIG. 41, in the configuration according to the third modification of the sixth embodiment, in the memory array in which MTJ memory cell MCDD shown in FIG.

  A word line WL and a bit line BL are arranged for the memory cell row and the memory cell column of the memory cells MCDD arranged in a matrix.

  Each word line WL is driven by a word driver WDD. A word driver having the same configuration as that of write word driver WDb1 shown in FIG. 33 is arranged for word line WL corresponding to the odd-numbered memory cell row. Similarly, a word driver having the same configuration as that of write word driver / WDb1 shown in FIG. 33 is arranged for word line WL corresponding to the even-numbered memory cell row. Supply of the ground voltage Vss to each word driver is executed via a dummy bit line DMBL provided in the same direction as the bit line BL.

  Therefore, at the time of data writing, each of the two write word lines WWL corresponding to the odd-numbered row and the even-numbered row forming the write word line pair corresponding to the selected memory cell row is connected to the ground voltage Vss and Set to power supply voltage Vcc. Further, when each short-circuit transistor is turned on, a data write current flows as a reciprocating current in the write word line pair corresponding to the selected memory cell row.

  On the other hand, at the time of data reading, each short-circuit transistor is turned off and only the word line WL corresponding to the selected memory cell row is selectively set to the ground voltage Vss (L level voltage).

  FIG. 41 representatively shows word lines WL1 to WL3 and word drivers WDD1 to WDD3 corresponding to the first to third memory cell rows. Write word lines WWL1 and WWL2 (/ WWL1) form a write word line pair WWLP1, and a short-circuit transistor 42-1 is arranged between them. The read word line, the write word line, and the drive inverter are similarly arranged for the subsequent memory cell rows.

  Although illustration of a circuit configuration for supplying the data write current ± Iw to the bit line BL is omitted, as in the case of the first embodiment, by controlling the voltage across the bit line BL, the data A write current ± Iw can flow.

  With such a configuration, even in a memory array in which memory cells MCDD using a single word line WL are arranged, the data write current Ip can be supplied by the word line WL that forms a round trip path. As a result, it is possible to simplify the peripheral circuit and reduce the magnetic field noise.

  In addition, by arranging the data bus DB and the word line WL in the same manner as the source line SL and the data bus DB in FIG. 26, the resistance value of the sense current path regardless of the position of the selected memory cell column. Can be kept almost constant.

  Further, by arranging the dummy bit line DMBL and the bit line BL in the same manner as in FIG. 27, the sense is performed regardless of the position of the selected memory cell row as in the fourth embodiment and its modification. The sum total of the resistance values of the current path can be kept substantially constant.

  In this manner, even in a memory array in which MTJ memory cells MCDD suitable for high integration are arranged, even when a data write current is made to flow by forming a reciprocal current path, the memory cell is placed at the position of the selected memory cell. The fluctuation of the dependent sense current can be suppressed, and the operation margin at the time of data reading of the MRAM device can be stably secured.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  10 memory array, 20 row decoder, 25 column decoder, 30 word line driver, 40 word line current control circuit, 42 short-circuit transistor, 50, 60 read / write control circuit, 51 data read circuit, 70 leak current cut-off circuit, ATR Access transistor, BL bit line, CSG column selection gate, DMBL dummy bit line, FL free magnetic layer, MRWL main read word line, MTJ magnetic tunnel junction, RWL read word line, RWWL word line, SL source line, TB tunnel barrier , VL pinned magnetic layer, WWL write word line.

Claims (5)

A memory array having a plurality of magnetic memory cells arranged in a matrix;
Each of the plurality of magnetic memory cells includes:
A storage unit whose resistance value changes according to the level of stored data to be written when a data write magnetic field applied by the first and second data write currents is larger than a predetermined magnetic field;
A memory cell selection gate for allowing a data read current to pass through the storage unit during data reading;
A plurality of write word lines provided corresponding to the rows of the magnetic memory cells, each being shared by two of the rows;
For at least one of the plurality of write word lines activated, a current path of the first data write current is formed in each of the data write and the data read, respectively. A word line current control circuit for blocking;
A word line drive circuit for activating the write word line corresponding to the selected row in each of the data reading and data writing;
A plurality of data lines respectively provided corresponding to the columns of the magnetic memory cells;
Read / write for supplying the second data write current and the data read current to the data line corresponding to the selected column in each of the data write and data read A control circuit;
A plurality of read word lines each provided corresponding to a row of the magnetic memory cells, each for conducting the corresponding memory cell selection gate in accordance with a row selection result in the data read operation; ,
Each read word line is selectively activated together with the corresponding write word line in accordance with the row selection result at the time of data reading. Each of the write word lines is formed of a wiring having a first resistivity,
Each of the read word lines is formed of a wiring having a second resistivity higher than the first resistivity,
In the memory array, the first data write current passed through the write word corresponding to the selected row and the second data write passed through the data line corresponding to the selected column. The thin film magnetic memory device according to claim 1, wherein the plurality of magnetic memory cells are arranged so that data writing is performed on one of the magnetic memory cells in combination with a built-in current.   2. The thin film magnetic memory device according to claim 1, wherein each of said read word lines is electrically coupled to a corresponding one of said plurality of write word lines. The memory array is divided into a plurality of regions along the column direction;
The plurality of read word lines are divided and arranged for each of the plurality of regions,
Each of the plurality of write word lines is shared by the adjacent rows and arranged in common in the plurality of regions,
The thin film magnetic memory device includes:
A plurality of read word line drivers respectively provided corresponding to the plurality of read word lines;
Each of the plurality of read word line drivers includes information indicating which one of the even-numbered row and the odd-numbered row is selected at the time of data reading, and activation of a corresponding one of the plurality of write word lines The thin film magnetic memory device according to claim 1, wherein the corresponding read word line is activated in response to. The memory cell selection gate is
5. The thin film magnetic memory device according to claim 1, further comprising a diode element coupled between the memory unit and the corresponding read word line.

Images