JP5095433B2 - Crystal oscillation circuit and phase synchronization circuit with start-up control circuit - Google Patents

Crystal oscillation circuit and phase synchronization circuit with start-up control circuit Download PDF

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JP5095433B2
JP5095433B2 JP2008026634A JP2008026634A JP5095433B2 JP 5095433 B2 JP5095433 B2 JP 5095433B2 JP 2008026634 A JP2008026634 A JP 2008026634A JP 2008026634 A JP2008026634 A JP 2008026634A JP 5095433 B2 JP5095433 B2 JP 5095433B2
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crystal oscillation
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JP2009188738A (en
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明洋 山岸
光男 中村
充 原田
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本発明は、水晶発振回路の起動制御を行う起動制御回路を含み、一定の発振周波数の信号を出力する起動制御回路付き水晶発振回路、および水晶発振回路の発振周波数と同等な安定度を有する任意の周波数の信号を出力する位相同期回路に関する。   The present invention includes a startup control circuit that controls startup of a crystal oscillation circuit, and includes a crystal oscillation circuit with a startup control circuit that outputs a signal of a constant oscillation frequency, and an arbitrary stability that is equivalent to the oscillation frequency of the crystal oscillation circuit The present invention relates to a phase synchronization circuit that outputs a signal having a frequency of.

水晶発振回路は、その発振周波数の安定性から種々の電子機器の周波数、時間などの基準として使用されている。携帯電話や無線ＬＡＮなどの無線通信端末では、その搬送波周波数の基準信号発振回路として使用されている。   The crystal oscillation circuit is used as a reference for the frequency and time of various electronic devices because of the stability of the oscillation frequency. Wireless communication terminals such as mobile phones and wireless LANs are used as reference signal oscillation circuits for the carrier frequency.

また、移動体通信に使用される無線通信端末では、その小型化、低消費電力化が強く要望されており、回路の動作電流の低減に配慮した回路設計が行われている。さらに、低消費電力化のために待ち受け状態の間は間欠的に電源をオンして基地局との通信を行い、自端末への着信の有無を確認し、着信がなければ再び電源をオフし、着信があれば連続的に受信を開始する間欠動作を行うことにより消費電力の低減を図っている。   In addition, wireless communication terminals used for mobile communication are strongly demanded for miniaturization and low power consumption, and circuit design is performed in consideration of reduction of circuit operating current. In addition, to reduce power consumption, the power is turned on intermittently during the standby state to communicate with the base station to check whether there is an incoming call to the terminal. If there is no incoming call, the power is turned off again. If there is an incoming call, power consumption is reduced by performing an intermittent operation that starts reception continuously.

ところで、水晶発振回路は、安定な発振周波数を得ることができるが発振周波数を切り替えることができないため、無線通信端末の局部発振器は水晶発振回路と位相同期回路を組み合わせて任意の周波数の信号を生成する構成をとっている。   By the way, the crystal oscillation circuit can obtain a stable oscillation frequency but cannot switch the oscillation frequency. Therefore, the local oscillator of the wireless communication terminal generates a signal of an arbitrary frequency by combining the crystal oscillation circuit and the phase synchronization circuit. The structure to be taken is taken.

位相同期回路は、図６に示すように、水晶発振回路（ＸＯＳＣ）５１の出力信号を基準分周器５２を介して分周した信号と、電圧制御発振器（ＶＣＯ）５３の出力信号を可変分周器５４を介して分周した信号とを位相比較器５５に入力し、その位相誤差信号をループフィルタ５６を介して電圧制御発振器５３に制御電圧としてフィードバックし、電圧制御発振器５３から水晶発振回路５１で得られる周波数安定度と同等な安定度をもつ任意の周波数の信号を出力する構成である。   As shown in FIG. 6, the phase synchronization circuit divides the output signal of the crystal oscillation circuit (XOSC) 51 through the reference frequency divider 52 and the output signal of the voltage controlled oscillator (VCO) 53 into variable amounts. The frequency-divided signal is input to the phase comparator 55 via the frequency divider 54, and the phase error signal is fed back as a control voltage to the voltage-controlled oscillator 53 via the loop filter 56. In this configuration, a signal having an arbitrary frequency having a stability equivalent to the frequency stability obtained in 51 is output.

なお、位相同期回路が同期状態にあるとき、水晶発振回路５１の出力周波数をｆ１、基準分周器５２の分周数をＮ１、可変分周器５４の分周数をＮ２、電圧制御発振器５１の発振周波数をｆ２、水晶発振回路５１の発振周波数をｆ１とすると、
ｆ１／Ｎ１＝ｆ２／Ｎ２
ｆ２＝ｆ１＊（Ｎ２／Ｎ１）
の関係があり、電圧制御発振器５１の発振周波数ｆ２は可変分周器５４の分周数Ｎ２に応じた値に設定される。 When the phase synchronization circuit is in a synchronized state, the output frequency of the crystal oscillation circuit 51 is f1, the frequency division number of the reference frequency divider 52 is N1, the frequency division number of the variable frequency divider 54 is N2, and the voltage controlled oscillator 51 If the oscillation frequency of f1 is f2, and the oscillation frequency of the crystal oscillation circuit 51 is f1,
f1 / N1 = f2 / N2
f2 = f1 * (N2 / N1)
The oscillation frequency f2 of the voltage controlled oscillator 51 is set to a value corresponding to the frequency division number N2 of the variable frequency divider 54.

図７は、水晶発振回路の構成例を示す。図７(1),(2) に示す例は一般的なものであり、いずれも水晶振動子６１による共振器とインバータ６２またはトランジスタ６３を用いた負性抵抗回路を組み合わせて構成される。水晶発振回路の安定性は、水晶振動子６１の高いＱ値により得られるものであるが、そのＱ値が高いほど過渡現象が長く発振周波数が安定するまでに時間（通常は数ミリ秒程度）がかかる。そのため、間欠動作を行う無線通信端末では、余裕をもって電源をオンする必要があり、低消費電力化の効果を低減する要因になっている。   FIG. 7 shows a configuration example of the crystal oscillation circuit. The examples shown in FIGS. 7A and 7B are general ones, and both are configured by combining a resonator using a crystal resonator 61 and a negative resistance circuit using an inverter 62 or a transistor 63. The stability of the crystal oscillation circuit is obtained by the high Q value of the crystal unit 61. The higher the Q value, the longer the transient phenomenon and the longer the oscillation frequency becomes stable (usually about several milliseconds). It takes. For this reason, in a wireless communication terminal that performs intermittent operation, it is necessary to turn on the power supply with a margin, which is a factor that reduces the effect of reducing power consumption.

この課題に対して、特許文献１では、負性抵抗回路の負性抵抗値を一時的に大きくすることにより高速化をはかる方法を提案しているが、その高速化の効果は限定的であった。   To deal with this problem, Patent Document 1 proposes a method for speeding up by temporarily increasing the negative resistance value of the negative resistance circuit, but the speed-up effect is limited. It was.

なお、水晶発振回路の起動特性は、電源投入直後の初期振幅から指数関数的に振幅が増加して定常発振に達することが知られている。非特許文献１では、コルピッツ型トランジスタ水晶発振回路において、発振のきっかけとなる励振源（雑音源）がなくても、電源投入によって発生するステップ電圧を励振源として直ちに発振が始動することを解析しているが、定常発振に達するまでの時間については言及していない。
特開平１１−１８６８４７号公報 盧、都築、「水晶発振回路の起動特性の解析」、電子情報通信学会論文誌Ｃ−II、Vol.J74-C-II、No.3、pp.115-120、1991年３月 It is known that the start-up characteristics of the crystal oscillation circuit increase in amplitude exponentially from the initial amplitude immediately after power-on and reach steady oscillation. Non-Patent Document 1 analyzes that in a Colpitts-type transistor crystal oscillation circuit, even if there is no excitation source (noise source) that triggers oscillation, oscillation starts immediately using the step voltage generated by power-on as the excitation source. However, it does not mention the time until steady oscillation is reached.
Japanese Patent Laid-Open No. 11-186847 Tsuji, Tsuzuki, “Analysis of Start-up Characteristics of Crystal Oscillator”, IEICE Transactions C-II, Vol.J74-C-II, No.3, pp.115-120, March 1991

間欠動作によって低消費電力化を図る装置では、従来の水晶発振回路の起動時間（数ミリ秒）を考慮して早めに起動しなければならず、間欠動作の動作時と停止時の比率を大きくできない課題があった。   In devices that achieve low power consumption by intermittent operation, it is necessary to start up earlier in consideration of the startup time (several milliseconds) of the conventional crystal oscillation circuit, increasing the ratio between intermittent operation and stoppage. There was a problem that could not be done.

本発明は、水晶発振回路が定常発振に達するまでの起動時間を短くすることができる起動制御回路付き水晶発振回路、水晶発振回路の起動時間を短くすることで間欠動作の比率を大きくし、低消費電力化に寄与することができる位相同期回路を提供することを目的とする。   The present invention provides a crystal oscillation circuit with a start control circuit that can shorten the start-up time until the crystal oscillation circuit reaches steady oscillation, and increases the ratio of intermittent operation by reducing the start-up time of the crystal oscillation circuit. It is an object of the present invention to provide a phase locked loop that can contribute to power consumption.

第１の発明は、水晶振動子と負性抵抗回路を備えた水晶発振回路の起動制御を行う起動制御回路を含み、一定の発振周波数の信号を出力させる起動制御回路付き水晶発振回路であって、水晶発振回路は、水晶振動子を励振する励振信号を外部から入力するための信号入力端子を備え、起動制御回路は、電圧制御発振器を備え、電圧制御発振器の制御電圧を制御して発振周波数またはそれに近い周波数を有する励振信号を生成し、水晶発振回路の起動時に励振信号を信号入力端子に入力し、水晶発振回路の発振周波数が安定する前に励振信号の入力を停止する構成である。 A first aspect of the present invention is a crystal oscillation circuit with a startup control circuit that includes a startup control circuit that controls startup of a crystal oscillation circuit including a crystal resonator and a negative resistance circuit, and that outputs a signal having a constant oscillation frequency. The crystal oscillation circuit has a signal input terminal for inputting an excitation signal for exciting the crystal resonator from the outside, the start control circuit has a voltage controlled oscillator, and controls the control voltage of the voltage controlled oscillator to control the oscillation frequency. or to generate an excitation signal having a frequency close to it, the excitation signal at the start of the crystal oscillator input to signal input terminal, the oscillation frequency of the crystal oscillation circuit is configured to stop the input of the excitation signal before stable .

第２の発明は、水晶振動子と負性抵抗回路を備えた水晶発振回路の起動制御を行う起動制御回路を含み、一定の発振周波数の信号を出力させる起動制御回路付き水晶発振回路であって、水晶発振回路は、水晶振動子を励振する励振信号を外部から入力するための信号入力端子を備え、起動制御回路は、電圧制御発振器およびその出力信号を分周する分周器を備え、電圧制御発振器の制御電圧および分周器の分周数を制御して発振周波数またはそれに近い周波数を有する励振信号を生成し、水晶発振回路の起動時に励振信号を信号入力端子に入力し、水晶発振回路の発振周波数が安定する前に励振信号の入力を停止する構成である。 A second aspect of the invention is a crystal oscillation circuit with a startup control circuit that includes a startup control circuit that controls startup of a crystal oscillation circuit including a crystal resonator and a negative resistance circuit, and that outputs a signal having a constant oscillation frequency. The crystal oscillation circuit includes a signal input terminal for inputting an excitation signal for exciting the crystal resonator from the outside, and the activation control circuit includes a voltage controlled oscillator and a frequency divider for dividing the output signal, The control voltage of the controlled oscillator and the frequency divider frequency are controlled to generate an excitation signal having an oscillation frequency or a frequency close thereto, and the excitation signal is input to the signal input terminal when the crystal oscillation circuit starts up. The input of the excitation signal is stopped before the oscillation frequency becomes stable.

第３の発明は、水晶発振回路から出力される一定の発振周波数の出力信号を基準分周器（分周数Ｎ１）を介して分周した信号と、電圧制御発振器の出力信号を可変分周器（分周数Ｎ２）を介して分周した信号とを位相比較器に入力し、その位相誤差信号をループフィルタを介して当該電圧制御発振器に制御電圧としてフィードバックし、電圧制御発振器から水晶発振回路で得られる周波数安定度と同等な安定度をもつ任意の周波数の信号を出力する位相同期回路において、水晶発振回路は、水晶振動子を励振する励振信号を外部から入力するための信号入力端子を備え、可変分周器の出力信号を分岐して信号入力端子に入力する経路に挿入され、可変分周器の出力信号を水晶発振回路に励振信号として入力するか否かを切り替えるスイッチと、位相同期回路の起動時にスイッチを閉じ、励振信号の周波数が水晶発振回路の発振周波数またはそれに近い周波数になるように、電圧制御発振器の制御電圧と可変分周器の分周数Ｎ２′を設定して生成した励振信号を信号入力端子に入力し、水晶発振回路の発振周波数が安定する前にスイッチを開いて励振信号の入力を停止し、電圧制御発振器の制御電圧の印加を停止し、可変分周器の分周数Ｎ２に設定する制御手段とを備える。 According to a third aspect of the present invention, a signal obtained by frequency-dividing an output signal having a constant oscillation frequency output from a crystal oscillation circuit through a reference frequency divider (frequency division number N1) and an output signal from the voltage controlled oscillator are variable-divided. The signal divided by the frequency divider (frequency division number N2) is input to the phase comparator, and the phase error signal is fed back as a control voltage to the voltage controlled oscillator via the loop filter. In a phase-locked loop that outputs a signal of an arbitrary frequency having a stability equivalent to the frequency stability obtained by the circuit, the crystal oscillation circuit is a signal input terminal for inputting an excitation signal for exciting the crystal resonator from the outside. the provided, is inserted in the path to be input to the signal input terminal branches the output signal of the variable frequency divider, a switch for switching whether or not to input the output signal of the variable frequency divider as the excitation signal to the crystal oscillator circuit Close the switch when starting the phase-locked loop, and set the control voltage of the voltage-controlled oscillator and the frequency divider N2 'so that the frequency of the excitation signal is at or close to the oscillation frequency of the crystal oscillation circuit. the excitation signal generated Te input to signal input terminal, the oscillation frequency of the crystal oscillation circuit stops input of the excitation signal to open the switch before stable, and stops applying the control voltage of the voltage controlled oscillator, variable Control means for setting the frequency division number N2 of the frequency divider.

第３の発明における位相同期回路は、電圧制御発振器の制御電圧をモニタする制御電圧モニタを備え、制御手段は、制御電圧モニタから間欠動作する位相同期回路の動作安定時における電圧制御発振器の制御電圧ｖ１、基準分周器の分周数Ｎ１および可変分周器の分周数Ｎ２を保持し、間欠動作する位相同期回路の起動時に当該制御電圧ｖ１を電圧制御発振器に設定し、分周数Ｎ２′＝Ｎ１／Ｎ２を可変分周器に設定する構成である。
A phase locked loop circuit according to a third aspect of the present invention includes a control voltage monitor that monitors a control voltage of the voltage controlled oscillator, and the control means controls the control voltage of the voltage controlled oscillator when the operation of the phase locked loop that operates intermittently from the control voltage monitor is stable. v1, the frequency division number N1 of the reference frequency divider and the frequency division number N2 of the variable frequency divider are held, and the control voltage v1 is set in the voltage controlled oscillator when the phase synchronization circuit that operates intermittently is started. '= N1 / N2 is set in the variable frequency divider.

本発明の起動制御回路付き水晶発振回路は、起動時に水晶発振回路の発振周波数またはそれに近い周波数を有する励振信号を水晶発振回路に入力することにより、発振の始動から安定した発振周波数になるまでの起動時間を短縮することができる。   The crystal oscillation circuit with a start control circuit according to the present invention inputs an excitation signal having an oscillation frequency of the crystal oscillation circuit or a frequency close to the crystal oscillation circuit to the crystal oscillation circuit at the time of startup until the oscillation frequency becomes stable from the start of oscillation. Startup time can be shortened.

本発明の位相同期回路は、起動時に水晶発振回路の発振周波数またはそれに近い周波数を有する励振信号を水晶発振回路に入力することにより、水晶発振回路の高速起動が可能となり、それによって間欠動作する際の動作時と停止時の比率を大きくし、効果的に低消費電力化を実現することができる。   The phase-locked loop of the present invention enables the crystal oscillation circuit to be started at high speed by inputting an excitation signal having an oscillation frequency of the crystal oscillation circuit or a frequency close to the crystal oscillation circuit at the time of startup, thereby enabling intermittent operation. The ratio between the time of operation and the time of stop can be increased, and low power consumption can be effectively realized.

（起動制御回路付き水晶発振回路の実施形態）
図１は、本発明の起動制御回路付き水晶発振回路の実施形態を示す。
図において、本実施形態の起動制御回路付き水晶発振回路は、水晶発振回路（ＸＯＳＣ）１１、スイッチ（ＳＷ）１２、可変分周器１３、電圧制御発振器（ＶＣＯ）１４および制御部１５から構成される。水晶発振回路１１は、図７(1),(2) に示す水晶振動子６１とインバータ６２またはトランジスタ６３を用いた標準的な構成に対して、図２(1),(2) に示すように、インバータ６２またはトランジスタ６３の入力端に容量素子１６を介して信号入力端子１７を接続した構成である。この信号入力端子１７から水晶振動子６１を励振する励振信号が入力される。なお、励振信号は水晶振動子６１を励振するためのものであるので、例えばインバータ６２またはトランジスタ６３の出力端に容量素子１６を介して信号入力端子１７を接続する構成でもよい。さらに、図２(2) はトランジスタ６３にＭＯＳトランジスタを使用したコルピッツ型トランジスタ水晶発振回路の例であるが、バイポーラトランジスタを使用した構成であってもよい。 (Embodiment of crystal oscillation circuit with start-up control circuit)
FIG. 1 shows an embodiment of a crystal oscillation circuit with a startup control circuit of the present invention.
In the figure, the crystal oscillation circuit with a start control circuit according to the present embodiment includes a crystal oscillation circuit (XOSC) 11, a switch (SW) 12, a variable frequency divider 13, a voltage controlled oscillator (VCO) 14, and a control unit 15. The The crystal oscillation circuit 11 is shown in FIGS. 2 (1) and (2) in contrast to the standard configuration using the crystal resonator 61 and the inverter 62 or transistor 63 shown in FIGS. 7 (1) and (2). In addition, the signal input terminal 17 is connected to the input terminal of the inverter 62 or the transistor 63 via the capacitive element 16. An excitation signal for exciting the crystal unit 61 is input from the signal input terminal 17. Since the excitation signal is for exciting the crystal unit 61, the signal input terminal 17 may be connected to the output terminal of the inverter 62 or the transistor 63 via the capacitive element 16, for example. Further, FIG. 2 (2) shows an example of a Colpitts-type transistor crystal oscillation circuit using a MOS transistor as the transistor 63, but a configuration using a bipolar transistor may also be used.

電圧制御発振器（ＶＣＯ）１４の出力信号は可変分周器１３で分周され、励振信号としてスイッチ１２を介して水晶発振回路１１の信号入力端子１７に入力される。制御部１５は、電圧制御発振器１４の制御電圧および可変分周器１３の分周数を制御して励振信号の周波数を設定し、またスイッチ１２を開閉して励振信号の入力タイミングを制御する。   The output signal of the voltage controlled oscillator (VCO) 14 is frequency-divided by the variable frequency divider 13 and input to the signal input terminal 17 of the crystal oscillation circuit 11 through the switch 12 as an excitation signal. The control unit 15 controls the control voltage of the voltage controlled oscillator 14 and the frequency division number of the variable frequency divider 13 to set the frequency of the excitation signal, and opens and closes the switch 12 to control the input timing of the excitation signal.

ここで、本実施形態の起動制御回路付き水晶発振回路の起動時、すなわち電源投入後の動作について説明する。電源投入と同時に、水晶発振回路１１および電圧制御発振器１４は発振を開始する。このとき、電圧制御発振器１４の制御電圧および可変分周器１３の分周数は、励振信号の周波数が水晶発振回路１１の発振周波数またはそれに近い周波数になるように制御され、スイッチ１２は閉じられる。水晶発振回路１１の発振の立ち上がりは電圧制御発振器１４に比べて非常に遅いため（例えば前者は数ミリ秒、後者は数マイクロ秒）、電圧制御発振器１４から可変分周器１３、スイッチ１２を介して出力される励振信号が水晶発振回路１１の信号入力端子１７に入力すると、水晶発振回路１１の出力は励振信号と同じ周波数になるとともに、水晶振動子６１に励振電流が流れ、水晶発振回路１１の発振の始動が早まる。なお、可変分周器１３を用いず、電圧制御発振器１４から直接所要の周波数に制御した励振信号を出力するようにしてもよい。   Here, the operation when the crystal oscillation circuit with the start control circuit of the present embodiment is started, that is, after the power is turned on, will be described. Simultaneously with power-on, the crystal oscillation circuit 11 and the voltage controlled oscillator 14 start oscillating. At this time, the control voltage of the voltage controlled oscillator 14 and the frequency dividing number of the variable frequency divider 13 are controlled so that the frequency of the excitation signal becomes the oscillation frequency of the crystal oscillation circuit 11 or a frequency close thereto, and the switch 12 is closed. . Since the rise of oscillation of the crystal oscillation circuit 11 is much slower than that of the voltage controlled oscillator 14 (for example, the former is several milliseconds and the latter is several microseconds), the voltage controlled oscillator 14 passes through the variable frequency divider 13 and the switch 12. When the excitation signal output in this way is input to the signal input terminal 17 of the crystal oscillation circuit 11, the output of the crystal oscillation circuit 11 has the same frequency as the excitation signal and an excitation current flows through the crystal resonator 61. The start of oscillation is accelerated. In addition, you may make it output the excitation signal controlled to the required frequency directly from the voltage control oscillator 14, without using the variable frequency divider 13. FIG.

次に、水晶発振回路１１の出力周波数が安定する前、例えば電源投入から15マイクロ秒後に、スイッチ１２を開いて水晶発振回路１１の信号入力端子１７に対する励振信号の入力を停止する。すると、水晶発振回路１１は、負性抵抗と水晶振動子６１の共振周波数で発振動作を継続する。このとき、すでに水晶振動子６１はある程度励振されているので、水晶発振回路１１は速やかに一定の発振周波数まで立ち上がることができる。   Next, before the output frequency of the crystal oscillation circuit 11 is stabilized, for example, 15 microseconds after the power is turned on, the switch 12 is opened to stop the input of the excitation signal to the signal input terminal 17 of the crystal oscillation circuit 11. Then, the crystal oscillation circuit 11 continues the oscillation operation at the negative resistance and the resonance frequency of the crystal resonator 61. At this time, since the crystal unit 61 has already been excited to some extent, the crystal oscillation circuit 11 can quickly rise to a constant oscillation frequency.

図３は、従来構成および本発明構成の水晶発振回路の立ち上がりシミュレーション結果を示す。
図３(1) は、図７(1) に示す従来の水晶発振回路において、時刻０に電源電圧を入力したときの出力信号を示す。図３(2) は、図１に示す本発明の起動制御回路付き水晶発振回路において、時刻０に電源電圧を入力してから15マイクロ秒だけ外部から励振信号を入力したときの出力信号を示す。なお、水晶振動子のモデル、インバータのトランジスタサイズなどのパラメータは両者とも同じである。従来の水晶発振回路では、発振周波数が安定するまでの起動時間は約 2.9ミリ秒であった。本発明の起動制御回路付き水晶発振回路では、発振周波数が安定するまでの起動時間は約 0.9ミリ秒であり、従来構成に比べて１／３程度に短縮されていることがわかる。 FIG. 3 shows the rise simulation results of the crystal oscillation circuit of the conventional configuration and the configuration of the present invention.
FIG. 3 (1) shows an output signal when a power supply voltage is input at time 0 in the conventional crystal oscillation circuit shown in FIG. 7 (1). FIG. 3 (2) shows an output signal when the excitation signal is inputted from the outside for 15 microseconds after the power supply voltage is inputted at time 0 in the crystal oscillation circuit with the start control circuit of the present invention shown in FIG. . The parameters such as the crystal oscillator model and the inverter transistor size are the same. In the conventional crystal oscillation circuit, the startup time until the oscillation frequency is stabilized is about 2.9 milliseconds. In the crystal oscillation circuit with a startup control circuit of the present invention, it can be seen that the startup time until the oscillation frequency is stabilized is about 0.9 milliseconds, which is shortened to about 1/3 of the conventional configuration.

なお、本シミュレーションにおいて、水晶発振回路に入力する励振信号の周波数は、水晶発振回路の最終的な出力信号の周波数と完全に一致している必要はなく、例えば 0.5％程度の誤差があっても十分に高速化の効果が確認された。すなわち、水晶発振回路の起動時に、その発振周波数またはそれに近い周波数を有する励振信号をごく短時間だけ入力することにより、水晶発振回路の起動の高速化が可能なことが確認された。   Note that in this simulation, the frequency of the excitation signal input to the crystal oscillation circuit does not need to completely match the frequency of the final output signal of the crystal oscillation circuit, even if there is an error of about 0.5%, for example. A sufficiently high speed effect was confirmed. That is, it was confirmed that the crystal oscillation circuit can be started up at a high speed by inputting an excitation signal having the oscillation frequency or a frequency close to the oscillation frequency for a very short time.

（位相同期回路の第１の実施形態）
図４は、本発明の位相同期回路の第１の実施形態を示す。
図において、本実施形態の位相同期回路は、図６に示す従来の位相同期回路の水晶発振回路（ＸＯＳＣ）５１、電圧制御発振器（ＶＣＯ）５３、可変分周器５４として、図１および図２に示す信号入力端子１７を備える水晶発振回路１１、電圧制御発振器（ＶＣＯ）１４、可変分周器１３を用いた構成としたものである。 (First Embodiment of Phase Synchronization Circuit)
FIG. 4 shows a first embodiment of the phase locked loop of the present invention.
In the figure, the phase locked loop circuit of this embodiment includes a crystal oscillator circuit (XOSC) 51, a voltage controlled oscillator (VCO) 53, and a variable frequency divider 54 of the conventional phase locked loop circuit shown in FIG. The crystal oscillation circuit 11, the voltage controlled oscillator (VCO) 14, and the variable frequency divider 13 having the signal input terminal 17 shown in FIG.

すなわち、水晶発振回路１１の出力信号を基準分周器（分周数Ｎ１）５２を介して分周した信号と、電圧制御発振器１４の出力信号を可変分周器（分周数Ｎ２）１３を介して分周した信号とを位相比較器５５に入力し、その位相誤差信号をループフィルタ５６を介して電圧制御発振器１４に制御電圧としてフィードバックし、電圧制御発振器１４から水晶発振回路１１で得られる周波数安定度と同等な安定度をもつ任意の周波数の信号を出力する構成において、可変分周器１３の出力信号を分岐して水晶発振回路１１の信号入力端子に入力する経路にスイッチ（ＳＷ）１２を挿入し、制御部１５は、電圧制御発振器１４の制御電圧および可変分周器１３の分周数を制御して水晶発振回路１１に入力する励振信号の周波数を設定し、またスイッチ１２を開閉して励振信号の入力タイミングを制御する。   That is, a signal obtained by frequency-dividing the output signal of the crystal oscillation circuit 11 via the reference frequency divider (frequency division number N1) 52 and the output signal of the voltage controlled oscillator 14 are supplied to the variable frequency divider (frequency division number N2) 13. And the phase error signal is fed back as a control voltage to the voltage controlled oscillator 14 via the loop filter 56 and obtained from the voltage controlled oscillator 14 by the crystal oscillation circuit 11. In a configuration for outputting a signal of an arbitrary frequency having a stability equivalent to the frequency stability, a switch (SW) is provided in a path for branching the output signal of the variable frequency divider 13 and inputting it to the signal input terminal of the crystal oscillation circuit 11. 12, the control unit 15 controls the control voltage of the voltage controlled oscillator 14 and the frequency dividing number of the variable frequency divider 13 to set the frequency of the excitation signal input to the crystal oscillation circuit 11. 12 closing to control the input timing of the excitation signal.

ここで、本実施形態の位相同期回路の起動時、すなわち電源投入後の動作について説明する。電源投入と同時に、水晶発振回路１１および電圧制御発振器１４は発振を開始する。このとき、電圧制御発振器１４の制御電圧および可変分周器１３の分周数Ｎ２′は、励振信号の周波数が水晶発振回路１１の発振周波数ｆ１またはそれに近い周波数になるように制御され、スイッチ１２は閉じられる。これにより、電圧制御発振器１４から可変分周器１３、スイッチ１２を介して出力される励振信号は水晶発振回路１１の信号入力端子１７に入力し、水晶発振回路１１の発振の始動が早まる。次に、水晶発振回路１１の出力周波数が安定する前にスイッチ１２を開き、水晶発振回路１１の信号入力端子１７に対する励振信号の入力を停止するが、水晶発振回路１１の水晶振動子はすでにある程度励振されているので、水晶発振回路１１は速やかに一定の発振周波数まで立ち上がる。また、そのとき可変分周器１３を本来の分周数Ｎ２に設定すると、それ以降の位相同期回路の動作は従来の構成と同様になる。   Here, the operation when the phase locked loop of the present embodiment is started, that is, after the power is turned on, will be described. Simultaneously with power-on, the crystal oscillation circuit 11 and the voltage controlled oscillator 14 start oscillating. At this time, the control voltage of the voltage controlled oscillator 14 and the frequency division number N2 ′ of the variable frequency divider 13 are controlled so that the frequency of the excitation signal becomes the oscillation frequency f1 of the crystal oscillation circuit 11 or a frequency close thereto. Is closed. As a result, the excitation signal output from the voltage controlled oscillator 14 via the variable frequency divider 13 and the switch 12 is input to the signal input terminal 17 of the crystal oscillation circuit 11, and the start of oscillation of the crystal oscillation circuit 11 is accelerated. Next, the switch 12 is opened before the output frequency of the crystal oscillation circuit 11 is stabilized, and the input of the excitation signal to the signal input terminal 17 of the crystal oscillation circuit 11 is stopped. Since it is excited, the crystal oscillation circuit 11 quickly rises to a constant oscillation frequency. At that time, when the variable frequency divider 13 is set to the original frequency division number N2, the subsequent operation of the phase synchronization circuit is the same as the conventional configuration.

なお、スイッチ１２を閉じて水晶発振回路１１に励振信号を入力している期間は、位相同期回路の起動時から水晶発振回路１１の出力周波数が安定する前のごく短時間であるので、位相同期回路自体の動作には影響を与えないが、その期間に制御部１５の制御によって位相比較器５５から電圧制御発振器１４までの区間を遮断するスイッチを設けてもよい。   The period in which the switch 12 is closed and the excitation signal is input to the crystal oscillation circuit 11 is a very short time before the output frequency of the crystal oscillation circuit 11 is stabilized after the phase synchronization circuit is activated. Although it does not affect the operation of the circuit itself, a switch for cutting off the section from the phase comparator 55 to the voltage controlled oscillator 14 under the control of the control unit 15 may be provided during that period.

このように、図１に示す本発明の起動制御回路付き水晶発振回路の主な構成要素である電圧制御発振器１４および可変分周器１３は、すでに位相同期回路の要素回路として用意されているため、大きな構成要素の追加なしに水晶発振回路１１の立ち上がり時間の高速化は実現することができる。すなわち、コストアップを伴うことなく、水晶発振回路を含む位相同期回路の高速起動を実現することができる。   Thus, the voltage controlled oscillator 14 and the variable frequency divider 13 which are the main components of the crystal oscillation circuit with a start control circuit of the present invention shown in FIG. 1 are already prepared as element circuits of the phase locked loop circuit. The rise time of the crystal oscillation circuit 11 can be increased without adding a large component. That is, high-speed startup of the phase locked loop including the crystal oscillation circuit can be realized without increasing the cost.

なお、本実施形態では、位相同期回路の周波数基準となる水晶発振回路に電圧制御発振器から励振信号を与えて高速起動制御を行っているが、他に備える水晶発振回路にも電圧制御発振器から励振信号を与える構成としてもよい。   In this embodiment, the crystal oscillator circuit that is the frequency reference of the phase-locked loop circuit is supplied with an excitation signal from the voltage-controlled oscillator to perform high-speed start-up control. It is good also as a structure which gives a signal.

（位相同期回路の第２の実施形態）
図５は、本発明の位相同期回路の第２の実施形態を示す。
本実施形態の位相同期回路は、図４に示す第１の実施形態における電圧制御発振器１４の制御電圧をモニタする制御電圧モニタ１８を追加し、制御部１５でモニタした制御電圧、基準分周器５２の分周数Ｎ１、可変分周器１３の分周数Ｎ２の関係に基づく制御を行う構成を特徴とする。 (Second Embodiment of Phase Synchronization Circuit)
FIG. 5 shows a second embodiment of the phase locked loop of the present invention.
The phase-locked loop according to the present embodiment includes a control voltage monitor 18 that monitors the control voltage of the voltage controlled oscillator 14 according to the first embodiment shown in FIG. 4, and the control voltage and reference frequency divider monitored by the control unit 15. The control is based on the relationship between the frequency division number N1 of 52 and the frequency division number N2 of the variable frequency divider 13.

位相同期回路が同期状態にあるとき、基準分周器５２の分周数をＮ１、可変分周器１３の分周数をＮ２、電圧制御発振器１４の発振周波数をｆ２、水晶発振回路１１の発振周波数をｆ１とすると、
ｆ１／Ｎ１＝ｆ２／Ｎ２
ｆ１＝ｆ２＊（Ｎ１／Ｎ２）
で示される。このときの電圧制御発振器１４の制御電圧がｖ１であれば、反対に電圧制御発振器１４に制御電圧ｖ１を与え、可変分周器１３の分周数を（Ｎ１／Ｎ２）とすれば、可変分周器１３の出力周波数は水晶発振回路１１の出力周波数ｆ１と一致する。 When the phase synchronization circuit is in a synchronized state, the frequency division number of the reference frequency divider 52 is N1, the frequency division number of the variable frequency divider 13 is N2, the oscillation frequency of the voltage controlled oscillator 14 is f2, and the oscillation of the crystal oscillation circuit 11 If the frequency is f1,
f1 / N1 = f2 / N2
f1 = f2 * (N1 / N2)
Indicated by If the control voltage of the voltage controlled oscillator 14 at this time is v1, conversely, the control voltage v1 is given to the voltage controlled oscillator 14, and if the frequency dividing number of the variable frequency divider 13 is (N1 / N2), the variable divided The output frequency of the frequency divider 13 coincides with the output frequency f1 of the crystal oscillation circuit 11.

この原理に基づき、制御部１５は、制御電圧モニタ１８から間欠動作する位相同期回路の動作安定時、例えば直前の動作時の間欠動作の動作終了直前における電圧制御発振器１４の制御電圧ｖ１をモニタし、基準分周器５２の分周器Ｎ１、可変分周器１３の分周数Ｎ２を保持しておき、次の位相同期回路の起動時に電圧制御発振器１４に制御電圧ｖ１を設定し、可変分周器１３に分周数（Ｎ１／Ｎ２）を設定する。これにより、位相同期回路の起動時に、電圧制御発振器１４および可変分周器１３を用いて水晶発振回路１１の発振周波数ｆ１と同じ周波数の励振信号を生成し、水晶発振回路１１に入力することができる。   Based on this principle, the control unit 15 monitors the control voltage v1 of the voltage controlled oscillator 14 immediately before the end of the intermittent operation at the time of the immediately preceding operation, for example, when the operation of the phase synchronization circuit that operates intermittently from the control voltage monitor 18 is stable. The frequency divider N1 of the reference frequency divider 52 and the frequency division number N2 of the variable frequency divider 13 are held, and the control voltage v1 is set to the voltage controlled oscillator 14 at the time of starting the next phase synchronization circuit, and the variable frequency divider is set. The frequency dividing number (N1 / N2) is set in the device 13. As a result, when the phase locked loop circuit is activated, an excitation signal having the same frequency as the oscillation frequency f1 of the crystal oscillation circuit 11 can be generated using the voltage controlled oscillator 14 and the variable frequency divider 13 and input to the crystal oscillation circuit 11. it can.

なお、基準分周器５２の分周数Ｎ１および可変分周器１３の分周数Ｎ２は、位相同期回路の出力周波数ｆ２に応じて決められるが、本発明では位相同期回路の起動時の短時間だけ電圧制御発振器１４の制御電圧ｖ１と、可変分周器１３の分周数（Ｎ１／Ｎ２）を設定するところがポイントである。その短時間の経過後にはスイッチ１２を開き、可変分周器１３の分周数をＮ２に戻す。   The frequency division number N1 of the reference frequency divider 52 and the frequency division number N2 of the variable frequency divider 13 are determined according to the output frequency f2 of the phase synchronization circuit. The point is that the control voltage v1 of the voltage controlled oscillator 14 and the frequency dividing number (N1 / N2) of the variable frequency divider 13 are set for the time. After the short time has elapsed, the switch 12 is opened, and the frequency dividing number of the variable frequency divider 13 is returned to N2.

本実施形態では、電圧制御発振器１４の特性ばらつきや経年変化や周辺環境の変化による発振周波数の誤差に対して追従することが可能となり、常に小さい誤差で励振信号を水晶発振回路１１に入力することができるので、位相同期回路の第１の実施形態の高速性をより効果的に発揮させることができる。   In the present embodiment, it is possible to follow the oscillation frequency error due to the characteristic variation of the voltage controlled oscillator 14, the secular change, and the change of the surrounding environment, and the excitation signal is always input to the crystal oscillation circuit 11 with a small error. Therefore, the high speed of the first embodiment of the phase locked loop can be more effectively exhibited.

なお、本実施形態では、電圧制御発振器１４の制御電圧を制御電圧モニタ１８でモニタしているが、制御部１５に制御電圧のモニタ機能を備えてもよい。   In this embodiment, the control voltage of the voltage controlled oscillator 14 is monitored by the control voltage monitor 18, but the control unit 15 may be provided with a control voltage monitoring function.

本発明の起動制御回路付き水晶発振回路の実施形態を示す図。The figure which shows embodiment of the crystal oscillation circuit with a starting control circuit of this invention. 水晶発振回路１１の構成例を示す図。FIG. 3 is a diagram illustrating a configuration example of a crystal oscillation circuit 11. 従来構成および本発明構成の水晶発振回路の立ち上がりシミュレーション結果を示す図。The figure which shows the rise simulation result of the crystal oscillation circuit of a conventional structure and this invention structure. 本発明の位相同期回路の第１の実施形態を示す図。The figure which shows 1st Embodiment of the phase-locked loop circuit of this invention. 本発明の位相同期回路の第２の実施形態を示す図。The figure which shows 2nd Embodiment of the phase-locked loop circuit of this invention. 従来の位相同期回路の構成例を示す図。The figure which shows the structural example of the conventional phase-locked loop circuit. 従来の水晶発振回路の構成例を示す図。The figure which shows the structural example of the conventional crystal oscillation circuit.

符号の説明Explanation of symbols

１１ 水晶発振回路（ＸＯＳＣ）
１２ スイッチ（ＳＷ）
１３ 可変分周器
１４ 電圧制御発振器（ＶＣＯ）
１５ 制御部
１６ 容量素子
１７ 信号入力端子
１８ 制御電圧モニタ
５１ 水晶発振回路（ＸＯＳＣ）
５２ 基準分周器
５３ 電圧制御発振器（ＶＣＯ）
５４ 可変分周器
５５ 位相比較器
５６ ループフィルタ
６１ 水晶振動子
６２ インバータ
６３ トランジスタ 11 Crystal oscillation circuit (XOSC)
12 Switch (SW)
13 Variable frequency divider 14 Voltage controlled oscillator (VCO)
DESCRIPTION OF SYMBOLS 15 Control part 16 Capacitance element 17 Signal input terminal 18 Control voltage monitor 51 Crystal oscillation circuit (XOSC)
52 Reference divider 53 Voltage controlled oscillator (VCO)
54 variable frequency divider 55 phase comparator 56 loop filter 61 crystal resonator 62 inverter 63 transistor

Claims (4)

水晶振動子と負性抵抗回路を備えた水晶発振回路の起動制御を行う起動制御回路を含み、一定の発振周波数の信号を出力させる起動制御回路付き水晶発振回路であって、
前記水晶発振回路は、前記水晶振動子を励振する励振信号を外部から入力するための信号入力端子を備え、
前記起動制御回路は、電圧制御発振器を備え、電圧制御発振器の制御電圧を制御して前記発振周波数またはそれに近い周波数を有する前記励振信号を生成し、前記水晶発振回路の起動時に前記励振信号を前記信号入力端子に入力し、前記水晶発振回路の発振周波数が安定する前に前記励振信号の入力を停止する構成である
ことを特徴とする起動制御回路付き水晶発振回路。 A crystal oscillation circuit with a startup control circuit that outputs a signal of a constant oscillation frequency, including a startup control circuit that performs startup control of a crystal oscillation circuit including a crystal resonator and a negative resistance circuit,
The crystal oscillation circuit includes a signal input terminal for inputting an excitation signal for exciting the crystal resonator from the outside.
The start-up control circuit includes a voltage-controlled oscillator, and controls the control voltage of the voltage-controlled oscillator to generate the excitation signal having the oscillation frequency or a frequency close to the oscillation frequency. enter the relaxin signal input terminal, the crystal oscillation start control crystal oscillator whose oscillation frequency is equal to or is configured to stop the input of the excitation signal prior to stabilize the circuit. 水晶振動子と負性抵抗回路を備えた水晶発振回路の起動制御を行う起動制御回路を含み、一定の発振周波数の信号を出力させる起動制御回路付き水晶発振回路であって、
前記水晶発振回路は、前記水晶振動子を励振する励振信号を外部から入力するための信号入力端子を備え、
前記起動制御回路は、電圧制御発振器およびその出力信号を分周する分周器を備え、電圧制御発振器の制御電圧および分周器の分周数を制御して前記発振周波数またはそれに近い周波数を有する前記励振信号を生成し、前記水晶発振回路の起動時に前記励振信号を前記信号入力端子に入力し、前記水晶発振回路の発振周波数が安定する前に前記励振信号の入力を停止する構成である
ことを特徴とする起動制御回路付き水晶発振回路。 A crystal oscillation circuit with a startup control circuit that outputs a signal of a constant oscillation frequency, including a startup control circuit that performs startup control of a crystal oscillation circuit including a crystal resonator and a negative resistance circuit,
The crystal oscillation circuit includes a signal input terminal for inputting an excitation signal for exciting the crystal resonator from the outside.
The start control circuit includes a voltage controlled oscillator and a frequency divider that divides the output signal thereof, and controls the control voltage of the voltage controlled oscillator and the frequency dividing number of the frequency divider to have the oscillation frequency or a frequency close thereto. in configurations wherein generating an excitation signal, the excitation signal at the start of the crystal oscillation circuit is input before relaxin signal input terminal, the oscillation frequency of the crystal oscillation circuit stops input of the excitation signal before stable A crystal oscillation circuit with a start-up control circuit characterized by 水晶発振回路から出力される一定の発振周波数の出力信号を基準分周器（分周数Ｎ１）を介して分周した信号と、電圧制御発振器の出力信号を可変分周器（分周数Ｎ２）を介して分周した信号とを位相比較器に入力し、その位相誤差信号をループフィルタを介して当該電圧制御発振器に制御電圧としてフィードバックし、前記電圧制御発振器から水晶発振回路で得られる周波数安定度と同等な安定度をもつ任意の周波数の信号を出力する位相同期回路において、
前記水晶発振回路は、水晶振動子を励振する励振信号を外部から入力するための信号入力端子を備え、
前記可変分周器の出力信号を分岐して前記信号入力端子に入力する経路に挿入され、前記可変分周器の出力信号を前記水晶発振回路に前記励振信号として入力するか否かを切り替えるスイッチと、
前記位相同期回路の起動時に前記スイッチを閉じ、前記励振信号の周波数が前記水晶発振回路の発振周波数またはそれに近い周波数になるように、前記電圧制御発振器の制御電圧と前記可変分周器の分周数Ｎ２′を設定して生成した励振信号を前記信号入力端子に入力し、前記水晶発振回路の発振周波数が安定する前に前記スイッチを開いて前記励振信号の入力を停止し、前記電圧制御発振器の制御電圧の印加を停止し、前記可変分周器の分周数Ｎ２に設定する制御手段と
を備えたことを特徴とする位相同期回路。 A signal obtained by frequency-dividing an output signal of a constant oscillation frequency output from the crystal oscillation circuit through a reference frequency divider (frequency division number N1) and a voltage-controlled oscillator output signal are variable frequency dividers (frequency division number N2). ) Is input to the phase comparator, and the phase error signal is fed back as a control voltage to the voltage controlled oscillator via the loop filter, and the frequency obtained from the voltage controlled oscillator by the crystal oscillation circuit. In a phase locked loop that outputs a signal of any frequency with stability equivalent to the stability,
The crystal oscillation circuit includes a signal input terminal for inputting an excitation signal for exciting a crystal resonator from the outside.
Is inserted in the path to be input before the venlafaxine signal input terminal branches the output signal of the variable frequency divider, whether to input the output signal of the variable frequency divider as the excitation signal to the crystal oscillation circuit A switch to switch,
When the phase-locked loop circuit is activated, the switch is closed, and the control voltage of the voltage-controlled oscillator and the frequency divider of the variable frequency divider are set so that the frequency of the excitation signal is equal to or close to the oscillation frequency of the crystal oscillation circuit. the excitation signal generated by setting the number N2 'entered before relaxin signal input terminal, the oscillation frequency of the crystal oscillation circuit stops input of the excitation signal to open the switch prior to stabilize, the voltage And a control means for stopping application of the control voltage of the controlled oscillator and setting the frequency division number N2 of the variable frequency divider. 請求項３に記載の位相同期回路において、
前記電圧制御発振器の制御電圧をモニタする制御電圧モニタを備え、
前記制御手段は、前記制御電圧モニタから間欠動作する位相同期回路の動作安定時における前記電圧制御発振器の制御電圧ｖ１、前記基準分周器の分周数Ｎ１および前記可変分周器の分周数Ｎ２を保持し、間欠動作する位相同期回路の起動時に当該制御電圧ｖ１を前記電圧制御発振器に設定し、分周数Ｎ２′＝Ｎ１／Ｎ２を前記可変分周器に設定する構成である
ことを特徴とする位相同期回路。 The phase locked loop circuit according to claim 3 ,
A control voltage monitor for monitoring a control voltage of the voltage controlled oscillator;
The control means includes a control voltage v1 of the voltage controlled oscillator, a frequency division number N1 of the reference frequency divider, and a frequency division number of the variable frequency divider when the operation of the phase locked loop that operates intermittently from the control voltage monitor is stable. The control voltage v1 is set in the voltage controlled oscillator at the start of the phase synchronization circuit that holds N2 and operates intermittently, and the frequency division number N2 ′ = N1 / N2 is set in the variable frequency divider. A characteristic phase synchronization circuit.
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