JP5092338B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a method for manufacturing a semiconductor device including a polyimide passivation step and a step of thinning a back surface side of a semiconductor substrate as a manufacturing process. In particular, the present invention relates to a manufacturing method for reducing variations in forward voltage drop characteristics of a semiconductor device manufactured by such a manufacturing method.

  In order to reduce the cost of a power semiconductor element, for example, an IGBT (Insulated Gate Bipolar Transistor) which is a typical power semiconductor element has a structure using an expensive epitaxial wafer, and a non-use using an inexpensive FZ silicon wafer (semiconductor substrate). Improvements are being made to punch-through type IGBTs, and further to field stop type IGBTs for improving characteristics by thinning such FZ silicon wafers (semiconductor substrates).

  On the other hand, in a power diode used as a freewheeling diode in a power conversion circuit or the like in combination with the IGBT or the like, an inexpensive FZ silicon wafer (semiconductor substrate) and a device thinned by back surface grinding are applied. Yes. Both of the freewheeling diodes used in combination with the above-described IGBT are required to be not only low on-voltage but also low switching loss devices. Therefore, in these manufacturing processes, lifetime control of minority carriers is performed by electron beam irradiation and subsequent annealing treatment. As already known, lifetime control by electron beam irradiation is performed by forming a main pn junction structure on a semiconductor substrate and then irradiating the electron beam to remove crystal defects that become recombination centers of minority carriers in the substrate. In this method, the lifetime is once reduced by induction, and the crystal defects are recovered by a required amount by a thermal history by annealing treatment, and adjusted to a required lifetime value. When the annealing temperature is increased, the recovery rate of crystal defects is increased, so that the lifetime is increased and the on-voltage is decreased, but the switching loss is increased. The reverse occurs if the annealing temperature is lowered. Therefore, it is necessary to adjust the lifetime to be optimal for the required device characteristics in view of both characteristics. For electron beam irradiation, for example, crystal defects were introduced into the semiconductor substrate with an acceleration voltage of 4.8 MeV and a dose of 100 kGy. According to the annealing treatment at 330 ° C. to 350 ° C. for about 1 hour after the electron beam irradiation, favorable characteristics can be obtained with respect to the on-voltage and switching loss.

FIG. 3 is a flow diagram of a diode manufacturing process using such an n-type FZ silicon semiconductor substrate. FIG. 3 is a manufacturing process flow diagram using an enlarged cross-sectional view of one chip portion of a wafer (semiconductor substrate) manufactured by arranging and arranging a plurality of element structures (chips).
First, on one surface of the n-type FZ silicon semiconductor substrate 11, an anode p ⁺ layer 12, a peripheral breakdown voltage structure portion 13 such as a guard ring structure, an aluminum-based anode metal electrode film 14 and the like are formed (FIG. 3A). ). Next, the FZ silicon semiconductor substrate 11 is thinned to a required thickness determined by the withstand voltage through grinding, polishing, and etching of the back surface side of the silicon semiconductor substrate by the back surface back grinding process (FIG. 3B). Next, in order to form the cathode n ⁺ layer 15 on the back surface, an impurity introduction step by ion implantation of phosphorus, arsenic or the like and an activation step thereof are performed (FIG. 3C). Thereafter, a polyimide film 16 is applied on the surface side and patterned to selectively form a passivation film on the peripheral voltage withstanding structure 13 (FIG. 3D). Next, electron beam irradiation and annealing are performed, and the lifetime of the diode is adjusted so as to be optimal for the design element characteristics as described above (FIG. 3E). Finally, a cathode metal electrode film 17 such as Ti / Ni / Au is formed on the surface of the cathode n ⁺ layer 15 on the back surface, and the wafer process is completed (FIG. 3F). Thereafter, chips are cut from the wafer by dicing with a high-speed rotating diamond blade, and are individually assembled into a package. In the manufacturing process of the diode wafer shown in FIG. 3, the same thin wafer processing technology and polyimide passivation technology as those already employed in the manufacturing process of the non-punch through and field stop type IGBTs are used. It is a feature.

On the other hand, a method for manufacturing a diode including a polyimide passivation film forming step included in the diode wafer manufacturing step shown in FIG. 3 and a manufacturing process including an electron beam irradiation step for adjusting the magnitude of the on-voltage has already been disclosed in Patent Documents. Furthermore, the relationship between the ON voltage, the curing temperature at the time of forming the polyimide film, and the annealing temperature for electron beam irradiation in the manufacturing process of the diode is also disclosed in the same document (Patent Document 1). ).
JP-A-8-274314

  However, one of the important semiconductor characteristics of the semiconductor device such as the diode described above is a forward voltage drop (hereinafter referred to as an on-voltage). However, the conventional semiconductor device manufacturing method, particularly the wafer manufacturing process, is back grounded. In a method for manufacturing a semiconductor device comprising a wafer thinning process for scraping the back surface of the wafer to a thickness required for pressure resistance, a polyimide resin film passivation process and a lifetime control process by valence particle irradiation on the front surface side of the wafer. When the diameter of the wafer (semiconductor substrate) is increased, particularly in the case of a wafer having a diameter of 6 inches or more, there is a problem that on-voltage variation among a plurality of chips in the wafer increases, and a chip with a defective on-voltage is likely to be generated. The distribution state of the variation of the on-voltage in the wafer indicates, for example, a distribution state in which the on-voltage of the chip in the central portion in the wafer is high and the on-voltage of the chip from the central portion to the peripheral portion gradually decreases. In particular, when the wafer diameter is 6 inches or more, the larger the chip at the center of the wafer is, the more likely it is to be larger. Naturally, such a variation in the on-voltage is desirably small because it leads to an improvement in the yield rate.

  The present invention has been made in view of the above points, and an object of the present invention is to reduce the variation in on-voltage even when a wafer having a diameter of 6 inches or more is used. Another object of the present invention is to provide a method of manufacturing a semiconductor device capable of improving the rate.

  According to the first aspect of the present invention, the step of forming the first semiconductor functional region on one main surface of the semiconductor substrate, the substrate thinning step of cutting the other main surface, and the other main surface side In a method for manufacturing a semiconductor device comprising a step of forming a second semiconductor functional region, a polyimide resin film passivation treatment step, a charged particle irradiation and an annealing treatment step for lifetime control, a first surface on one main surface of the semiconductor substrate Manufacturing of a semiconductor device after the step of forming a semiconductor functional region and before the substrate thinning step, sequentially performing the polyimide resin film passivation treatment step and the charged particle irradiation and annealing step for lifetime control By the method, the object is achieved.

  According to the invention of claim 2, the curing temperature of the polyimide resin film in the polyimide resin passivation treatment step is 370 ° C. or higher, and charged particle irradiation and annealing treatment for the lifetime control. The method for manufacturing a semiconductor device according to claim 1, wherein the processing temperature in step 1 is any one of 300 ° C. to 360 ° C.

According to the invention described in claim 3, it is more preferable that the semiconductor device is a semiconductor device according to claim 1 or 2 in which the semiconductor device is a diode.
According to the invention of claim 4, the invention further comprises a step of forming a p-type first semiconductor functional region on one main surface of the n-type semiconductor substrate. It is desirable to use the method for manufacturing a semiconductor device according to any one of the above.

According to the invention described in claim 5, the charged particle irradiation is any one of electron beam irradiation, proton irradiation, and helium irradiation. More preferably, the semiconductor device manufacturing method is used.
In short, the present invention applies a polyimide coating and patterning process in a thick wafer state in order to suppress variations in on-voltage of semiconductor devices such as diodes. After that, the manufacturing method of the semiconductor device performs the back surface n ⁺ cathode layer forming step and the back surface electrode forming step through the electron beam irradiation and annealing process, the back grinding step, the back surface grinding and the silicon etching step.

  According to the present invention, it is possible to provide a method for manufacturing a semiconductor device with a high on-voltage non-defective product rate while suppressing variations in on-voltage within a wafer.

  FIG. 1 is a cross-sectional view of main parts of a semiconductor substrate showing a method for manufacturing a diode according to Example 1 of the present invention. FIG. 2 is an on-voltage distribution diagram in the semiconductor substrate of each diode produced by the present invention and the conventional manufacturing method. FIG. 3 is a fragmentary cross-sectional view of a semiconductor substrate showing a conventional diode manufacturing method.

Hereinafter, a method of manufacturing a semiconductor device according to the present invention will be described in detail with reference to the drawings. The present invention is not limited to the description of the examples described below unless it exceeds the gist.
FIG. 1 illustrates a first embodiment of a method for manufacturing a semiconductor device according to the present invention, with reference to cross-sectional views of semiconductor substrates (wafers) arranged for each manufacturing process of main semiconductor substrates. Actually, a plurality of the cross-sectional structures shown in FIG. 1 are arranged on the entire wafer.

For example, in order to manufacture a diode having a withstand voltage of 600 V and 1200, a specific resistance of about 30 Ωcm and about 60 Ωcm and a thickness of about 500 to 600 μm, respectively, for example, one main of an n-type FZ silicon semiconductor substrate 1 having a diameter of 6 inches. On the surface (surface), as the first semiconductor functional layer, by ion implantation of boron, an anode p ⁺ layer 2 having a surface impurity concentration of 5 × 10 ¹⁶ cm ³ and a depth of 3 μm is selected simultaneously with the formation of this anode p ⁺ layer Peripheral breakdown voltage structure 3 such as a guard ring formed as an example, as one of the peripheral breakdown voltage structures, formation of a field oxide film (not shown) formed on the surface, anode metal electrode film in ohmic contact with the anode layer 4 is formed of an aluminum-based metal film or the like (FIG. 1A).

Next, the polyimide resin film 6 is patterned as a surface passivation film in the state of the thick silicon semiconductor substrate 1 at the time of introduction into the process as described above so as to be mainly applied to the surface of the peripheral pressure-resistant structure 3, and the glass transition of the resin It hardens | cures at about 380 degreeC higher than temperature (FIG.1 (b)).
Next, in order to control the lifetime of minority carriers of the diode, electron beam irradiation and annealing treatment are performed (FIG. 1C). For the electron beam, crystal defects are uniformly introduced into the semiconductor substrate by irradiating with an acceleration voltage of 4.8 MeV and a dose of 100 kGy. After the electron beam irradiation, the lifetime is adjusted to a required value by annealing for about 1 hour at any temperature in the range of 300 ° C. to 360 ° C.

As described with reference to FIG. 3, conventionally, the polyimide resin film passivation process (FIG. 3D) is performed by the substrate thinning process (FIG. 3B) by grinding the back surface of the silicon semiconductor substrate and the cathode n ⁺ on the back surface. This is performed after the layer formation step (FIG. 3C), and the thickness of the large-diameter wafer having a diameter of 6 inches or more is reduced to about 80 μm at 600 V withstand voltage and 150 μm at 1200 V withstand voltage. The wafer warpage is very large due to the influence of the polyimide film coating, and the crystal defects due to electron beam irradiation are not uniform due to the warpage. On the other hand, in the case of Example 1 of the present invention, since the polyimide film is formed on a thick wafer having a wafer thickness of about 500 μm to 600 μm at the beginning, the wafer warpage is small. In the first embodiment of the present invention, since the wafer warpage is reduced as described above, even when a large-diameter wafer of 6 inches or more is used, the distortion of the wafer is reduced, and the crystal defect when the electron beam is irradiated is the wafer. It seems that the distribution of the on-voltage is relatively uniform, the variation in the on-voltage is reduced, and the on-voltage non-defective rate is improved.

  The order of the polyimide process, the electron beam irradiation, and the annealing process is determined for the following reason. Since the polyimide curing temperature is around 380 ° C., the annealing temperature after electron beam irradiation should be higher than 300 ° C. to 360 ° C. In addition, for the polyimide resin curing treatment, it is common to use a normal baking furnace with much lower accuracy than the high-precision temperature control required for the annealing treatment after electron beam irradiation. It is not suitable for annealing treatment. In particular, since the curing temperature of the polyimide resin is higher than the annealing temperature required after electron beam irradiation, the polyimide treatment is performed before the electron beam irradiation and annealing process. Further, it is determined from the fact that it is not changed in the subsequent processes. Next, the back surface side of the silicon semiconductor substrate is thinned to a predetermined thickness determined by the withstand voltage by a back grind (back surface thinning) process (FIG. 1D).

For example, when the breakdown voltage is 600 V, the silicon substrate is processed to a thickness of about 80 μm. Next, by performing ion implantation of phosphorous, arsenic, and the like as a second semiconductor functional layer and an activation process on the back surface, the cathode n ⁺ layer 5 having an impurity concentration of 1 × 10 ¹⁹ cm ³ and a depth of about 1 μm or less is formed. (FIG. 1 (e)).
The process order of the electron beam irradiation process and the back-side back grinding process of the semiconductor substrate is determined for the following reason. One is that running the process in the state of a thinly processed semiconductor substrate after the back-grinding process is likely to cause defects such as cracks and cracks. Second, as described above, it is estimated from the measurement results that electron beam irradiation in the state of a semiconductor substrate that has been processed thinly after the back grinding process and has a warped wafer causes an increase in on-voltage variation. It is decided from what is done. Therefore, in order to shorten the process flow of the thinly processed semiconductor substrate as much as possible and to irradiate the thick semiconductor substrate with the electron beam, the back grinding process is performed after the electron beam irradiation process. Finally, when the cathode metal electrode film 7 such as Ti / Ni / Au is formed on the surface of the cathode n ⁺ layer, the wafer process of the diode is completed (FIG. 1 (f)).

  FIG. 2 shows the horizontal and vertical directions of the 6-inch wafer surface on the horizontal axis and the on-voltage (forward voltage drop) on the vertical axis in order to show the in-wafer variation of the on-voltage showing the effect of the first embodiment. FIG. 6 is an on-voltage distribution diagram of a diode. (A), (b) is an on-voltage distribution diagram of the diode which shows the effect by the manufacturing method of the semiconductor device concerning the past and this invention, respectively. First, the backside grinding process on the back side of the semiconductor substrate is processed into a thin wafer and then the polyimide process is applied, and then the electron beam irradiation is applied to a series of conventional manufacturing methods shown in FIG. In the diode according to the order of the manufacturing process according to the present invention shown in Example 1, it is apparent that the variation in the on-voltage distribution in the semiconductor substrate is greatly improved.

In the description of the first embodiment, the electron beam irradiation is used as the valence particle irradiation used for lifetime control, but proton irradiation, helium irradiation, and the like can also be used.
In the manufacturing method of other semiconductor devices such as MOSFET and IGBT using polyimide as a surface protective film and having a process of controlling lifetime by irradiation with charged electron particles, the same process is performed when the same semiconductor substrate thinning process is performed. Of course it is effective.

It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the diode concerning Example 1 of this invention. It is an on-voltage distribution diagram in a semiconductor substrate of each diode produced by the present invention and a conventional manufacturing method. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the conventional diode.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1, ... Wafer, semiconductor substrate, silicon semiconductor substrate 2, ... anode p ⁺ layer, 1st semiconductor functional layer 3, ... peripheral pressure | voltage resistant structure, guard ring 4, ... anode metal electrode film 5, ... n ⁺ cathode layer, 2nd Semiconductor functional layer 6, ... Polyimide resin film 7, ... Cathode metal electrode film

Claims (5)

Forming a first semiconductor functional region on one main surface of a semiconductor substrate; thinning a substrate on the other main surface; forming a second semiconductor functional region on the other main surface; polyimide resin film passivation treatment In a manufacturing method of a semiconductor device including a charged particle irradiation and annealing process for lifetime control, after the process of forming a first semiconductor functional region on one main surface of the semiconductor substrate, A method for manufacturing a semiconductor device, comprising: sequentially performing the polyimide resin passivation processing step, and charged particle irradiation and annealing processing steps for lifetime control, before the forming step. The curing temperature of the polyimide resin film in the polyimide resin passivation treatment step is 370 ° C. or higher, and the treatment temperature in the charged particle irradiation and annealing treatment for the lifetime control is any one of 300 ° C. to 360 ° C. 2. The method of manufacturing a semiconductor device according to claim 1, wherein: 3. The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is a diode. 4. The method of manufacturing a semiconductor device according to claim 1, further comprising a step of forming a p-type first semiconductor functional region on one main surface of the n-type semiconductor substrate. 5. The method for manufacturing a semiconductor device according to claim 1, wherein the charged particle irradiation is any one of electron beam irradiation, proton irradiation, and helium irradiation.

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