JP5091195B2 - High frequency power amplifier circuit and design method thereof - Google Patents

Description

  The present invention relates to a high frequency power amplifier circuit and a design method thereof.

  In high-frequency amplifier circuits, it is a big problem in application to suppress the wear deterioration of transistors and to ensure long-term reliability, and research and improvement on wear deterioration have been conducted for a long time. This problem is particularly remarkable in a high-frequency power amplifier circuit in which a transistor operates on a large signal. This is because in the high frequency power amplifier circuit, the applied current voltage to the transistor is large and a large bias stress is applied.

  Bias stress promotes deterioration of semiconductor characteristics by flowing current to a semiconductor constituting the transistor.

  Particularly remarkable deterioration is seen in an increase in parasitic resistance due to a decrease in transistor carrier concentration, a decrease in amplification factor, and the like. As a result, the high frequency characteristics of the transistor are also deteriorated, and it is finally determined that the high-frequency power amplifier circuit has failed.

  The rate of deterioration depends on the magnitude of bias stress. When the applied voltage is low and the current flowing through the transistor is small, the deterioration rate is slow. Even when the applied voltage is high, the deterioration rate is relatively slow when the current flowing through the transistor is small. Considering that the speed of deterioration is determined by the synergistic effect of voltage and current, a general relationship between the deterioration speed and the bias stress is shown in FIG. It can be seen that when the transistor is operated in the high reliability region 116 (region inside the triangle) shown in FIG. 3, the deterioration is suppressed, and the failure of the high frequency power amplifier circuit is unlikely to occur.

  Next, the design of the high frequency power amplifier circuit will be described. In general, conjugate matching is often used as an output load condition of a transistor used in a high-frequency power amplifier circuit. When the impedance when viewing the inside of the transistor from the transistor output terminal is Z + jX, conjugate matching means that Z−jX is used as a load. This condition maximizes the transmitted power because the terms related to the reactance X cancel each other at the transistor output terminal, but other characteristics are not particularly considered. Other matching conditions are experimentally determined to satisfy desired characteristics mainly by load pull measurement (Non-Patent Document 1).

  For example, output load conditions that maximize the gain and output power are checked in advance, and the output load circuit is designed to satisfy those conditions. Similarly, it is often the case that an output load circuit that maximizes power added efficiency and linearity is empirically examined and an output load circuit is designed to satisfy the condition. Since these output load conditions are purely empirical, they are applicable only to the specific transistor bias conditions measured and do not have information about the reliability of the high frequency power amplifier circuit. The conventional output load conditions described above have not been optimized from the viewpoint of the reliability of the transistor amplifier circuit, and there has been no design guideline for providing an output load condition that minimizes the transistor degradation rate.

  Even in such a case, it is finally necessary to ensure the reliability of the high frequency power amplifier circuit. Therefore, as a consideration for reliability at the initial stage of design, the device size is given a margin based on empirical data, or the load line at the transistor output terminal using the large signal simulation is shown in FIG. It was confirmed for a while that it almost fits in the sex region 116. After that, it was necessary to finally conduct a deterioration acceleration test by bias stress to ensure that the product meets the specifications. If this test produces inadequate results, it is necessary to make the device larger and start over from the beginning of the design.

"Basics and Applications of MMIC Technology", Yasuyuki Ito, Nao Takagi, Realize, 1996, pp. 52, ISBN4-947655-87-9 “Reliability of Ku-Band GaAs Power FETs under High Stressed RF Operation,” Reliability Physics Symposium, 1983. 21st Annual, April 1983 Pages: 297-301, White, P. et al. M.M. Rogers, C .; G. Hewitt, B .; S. “Reliability of power GaAs field-effect transistors,” Electron Devices, IEEE Transactions on, Volume 29, Issue 3, Mar 1982 Page (s): 395-401, Hu. Wemble, S .; H. Irvin, J .; C. Niehaus, W .; C. Hwang, J .; C. M.M. Cox, H .; M.M. Schlosser, W .; O. DiLorenzo, J .; V.

  Conventionally, however, there is no matching circuit design method optimized from the viewpoint of reliability against bias stress in a high-frequency power amplifier circuit, and this has been dealt with mainly by increasing the device based on empirical data. Therefore, there is a problem that a larger device is required, power consumption is increased, efficiency is lowered, and heat dissipation is costly. If the final reliability test yielded insufficient results, it was necessary to make the device larger and start over.

  The present invention has been made in view of the above-described problems, and its object is to improve the reliability of a high-frequency power amplifier circuit, extract more output power, reduce power consumption, and improve efficiency. In other words, it is possible to reduce the heat radiation cost and shorten the product development time.

であることを特徴とする。 The high frequency power amplifier circuit of the present invention is a high frequency power amplifier circuit comprising a transistor and an output load circuit connected to an output side of the transistor, wherein the transistor in a region where an AC load line of the transistor output may exist The high-reliability region determined as a region having high reliability includes an AC load line in the intrinsic region, which is a core portion that is composed of the drain current source and drain conductance of the transistor and is responsible for transistor operation. The output load circuit is characterized in that the transistor is a field effect transistor, the output load circuit is connected to the drain of the transistor, the gate-drain capacitance of the transistor is Cgd, and the drain source of the transistor is The capacitance between the Cds and the output of the transistor When the gradient of the AC load line is Gd, the gradient of the AC load line in the intrinsic region of the transistor is GL, and the drain resistance of the transistor is Rd, Re (Z) and imaginary number corresponding to the real number of the impedance of the output load circuit The minute Im (Z) is

It is characterized by being.

であることを特徴とする。 The method for designing a high-frequency power amplifier circuit according to the present invention is a method for designing a high-frequency power amplifier circuit including a transistor and an output load circuit connected to the output side of the transistor. In the intrinsic region, which is a core part responsible for transistor operation, which is composed of a drain current source and drain conductance of the transistor in a predetermined high reliability region as a region in which the transistor has high reliability. The output load circuit is characterized to include a load line , the transistor is a field effect transistor, the output load circuit is connected to a drain of the transistor, and a gate-drain capacitance of the transistor is defined as Cgd, The drain-source capacitance of the transistor is Cds, When the gradient of the AC load line of the transistor output is Gd, the gradient of the AC load line in the intrinsic region of the transistor is GL, and the drain resistance of the transistor is Rd, Re (Z ) And the imaginary part Im (Z) are

It is characterized by being.

  It is characterized by being.

  According to the present invention, the reliability of the high-frequency power amplifier circuit is improved, more output power can be extracted, power consumption is reduced, efficiency is improved, heat radiation cost can be reduced, and product development time can be shortened. is there.

It is a figure which shows the detailed equivalent circuit of a field effect transistor. It is a figure which shows the relationship between the cross-sectional structure of a field effect transistor, and an equivalent circuit. It is a figure which shows the relationship between the reliability of a field effect transistor, and a current-voltage characteristic. It is a figure which shows the equivalent circuit of the simplified field effect transistor. It is a figure which shows the example of the load line by the conventional conjugate matching. It is a figure which shows the example of the load line by embodiment of this invention. It is a figure which shows the evaluation circuit of the load condition using a SPICE model. It is a figure which shows the example of the load line using a SPICE model.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. Specifically, a high frequency power amplifier circuit including a transistor and an output load circuit connected to the output side of the transistor and a design method thereof will be described.

  FIG. 1 shows a detailed equivalent circuit of a field effect transistor, which is a kind of transistor used in an embodiment of the present invention, an external load, and definitions of current voltages of respective parts. The equivalent circuit includes gate resistance 6 (Rg), source resistance 8 (Rs), drain resistance 7 (Rd), drain conductance 13 (Gd), drain current source 12 (gm), gate-source capacitance 9 (Cgs), gate A drain-to-drain capacitance 10 (Cgd), a drain-source capacitance 11 (Cds), an input load 1 (ZS), and an output load 2 (ZL) are included. Here, the drain current source 12 is generally a non-linear current source represented by a voltage applied to the gate-source capacitance 9. Further, the gate-source capacitance 9, the gate-drain capacitance 10, and the drain-source capacitance 11 are also nonlinear capacitances whose capacitance values change depending on the voltage applied to them.

  FIG. 2 shows the relationship between the cross-sectional structure of the field effect transistor and the above-described equivalent circuit. It can be seen that the resistors, capacitors, etc. in the equivalent circuit of FIG. 1 are associated with the physical structure shown in FIG. Here, the characteristic deterioration mechanism of the field effect transistor will be described. A large bias voltage is applied between the gate electrode 110 and the drain electrode 112 during the operation of the transistor, and a drain depletion layer 115 is formed in the vicinity of the gate electrode 110. Electrons flowing in the drain depletion layer 115 are subjected to electric field acceleration by a high electric field in the depletion layer, become hot electrons, and damage surrounding semiconductors. As a result of the accumulation of the damage, the electron concentration in the vicinity of the drain depletion layer 115 is reduced and the electron mobility is also lowered, so that transistor characteristics are deteriorated. In other words, it can be understood that intensive characteristic deterioration occurs in the drain current source 12 and the drain conductance 13 which are the parts representing the drain depletion layer 115 in the elements constituting the equivalent circuit. The drain current source 12 and the drain conductance 13 are collectively referred to as an intrinsic region 18 in the sense that it is a core part responsible for transistor operation. In order to prevent rapid deterioration due to the bias stress of the transistor, it is essentially required to prevent the deterioration of the intrinsic region 18.

  FIG. 3 shows an example of the relationship between transistor reliability and current-voltage characteristics. The region inside the triangle shown in FIG. 3 is the high reliability region 116 with little bias stress, and the outside is the low reliability region 117 with large bias stress. The deterioration of the characteristics of the transistor proceeds rapidly under the condition where a large voltage and current are applied simultaneously, and in the opposite case, the deterioration of the device characteristics is small. This is a reasonable tendency considering the characteristic deterioration mechanism of the intrinsic region 18. That is, the deterioration is promoted as the condition where more hot electrons are generated. Here, a method of taking out as much output power as possible while suppressing deterioration of the transistor is considered. Considering the deterioration rate, the condition that the load line is within the triangle shown in FIG. 3 is preferable. On the other hand, in order to increase the output power, it is preferable that the load line runs as much as possible in the upper right corner of the triangle. Considering these factors, it can be seen that both the suppression of deterioration and the maximization of output are performed under the condition that the load line runs on the hypotenuse of the triangle indicated by the broken line in FIG. Here, the load line at that time is defined as the optimum load line 118, and the gradient is GL.

  The design method in the embodiment of the present invention in which the degradation rate of the field effect transistor is minimum and the maximum output power can be obtained will be described using the matters described so far. In the conventional design method, the load line is defined at the drain terminal 4 of FIG. In the embodiment of the present invention, there is a significant difference from the prior art in that the load line in the intrinsic region 18 of the transistor is changed. The current-voltage characteristic of the intrinsic region 18 with respect to the AC signal is strongly influenced by the peripheral gate-source capacitance 9, the gate-drain capacitance 10, and the drain-source capacitance 11, causing phase rotation, and the load line defined by the drain terminal 4 It will be different. This difference becomes more pronounced as the frequency becomes higher, and the two tend to be completely different in a frequency band exceeding 10 GHz. Considering that degradation due to bias stress occurs in the intrinsic region 18 of the device, the condition that the load line defined by the intrinsic region current 17 and intrinsic region voltage 16 essentially runs on the broken line shown in FIG. It can be seen that this is the optimum value for obtaining the maximum output power within the range in which the characteristics can be maintained. In the conventional design method, this fact is not taken into consideration even at a high frequency, and a load line defined by the drain terminal 4 is used as an alternative. For this reason, the bias stress on the intrinsic region 18 is not minimized, and many adjustments based on accumulated experience are required.

Next, the difference between the load condition of the embodiment of the present invention and the normal conjugate matching condition defined by the conventional drain terminal 4 will be described using a calculation formula, and the difference between the two will be clarified. The detailed equivalent circuit of FIG. 1 uses a simplified equivalent circuit because it is difficult to derive an analytical expression. First, let us consider a case where the frequency is sufficiently high and the impedance of the gate-source capacitance 9 and the impedance of the input load 1 are sufficiently low, and these can be approximated to zero. Consider a case where a field effect transistor is fabricated so that the source resistance 8 is sufficiently low and can be regarded as approximately zero. Further, the non-linearity of each capacitor and drain current source 12 is ignored. In this case, the equivalent circuit of FIG. 1 is rewritten as shown in FIG. The conjugate matching condition at the drain terminal 4 at the frequency w is expressed by the expressions (1) and (2), and the condition that the load line of the intrinsic region 18 runs on the hypotenuse of the triangle indicated by the broken line in FIG. Shown in (4).

Here, Cgd is a gate-drain capacitance of the transistor.
Cds is the drain-source capacitance of the transistor.
Gd is the gradient of the AC load line of the transistor output.
GL is the gradient of the AC load line in the intrinsic region of the transistor.
Rd is the drain resistance of the transistor.
Re (Z) and Im (Z) are respectively the real number and the imaginary number of the impedance of the output load circuit.

  Using these relational expressions, FIG. 5 shows an example of conventional conjugate matching, and FIG. 6 shows an example of a load line according to the embodiment of the present invention. In both figures, two types of load lines defined by the drain terminal 4 and the intrinsic region 18 and an optimum load line 118 are shown superimposed. Moreover, both figures are shown so that the high frequency electric power taken out by the output load 2 may become the same. Under the conventional conjugate matching condition shown in FIG. 5, it can be seen that load lines of elliptical orbits are drawn in both the drain terminal 4 and the intrinsic region 18. As a result, the conventional intrinsic region load line 118 easily enters the low reliability region 117, and the deterioration of the transistor is promoted. On the other hand, the load condition according to the embodiment of the present invention shown in FIG. 6 is adjusted to be a pure resistance load line having a gradient GL in the intrinsic region 18, and only the drain terminal 4 becomes an elliptical orbit load line. I understand. The intrinsic region load line 123 according to the embodiment of the present invention coincides with the optimum load line 118 (which is slightly shifted for easy viewing in FIG. 6), and always operates in the high reliability region 116. Thus, it can be seen that the load condition in the embodiment of the present invention is excellent from the viewpoint of reliability when the output power of the same magnitude is obtained.

  On the contrary, it can be seen that in order to obtain the same reliability as that of the embodiment of the present invention in the conventional high frequency power amplifier circuit based on conjugate matching, it is necessary to use a larger transistor. By using the present invention, high-frequency power can be extracted more efficiently than before, and power consumption can be reduced by reducing power consumption, reducing trial and error and reducing product development time. It becomes.

  In order to obtain sufficient design accuracy in actual circuit design, it is necessary to consider all circuit elements and nonlinearities included in the detailed equivalent circuit of FIG. 1, and a nonlinear large signal transistor model such as SPICE is used for this. The method is easy to implement. A circuit diagram for performing this operation is shown in FIG. In this case, the load line of the intrinsic region 18 is calculated as a numerical solution. Therefore, the authenticity according to the embodiment of the present invention is obtained as a numerical solution while manipulating the real part of input load 1 and output load 2 in FIG. 7 from zero to plus infinity and the imaginary part from minus infinity to plus infinity. The condition where the area load line 123 matches the optimum load line 118 is searched. The reason for operating not only the output load 2 but also the input load 1 is that the transistors are not unidirectional at high frequencies. In this case, the condition of the input load 1 also slightly affects the trajectory of the intrinsic region load line 123. In addition, since there are requirements for other characteristics, power gain, and input reflection loss, it is necessary to operate the input load 1 at the same time. In the SPICE large signal transistor model of FIG. 7, the intrinsic region voltage 16 and the intrinsic region current 17 can be acquired as the node voltage and node current of the node representing the drain current source 12. It is necessary to use a current-voltage relationship that provides the optimum load line 118 of the transistor, which is determined in advance by a bias stress test of the transistor.

  FIG. 8 shows an example of a numerical solution based on the SPICE large signal transistor model. As a large signal transistor model of SPICE, a Curtis model is used as a DC model representing the drain current source 12, and a stats model is used as a capacity model representing the gate-source capacitance 9, the gate-drain capacitance 10, and the drain-source capacitance 11. ing. The device parameters necessary for the SPICE model are determined in advance by evaluating the current-voltage characteristics and S parameters of the field effect transistor to be modeled. Since the calculation is performed in the time domain, the locus is at the bias point 125 in FIG. 8 at time zero, and with time, the intrinsic region load line 123 of the embodiment of the present invention or the drain terminal load line of the embodiment of the present invention. It converges to 122. Here, since the input / output load conditions are optimized so that the intrinsic region load line 123 and the optimum load line 118 of the embodiment of the present invention shown in FIG. It is possible to stay within a region corresponding to the three high reliability regions 116.

  In this embodiment, the field effect transistor is taken as an example, but the same load condition exists in the case of the bipolar transistor, and the reliability of the high frequency power amplifier circuit can be improved. This is because even in bipolar transistors, bias stress to the intrinsic region is an essential factor for characteristic deterioration, and the load line in the intrinsic region has not been optimized under conventional matching conditions.

DESCRIPTION OF SYMBOLS 1 Input load 2 Output load 3 Gate terminal 4 Drain terminal 5 Source terminal 6 Gate resistance 7 Drain resistance 8 Source resistance 9 Gate-source capacity 10 Gate-drain capacity 11 Drain-source capacity 12 Drain current source 13 Drain conductance 14 Drain voltage 15 Drain current 16 Intrinsic region voltage 17 Intrinsic region current 18 Intrinsic region 110 Gate electrode 111 Source electrode 112 Drain electrode 113 Semiconductor active layer 114 Semiconductor substrate 115 Drain depletion layer 116 High reliability region 117 Low reliability region 118 Optimal load line 119 Conventional Drain terminal load line 120 Conventional intrinsic region load line 122 Drain terminal load line 123 of the embodiment of the present invention Intrinsic region load line of the embodiment of the present invention 124 Gate voltage 125 Bias point

Claims (2)

In a high frequency power amplifier circuit comprising a transistor and an output load circuit connected to the output side of the transistor,
A transistor configured by a drain current source and a drain conductance of the transistor in a predetermined high reliability region as a region where the transistor has high reliability in a region where an AC load line of the transistor output can exist The characteristics of the output load circuit are determined so that an AC load line in the intrinsic region, which is a core part responsible for the operation, is included ,
The transistor is a field effect transistor;
The output load circuit is connected to a drain of the transistor;
The gate-drain capacitance of the transistor is Cgd,
The drain-source capacitance of the transistor is Cds,
The gradient of the AC load line at the output of the transistor is Gd,
The gradient of the AC load line in the intrinsic region of the transistor is GL,
When the drain resistance of the transistor is Rd,
The real number Re (Z) and the imaginary number Im (Z) of the impedance of the output load circuit are:

High frequency power amplifier circuit, characterized in that it. In a design method of a high frequency power amplifier circuit comprising a transistor and an output load circuit connected to the output side of the transistor,
A transistor configured by a drain current source and a drain conductance of the transistor in a predetermined high reliability region as a region where the transistor has high reliability in a region where an AC load line of the transistor output can exist Determine the characteristics of the output load circuit to include an AC load line in the intrinsic region that is the core part responsible for operation ,
The transistor is a field effect transistor;
The output load circuit is connected to a drain of the transistor;
The gate-drain capacitance of the transistor is Cgd,
The drain-source capacitance of the transistor is Cds,
The gradient of the AC load line at the output of the transistor is Gd,
The gradient of the AC load line in the intrinsic region of the transistor is GL,
When the drain resistance of the transistor is Rd,
The real number Re (Z) and the imaginary number Im (Z) of the impedance of the output load circuit are:

A method for designing a high-frequency power amplifier circuit, characterized in that:

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