JP5091150B2 - Multiple semiconductor devices and carrier substrate manufacturing method - Google Patents

Abstract

Individual devices (100) are locally attached to a carrier substrate (10), so that they can be removed therefrom individually. This is achieved through the use of a patterned release layer, particularly a layer that is removable through decomposition into gaseous or vaporized decomposition products. The mechanical connection between the carrier substrate (10) and the individual devices (100) is provided by a bridging portion (43) of an adhesion layer (40).

Description

The present invention is a method of manufacturing a plurality of microelectronic devices each having a circuit of electrical elements attached to a carrier substrate:
-Providing a carrier substrate with a patterned release layer and device group; and-removing the release layer, thereby creating a gap between the release region of the microelectronic device group and the carrier substrate, Leaving the devices locally attached to the carrier substrate by a bridging material disposed adjacent to the void;
Relates to a method comprising:

  The present invention also provides a carrier substrate to which a plurality of microelectronic devices each having a circuit of an electric element are attached, each device being separated from the carrier substrate by a gap in the release region, and the device group is a single unit. The carrier substrate is formed in one batch and the device group is locally attached to the carrier substrate by a bridging material disposed adjacent to the air gap.

  The invention further relates to the use of this carrier substrate.

  Such a method and carrier substrate are known from US Pat. It discloses that a double transfer process can be used to transfer a plurality of microelectronic devices from a substrate on which a device group has been processed to a final substrate. This double transfer process is particularly aimed at producing active matrix arrays for display applications. Here, a microelectronic device refers in particular to an integrated circuit consisting of active and / or passive elements, which can include sensors.

  The carrier substrate in the known method is a silicon substrate. The oxide layer thereon is used as a release layer. This oxide layer is covered by a protective layer of a further silicon oxynitride layer chosen by having a lower etching rate than silicon oxide. A single crystal silicon layer is formed thereon. The resulting substrate structure is therefore of the silicon on insulator (SOI) type known in the art. Electronic devices are formed inside and on the surface of the single crystal silicon layer. These devices are semiconductor devices consisting of thin film transistors and comprise polysilicon gates, pixel electrodes, and suitable metallization.

  The bridging material is then provided in the form of oxide posts (support posts) provided in the etching openings extending to the carrier substrate. Since the etching rate of silicon oxynitride is lower than that of silicon oxide, the etching opening includes a narrow portion in the plane of the silicon oxynitride. This narrowing provides mechanical fixation of the oxide post. Thereafter, the oxide release layer is removed by etching. Epoxy is provided on the resulting structure, and the epoxy is cured in areas not located on the support. And a glass plate is attached to it. Finally, the carrier substrate is removed from the device group by cutting the oxide posts and decomposing the uncured epoxy.

The disadvantage of the known method is that the devices cannot be obtained directly from the carrier substrate, for example by some device such as a component handling machine. After removal of the uncured epoxy, the glass plate must be separated into several pieces. If a glass plate is not used, multiple devices will immediately scatter into individual devices.
US Pat. No. 5,258,325

  The present invention firstly aims to provide a method of the kind described above which results in a carrier substrate in which individual devices can be removed individually using a standard or slightly improved component handling apparatus. And

  The present invention secondly aims to provide a carrier substrate on which the individual devices are still attached.

This primary purpose is:
Providing a sub-assembly of a carrier substrate and a handling substrate, wherein there is a patterned release layer and adhesive layer between the carrier substrate and the handling substrate and having a device;
Providing a through hole group penetrating the handling substrate, at least part of which functions as a separation lane between adjacent microelectronic devices; and-via at least part of the through hole group Removing the release layer, thereby creating a gap between the free area of the microelectronic device and the carrier substrate, where each microelectronic device is individually separated from the carrier substrate by selective cutting of the adhesive layer The microelectronic device is left attached to the carrier substrate by the adhesive layer so that the cross-linked portion of the adhesive layer is adjacent to the air gap;
Is achieved by a method having

  The desired substrate according to the present invention is obtained by removing the release layer after the handling substrate is provided and the necessary through holes are formed to penetrate the handling substrate. And since the area between the handling substrate and the carrier substrate is accessible only through the through-hole, the bridging material must be provided as an adhesive layer before or during the preparation of the subassembly. Since other methods make the device very fragile and very fragile, a handling substrate is required here for individual removal of the device.

  Advantageously, the through hole is formed by etching. This has the advantage that the effective width of the through holes and especially the separation lanes can be very small. The width of the separation lane here is not determined by the (cutting) technique used for the separation, but by the resolution of a simple etching process. This reduction in the width of the separation lane directly leads to an improvement in yield and a reduction in cost, particularly when the carrier substrate is a semiconductor substrate. The separation lane in the prior art cannot be so narrow because of the need to separate the glass plates.

  The release layer preferably comprises an organic material. This type of material can be decomposed or removed selectively with respect to other materials with relative ease.

  In one advantageous embodiment, the release layer is removed by decomposition into a gaseous material. The advantage of this type of release is that it does not leave any residue. Also, this decomposition can be performed effectively at temperatures up to 400 ° C. The actual decomposition temperature depends mainly on the material selection of the release layer. A suitable material is, for example, polymethyl methacrylate (PMMA), which is provided as a void material. The stability of this material at temperatures above 300 ° C. allows various processing steps to be performed after decomposition of the release layer. Furthermore, due to the decomposition temperature below 400 ° C., the decomposition does not damage the other layers of the subassembly. Preferably, the release layer material is photosensitive so that no further photoresist is required for its patterning to the desired shape.

  The adhesive layer preferably extends on one substrate, either the handling substrate or the carrier substrate, and is not just a local support. This realizes that the adhesive layer is completely integrated in the device. Most preferably, the adhesive layer comprises an inorganic material such as an oxide, oxynitride, or the like. Such materials can be applied to any desired thickness using standard semiconductor techniques such as, for example, chemical vapor deposition.

  Deposition of an adhesive layer on a patterned release layer is highly preferred compared to deposition that planarizes an existing shape, particularly when the adhesive layer is deposited to have a relatively uniform thickness. . Such deposition results in the bridging portion of the adhesive layer having an internal plane that is not parallel to the substrate. As a result, this cross-linked portion can be cut very easily. The strength of the cross-linked portion and the angle of this plane naturally depend on the thickness of the adhesive layer and the release layer.

  The adhesive layer is preferably designed to create a cross-linked portion present in the through hole that serves as a separation lane between the individual microelectronic devices. Preferably, the bridging portion does not completely cover the separation lane and is patterned in stripes. More preferably, the adhesive layer is further patterned to create additional through holes that expose the release layer, as does the handling substrate.

  The handling substrate is preferably a layer made of a polymer material. However, the handling substrate may be an inorganic coating with radiation deterrent properties that can be sufficiently patterned by modification of the surface properties, for example as known from US Pat. No. 6,198,155. In other examples, the handling substrate may be a heat sink or other heat dissipation means. If later patterned, a glass layer attached with an adhesive may also be applied. One suitable technique is known from US Pat. No. 6,177,295.

  In one embodiment, the release layer, the device stack in which the device is defined, and the adhesive layer are subsequently provided on the carrier substrate. In this embodiment, the device is made by thin film technology. This may include sensors, thin film transistors, passive elements, filters, and the like. Preferably, the circuit comprises a transistor or other semiconductor element. Suitable semiconductor materials that can be processed at temperatures below the decomposition temperature of the release layer include not only organic semiconductors such as pentacene, but also amorphous silicon and low temperature polysilicon. One feature of this embodiment is that both the release layer and the adhesive layer preferably function as an etch stop material during the formation of through holes by etching.

  In another embodiment, the release layer and the adhesive layer are attached to the carrier substrate after being subsequently provided on the processing substrate on which the device is present, and the processing substrate is a handling substrate or to the carrier substrate. It is replaced by the handling board after installation. The processing substrate is not necessarily so, but is preferably a semiconductor substrate on the surface of which a part of the electric element group is defined. After providing the subassembly, the processing substrate is at least partially removed, usually by polishing and subsequent etching, and may be replaced with a handling substrate having another property, such as a polymer material. The device is preferably provided with passivation and scratch protection prior to being provided with a release layer. The first feature of this embodiment is the use of an adhesive in the carrier substrate in addition to the adhesive layer (ie, oxide). One feature of this embodiment is that the formation of the through-hole is a very two-step process in which the through-hole is first provided in the handling substrate, followed by patterning of the device stack and the adhesive layer thereon. It is preferably performed. In this case, the release layer and the adhesive function as an etching stop layer.

  A second object of the present invention is to provide a carrier substrate having a group of microelectronic devices each having an electric element circuit and capable of being individually removed. The purpose is that each device comprises a handling substrate and is separated from the carrier substrate by a gap in the release region, the device group is formed in a single batch and penetrates the handling substrate. Separated from each other by extending separation lanes, the device is attached to the carrier substrate by an adhesive layer, a bridging portion of the adhesive layer is placed adjacent to the gap, and the adhesive layer is an individual microelectronic This is accomplished by extending over at least one of the handling substrate and the carrier substrate so that the device can be individually detached from the carrier substrate by selective cutting of the adhesive layer.

  By using an adhesive layer that extends into the electronic device, the weakest point of the adhesive layer will be at or near the location of the contact with the carrier substrate. As a result, the adhesive layer can then be broken with very little force. As a result, the device can be mechanically removed from the carrier substrate using a component placement machine.

  Advantageously, the adhesive layer comprises a first part attached to the microelectronic device, a second part attached to the carrier substrate, and a bridging part between the first part and the second part and adjacent to the gap. And the bridging portion has an angle between 0 ° and 180 ° relative to the carrier substrate. With this arrangement, the bridging portion protrudes from the substrate, forming a reliable connection, albeit based on a very thin layer group.

  In a preferred variation of this, the electronic device is attached to the carrier substrate at a number of attachment points. Preferably, at least 3 attachment points are used, more preferably 4 attachment points are used. This results in a stable structure that can be transported without any problems. As will be appreciated, more than one electronic device can be attached to the carrier substrate at a single attachment point. That is, one strip of adhesive layer that extends to different electronic devices at its lateral ends can contact the carrier substrate at this attachment point.

  In another example, the adhesive layer has a first surface and a second surface opposite to the first surface, the first surface of the adhesive layer being attached to the carrier substrate at the bridging portion, and the first surface. The second surface is attached to a part of the encapsulated device or the handling substrate. In this embodiment, the device is attached to the carrier substrate only in a limited area. This embodiment is particularly useful for devices that further include larger or deformable elements such as interconnects and antennas.

  Preferably, the circuit of the electric element includes a protective layer and is disposed between the handling substrate and the gap. This embodiment provides protection for the microelectronic device while attached to the carrier substrate. This further has the advantage that known techniques for generating through holes from the bottom surface of the semiconductor substrate can be applied.

  In one interesting embodiment, the microelectronic device has a deformable portion having at least one conductor extending over the handling substrate, the portion having a shape substantially defined by the conductor. Have. A so-called stretchable, in which deformable conductors between islands with electrical elements are used to increase the distance between these elements and / or to remove stress due to bending etc. There is a growing interest in electronics. The desire to increase the mutual distance stems from the desire to manufacture devices cost effectively on a small area. Such a stretchable electronics structure is disclosed, for example, in US Pat. No. 6,479,890.

  The use of stretchable electronics allows for an ultra-thin, very flexible radio frequency (RF) ID transponder in which a magnetic loop antenna is integrated on the chip to eliminate electrical contact between the integrated circuit and the external antenna. Is expected for. Since the size of the magnetic loop antenna is not scaled with the circuit portion of the RFID transponder, a large portion of the surface area of the substrate remains unused, resulting in higher costs. A similar situation applies for autonomous devices that consume energy and communicate with each other and / or with base stations. Such an autonomous device requires an antenna such as a dipole antenna that is larger than an integrated circuit in order to achieve efficient transmission of RF energy. The solution proposed here is to manufacture the antenna by folding it, and then deploy the antenna after the microelectronic device is singulated.

  The use of stretchable electronics is further expected in the sensor field where it is desired to have a properly characterized sensor while extending over a large area.

  In that embodiment, the deformable portion can be deformed to increase the lateral distance between its ends. The deformable portion is, for example, a spiral conductor that can be returned to an unrolled state.

  In another embodiment, the deformable part is present between the first unit and the second unit of the circuit of electrical elements.

  In a further embodiment, the deformable portion has an antenna structure that can be deformed by folding or unfolding.

  Individual devices may be separated from the carrier substrate by cutting the adhesive layer as long as they are attached to one semiconductor device. This can be done preferably using a part handling machine.

  These and other aspects of the invention will be further elucidated with reference to the drawings. The drawings are not drawn to scale and are completely schematic. Also, in the drawings, the same reference numerals represent similar parts.

  FIG. 1 schematically shows a cross-sectional view of a carrier substrate 10 to which a plurality of microelectronic devices 100 are attached. The device group is attached by an adhesive layer 40. The first portion 41 of the adhesive layer 40 is a part of the device 100, and the second portion 42 is attached to the carrier substrate 10. An intermediate bridging portion 43 extends between the first portion 41 and the second portion 42. A gap 70 extends between the microelectronic device 100 and the carrier substrate 10. The bridging portion 43 is located adjacent to the gap 70. As can be seen in FIG. 3, this bridging portion 43 is cut when the microelectronic device is removed from the carrier substrate 10.

  For example, the microelectronic device 100 includes a handling substrate 20 so as to be individually removed by a component placement machine. In this example, the handling substrate 20 is a polyimide layer having a thickness of 10 μm, for example, and preferably has a thickness between 2 μm and 100 μm. The microelectronic device 100 further includes a device layer 50. In this example, the device layer 50 is a stacked body having thin film transistors. The semiconductor layer of the thin film transistor can be organic, amorphous silicon, polysilicon, or any other semiconductor material suitable for thin film transistors and deposited at temperatures up to about 300 ° C. Although not shown, preferably, the microelectronic device embodiment has an integrated antenna. This allows for wireless transmission between the device 100 and the reader, assuming that the device 100 has the necessary circuitry for transferring data and preferably energy. Such circuits are known per se in the field of identification (ID) transponders. Alternatively or additionally, there may be contact pads for electrical coupling between the device 100 and some component such as a printed circuit board. Such a bond pad may be provided in the lowermost portion of the device layer 50, as is apparent from the cross-sectional view. In another example, the bond pads are provided on top of the handling substrate 20 and, in addition, a longitudinal interconnection through the handling substrate 20 is formed. Although not always necessary, it is advantageous to use a photosensitive material for the handling substrate. The bond pad may be delimited by an oxide layer deposited on top of the handling substrate. Prior to the separation, an under bump metal, a metal bump, or a solder bump may be provided on the bonding pad.

  Individual microelectronic devices 100 are separated from each other by separation lanes 61. In addition, a through hole 60 is present to remove the release layer from the gap 70. In this example, the through hole also functions as a separation lane. However, particularly when the device 100 is larger, the through hole 60 may be located in the center of the single device 100.

  FIG. 2 shows a top view of the carrier substrate 10 with a plurality of devices 100. The position of the handling substrate 20 is shown as a dot area overlapping the device 100. This also overlaps the first part (not shown) of the adhesive layer. The second portion 42 of the adhesive layer is also shown. In addition, a separation lane 61 is also shown. The bridging portion 43 is indicated by a region bounded by a dashed line. FIG. 2 shows that each device 100 is attached to the carrier substrate 10 in this example at four attachment points located adjacent to the corners of the device.

  4A-4J show 10 successive steps of the method for reaching the carrier substrate 10 with the device 100 shown in FIG.

  FIG. 4A shows a carrier substrate 10 having a first surface 11 and a second surface 12 opposite to the first surface 11. A release layer 30 is present on the first surface 11 of the carrier substrate 10. The carrier substrate is made of silicon in this example, but may alternatively be made of another material such as glass. The release layer 30 comprises a polymethylmethacrylate material, such as that developed for the interconnect structure voids within an integrated circuit. Such a material is commercially available as XP-0733 from Shipley. This material can be applied by spin coating and is completely stable up to 300 ° C. after initial soft baking at approximately 150 ° C. When the temperature is higher than 350 ° C. and raised up to 400 ° C., the material decomposes without leaving any residue. Instead of this void material, a release layer that can be selectively etched with respect to both the substrate and the layer group deposited on top of the release layer may be used. An example is a metal release layer.

  FIG. 4B shows the carrier substrate 10 after the second step, in which an etching mask and device layer 50 are provided. Preferably, particularly in combination with the organic release layer 30, the etching mask comprises an inorganic material. Good results have been obtained with oxides deposited using plasma enhanced chemical vapor deposition (PECVD). However, nitrides, oxynitrides and other materials and other deposition methods may also be applied. This etching mask is also the substrate layer on which the device layer 50 is deposited. In this example, the device layer 50 is a laminate. One of the layers consists of a semiconductor material such as amorphous silicon or low temperature polysilicon. A further layer group is a conductive layer and an electrically insulating layer for defining electrodes and conductors and the separation between them. The device layer 50 includes a plurality of electrical elements such as transistors, capacitors, and resistors that are interconnected according to a desired design. It is also necessary to provide coupling means in the device. Such energy and / or data coupling means may be implemented as an antenna, such as a dipole antenna, an inductor, or a capacitive coupling plate. In another example, the coupling means may be implemented as a contact pad for electrical coupling. At this time, preferably, such a contact pad is defined adjacent to the release layer 30.

  FIG. 4C shows the carrier substrate 10 after the third step, in which the device layer 50 is patterned. As will be apparent, the patterning of the device layer 50 is performed in areas where any electrical elements are left absent. This patterning is preferably done using photoresist and illumination.

  FIG. 4D shows the carrier substrate 10 after the release layer 30 has been patterned. At this time, an adhesive region is defined on the carrier substrate 10.

  FIG. 4E shows the carrier substrate 10 after one further step, with the adhesive layer 40 applied to the top of the device layer 50. As a result of patterning both the device layer 50 and the release layer 30, a portion of the adhesive layer is attached to the carrier substrate. Thus, the adhesive layer 40 has at least three parts: a first part 41 deposited on the device layer 50; a second part 42 deposited on the carrier substrate 10; and between the first part 41 and the second part 42. Can be subdivided into cross-linked portions 43 extending into The bridging portion 43 has an angle between 0 ° and 180 ° with respect to the carrier substrate. In this example, it is clear that this is a schematic diagram, but this angle is about 90 °. Generally, this angle is 30 ° or more, more preferably 45 ° or more, and 150 ° or less, more preferably 135 ° or less, at the steepest point. This angle is preferably close to 90 °. This is because an angle close to 90 ° tends to keep the force when removing the device from the carrier substrate 10 within a certain range. An angle close to 90 ° also tends to reduce the possibility that the adhesive layer will be cut at locations other than the cross-linked portion 43.

  FIG. 4F shows the carrier substrate 10 after the patterning of the adhesive layer 40. At this time, a through hole 60 reaching the release layer 30 is defined. At the same time, this step also defines a separation lane 61.

  In the step shown in FIG. 4G, the handling substrate 20 is provided on the adhesive layer 40. In this example, the handling substrate 20 is a resin layer that enables the resulting device to be mechanically bent, and a thickness of 10 μm is used. A suitable example of the resin layer is polyimide applied by spin coating. In this example, the resin layer is not photosensitive. Therefore, a further photoresist layer 23 is applied to the top of the resin layer 20. This resist layer is applied after the resin layer is dried by soft baking at 120 ° C.

  FIG. 4H shows the result of patterning the photoresist layer 23. The pattern of the photoresist layer overlaps with the previously formed separation lane 61 and through hole 60. Although it may be useful to apply resolution correction, this pattern may also be approximately the same. Further, this pattern may be different near the edge of the carrier substrate 10.

  FIG. 4I shows the carrier substrate 10 after the patterning of the handling substrate 20. This can be done using an etchant such as TMAH.

  FIG. 4J shows the carrier substrate 10 after the removal of the photoresist layer 23. The carrier substrate 10 with the individual devices 100 attached is almost ready at this stage. In this example, the step of curing the resin layer of the handling substrate 20 is performed simultaneously with the removal of the release layer 30. This is because both processes require the same temperature. The result of this step is shown in FIG.

  5A-5F show schematic cross-sectional views of a second embodiment of the method according to the invention. This embodiment is structurally different from the first embodiment in that the handling substrate 20 is a processing substrate for the device 100. A release layer 30 is provided at the end of the process. This has the advantage that temperatures above 300 ° C. can be used, as will be apparent. In addition, a single crystal silicon substrate can be used, enabling higher performance devices and processing in conventional semiconductor manufacturing.

  As a result of this treatment, the carrier substrate simply functions as a temporary carrier. That is, the substrate transfer as in the first embodiment is not performed. However, such substrate transfer may be additionally performed such that the processing substrate is at least partially removed and replaced with another substrate. The other substrate may be a metal substrate, but is preferably an electrically insulating, mechanically flexible substrate such as the type of resin layer used in the first embodiment.

  This second embodiment is further different in that the removal of the release layer releases the first part of the circuit from the carrier substrate 10 while not releasing the second part. This is particularly suitable when the first part to be released can be mechanically deformed. This deformation can be performed by folding, stretching and folding, and preferably includes specific means for that purpose.

  FIG. 5A shows a cross-sectional view of the processing substrate / handling substrate 20 having the first surface 21 and the second surface 22. On the first surface 21, a laminate that is also referred to as the device layer 50 is defined. A thermal oxide film 55 is provided on the first surface 21 of the handling substrate 20. The first surface 21 defines an integrated circuit 52 in a manner known to those skilled in the art. At least one conductor 53 is provided on the first surface 21. Conductor 53 is shown here on top of integrated circuit 52, but is preferably part of a conductive layer in the interconnect structure of integrated circuit 52. In this example, the conductor 53 is a spiral conductor track designed to be stretchable. As is apparent, the conductor 53 may constitute an antenna such as a dipole antenna or a winding of an inductor. In other examples, there may be more than one electrical element integrated circuit 52 coupled through this conductor track. Such a structure may be advantageous with respect to the mechanical properties of the flexible circuit. Other applications are possible in the field of sensor arrays. The sensors may then have a greater spacing from one another after processing. A circuit including both the conductor 53 and the integrated circuit 52 is covered with a protective layer 54. This protective layer 54 is preferably a passivation layer made of, for example, silicon nitride. This is particularly effective when the conductor 53 is part of an interconnect structure. In other examples, the conductor 53 may be provided on top of the passivation layer of the integrated circuit. At that time, the protective layer need not have a passivation function and can be selected from a wider range of materials.

  FIG. 5B shows the handling substrate 20 after the second step in this method. A release layer 30 is applied and patterned. Subsequently, the adhesive layer 40 is applied. Here, the same material as in the first embodiment is selected for the release layer 30 and the adhesive layer 40. This, however, does not exclude other materials. As a result of the patterning of the release layer 30, the device 100 can be divided into a release region 51 where the adhesive layer 40 is not attached to the device layer 50 and an attachment region 56. A portion of the conductor group 53 is defined in the attachment region 56, and another portion of the conductor group 53 and the integrated circuit 52 are defined in the release region 51.

  FIG. 5C shows an assembly of the handling substrate 20 and the carrier substrate 10. Here, the carrier substrate 10 is attached to the adhesive layer 40 using the adhesive 13. The carrier substrate 10 is preferably a glass layer, but may be any other object that is sufficiently stable and rigid to function as a substrate during etching. The adhesive is suitably selected to be etch resistant to etchants that can etch the adhesive layer and not the release layer. One embodiment thereof, as will be apparent, is that the adhesive is selected from the same type of material as the release layer, for example, preferably when the release layer comprises PMMA, preferably an organic layer. Ester type materials, more preferably acrylates, and most preferably PMMA. However, in another example, it may not be decomposable.

  FIG. 5D shows the assembly turned upside down so that the carrier substrate 10 acts as a carrier. The handling substrate 20 is patterned into islands separated by through holes 60 appropriately designed as lanes. Here, the conductor 53 is formed by disposing the handling substrate 20 mechanically attached to the handling substrate 20 of the integrated circuit 52 only in a limited area, for example, where the conductor 53 substantially contacts the integrated circuit 52. I have. Effectively, separation lanes are also provided, but they are not shown here. Providing a trench in a silicon substrate is well known in the art and is preferably performed by dry etching through a silicon nitride mask. At this time, the thermal oxide film 55 functions as an etching stop layer. Although not shown, the handling substrate 20 is preferably thinned prior to defining the through hole 60.

  FIG. 5E shows the carrier substrate 10 with the device 100 after continued etching. This etching is performed by reactive ion etching (RIE), but does not exclude other techniques such as laser cutting. In a preferred example, adhesive 13, release layer 30 and adhesive layer 40 are selected such that release layer 30 and adhesive 13 function as an etch stop layer while the adhesive layer is etched away. Thereby, the release layer is exposed.

  FIG. 5F shows the carrier substrate 10 with the device 100 after removal of the release layer 30. At this stage, the release region 51 of the device 100 is separated from the carrier substrate 10 by the air gap 70. A cross-linked portion 43 of the adhesive layer is adjacent to the gap. This is cut to remove the devices 100 from the carrier substrate 10 individually. Here, the cross-linked portion is understood as a combined body of the adhesive layer 40 and the adhesive 13. Any disconnection can go through either or both. Since the device is actually designed to be stretchable and the attachment region only includes a portion of the conductor 53, it is not a problem that the adhesion to the carrier substrate 10 in the attachment region is stronger. Furthermore, since the adhesive 13 can be made relatively thick, cutting may be accommodated using a tool such as a saw.

  6A and 6C show sectional views of modifications of the second embodiment. In this modification, as compared with FIG. 5, the force for individually removing the device 100 from the carrier substrate 10 is reduced. This variation is shown with reference to a device with a stretchable conductor 53, but is not limited thereto and can be applied to a device similar to that shown in FIG. . The release layer 30 is patterned so that it resides under a portion of the attachment region 56 of the device 100. The release layer 30 is exposed so as to extend to the edge of the adhesion region 56 only in a part of the region. Specifically, FIG. 6B shows that the rotation of the release layer 30 relative to the attachment area 56 mask (eg, a mask for patterning the handling substrate 20) causes the release layer 30 to be exposed at the edge of the attachment area at an exposure point 39. Indicates that As will be appreciated, there are many ways to define the exposed point 39 in addition to the rotation of one feature within the mask. One example is translation and another example is the use of a cross pattern for either the release layer 30 pattern or the deposition region 56 pattern. One advantage of this masking operation is that no additional layer patterning is required.

  FIG. 6C shows the result that the bridging portion 43 is confined to a strictly confined area and the further void 71.

  FIGS. 7-10 relate to another embodiment according to the invention, but it can be seen from FIG. 8, for example, that in this embodiment it is not necessary to remove the carrier substrate after processing. The carrier substrate is diced into individual units prior to the device layer deformation step. However, as will be appreciated, in one preferred embodiment, the carrier substrate is removed to achieve device flexibility. As will be further understood, the technique shown in FIGS. 6A-6C is also very effective in this embodiment.

  7A-7C illustrate the three steps in the method resulting in the device shown in FIG. As before, all cross-sectional views are schematic in nature. This method is almost identical to the method described with reference to FIGS. 5A-5F. Unless otherwise explained, the details described above with reference to FIGS. 5A-5F also apply to the method according to this embodiment.

  FIG. 7A shows a step corresponding to the step shown in FIG. 5B. The illustrated part includes two separate devices in this example. The handling substrate 20 includes a thermal oxide layer 55 and an integrated circuit 52. As will be described with reference to FIGS. 9 and 10, a conductor 53 designed to be deformable by folding is provided. The conductor 53 suitably extends to the integrated circuit 52, specifically the portion known as the 'interconnect structure' or 'back end'. The structure consisting of conductor 53 and integrated circuit 52 is covered with a passivation layer 54 resulting in a stack 50 of device layers. On top of this, a release layer 30 is provided and appropriately patterned according to a desired pattern. The release layer 30 is covered with the adhesive layer 40. Due to the applied patterning, the release area 56 and the deposition area 51 are distinguished. In this embodiment, the adhesion area 51 corresponds to the area of the integrated circuit 52 and the release area corresponds to the area of the conductor 53.

  FIG. 7B shows a further stage in which the carrier substrate 10 is attached to the first surface 21 of the handling substrate 20 by means of an adhesive 13. This adhesive constitutes a bond between the carrier substrate 10 and the adhesive layer 40. Thereafter, the handling substrate 20 is thinned from its second surface to a suitable thickness. Although not shown, the handling substrate 20 may be replaced partially or substantially entirely (without damaging the integrated circuit 52) with a flexible layer such as polyimide, polyacrylate, epoxy, etc. .

  FIG. 7C shows a further stage, in which the handling substrate 20 is patterned. This stage corresponds to the stage shown in FIG. 5E. Specifically, in a region where neither the integrated circuit 52 nor the conductor 53 exists, the handling substrate 20 and the device layer 50 thereon are removed. This removal creates a separation lane 61 and other through holes 60. The through hole 60 has a channel or a similar shape.

  FIG. 8 shows the device 100 obtained after the dicing process. The carrier substrate 10 is singulated. Thereafter, the adhesive layer is removed, and the conductor is released from the carrier substrate 10. As will be appreciated, this dicing process may be postponed until after removal of the release layer 30. Individual devices 100 are not mechanically robust at this stage, but the separation lanes do not completely cut the handling substrate 20 or the device layer 50. As will be further appreciated, the device 100 may be removed from the carrier substrate 10 without separating the carrier substrate 10. This is however less preferred, as will be explained with reference to FIG.

  FIG. 9 shows the device 100 after removal of the release layer 30 and deformation of the conductor. In this embodiment, the conductor is deformed by unfolding the folded one. The resulting structure is, for example, a dipole antenna. Other structures can also be formed by the cutting, folding and stretching techniques described in the unpublished application PH890, for example. This document is incorporated herein by reference. Most preferably, a conductor is provided so that deformation is achieved directly when the release layer 30 is removed.

  FIG. 10 shows the device 100 of FIG. 9 in a top view. The effect of deformation is obvious. It will also be appreciated that the deformed structure is preferably attached to a further carrier so that it is protected from damage.

  In summary, the individual devices (100) are locally attached to the carrier substrate (10) so that they can be individually removed from the carrier substrate (10). This is accomplished by the use of a patterned release layer, specifically a layer that can be removed by decomposition into gaseous or vaporized decomposition products. Mechanical connection between the carrier substrate (10) and the individual devices (100) is provided by the bridging portion (43) of the adhesive layer (40).

It is sectional drawing which shows the carrier substrate provided with the device group. It is a top view which shows the carrier substrate provided with the device group. It is sectional drawing which shows the carrier substrate after the device group was removed. It is sectional drawing which shows one of the 10 continuous processes in manufacture of the carrier board | substrate shown by FIG. It is sectional drawing which shows one of the 10 continuous processes in manufacture of the carrier board | substrate shown by FIG. It is sectional drawing which shows one of the 10 continuous processes in manufacture of the carrier board | substrate shown by FIG. It is sectional drawing which shows one of the 10 continuous processes in manufacture of the carrier board | substrate shown by FIG. It is sectional drawing which shows one of the 10 continuous processes in manufacture of the carrier board | substrate shown by FIG. It is sectional drawing which shows one of the 10 continuous processes in manufacture of the carrier board | substrate shown by FIG. It is sectional drawing which shows one of the 10 continuous processes in manufacture of the carrier board | substrate shown by FIG. It is sectional drawing which shows one of the 10 continuous processes in manufacture of the carrier board | substrate shown by FIG. It is sectional drawing which shows one of the 10 continuous processes in manufacture of the carrier board | substrate shown by FIG. It is sectional drawing which shows one of the 10 continuous processes in manufacture of the carrier board | substrate shown by FIG. It is sectional drawing which shows one of 5 continuous processes in manufacture of the carrier substrate which concerns on 2nd Embodiment. It is sectional drawing which shows one of 5 continuous processes in manufacture of the carrier substrate which concerns on 2nd Embodiment. It is sectional drawing which shows one of 5 continuous processes in manufacture of the carrier substrate which concerns on 2nd Embodiment. It is sectional drawing which shows one of 5 continuous processes in manufacture of the carrier substrate which concerns on 2nd Embodiment. It is sectional drawing which shows one of 5 continuous processes in manufacture of the carrier substrate which concerns on 2nd Embodiment. It is sectional drawing which shows the carrier substrate which concerns on 2nd Embodiment provided with the device group obtained by the method shown by FIG. 5A-5E. It is sectional drawing which shows the modification of the carrier substrate which concerns on 2nd Embodiment. It is a top view which shows a part of FIG. 6A and 6C. It is sectional drawing which shows the modification of the carrier substrate which concerns on 2nd Embodiment. FIG. 6 is a cross-sectional view illustrating one of three consecutive steps in a method of manufacturing a further embodiment. FIG. 6 is a cross-sectional view illustrating one of three consecutive steps in a method of manufacturing a further embodiment. FIG. 6 is a cross-sectional view illustrating one of three consecutive steps in a method of manufacturing a further embodiment. FIG. 6 is a cross-sectional view of a resulting carrier substrate with devices in one configuration. FIG. 6 is a cross-sectional view of a resulting carrier substrate with devices in one configuration. FIG. 10 is a top view corresponding to FIG. 9.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Carrier substrate 11 First surface of carrier substrate 12 Second surface of carrier substrate 13 Adhesive 20 Handling substrate 21 First surface of handling substrate 22 Second surface of handling substrate 23 Photoresist layer 30 Peeling layer 33 Etching Mask (oxide layer)
40 Adhesive Layer 41 First Part of Adhesive Layer 42 Second Part of Adhesive Layer 43 Cross-Linked Part of Adhesive Layer 50 Device Layer 51 Release Area 52 Integrated Circuit 53 Conductor 54 Protective Layer 55 Thermal Oxide Film 56 Adhesive Area 60 Through Hole 61 Separation Lane 70 Air gap 100 Microelectronic device

Claims (11)

A method of manufacturing a carrier substrate having a plurality of microelectronic devices each having a circuit of electrical elements attached thereto:
Providing a sub-assembly of a carrier substrate and a handling substrate, wherein there is a patterned release layer and adhesive layer between the carrier substrate and the handling substrate and having the device;
A step of providing a through hole group penetrating the handling substrate, at least part of which functions as a separation lane between adjacent microelectronic devices; and at least part of the through hole group Removing the release layer through, thereby creating a void between the released region of the microelectronic device and the carrier substrate ;
Have
The microelectronic device is left attached to the carrier substrate by the adhesive layer so that individual microelectronic devices can be individually detached from the carrier substrate by selective cutting of the adhesive layer, and the adhesive layer Is disposed so that the cross-linked portion of the
A method characterized by that .   The method of claim 1, wherein the release layer is removed by decomposition into a gaseous material.   The release layer, the device stack in which the device is defined, and the adhesive layer are continuously provided on the carrier substrate, and the adhesive layer is provided on the carrier substrate even after the release layer is removed. 2. The patterned pattern of creating an exposed area in the release layer corresponding to the first set of separation lanes and continuous in the second set of separation lanes so as to adhere. Method.   The release layer and the adhesive layer are continuously provided on the processing substrate on which the device exists, and then attached to the carrier substrate, and the processing substrate is the handling substrate or to the carrier substrate. The method of claim 1, wherein the method is replaced by the handling substrate after attachment.   The method according to claim 1, 3 or 4, wherein the handling substrate comprises a flexible material. A carrier substrate having a plurality of microelectronic devices attached thereto, each microelectronic device having a circuit of electrical elements, including a handling substrate, and separated from the carrier substrate by a gap in a release region. The devices are formed in a single batch and separated from each other by separation lanes extending through the handling substrate ;
The device is attached to the carrier substrate by an adhesive layer, and a bridging portion of the adhesive layer is disposed adjacent to the gap, and the adhesive layer further includes an individual microelectronic device of the adhesive layer. Extending on at least one of the handling substrate and the carrier substrate so that it can be individually removed from the carrier substrate by selective cutting;
A carrier substrate characterized by that .   The adhesive layer includes a first portion attached to the microelectronic device, a second portion attached to the carrier substrate, and a bridge between the first portion and the second portion and adjacent to the gap. 7. A carrier substrate according to claim 6, comprising a portion, wherein the bridging portion has an angle between 0 ° and 180 ° relative to the carrier substrate.   The carrier substrate according to claim 7, wherein each microelectronic device is attached to the carrier substrate by a plurality of bridging portions of the adhesive layer.   The adhesive layer has a first surface and a second surface opposite to the first surface, and in the bridging portion, the first surface is attached to the carrier substrate, and the second surface is The carrier substrate according to claim 6, attached to a part of an encapsulated device or to the handling substrate.   The carrier substrate according to claim 6, wherein the circuit of the electric element includes a protective layer and is disposed between the handling substrate and the gap.   The microelectronic device has a deformable portion having at least one electrical conductor extending on the handling substrate, the portion having a shape substantially defined by the electrical conductor. Or the carrier substrate according to 10.

Images