JP5090268B2 - Data communication system and data communication method - Google Patents

Description

The present invention
The present invention relates to a data communication system and a data communication method for performing data communication between a parent device, a relay device, and a plurality of slave devices belonging to the relay device, and in particular, power line communication (PLC: Power) that performs information communication via a power line. The present invention relates to a data communication system and a data communication method optimum for use in a line communication system.

  Of course, game machines (halls) such as pachinko parlors are provided with pachinko machines for each player, and schools often have personal computers (computers) for each child, student or student and staff. . Furthermore, some recent hospitals have not only a personal computer for each doctor or nurse but also an information terminal for each bed in the ward.

  Gaming machines, personal computers, information terminals, etc. (hereinafter collectively referred to as “terminals”) and servers, management devices, etc. are usually connected via a dedicated communication cable. Laying it takes both money and time. Therefore, recently, a PLC system that is installed in a facility from the beginning and performs information communication via a power line that supplies power to a terminal has been proposed as follows.

  That is, conventionally, there are multiple access and multiple transmission methods for performing point-to-multipoint digital transmission of data via a power line network. In this method, a plurality of user devices and one head-end device that perform bidirectional communication on the power line network are provided by the upstream channel and the downstream channel. In the upstream channel, data is transmitted from the plurality of user devices to the headend device, and in the downstream channel, data is transmitted from the headend device to the plurality of user devices.

  Each user device and each head end device includes a medium access controller (MAC) for maximizing the amount of information that can be transmitted by the plurality of user devices and minimizing the delay time in the plurality of user devices. The power line network is divided into an upstream channel and a downstream channel by at least one of frequency division multiplexing and time division multiplexing.

  Also, in this method, a plurality of user apparatuses in the upstream channel are used by using at least one access method of OFDMA (Orthogonal Frequency Division Multiple Access), TDMA (Time Division Multiple Access) and CDMA (Code Division Multiple Access). Can be accessed simultaneously.

  In addition, this method increases the transmission capacity of each carrier in the OFDM system by increasing the number of bits per carrier or improving the S / N, and maximizes the transmission capacity in both the upstream channel and the downstream channel. Supports criteria for dynamically allocating each carrier to one or more user equipments having information to transmit at that time.

  This method also supports adjusting quality of service (QoS) depending on the type of information and the user equipment requesting transmission. The quality of service can be adapted according to the frequency response at different moments and the different distances between multiple user devices and headend devices.

  Furthermore, in this method, the available bandwidth between individual communication requests is always calculated and monitored over the entire bandwidth of the system by the S / N observed by multiple user devices and headend devices. Supports dynamic allocation of width by the headend device. This ensures that every carrier in the OFDM system has a transmission requirement for each user equipment at each moment, quality of service (QoS) parameters established for that user equipment, and a criterion that maximizes the total capacity of the system. And a criterion that minimizes the transmission delay time.

  The transmission resources to be distributed include a plurality of carriers related to one symbol when OFDMA is used, a time interval between symbols when TDMA is used, and a plurality of carriers when CDMA is used. In the code, the redistribution is optimized by constantly monitoring the power line quality parameters that are redistributed among a plurality of user apparatuses and constantly change (see, for example, Patent Document 1).

JP-T-2004-531944

  By the way, the number of terminals naturally increases as the above-mentioned facilities such as halls, schools, and hospitals become larger. In the hall, for example, a maximum of 2400 gaming machines may be installed. In the hall, a group of multiple gaming machines are called “islands” and the entire system is built by providing multiple “islands”. In large halls, a maximum of 63 “islands” are created. It is assumed that it is provided. Therefore, in order to construct a system in which a maximum of 2400 terminals are connected, 63 relays are installed at each of the 63 “island” entrances, and a maximum of 64 slaves are connected to each relay. Each must be installed.

For this reason, when 63 repeaters transmit signals simultaneously, it is necessary to multiplex-transmit the signals in 63 divisions in order to avoid signal collision. If only frequency division is adopted as a signal division method from the viewpoint of time efficiency and code efficiency, it is necessary to use 63 divisions. Some commercially available indoor high-speed PLC modems are advertised as being capable of simultaneously using a maximum of 64 units and expanding up to a maximum of 1024 units by using the repeater function. For example, see http: www.hitachijoho.com/solution/network/plc.html.
However, since the PLC system cannot guarantee transmission at a specific frequency, it is necessary to limit the number of divisions to some extent in order to establish stable synchronization. From the past experience of the inventors, it is considered that the actual number of divisions should be suppressed to 16 to 32 divisions or less at the maximum.

  On the other hand, when code division is adopted as a signal division method, the code length becomes long and overhead (in order to secure the minimum necessary identification gain for identifying each signal, particularly, a synchronization signal, (Time not directly related to signal processing) increases, and MAC efficiency (utilization efficiency with respect to the physical layer) decreases. This is because when a single master unit, a plurality of repeaters, and a plurality of slave units for each repeater are configured, each repeater transmits a synchronization signal (first synchronization signal) transmitted from the master unit. Although it is received, the adjacent relay station outputs a synchronization signal (second synchronization signal) different from the first synchronization signal to each slave unit belonging to the relay station, so it is necessary to be able to identify the first synchronization signal There is. On the other hand, since the slave unit may receive a first synchronization signal transmitted from the master unit or a plurality of second synchronization signals transmitted from a plurality of repeaters, it identifies the second synchronization signal addressed to itself. If this is not possible, there is a risk of synchronization with the second synchronization signal transmitted from the repeater to which the own device does not belong.

  Further, the above-described multiple access and multiple transmission methods have a problem in that a large reception dynamic range cannot be secured because the frequency and the time axis are divided and multiplexed. The reason will be described below. When data communication is performed by frequency division multiplexing, for example, considering a slave unit as a center, the level of a signal transmitted from a nearby slave unit is high, while the level of a signal transmitted from a remote relay unit is small. These signals are multiplexed by the power line and then received by the slave unit. In the A / D converter on the receiving side of the slave unit, for example, when the resolution is 12 bits, the S / N is limited to about 74 dB at the maximum. Since it is necessary to capture the received signal without saturating, the gain of the amplifier in front of the A / D converter can be kept low. As a result, small received signals are increasingly buried in noise.

  The present invention has been made in view of the above-described circumstances, and is intended to solve the above-described problems as an example, and a data communication system and data communication that can solve these problems It aims to provide a method.

In order to solve the above-described problem, a data communication system according to the first aspect of the present invention is a data communication for performing data communication between a master unit, a relay unit, and a plurality of slave units belonging to the relay unit. A first synchronization signal for synchronization between the parent device and the relay device, and multiplexing for synchronization between the relay device and each slave device belonging to the relay device. Synchronization signal generating means for generating a second synchronized signal, and demultiplexing processing means for separating the second synchronization signal, wherein the synchronization signal generating means corresponds to the number of the repeaters. The second synchronization signal is code-division-multiplexed with a plurality of different types of M-sequence codes, and is generated by frequency-division multiplexing for each of the M-sequence codes. The same coefficient as the M sequence code to be selected from among the M sequence codes Correlation detection of the second synchronization signal is performed using a correlation filter as a filter coefficient, and the second synchronization signal is detected by extracting and determining the maximum correlation value of the correlation filter in a predetermined period. ,
The data other than the second synchronization signal is transmitted without frequency division multiplexing of different user data.
The invention according to claim 2 relates to the data communication system according to claim 1, wherein the number of stages of the M-sequence code is p (p is a positive integer), and the sampling period of the correlation filter is T. In some cases, the predetermined period of time determined by extracting the maximum correlation value of the correlation filter is (3 × p × T).
A data communication method according to a third aspect of the present invention is a data communication method for performing data communication between a parent device, a relay device, and a plurality of slave devices belonging to the relay device, A first synchronization signal is generated for synchronization between the parent device and the relay device, and the relay device for synchronization between the relay device and each child device belonging to the relay device. When the number of second synchronization signals is code-division-multiplexed with a plurality of different types of M-sequence codes and generated by frequency-division multiplexing for each M-sequence code, the second synchronization signals are separated. Among the plurality of types of M-sequence codes on the transmission side, correlation detection of the second synchronization signal is performed using a correlation filter using the same coefficient as the corresponding M-sequence code as a filter coefficient, and the correlation filter of the correlation filter in a predetermined period is detected. To extract and determine the maximum correlation value Detecting the second synchronization signal, the data other than the second synchronizing signal, characterized by transmission without frequency division multiplexing different user data.
The invention according to claim 4 relates to the data communication method according to claim 3, wherein the number of stages of the M-sequence code is p (p is a positive integer), and the sampling period of the correlation filter is T. In some cases, the predetermined period of time determined by extracting the maximum correlation value of the correlation filter is (3 × p × T).

According to the present invention, the number of slave units constituting a data communication system including a master unit, a plurality of relay units, and a plurality of slave units belonging to each of the relay units is, for example, as many as about 2400 units. Even when a plurality of repeaters simultaneously transmit signals, data communication can be performed without collision of signals and with a minimum necessary identification gain for identifying synchronization signals.
Further, according to the present invention, since data other than the second synchronization signal is transmitted without frequency division multiplexing of different user data, a large reception dynamic range can be secured.
Further, according to the present invention, when separating the second synchronization signal, a correlation filter using a filter coefficient as the same coefficient as the corresponding M sequence code among the plurality of types of M sequence codes on the transmission side is provided. Since the second synchronization signal is detected by detecting the correlation of the second synchronization signal and extracting and determining the maximum value of the correlation value of the correlation filter in a predetermined period, high stability and The identification gain can be ensured.

The best mode for carrying out the present invention will be described below with reference to the drawings.
FIG. 1 is a block diagram showing a schematic configuration of a PLC system to which a data communication system according to an embodiment of the present invention is applied. The PLC system according to the present embodiment is applied to a hall in which 2400 gaming machines (terminals) 1 are installed at the maximum. Each terminal 1 is connected to a handset 2 having a PLC modem (not shown). Here, the terminal 1 is, for example, a pachinko gaming machine (CR machine) or a swivel type gaming machine (pachislot) that supports a prepaid card, and the slave unit 2 is arranged beside the pachinko gaming machine, for example, Ball rental card reader unit (CR unit) that is connected to the machine, placed above the pachinko gaming machine and the revolving game machine, connected to the pachinko gaming machine and the revolving game machine, etc. It is a data display that displays the above data.
Each terminal 1 is composed of a maximum of 64 units to form an island 3, and each island 3 is provided with one relay 4 having a PLC modem (not shown). Since 63 islands 3 are provided at the maximum, 63 relay machines 4 are required at the maximum.

  Each repeater 4 is connected to, for example, a 32-branch circuit 6 and a branch adapter (branch ADP) 7 via a power cable 5 for supplying AC 100V power. The 32-branch circuit 6 branches the voltage of AC100V single-phase 2-wire or AC100V single-phase 3-wire supplied from a floor entrance distribution board 31 (to be described later) up to 32 and relays the power via the power cables 5 and 8, respectively. Supply to machine 4, branch ADP7 and transformer 9. The branch ADP 7 branches a signal supplied from the repeater 4 via the power cable 5 and supplies the signal to each slave unit 2 via the communication line 10 and also supplied from each slave unit 2 via the communication line 10. Are collectively supplied to the repeater 4 via the power cable 5. The transformer 9 converts the voltage of AC100V into AC24V and supplies it to each terminal 1 via the power cable 11.

  On the other hand, for example, on the roof of the building where the hall is located, power receiving equipment (not shown) is provided. The power receiving facility is provided with a distribution board 21 in the power receiving facility. The power distribution facility internal distribution board 21 includes a transformer 22 and, for example, a six-branch circuit 23. The transformer 22 converts an AC 6.6 kV voltage supplied from the outside into an AC 100 V voltage and supplies the converted voltage to the six branch circuit 23 via the power cable 24. The 6-branch circuit 23 branches the voltage of AC 100V supplied from the transformer 22 into 6 branches at the maximum and supplies it to the floor entrance distribution board 31 via the power cable 25.

The floor entrance distribution board 31 has one, for example, 32 branch circuit 32, a plurality of, for example, 32 branch circuits 33, base units 34 ₁ and 34 _2, and a branch adapter (branch ADP) 35. ing. One 32-branch circuit 32 and a plurality of 32-branch circuits 33 are supplied with AC 100 V power from the above-described six-branch circuit 23 via independent power cables 25. 32 branching circuit 32 supplies power of AC100V the parent device 34 ₁ via the power cable 26. The power cable 26 is connected to the power cable 42. The power cable 42 is connected to a wall outlet 43 of the monitoring room 41 in the hall.

Base unit 34 ₁ has a PLC modem 61 (see FIG. 6), via a signal line 37 _1, and signals base unit 34 ₂ is supplied through the power cable 42 and 26 from the holes in the monitoring room 41 Various signal processing is performed based on the supplied signal. On the other hand, base unit 34 ₂ also has a PLC modem 61 (not shown), is supplied via the communication line 37 ₂ from the signal and branch ADP35 supplied via the signal line 37 ₁ from the main unit 34 ₁ Various signal processing is performed based on the signal. Furthermore, base unit 34 ₂ is supplied to the branch ADP35 the generated signal through the communication line 37 _2. Branch ADP35, together via a power cable 38 branches a signal supplied via the communication line 37 ₂ from the base unit 34 ₂ is supplied to each of 32 branch circuit 33, the power cable 38 from the 32 branch circuits 33 through supplies the base unit 34 ₂ via the communication line 37 ₂ are collectively signals supplied.

  In the monitoring room 41 in the hall, a server 44, a LAN 45 in the hall, and a slave unit 46 are roughly installed. The slave unit 46 has a PLC modem (not shown), is connected to the wall outlet 43 via a power cable 47 and a plug 48 and is connected to the LAN 45 in the hall via a communication line 49. Yes. The server 44 is connected to the in-hall LAN 45 via the communication line 50. The intra-hall LAN 45 is connected via a communication line 51, a WAN 52, and a communication line 53 to a center server 54 installed in the remote monitoring center.

  In the configuration described above, when up to 63 repeaters 4 transmit and receive signals at the same time, it is necessary to multiplex-transmit signals in 63 divisions in order to avoid signal collision. As described above, only one of the frequency division and the code division is not suitable for the construction of the PLC system as a signal division method. Therefore, in this embodiment, the frequency division is set to 16 divisions and the code division is set to 4 divisions, thereby satisfying the condition of a total of 63 divisions.

  First, since the frequency division is 16 divisions and is set lower than the maximum of 32 divisions, which is the limit of the number of frequency divisions described above, the margin is large and high stability can be obtained. Next, since the number of code divisions is as small as four, leakage radio waves can be reduced to 6 dB or less. Usually, adding four codes means that the four repeaters 4 transmit signals simultaneously, and the leaked radio wave also increases by 6 dB. However, while using a known peak leak suppression modulation technique and the like together, By adopting a code sequence in an orthogonal relationship, it is possible to easily reduce leaked radio waves within a desired tolerance. The allowable values for leaked radio waves have been standardized, edited by the Institute of Electrical Engineers of Japan, High Speed Power Line Communication System and EMC Research Special Committee, “High Speed Power Line Communication System (PLC) and EMC”, First Edition, First Print, Stock Company Ohm Co., p. November 20, 2007 (hereinafter referred to as “technical literature”). 11-p. It is detailed in 15.

  Here, the known peak leakage suppression modulation technique is that when transmitting one signal, the energy is dispersed on the time axis and transmitted, so that the peak when multiplexed is dispersed. The peak leakage is suppressed. As for the known peak leakage suppression modulation technique, for example, p. 97 and Japanese Patent Application Laid-Open No. 2007-325071.

  Next, as a condition for selecting a code (multiplex code), for example, (1) it can be orthogonal, (2) an identification gain for distinguishing from other signals can be secured, (3) code division multiplexing can be performed, (4 (2) A sufficient frequency tolerance range can be secured, and (5) a number of different codes corresponding to the number of code divisions can be secured.

  Among these, even if the arrangement of “0” and “1” is different at first sight under the condition of (5) described above, if they are completely overlapped by bit shift, only the phases are different and the same code is used. It can be considered that there is. Such spreading codes having only different phases can be used in synchronous code division multiple access (S-CDMA) in which a plurality of pieces of information are transmitted in synchronization at the same timing. However, as in the present embodiment, it is difficult to use in asynchronous code division multiple access (A-CDMA) that transmits a plurality of information without synchronizing at the same timing. That is, the codes are all different, and there is a requirement that there is no correlation (similarity) between the codes.

  Therefore, an M sequence (maximum length sequence) code, which is a kind of pseudo noise (PN) code, is used as a condition that satisfies the above-described five conditions. In this regard, the Gold series code is not appropriate because it does not satisfy the condition (2) described above when the code length is short, and does not satisfy the condition (4) described above when the code length is long.

  Based on the above conditions (1) to (4), the present inventors have a short one stage (1PN), two stages (1PN), three stages (1PN), four stages (1PN),. In order from the code length, as a result of investigating M-sequence codes that can ensure the number of different types of codes (4 in this case) as the condition of (5), 13 stages (13PN) is the shortest code length. It has been found that four different M-sequence codes can be secured. Therefore, in this embodiment, the 13-stage M-sequence code (13PN) shown in FIG. 3 is a frequency-multiplexed synchronization signal, and each slave unit belonging to each repeater is synchronized with the repeater. This is adopted as a basic pattern of a beacon 2 signal (synchronization signal) BC2 for taking Details of FIG. 3 will be described later. Further, data other than the beacon 2 signal (synchronization signal) BC2 is transmitted by time division multiplexing without frequency division multiplexing including the beacon 1 signal (synchronization signal) BC1.

Next, in this embodiment, the wireless handset 2 and 46, PLC modems that make up the repeater 4 and base unit 34 ₁ and 34 _2, the timing constitutes a demultiplexing unit 73 to be described later synchronization unit (TIM extraction & PLL ) The beacon signal BC2 detection circuit 101 (see FIG. 7) provided in 82 (see FIG. 6) uses a double PN filter configuration (double orthogonal filter means) of the PN filters (PNF) 102 and 109. Yes. In addition, the signal sequence reproduction circuit 107 (see FIG. 7) reproduces a signal sequence relative phase signal. By the above, to adjust the synchronization beacon signal for taking (synchronization signal) BC1 or, phase and amplitude of the final carrier without individual channel interference between the base unit 34 ₂ and the relay device 4 Therefore, a stable high discrimination gain can be realized using the beacon signal BC2 even in an environment where any one of the training signals TR is present.

Further, in this embodiment, the wireless handset 2 and 46 has a PLC modem, repeater 4 and base unit 34 _2, the timing synchronization unit constituting the demultiplexing processing section 73 to be described later (TIM extraction & PLL) 82 (FIG. 6 The maximum extraction circuit 111 for 39 cycles is provided in the final stage of the beacon signal BC2 detection circuit 101 (see FIG. 7). Thereby, high stability and ensuring of identification gain can be realized.

Hereinafter, this embodiment will be described in more detail.
FIG. 2 is a diagram illustrating an example of a configuration of a master frame transmitted and received by the PLC system according to the present embodiment. As shown in FIG. 2, the master frame is composed of a synchronization signal area used for transmission / reception of beacon signals BC1 and BC2 as first and second synchronization signals, a data area used for transmission / reception of data, and the like. Yes. As can be seen from FIG. 2, the beacon 2 signal BC2 is multiplexed, and four different beacon signals BC2A, beacon signal BC2B, beacon signal BC2C, and beacon signal BC2D are transmitted and received as four code divisions. 16 types of beacon signals BC2A # 01 to BC2A # 16, BC2B # 01 to BC2B # 16, BC2C # 01 to BC2C # 16 and BC2D # 01 for each beacon signal BC2A, BC2B, BC2C and BC2D ~ BC2D # 16 is transmitted and received.

  FIG. 3 shows a non-inverted pattern and an inverted pattern for four different beacon signals BC2A, BC2B, BC2C, and BC2D corresponding to the number of code divisions of four. The inversion pattern is obtained by rotating the phase of the non-inversion pattern by 180 degrees and inverting the signs (positive sign “+” and negative sign “−”). The reason why the non-inversion pattern and the inversion pattern are provided is to maintain an orthogonal relationship between the even channel and the odd channel and to obtain a high discrimination gain.

  FIG. 4 is a diagram illustrating an example of the autocorrelation characteristic of the beacon signal BC2A among the four different beacon signals BC2 described above. The beacon signal BC2 shows the same autocorrelation characteristic for both the non-inverted pattern and the inverted pattern. The reason why the beacon signals BC2A to BC2D are configured in this way is to obtain as much correlation as possible, to suppress the peak of the time waveform when multiplexed, and to avoid gain correlation with noise.

  FIG. 5 is a diagram illustrating an example of a transmission pattern of the beacon signal BC2A. 5 divides the code code of the beacon signal BC2A into two stages, upper and lower, and the upper transmission pattern shown in FIG. 3 above the code code (13PN orthogonal sequence) which is the lower transmission pattern shown in FIG. The code code (13PN orthogonal sequence) is double-multiplexed to generate a transmission code for 13 cycles, which is the final transmission pattern.

  In FIG. 5, the code pattern has two stages of even number and odd number, which indicate the even channel and the odd channel on the frequency axis, respectively. In the present embodiment, the orthogonality is ensured by shifting the codes of the even channel and the odd channel on the time axis, the peak value is reduced on the transmission side, and the inter-adjacent interference on the reception side is minimized. , Ensure identification gain. In FIG. 5, either one of the non-inverted pattern and the inverted pattern is used for the lower pattern, and which one is used is determined by the polarity of the upper code code.

Figure 6 is a block diagram showing a configuration of a PLC modem 61 which constitutes the base unit 34 ₁ or 34 _2. The PLC modem 61 corresponds to the multiplex transmission apparatus in the claims. The PLC modem 61 includes a digital unit 62, an analog unit 63, a power supply unit 64, a transmission driver circuit (DV) 65, a transformer 66, a common mode choke (CMC) 67, and a connection unit 68. Yes.

  The digital unit 62 includes a PLC media access (PLC-MAC) control unit 71, a multiplexing processing unit 72, and a demultiplexing processing unit 73. The PLC-MAC control unit 71 exchanges transmission / reception data with the outside via the connection unit 68, performs time division processing based on an instruction from the controller 85 including a CPU and the like, and receives control information from the controller 85. Transfer and user data time slot management. The multiplexing processing unit 72 multiplexes transmission data and transmits it. The demultiplexing processing unit 73 separates the received signal into received data.

  The multiplexing processing unit 72 includes a scrambler (SCR) / summing circuit 74, a signal point generation unit 75, an inverse fast Fourier transform unit (IFFT) 76, a modulation unit (MOD) 77, and a D / A converter. 78. The scrambler (SCR) / summing circuit 74 randomizes the transmission data from the PLC-MAC control unit 71, realizes stabilization of the transmission spectrum or stabilization of the leakage electric field, and phase summing to withstand line fluctuations. I do.

  The signal point generator 75 generates transmission signal points of a plurality of channels, and performs notch generation, spectrum spreading, and the like as necessary. In addition, the signal point generator 75 is a beacon signal BC1, beacon signals BC2A # 01 to BC2A # 16, BC2B # 01 to BC2B # 16, BC2C # 01 to BC2C # 16, and BC2D # 01 to BC2D # 16, which are synchronization signals. Are generated by code division multiplexing of 4 code divisions and frequency division multiplexing of 16 frequency divisions.

  In code division multiplexing, a specific code code is transmitted only for necessary channels. With this configuration, the frequency division multiplexing can be divided into 16. In order to multiplex this frequency division multiplexing into 16 divisions, a notch technique is used. The notch technique is performed by stopping transmission of a specific channel of IFTT 76. For details of the notch technique, see, for example, p. 54-p. See 60.

  The necessary transmission pattern is preferably stored in advance in a ROM or the like provided in the signal point generator 75, for example. The function of the signal point generator 75 that generates the beacon signal BC1, the beacon signals BC2A # 01 to BC2A # 16, BC2B # 01 to BC2B # 16, BC2C # 01 to BC2C # 16, and BC2D # 01 to BC2D # 16 It can be called a synchronization signal generating means.

  The IFFT 76 converts information on the frequency axis, which is a transmission signal point of a plurality of channels, supplied from the signal point generator 75 into information on the time axis. The MOD 77 modulates the information on the time axis supplied from the IFFT 76 after waveform shaping. IFTT 76 and MOD 77 are configured to multiplex signal points at the Nyquist time interval on the time axis and at the Nyquist frequency interval on the frequency axis. The D / A converter 78 converts the modulation signal from the MOD 77 into an analog signal.

  The demultiplexing processing unit 73 includes an A / D converter 79, a demodulation unit (DEM) 80, a fast Fourier transform unit (FFT) 81, a timing synchronization unit (TIM extraction & PLL) 82, a signal point determination unit 83, , And a differential / descramble (DSCR) circuit 84, and serves as demultiplexing processing means for performing demultiplexing processing of the beacon signal BC2. The A / D converter 79 converts the received signal from the analog unit 63 into a digital signal. The DEM 80 demodulates the received signal converted into the digital signal from the A / D converter 79 to obtain a baseband signal, and then removes unnecessary bands.

  The FFT 81 converts information on the time axis of the signal from the DEM 80 into information on the frequency axis. The signal point determination unit 83 determines a reception signal point for information on the frequency axis from the FFT 81. Based on the information on the individual frequency axes from the FFT 81, the timing synchronization unit 82 is a beacon signal BC1, beacon signals BC2A # 01 to BC2A # 16, BC2B # 01 to BC2B # 16, BC2C # 01 to BC2C # 01 to BC2C # 16 and BC2D # 01 to BC2D # 16 are processed, and beacon signals BC1, BC2A # 01 to BC2A # 16, BC2B # 01 to BC2B # 16, BC2C # 01 to BC2C # 16 and BC2D # 01 to BC2D # 16 is detected. The timing synchronization unit 82 then controls the DCXO 94 to establish desired synchronization.

  The difference / DSCR circuit 84 obtains the phase difference of the signal whose reception signal point is determined, and then restores the randomized state to reproduce the transmission data. This transmission data is transferred to a terminal (not shown) via the PLC-MAC control unit 71 and the connection unit 68.

  The analog unit 63 includes a first low-pass filter (LPF) 91, a high-pass filter and gain switch unit (HPF & GSW) 92, a second LPF 93, and a digitally controlled crystal oscillator (DCXO) 94. The first LPF 91 removes unnecessary bands on the analog signal supplied from the multiplexing processing unit 72. The HPF & GSW 92 removes unnecessary low frequency components from the received signal input via the CMC 67 and the transformer 66, and then amplifies the signal to a predetermined level. The second LPF 93 removes a high-frequency unnecessary band component of the received signal from the HPF & GSW 92. The DCXO 94 generates a reference clock having a predetermined oscillation frequency based on the analog signal supplied from the timing synchronization unit 82 and supplies the reference clock to the A / D converter 79.

  The connection unit 68 includes an Ethernet (registered trademark) processing unit (Ether-PHY) 86 that processes a signal (LAN data) input / output from the 100BASE-TX side, a filtering process, a fragment process, a retransmission process, an encryption process, It comprises a PLC switch unit (PLC-SW) 87 that performs switching processing and the like.

  The power supply unit 64 includes, for example, a power supply output unit 95 that supplies an operating voltage of a DC voltage of 5 V to each unit, and a power supply filter 96 that suppresses switching noise leakage of the power supply output unit 95 configured by a switching power supply. Yes. The transmission driver circuit 65 amplifies the signal supplied from the first LPF 91 and then transmits the amplified signal to the AC 100V indoor distribution line side via the transformer 66 and the CMC 67.

  FIG. 7 is a block diagram showing a configuration of the beacon signal BC2 detection circuit 101 provided in the timing synchronization unit 82 described above. The beacon signal BC2 detection circuit 101 includes a correlation filter circuit (PNF) 102, a square circuit 103, a maximum power extraction circuit 104, a maximum signal extraction circuit 105, a complex conjugate inversion detection circuit 106, and a signal series reproduction circuit 107. The power signal regeneration circuit 108, the 13 period filter circuit 109, the sum of squares circuit 110, the maximum extraction circuit 111, and the beacon detection circuit 112.

  The PNF 102 is a correlation filter using the same coefficient as the coefficient of the beacon signal BC2 on the transmission side as a filter coefficient. The PNF 102 detects the correlation between beacon signals BC1 and BC2 of individual channels on the frequency axis from information on the frequency axis supplied from the FFT 81 shown in FIG. The PNF 102 outputs a signal S1 having a waveform obtained by inverting the polarity of the peak value of the beacon signal BC2 for 13 periods in accordance with the upper code code.

  The squaring circuit 103 squares the output signal S1 of the PNF 102 and outputs a signal S2. The maximum power extraction circuit 104 extracts the maximum power value S3 and its time address information (hereinafter referred to as “maximum address information”) MA within one cycle (lower 13PN time length) of the output signal S2 of the square circuit 103. The maximum signal extraction circuit 105 extracts the maximum signal point of the output signal S1 of the PNF 102 based on the maximum address information MA supplied from the maximum power extraction circuit 104, and uses one sample signal per cycle as the representative point signal S4. Output.

  The complex conjugate inversion detection circuit 106 determines the phase of the newly received representative point signal based on the representative point signal S4 supplied from the maximum signal extraction circuit 105 and the representative point signal (reference) output in the previous period. It is determined whether or not the phase has been inverted, and a phase inversion signal S5 that is “1” if there is phase inversion and “0” if there is no phase inversion is output. The signal series reproduction circuit 107 sequentially reproduces the signal series relative phase signal S6 using the phase inversion signal S5 supplied from the complex conjugate inversion detection circuit 106.

  The power signal reproduction circuit 108 is close to the original transmission signal series based on the maximum power value S3 supplied from the maximum power extraction circuit 104 and the relative phase signal S6 of the signal series supplied from the signal series reproduction circuit 107. The power series S7 is reproduced. Since the power signal reproduction circuit 108 reproduces the beacon signal BC2 waveform based on the relative phase signal S6 for each period even when the PLL provided in the timing synchronization unit 82 is not pulled in, the high frequency allowable range Is obtained.

  The PNF 109 outputs a correlation waveform S8 for 13 periods of the power sequence S7 supplied from the power signal reproduction circuit 108. In this case, since the power sequence S7 uses the maximum point for each period of the power of the signal S1 output from the PNF 102, a stable beacon signal BC2 independent of the phase of the received carrier can be detected.

  The square sum circuit 110 squares the correlation waveform S8 for 13 periods supplied from the PNF 109, and then multiplexes it on the frequency axis by the number of channels. The maximum extraction circuit 111 extracts the maximum beacon signal BC2 from the beacon signals BC2 for 39 periods. Although not shown, the beacon detection circuit 112 has a dB median determination means. Here, the dB median determination is performed by discriminating and determining the detection threshold of the beacon signal BC2 from the ideal reception point of the typical value at a 6 dB down point that is half of 12 dB when the identification gain is 12 dB in width, for example. The beacon signal BC2 is detected.

  Next, the operation of the beacon signal BC2 detection circuit 101 configured as described above will be described with reference to FIGS. First, the information on the frequency axis supplied from the FFT 81 shown in FIG. 6 passes through a beacon correlation filter (not shown), whereby the correlation detection is performed on the beacon signals BC1 and BC2 of individual channels on the frequency axis.

  Next, the PNF 102 shown in FIG. 7 outputs a signal S1 having a waveform obtained by inverting the polarity of the peak value for each cycle of the beacon signal BC2 for 13 cycles in accordance with the upper code code. FIG. 8 shows the signal S1 for one channel. Next, the squaring circuit 103 squares the output signal S1 of the PNF 102 and outputs a signal S2 shown in FIG. As can be seen from FIG. 9, there is no negative component. FIG. 9 shows the signal S1 for one channel.

  Next, the maximum power extraction circuit 104 extracts the maximum power value S3 and its time address information (hereinafter referred to as “maximum address information”) MA within one cycle (lower 13PN time length) of the output signal S2 of the squaring circuit 103. To do. On the other hand, the maximum signal extraction circuit 105 extracts the maximum signal point of the output signal S1 of the PNF 102 based on the maximum address information MA supplied from the maximum power extraction circuit 104, and the signal of one sample per cycle is shown in FIG. The representative point signal S4 is output.

  Next, the complex conjugate inversion detection circuit 106 receives the newly received representative point signal based on the representative point signal S4 supplied from the maximum signal extraction circuit 105 and the representative point signal (reference) output in the previous period. The phase inversion signal S5 (see FIG. 11) that is “1” when there is phase inversion and “0” when there is no phase inversion is output.

  Next, the signal series reproduction circuit 107 sequentially reproduces the relative phase signal S6 (see FIG. 11) of the signal series using the phase inversion signal S5 supplied from the complex conjugate inversion detection circuit 106. As a result, the power signal reproduction circuit 108 based on the maximum power value S3 supplied from the maximum power extraction circuit 104 and the relative phase signal S6 of the signal series supplied from the signal series reproduction circuit 107, A power series S7 (see FIG. 11) close to the series is reproduced. Since the power signal reproduction circuit 108 reproduces the beacon signal BC2 waveform based on the relative phase signal S6 for each period even when the PLL provided in the timing synchronization unit 82 is not pulled in, the high frequency allowable range Is obtained.

  The PNF 109 outputs a correlation waveform S8 for 13 periods of the power sequence S7 supplied from the power signal reproduction circuit 108. In this case, since the power sequence S7 uses the maximum point for each period of the power of the signal S1 output from the PNF 102, a stable beacon signal BC2 independent of the phase of the received carrier can be detected. FIG. 12 shows an image of the correlation waveform S8 for 13 cycles, but the correlation waveform is for 13 cycles.

  Next, the square sum circuit 110 squares the 13-period correlation waveforms S8 supplied from the PNF 109, and then multiplexes them on the frequency axis by the number of channels (for example, 384 channels). Thereby, the S / N is improved. Next, the maximum extraction circuit 111 extracts the maximum beacon signal BC2 ′ from the beacon signal BC2 for 39 periods.

  The beacon detection circuit 112 determines that the detection threshold of the beacon signal BC2 is 6 dB down point, which is half of 12 dB from the ideal reception point of the typical value, when the identification gain is 12 dB in width, for example, by the internal dB median determination means. The beacon signal BC2 is detected by discriminating and determining at. Since most of noise fluctuations, interference degradation, and the like are based on dB, stable discrimination can be performed by setting a determination threshold value to the median value of dB.

  Here, FIG. 14 shows the result of a simple simulation. (1) is a case where the supplied beacon signal BC2A is non-inverted, and (2) is a case where the supplied beacon signal BC2A is inverted. The first stage is the maximum power value S3 output from the maximum power extraction circuit 105, the second stage is the value of the representative point signal S4 output from the maximum signal extraction circuit 105, and the third stage is the complex conjugate inversion detection circuit. This is the value of the phase inversion signal S5 output from 106. The fourth stage shows values and errors of non-inverted reproduction and inverted reproduction of the relative phase signal S6 of the signal series output from the signal series reproduction circuit 107, respectively. It can be seen from FIG. 14 that the error is within an allowable range.

  As described above, according to the present embodiment, the beacon signals BC2 for 63 units of the repeater 4 are code-division multiplexed with four different codes, and are generated by frequency division multiplexing of 16 divisions for each code. ing. Therefore, even when a plurality of repeaters 4 transmit signals simultaneously, information can be multiplexed and transmitted without collision. For this reason, the overhead is not increased and the MAC efficiency is not lowered.

  In addition, according to the present embodiment, by providing the maximum power extraction circuit 104 and the maximum signal extraction circuit 105, the original beacon signal BC2 is drawn into an incorrect correlation point before and after the original beacon signal BC2, that is, the relay to which the own device does not belong. Synchronization with the beacon signal BC2 transmitted from the machine 4 is canceled. In addition, according to the present embodiment, 13PN orthogonal sequences are further multiplexed twice above 13PN to transmit beacon signal BC2, and double PNFs 102 and 109 are provided on the receiving side. As a result, the minimum necessary identification gain can be ensured.

  In addition, according to the present embodiment, other signals based on the relative changes in signal power and phase, which are reliable information when the frequency on the receiving side is not drawn, that is, synchronization is not established. Sequence playback, structural check, code amount check, filtering, and identification are performed. Therefore, the beacon signal BC1 can be ignored and the beacon signal BC2 from the repeater 4 to which the slave unit 2 belongs can be stably synchronized.

In addition, according to the present embodiment, data other than the second synchronization signal is transmitted by time division multiplexing without frequency division multiplexing of different user data, so that a large reception dynamic range can be secured. . This is because when data transmission is performed by time-division multiplexing, each signal is independent on the time axis, so that an amplifier (not shown) constituting the HPF & GSW 92 provided in the preceding stage of the A / D converter 79 is used. This is because, by adjusting the gain according to the reception signal level, the reception signal capture range can be considerably widened.
Further, according to the present embodiment, beacon signals BC2A # 01 to BC2A # 16, BC2B # 01 to BC2B # 16, BC2C # 01 to BC2C # generated by the signal point generator 75 of the PLC modem 61 shown in FIG. 16 and BC2D # 01 to BC2D # 16 use 13-stage (13PN) M-sequence codes, so the shortest code as an M-sequence code that can secure four types of multiplex codes Therefore, the overhead (time not directly related to signal processing) can be minimized, and a decrease in MAC efficiency (utilization efficiency with respect to the physical layer) can be suppressed as much as possible.
Further, according to the present embodiment, the demultiplexing processing unit 73 shown in FIG. 6 corresponds to the plurality of types of M-sequence codes on the transmission side when performing the demultiplexing processing of the second synchronization signal. Using the PN filters (PNF) 102 and 109 which are correlation filters having the same coefficients as the M-sequence code as filter coefficients, the multiplexed second synchronization signal is subjected to correlation detection, and the PN filter (PNF ) Since the second synchronization signal is selected and detected by extracting and determining the maximum value of the correlation value of the PN filter (PNF) 109 in the period of 39 sampling periods of 109, it is high. Stability and identification gain can be ensured.
Note that the period during which the maximum extraction circuit 111 extracts and determines the maximum correlation value of the 13-period filter circuit 109 is 39 periods of the sampling period of the 13-period filter circuit 109. The number of stages of the M-sequence code 109 for which correlation detection is performed is 13, and the maximum extraction circuit 111 determines the maximum value of the correlation value in 39 cycles that is three times this number, so that the second value is surely and efficiently obtained. This is because the synchronization signal can be detected.
Explaining this reason in detail and considering that the M-sequence code is a signal of one cycle and extracting and capturing a signal of one cycle in a period of one cycle, it is possible to capture a clean waveform if the phases match, If it does not match, you will not be able to capture cleanly. According to the sampling theorem here, the signal capture period needs to exceed twice the signal period, and if the period three times the signal period is captured, the waveform can be captured even if the phase is advanced or delayed. Become.

As described above, the embodiments of the present invention have been described in detail with reference to the drawings. However, the specific configuration is not limited to these embodiments, and the design can be changed without departing from the scope of the present invention. Is included in the present invention.
In the above embodiment has been described only the configuration of the PLC modem 61 constituting the base unit 34 _1. The configuration of the PLC modem that constitutes the master unit 34 ₂ , the slave units 2 and 46 and the relay unit 4 is not different from the configuration of the PLC 61 described above except for the configuration of the connection unit 68. However, signals, data, programs to be executed, and the like handled by each PLC modem are different.

In the above-described embodiment, since the maximum number of repeaters 4 is 63, an example is shown in which code division multiplexing is set to 4 divisions and frequency division multiplexing is set to 16 divisions. It is not limited to. More generalized and can be shown as follows. That is, when the number of repeaters is 1 or more (n = k × m) (n, k, m are positive integers) or less, code division multiplexing is set to k division (1 ≦ k ≦ 8) and frequency The division multiplexing can be divided into m divisions (1 ≦ m ≦ 32). If k is greater than 8, the frequency tolerance is not good.
In the above-described embodiment, since code division multiplexing is set to four divisions, the number of stages of the M-sequence code is set to 13, and the maximum value of the correlation value of the 13-period filter circuit 109 in which the maximum extraction circuit 111 is a correlation filter is set. The extracted and determined period is 39 periods of the sampling period of the 13-period filter circuit 109. The number of stages of the M-sequence code is p (p is a positive integer), and the period of the 13-period filter circuit 109 is When the sampling period is T, the predetermined period in which the maximum extraction circuit 111 extracts and determines the maximum value of the 13-period filter circuit 109 can be (3 × p × T).

  In the above-described embodiment, the example in which the PLC modem as the multiplex transmission apparatus includes both the multiplexing processing unit 72 and the demultiplexing processing unit 73 is shown, but the present invention is not limited to this. The multiplex transmission apparatus can be configured to include only one of the multiplex processing unit 72 and the demultiplexing processing unit 73, and the multiplex processing unit 72 on the transmission side in data transmission is the main part. The multiplex transmission apparatus or the multiplex transmission apparatus having the receiving side demultiplexing processing unit 73 as a main part can be provided. Similarly, only one of the multiplex transmission methods can be applied.

It is a block diagram which shows schematic structure of the PLC system to which the multiplex transmission apparatus which concerns on embodiment of this invention is applied. It is a figure which shows an example of a structure of the master frame transmitted / received by the PLC system which concerns on this Embodiment. It is a figure which shows a non-inversion pattern and an inversion pattern about beacon signal BC2A-BC2D. It is a figure which shows an example of the autocorrelation characteristic of beacon signal BC2A. It is a figure which shows an example of the transmission pattern of beacon signal BC2A. It is a block diagram which shows the structure of the PLC modem which comprises a main | base station. It is a block diagram which shows the structure of the beacon signal BC2 detection circuit with which the timing synchronization part shown in FIG. 5 was equipped. It is a figure for demonstrating operation | movement of the beacon signal BC2 detection circuit. It is a figure for demonstrating operation | movement of the beacon signal BC2 detection circuit. It is a figure for demonstrating operation | movement of the beacon signal BC2 detection circuit. It is a figure for demonstrating operation | movement of the beacon signal BC2 detection circuit. It is a figure for demonstrating operation | movement of the beacon signal BC2 detection circuit. It is a figure for demonstrating operation | movement of the beacon signal BC2 detection circuit. It is a figure which shows the result of having simulated simply the operation | movement of the beacon signal BC2 detection circuit.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Game machine (terminal), 2,46 ... Child machine, 3 ... Island, 4 ... Relay machine, 5, 8, 11, 24, 25, 26, 38, 42, 47 ... Power cable, 6, 32, 33 ... 32 branch circuit, 7, 35 ... Branch adapter (branch ADP), 9, 22 ... Transformer, ₁₀ , 37 ₁ , 37 ₂ , 49, 50, 51, 53 ... Communication line, 21 ... Distribution board in power receiving facility , 23 ... 6 branch circuit, 31 ... floor entrance distribution board, 34 ₁ , 34 ₂ ... master unit, 41 ... monitoring room in hall, 43 ... wall outlet, 44 ... server, 45 ... LAN in hall, 48 ... plug 52 ... WAN, 54 ... center server, 61 ... PLC modem, 62 ... digital unit, 63 ... analog unit, 64 ... power supply unit, 65 ... transmission driver circuit (DV), 66 ... transformer, 67 ... common mode choke ( CMC), 68 ... connection portion, 71 PLC media access (PLC-MAC) control unit, 72 ... multiplexing processing unit, 73 ... demultiplexing processing unit, 74 ... scrambler (SCR) / summing circuit, 75 ... signal point generation unit (synchronization signal generation means), 76: Inverse fast Fourier transform unit (IFFT), 77: Modulation unit (MOD), 78 ... D / A converter, 79 ... A / D converter, 80 ... Demodulation unit (DEM), 81 ... Fast Fourier transform unit ( FFT) 82... Timing synchronization unit (TIM extraction & PLL) 83 83 Signal point determination unit 84 84 Difference / descrambling (DSCR) circuit 85 85 Controller (CPU) 86 Ethernet processing unit (Ether-PHY) 87... PLC switch unit (PLC-SW) 91. First low pass filter (LPF) 92. High pass filter and gain switch unit (HPF & GSW) 93 2nd LPF, 94 ... Digitally controlled crystal oscillator (DCXO), 95 ... Power supply output unit, 96 ... Power supply filter, 101 ... Beacon signal BC2 detection circuit, 102 ... Correlation filter circuit (PNF), 103 ... Square circuit, 104 ... Maximum Power extraction circuit, 105 ... maximum signal extraction circuit, 106 ... complex conjugate inversion detection circuit, 107 ... signal series reproduction circuit, 108 ... power signal reproduction circuit, 109 ... 13 period filter circuit, 110 ... square sum circuit, 111 ... maximum extraction Circuit 112 ... beacon detection circuit

Claims (4)

A data communication system for performing data communication between a master unit, a relay unit, and a plurality of slave units belonging to the relay unit,
A first synchronization signal for synchronization between the parent device and the relay device and a multiplexed second signal for synchronization between the relay device and each child device belonging to the relay device Synchronization signal generating means for generating a synchronization signal of
Demultiplexing processing means for separating the second synchronization signal,
The synchronization signal generating means includes
The second synchronization signals for the number of the repeaters are code-division multiplexed with a plurality of different types of M-sequence codes, and are generated by frequency division multiplexing for each M-sequence code,
The demultiplexing processing means includes:
Among the plurality of types of M-sequence codes on the transmission side, correlation detection of the second synchronization signal is performed using a correlation filter having the same coefficient as the selected M-sequence code as a filter coefficient, and the correlation filter of the correlation filter in a predetermined period is detected. Detecting the second synchronization signal by extracting and determining the maximum correlation value;
The data other than the second synchronization signal transmits different user data without frequency division multiplexing.
A data communication system.   When the number of stages of the M-sequence code is p (p is a positive integer), and the sampling period of the correlation filter is T, the predetermined period for extracting and determining the maximum value of the correlation value of the correlation filter is: The data communication system according to claim 1, wherein the data communication system is (3 × p × T). A data communication method for performing data communication between a parent device, a relay device, and a plurality of slave devices belonging to the relay device,
Generating a first synchronization signal for synchronization between the master unit and the relay unit;
Code-division-multiplexing the second synchronization signals for the number of the repeaters for synchronization between the repeater and each slave unit belonging to the repeater with different types of M-sequence codes, Generated by frequency division multiplexing for each M-sequence code,
When separating the second synchronization signal, the second synchronization signal is used by using a correlation filter in which the same coefficient as the corresponding M-sequence code is used as a filter coefficient among the plurality of types of M-sequence codes on the transmission side. Detecting the second synchronization signal by extracting and determining the maximum correlation value of the correlation filter in a predetermined period,
The data other than the second synchronization signal transmits different user data without frequency division multiplexing.   When the number of stages of the M-sequence code is p (p is a positive integer), and the sampling period of the correlation filter is T, the predetermined period for extracting and determining the maximum value of the correlation value of the correlation filter is: The data communication method according to claim 3, wherein (3 × p × T).

Images