JP5087907B2 - Electronic component manufacturing method, device manufacturing method, and electronic component manufacturing system - Google Patents

Description

  The present invention relates to an electronic component manufacturing method, a device manufacturing method, and an electronic component manufacturing system.

In the electronic component manufacturing process, processing using a plurality of processing apparatuses may be performed.
As an example of a manufacturing process of an electronic component that is processed using such a plurality of processing apparatuses, in a semiconductor exposure (lithography) process, for example, a function of applying a photosensitive material on a substrate and development of the substrate after exposure are performed. An in-line lithography system in which a coater / developer apparatus (hereinafter referred to as a C / D apparatus) having a function to perform is connected in-line to an exposure apparatus may be used.
In this type of in-line lithography system, since the operation of the exposure apparatus must be stopped when the operation is stopped such as periodic maintenance and parts replacement in the C / D apparatus, the operation rate of the exposure apparatus is lowered. The number of factors is obviously larger than that of the exposure apparatus alone.

Therefore, in Patent Document 1, the exposure apparatus includes a main control device as an operation determination device that determines the operation of the own device based on information on maintenance from the C / D device. During the maintenance of the D apparatus, that is, when the original operation of the exposure apparatus must be stopped, this is an operation necessary for maintaining the performance of the own apparatus. A technique for determining to perform a specific operation that needs to be stopped is disclosed. According to this technique, the downtime of the exposure apparatus necessary for performing the specific operation can be reduced as a whole, thereby reducing the apparatus performance of the exposure apparatus connected inline to the substrate processing apparatus. , The operating rate can be improved.
International Publication No. 06/025302 Pamphlet

However, the following problems exist in the conventional technology as described above.
There is a difference in processing capacity between the C / D apparatus and the exposure apparatus, and in many cases, the exposure apparatus is superior in processing capacity, so that the C / D apparatus does not stop operation in the exposure apparatus. Even in the state, waiting time may occur.
As described above, there has been a demand for a method that can effectively utilize the waiting time that occurs in any of the apparatuses even when there is a difference in processing capability between the apparatuses.

  The present invention has been made in consideration of the above points, and provides an electronic component manufacturing method, a device manufacturing method, and an electronic component manufacturing system capable of effectively utilizing the waiting time generated in any of the apparatuses. With the goal.

In order to achieve the above object, the present invention adopts the following configuration corresponding to FIGS. 1 to 6 showing the embodiment.
The electronic component manufacturing method of the present invention is an electronic component that performs a second process on the object (W) that has been subjected to the first process by the first processing apparatus (50) by the second processing apparatus (10). In the manufacturing method, a plurality of times related to at least one of the first process and the second process in a free time caused by a difference between the processing capacity of the first processing apparatus and the processing capacity of the second processing apparatus. A selection process for selecting a high-priority related process from among the related processes, an adjustment process for adjusting the selected high-priority related process, and the adjusted high-priority related process are performed. And a process .
Therefore, in the method of manufacturing an electronic component according to the present invention, the first process and the second process are performed in the idle time caused by the difference between the processing capacity of the first processing apparatus (50) and the processing capacity of the second processing apparatus (10). Since the related process related to at least one of the processes is adjusted, it is not necessary to separately secure the adjustment time of the related process, and the free time can be effectively used, which contributes to the improvement of productivity.
As this relation, at least one of the measurement process related to the second process, the calibration process of the measurement process, and the replacement process of the material used for the second process can be selected.
The electronic component manufacturing method of the present invention is a method of manufacturing an electronic component in which a second processing apparatus performs a second process on an object that has been subjected to a first process by a first processing apparatus. Adjustment of related processing related to at least one of the first processing and the second processing is performed in the free time caused by the difference between the processing capability of the first processing device and the processing capability of the second processing device. An adjustment step to be performed, and in the adjustment step, the related processing is adjusted so that the processing time of the related processing is extended according to the idle time and the accuracy of the related processing is improved. It is.

The device manufacturing method of the present invention is characterized by using the electronic component manufacturing method described above.
Therefore, in the device manufacturing method of the present invention, a device can be manufactured by effectively utilizing the idle time.

The electronic component manufacturing system of the present invention includes a first processing device (50) that performs a first process on an object (W), and a second process that is performed on the object (W) that has been subjected to the first process. And a plurality of related processing devices (ALG) for performing related processing related to at least one of the first processing and the second processing. ) And a related processing device that performs high-priority related processing from among the plurality of related processing devices in a free time caused by the difference between the processing power of the first processing device and the processing power of the second processing device. And an adjustment device (120) that performs adjustment of the selected related processing device (ALG).
Therefore, in the electronic component manufacturing system of the present invention, the first process and the second process are performed in the idle time caused by the difference between the processing capacity of the first processing apparatus (50) and the processing capacity of the second processing apparatus (10). Since the related process related to at least one of the processes is adjusted, it is not necessary to separately secure the adjustment time of the related process, and the free time can be effectively used, which contributes to the improvement of productivity.
The electronic component manufacturing system of the present invention includes a first processing device that performs a first process on an object, and a second processing device that performs a second process on the object that has been subjected to the first process. An electronic component manufacturing system comprising: a related processing device that performs a related processing related to at least one of the first processing and the second processing; a processing capability of the first processing device; The related processing device is adjusted so as to extend the processing time of the related processing device according to the idle time caused by the difference in processing capacity of the second processing device and improve the accuracy of the related processing. And an adjusting device.

  In order to explain the present invention in an easy-to-understand manner, the description has been made in association with the reference numerals of the drawings showing one embodiment, but it goes without saying that the present invention is not limited to the embodiment.

  In the present invention, it is possible to contribute to the improvement of productivity and improve the processing accuracy by effectively utilizing the idle time caused by the difference in processing capacity.

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of an electronic component manufacturing method, a device manufacturing method, and an electronic component manufacturing system according to the present invention will be described below with reference to FIGS.
Here, for example, as a first processing apparatus, a coater / developer apparatus (hereinafter referred to as a first processing apparatus) that performs a photosensitive material coating process on a semiconductor wafer for manufacturing a semiconductor device as a first process and performs a developing process on the wafer that has been subjected to the exposure process And an exposure apparatus that performs an exposure process as a second process on a wafer transferred from the C / D apparatus will be described as the second processing apparatus.
In each drawing used for the following description, the scale of each member is appropriately changed to make each member a recognizable size.

(First embodiment)
FIG. 1 is a plan view showing the configuration of a lithography system according to the first embodiment configured to include an exposure apparatus and a C / D apparatus according to the present invention.
A lithography system (electronic component manufacturing system) 100 shown in FIG. 1 is installed in a clean room. The lithography system 100 includes an exposure apparatus (second processing apparatus) 10 installed on the floor surface of a clean room, and an inline interface unit (hereinafter referred to as the left side in FIG. 1) of the exposure apparatus 10. (Referred to as “inline I / F unit”) 110 and a C / D device 50 serving as a first processing device. The lithography system 100 is installed in a clean room.

  The exposure apparatus 10 includes a chamber 16 in which a partition wall 14 is provided at a position slightly closer to the center in the Y-axis direction in FIG. 1 and the X-axis direction on one side defined by the partition wall 14 inside the chamber 16 ( -X side) is divided by an exposure apparatus main body 10A (not shown in FIG. 1 except for the wafer stage WST and projection optical system PL) and a partition wall 14 inside the chamber 16 accommodated in the large room 12A. In addition, a wafer loader system 40 as a substrate transfer system in which most of the small chamber 12B on the other side in the X-axis direction (+ X side) is accommodated is provided. A laser apparatus 1 as a light source disposed outside the chamber 16 is connected to the exposure apparatus main body 10A via a routing optical system BMU.

  FIG. 2 schematically shows the configuration of the exposure apparatus 10 in a front view. However, in FIG. 2, the chamber 16 is indicated by a virtual line (two-dot chain line). The exposure apparatus 10 is a step-and-scan type scanning projection exposure apparatus, that is, a so-called scanner (also called a scanning stepper).

As the laser device 1, a pulse laser that oscillates pulsed light in the far ultraviolet region such as a KrF excimer laser (oscillation wavelength 248 nm) or an ArF excimer laser (oscillation wavelength 193 nm) is used. As the laser device 1, a vacuum ultraviolet light source such as an F ₂ laser (oscillation wavelength 157 nm) may be used.

  The exposure apparatus main body 10A includes an illumination unit ILU, a reticle stage RST that holds a reticle R as a mask, a projection optical system PL, a wafer stage WST that holds a wafer W and can move freely in an XY plane, and the reticle stage. A body BD on which the RST, the projection optical system PL, and the like are mounted, and a main controller 120 that comprehensively controls the entire apparatus are provided.

  The illumination unit ILU includes an illumination system housing 111, a beam shaping optical system, an energy coarse adjuster, an optical integrator, an illumination system aperture stop plate, a beam splitter, and a relay disposed in the illumination system housing 111 in a predetermined positional relationship. An illumination optical system including an optical system and the like (both not shown). In addition, a field stop (also referred to as a reticle blind or a masking blade) including a fixed blind and a movable blind (not shown) is disposed inside the relay optical system of the illumination optical system. As the optical integrator, a fly-eye lens, a rod type (internal reflection type) integrator, a diffractive optical element, or the like is used.

The laser device 1 is connected to the beam shaping optical system provided at the incident end of the illumination unit ILU, that is, the incident end of the illumination optical system, via the light transmission optical system BMU.
This illumination unit ILU has a uniform illuminance distribution on a rectangular (for example, rectangular) slit-like illumination area IAR (defined by the opening of a fixed blind) extending in the X-axis direction on the reticle R held on the reticle stage RST. Illuminate with. The internal configuration of the illumination unit similar to that of the present embodiment is disclosed in detail in, for example, Japanese Patent Laid-Open No. 6-349701.

  The reticle stage RST is provided above the upper surface of the reticle base 136 which is the top plate portion of the second column 134 constituting the body BD. On reticle stage RST, reticle R is fixed by, for example, vacuum chucking (or electrostatic chucking). Reticle stage RST is two-dimensionally (in the X-axis direction) in an XY plane perpendicular to the optical axis of the illumination optical system (matching optical axis AX of projection optical system PL) by reticle stage driving unit 112 including a linear motor and the like. In addition, it can be finely driven in the Y axis direction and the rotation direction (θz direction) around the Z axis orthogonal to the XY plane, and can be driven on the reticle base 136 at a scanning speed specified in the Y axis direction. .

The position of the reticle stage RST in the XY plane (including the rotation in the θz direction, which is the rotation direction around the Z axis) is transferred via the moving mirror 15 (and the X moving mirror (not shown) for X axis direction measurement) to the reticle. It is always detected by a reticle laser interferometer (hereinafter referred to as “reticle interferometer”) 13 fixed to the base 136.
Position information (or velocity information) of reticle stage RST is sent to main controller 120, and main controller 120 drives reticle stage RST via reticle stage drive unit 112 based on the position information (or velocity information). To do. A reticle fiducial mark plate (RFM plate) (not shown) is provided at a position on the −Y side of the mounting area of the reticle R of the reticle stage RST. A plurality of types of measurement marks are formed on the RFM plate. The RFM plate similar to the present embodiment is disclosed in detail in, for example, JP-A-2002-198303.

  The body BD includes a first column 132 and a second column 134 disposed on the first column 132. The first column 132 is supported by three leg portions 137A, 137B, and 137C (however, the leg portion 137C on the back side in FIG. 2 is not shown) and these leg portions 137A to 137C. And a lens barrel surface plate (also called a main frame) 138 constituting the top plate. Each of the leg portions 137 </ b> A to 137 </ b> C includes a support column 140 and a vibration isolation unit 139 fixed to the upper portion of the support column 140. Each vibration isolation unit 139 insulates minute vibrations from the floor surface as much as possible and hardly transmits to the lens barrel surface plate 138. The lens barrel surface plate 138 is formed with a circular opening (not shown) at substantially the center thereof, and the projection optical system PL is inserted into the opening from above. The lens barrel of the projection optical system PL is provided with a flange FLG, and the projection optical system PL is supported by the lens barrel surface plate 138 via the flange FLG. The second column 134 is provided on the upper surface of the lens barrel surface plate 138 so as to surround the projection optical system PL, and extends in the vertical direction, for example, three legs 41A, 41B, 41C (however, in FIG. 2) The leg 41C on the back side of the paper is not shown) and connects the upper end surfaces of the legs 41A to 41C with each other and the reticle base 136 supported by the legs 41A to 41C.

  Here, the projection optical system PL is a bilateral telecentric reduction system, and a refractive optical system including a plurality of lens elements having a common optical axis AX in the Z-axis direction is used. As this projection optical system PL, a reduction optical system having a projection magnification β of 1/4, for example, is used. For this reason, when the slit-shaped illumination area IAR on the reticle R is illuminated by the illumination light IL from the illumination unit ILU (illumination optical system), the illumination light IL that has passed through the reticle R is within the slit-shaped illumination area IAR. The reduced image (partial inverted image) of the circuit pattern of the reticle R through the projection optical system PL is exposed to an exposure area IA conjugate to the illumination area IAR on the wafer (substrate, object) W coated with photoresist on the surface. It is formed.

  Wafer stage WST includes XY stage 141 that is freely driven along the upper surface of stage base SB within an XY two-dimensional plane (including θz rotation) by a drive system (not shown) such as a linear motor or a planar motor, and XY stage. 141 and a wafer table TB mounted on 141. The stage base SB is also called a surface plate, and in the present embodiment, the stage base SB is supported via a plurality of, for example, three or four anti-vibration units 43 installed on the floor surface.

  Wafer stage WST includes XY stage 141 that is freely driven along the upper surface of stage base SB within an XY two-dimensional plane (including θz rotation) by a drive system (not shown) such as a linear motor or a planar motor, and XY stage. 141 and a wafer table TB mounted on 141. The stage base SB is also called a surface plate, and in the present embodiment, the stage base SB is supported via a plurality of, for example, three or four anti-vibration units 43 installed on the floor surface.

  On the wafer table TB, the wafer W is held by vacuum suction (or electrostatic suction) via the wafer holder 25. On the wafer table TB, a movable mirror 27 (and an X movable mirror (not shown) for measuring the X-axis direction) that reflects a laser beam from a wafer laser interferometer (hereinafter referred to as “wafer interferometer”) 31 is provided. The position in the XY plane of wafer table TB (wafer W) is always detected by wafer interferometer 31 that is fixed and supported by suspension from lens barrel surface plate 138. In the following description, it is assumed that the wafer interferometer 31 measures the positions of the wafer table TB in the X, Y, θz, θy, and θx directions with 5 degrees of freedom. The position information (or speed information) of the wafer table TB is sent to the main controller 120, and the main controller 120 controls the wafer table TB via the wafer stage drive unit 128 based on the position information (or speed information). .

  The wafer stage drive unit 128 includes a linear motor, a planar motor, a voice coil motor, or the like, but is shown as a simple block in FIG. 2 for convenience of illustration. On the wafer table TB, a reference mark plate FM whose surface is almost the same height as the surface of the wafer W is fixed. Various reference marks are formed on the surface of the reference mark plate FM. A reference plane plate 143 is fixed on the wafer table TB. The surface of the reference flat plate 143 has almost the same height as the surface of the wafer W, like the reference mark plate FM.

  A slit opening is formed in a part of the reference flat plate 143, and a portion other than the slit opening is a reflection surface on which a reflection film is formed. A photoelectric conversion element (not shown) such as a photomultiplier tube (PMT) is arranged inside the wafer table TB below the slit opening. A photoelectric conversion signal from the photoelectric conversion element is supplied to the main controller 120. Main controller 120 receives the photoelectric conversion signal from the photoelectric conversion element while positioning the aforementioned RFM plate in the field of view of projection optical system PL and moving wafer table TB in the Y-axis direction or the X-axis direction. Thus, the aerial images of various measurement marks formed on the image plane by the projection optical system PL can be measured by the slit scan method. That is, in the present embodiment, the aerial image measuring instrument disclosed in the above-mentioned Japanese Patent Application Laid-Open No. 2002-198303 including the slit opening formed in the reference plane plate 143, the photoelectric conversion element in the wafer table TB, and the like. It is configured.

  Furthermore, the exposure apparatus main body 10A of the present embodiment has a light transmission system 160a and a light receiving system 160b, and detects oblique incidence on the surface of the wafer W with respect to the optical axis AX direction (Z-axis direction) and inclination with respect to the XY plane. A multi-point focus position detection system (hereinafter referred to as “multi-point AF system” as appropriate) is provided. A multi-point AF system similar to the multi-point AF system of the present embodiment is disclosed in detail in, for example, Japanese Patent Laid-Open No. Hei 6-283403. In main controller 120, in addition to the movement of wafer stage WST in the Z-axis direction via wafer stage drive unit 128 based on the focus signals from multi-point AF systems 160a and 160b at the time of scanning exposure, etc., two-dimensionally In the irradiation area of the illumination light IL (the above-described exposure area IA) by controlling the tilt (that is, the rotation in the θx and θy directions), that is, by controlling the movement of the wafer stage WST using the multipoint AF system. Then, autofocusing (automatic focusing) and autoleveling are performed so that the imaging plane of the projection optical system PL substantially matches the surface of the wafer W.

  Further, in the exposure apparatus main body 10A, an off-axis alignment system ALG for detecting an alignment mark on the wafer W, a reference mark on the reference mark plate FM, and the like is disposed on the side surface of the lens barrel of the projection optical system PL. As this alignment system ALG, for example, a broadband detection light beam that does not sensitize the resist on the wafer W is irradiated to the target mark, and an image of the target mark formed on the light receiving surface by reflected light from the target mark is not shown. An image processing type FIA (Field Image Alignment) type sensor that captures an image of an index using an image sensor (CCD or the like) and outputs an image signal thereof is used. In addition to the FIA system, the target mark is irradiated with coherent detection light to detect scattered light or diffracted light generated from the target mark, or two diffracted lights (for example, of the same order) generated from the target mark. Alignment sensors that detect the interference may be used alone or in appropriate combination.

  Returning to FIG. 1, the wafer loader system 40 transports a Y guide 18 extending in the Y-axis direction and an X guide 20 positioned above the Y guide 18 (front side in FIG. 1) and extending in the X-axis direction. It is provided as a guide. A horizontal articulated robot 26 that moves along the Y guide 18 is provided on the Y guide 18. The X guide 20 is provided with a load arm 28 and an unload arm 30 that move along the X guide 20. The partition wall 14 has openings through which the load arm 28 and the unload arm 30 can pass. Furthermore, a turntable 32 in which a wafer edge sensor (not shown) is arranged in the vicinity is provided at a position on the −Y side in the vicinity of the + X side end of the X guide 20. Also, in the loader chamber 12B, each part of the wafer loader system 40 is controlled, and information exchange, that is, communication with respect to the wafer being transferred is performed with a C / D-side control device described later via a communication line. A loader control device 34 is provided.

  The inline I / F unit 110 includes an inline delivery unit 114, a carrier table 118, a horizontal articulated robot 116, and the like.

  The C / D device 50 includes a coating / development control device 62 as a control computer that comprehensively controls each part of the C / D device 50, a wafer transfer unit 64, a Y guide 66 extending in the Y-axis direction, and a Y guide. 66, a horizontal articulated robot 68 that moves along 66, a first developing unit 70, a second developing unit 72, a bake unit 74, a first coating unit 76, and a second coating unit 78 that are arranged to face the Y guide 66. The cooling unit 80 is provided. The coating / developing control device 62 controls the above-described scalar robot 116 in the inline I / F unit 110 as well as the wafer transfer system in the C / D device 50. In the vicinity of the end portion of the Y guide 66, a wafer transfer portion 82 is provided at a boundary portion with the inline I / F portion 110.

  FIG. 3 is a block diagram showing the configuration of the control system of the lithography system 100. As shown in FIG. 3, the control system on the exposure apparatus 10 side is configured with a main controller 120 as a center, and the loader controller 34 and the like described above are placed under the control of the main controller 120. The main control device 120 includes a workstation (or a microcomputer), and the main control device 120 is provided with a pointing device such as a keyboard and a mouse, and an input / output device 230 including a CRT display or a liquid crystal display. ing. On the other hand, the control system on the C / D device 50 side is configured with a coating / development control device 62 as a center, and the coating / development control device 62 controls the scalar robots 68, 116, and the like. An input / output device 63 similar to the input / output device 230 is also connected to the coating / developing control device 62.

  In the present embodiment, data is transferred between the loader control device 34 on the exposure apparatus 10 side and the coating / development control device 62 of the C / D device 50 and between the main control device 120 and the coating / development control device 62. Communication is possible. In this case, information relating to the wafer being transferred is mainly exchanged between the loader control device 34 and the coating / developing control device 62. Various information such as the time until the wafer W is supplied to the exposure apparatus 10 is exchanged between the main controller 120 and the coating / development controller 62.

Next, a wafer processing operation by the lithography system 100 will be described.
Here, it is assumed that a first wafer W (hereinafter referred to as “wafer W1” for convenience) as a substrate (object) is placed on the wafer transfer section 64. Therefore, the scalar robot 68 carries the wafer W from the wafer delivery unit 64 into the first application unit 76, for example. Thereby, the application of the resist on the wafer W is started in the first application unit 76. When the resist coating of the wafer W is completed, the robot 68 carries the wafer W from the first coating unit 76 to the bake unit 74. As a result, the wafer W is heat-treated (PB) in the bake unit 74.

  Then, when the heat-treated wafer W is carried into the cooling unit 80 and carried into the exposure chamber 12A, the temperature does not affect each part in the exposure chamber 12A, for example, 20 to 25 ° C. It is cooled to the temperature specified in the range. When the cooling in the cooling unit 80 is completed, the wafer W is placed on the wafer delivery unit 82 by the robot 68 and then placed on the inline delivery unit 114 by the robot 116.

  On the other hand, on the exposure apparatus 10 side, first, the robot 26 receives the wafer W from the inline delivery unit 114 and places it on the turntable 32. Here, the wafer edge is detected by the wafer edge sensor, and the turntable 32 is rotated by the loader control device 34 based on the detection signal so that the direction of the notch portion of the wafer W is adjusted to a predetermined direction. Thereafter, the load arm 28 receives the wafer W on the turntable 32, moves along the X guide 20, and carries it to the wafer stage WST.

  For wafer W transferred onto wafer stage WST, an operation for positioning reticle R (reticle stage RST) and wafer W (wafer stage WST) to a scanning start position for exposure of each shot area, and reticle The slit-shaped illumination area on the reticle R is illuminated with exposure illumination light while the R and the wafer W are moved synchronously, and the pattern of the reticle R is sequentially applied to each shot area on the wafer W via the projection optical system PL. The exposure process is performed by repeating the scanning exposure operation for transferring. When the exposure process is completed, the unload arm 30 receives the exposed wafer W and passes it to the robot 26. Then, the wafer W is transferred by the robot 26 and transferred to the inline transfer unit 114.

Thereafter, the exposed wafer W is transferred from the in-line transfer unit 114 to the wafer transfer unit 82 by the robot 116, and further transferred into the bake unit 74 by the robot 68. In the bake unit 74, PEB (post-bake) is performed. Is done.
On the other hand, the wafer W for which PEB has been completed is taken out of the bake unit 74 by the robot 68, and is carried into, for example, the first developing unit 70 and developed. The developed wafer W is placed on the wafer transfer section 64 by the robot 68.

Incidentally, there may be a difference in processing capability between the above-described C / D apparatus 50 and the exposure apparatus 10. In the present embodiment, a case where the processing capability in the exposure apparatus 10 is higher than the processing capability in the C / D apparatus 50 will be described.
When the processing capability in the exposure apparatus 10 is higher than the processing capability in the C / D apparatus 50, an idle time (waiting time) may occur before the exposure apparatus 10 starts processing on the wafer W. Further, in order to perform wafer processing operations smoothly over a long period of time, exposure processing is performed in order to maintain the performance of the apparatus such as the maintenance of each part of the exposure apparatus 10 and the C / D apparatus 50 constituting the lithography system 100. It is necessary to perform a specific operation (related process) required in connection with The specific operation is an operation necessary for maintaining the performance of the device, such as maintenance (including regular maintenance, other maintenance, part replacement, etc.) and self-calibration. Includes all operations that need to be stopped.
Therefore, in the present embodiment, the specific operation is adjusted in the idle time caused by the difference in processing capability between the devices 10 and 50.

Here, as an example of processing related to the exposure processing, a case where calibration A to C processing is performed as shown in FIG. 4 will be described. These calibrations A to C are performed at a frequency for each wafer or lot, and for example, focus calibration, calibration of a dose sensor, and the like are performed.
The execution time of the related processing shown in FIG. 4 is “short” for a relatively short time, “long” for a relatively long time, and a relatively short time and a relatively long time. Those in the middle are shown as “medium”.

  As for the above-described plurality of exposure-related processes (hereinafter simply referred to as related processes), the time required for the processes and the priority order are previously input to the main controller 120 via the input / output device 230 by the operator. And Further, these related processes and their adjustment processes are performed by appropriately selecting the following two modes according to the frequency with which the related processes should be performed.

(First mode)
FIG. 5A shows the free time and the exposure processing time on the exposure apparatus 10 side from the start to the end of processing in the lithography system 100 for 25 wafers per lot in the first mode (second step). It is the time chart which showed. As shown in this figure, after the vacant time T1 elapses after the resist coating process is completed from the time T0 when the processing for the wafer at the head of the lot is started in the C / D apparatus 50, the exposure apparatus 10 An exposure process is performed on the wafer W with the processing time Te, and thereafter, an exposure process is performed on the second and subsequent wafers W2 to W25 with the processing time Te through the idle time T2. The idle times T1 and T2 are output from the coating / developing control device 62 to the main control device 120.

  In the exposure apparatus 10, the main controller 120 serves as an adjustment apparatus, and sequentially performs the related processing based on the priority order set in advance in the exposure apparatus 10 during the idle times T <b> 1 and T <b> 2. Specifically, first, in the vacant time T1, among the related processes completed within the vacant time T1, processing is sequentially performed from the processing with the highest priority. In this case, for example, in the long idle time T1, calibration processing such as calibration C having a long processing time is performed. In the short idle time T2, calibration processing such as calibration A with a short processing time is performed. Furthermore, if there is a process that is completed within the remaining idle time in which the related processing is performed in the free times T1 and T2, the related process is performed, and until there is no related process to be completed in the remaining free time, Perform related processing. In any case, when there are a plurality of related processes that can be executed, it is preferable to select different related processes to be executed according to the set priority.

  In the idle time T2 that occurs after the exposure processing of the wafer W2, among the related processes that are completed within the idle time T2, the related processes that have not been performed in the idle times T1 and T2 before the previous processing are preferentially selected. ·carry out. Also in this case, if a plurality of related processes can be selected, the process with the higher priority is selected, and if a plurality of related processes can be performed, these related processes are selected and continuously executed. .

(Second mode)
Subsequently, the second mode (first step) will be described.
For example, other than the above calibration, for example, replacement of a gas that is a material of a laser used for exposure or replacement of a liquid used in an immersion exposure apparatus that forms a pattern through an optical system and a liquid may take about 30 minutes. Therefore, it is difficult to secure the processing time with the free times T1 and T2 in the first mode. Therefore, when it is necessary to perform related processing having a long processing time, a mode that can secure a long processing time without increasing the total processing time for the wafer is selected.

  FIG. 5B is a time showing the free time and the exposure processing time on the exposure apparatus 10 side from the start to the end of processing in the lithography system 100 for 25 wafers in one lot in the second mode. It is a chart. As shown in this figure, in the second mode, the idle time T2 that is known in advance output from the coating / development control device 62 of the C / D device 50 is summed according to the number of wafers, and is further free. The free time T3 combined with the time T1 is set (in FIG. 5 (b), only the free time T2 is shown for four sheets, but actually 24 sheets). Then, the exposure processing for the wafers W1 to W25 is continuously performed without providing a free time after the free time T3 has elapsed.

In the exposure apparatus 10, as in the first mode, the main controller 120 performs the above-described related processing according to the free time T3. However, in the second mode, a long free time T3 can be secured. The above-described calibration, laser gas exchange processing, and the like can be performed. Also in this mode, if there is a process that is completed in the free time after the related process is performed, the related process is performed, and the related process is performed until there is no related process to be completed in the remaining free time. carry out. When there are a plurality of related processes that can be executed, it is preferable to select different related processes to be executed according to the set priority order.
In this embodiment, the case where the processing capability in the exposure apparatus 10 is higher than the processing capability in the C / D apparatus 50 has been described, but the processing capability in the exposure apparatus 10 is lower than the processing capacity in the C / D apparatus 50. However, it goes without saying that the present invention can be used.

As described above, in this embodiment, even when the C / D device 50 is not stopped, the exposure-related processing and the adjustment processing are performed in the free time caused by the difference in processing capability. By doing so, for example, it is not necessary to separately provide time for the related processing and its adjustment processing, which can contribute to improvement of productivity.
Further, in the present embodiment, for example, calibration related to various measurement processes can be performed at a timing not conventionally performed. Therefore, the measurement accuracy in the subsequent exposure processing is improved, and the pattern transfer accuracy and the pattern line width are improved. It can also contribute to improvement of exposure accuracy such as miniaturization.
Furthermore, in this embodiment, since the first mode and the second mode can be selected according to the time required for the related processing to be performed, even when there is a related processing with a long processing time, the exposure processing time is not lengthened. The performance of the exposure apparatus 10 can be ensured by performing the related processing.

(Second Embodiment)
Next, a second embodiment of the present invention will be described with reference to FIG. Here, the same reference numerals are used for the same or equivalent components as those in the first embodiment described above, and descriptions thereof are omitted. The lithography system of the second embodiment is different from the first embodiment described above only in the configuration of the control system, and therefore, the following description will be focused on this difference.

  FIG. 6 is a block diagram showing the configuration of the control system of the lithography system according to the second embodiment. As shown in FIG. 6, in the second embodiment, a host computer 90 as a management device is shared by the coating and developing device 62 on the C / D device 50 side and the main control device 120 of the exposure device 10. It is connected. In this lithography system, information related to the various related processes (processing contents, timing (timing), required time, etc.) on the exposure apparatus 10 side managed by the main controller 120 is constantly sent to the host computer 90. Yes. Information relating to exposure-related processing on the C / D device 50 side managed by the coating / development control device 62 is always sent to the host computer 90. The host computer 90 comprehensively manages the necessity of related processing on the exposure apparatus 10 side and the C / D apparatus 50 side, and related processing on the C / D apparatus 50 side and related processing on the exposure apparatus 10 side. Are coordinated as an adjustment device.

  Specifically, the host computer 90 predicts the idle time until the wafer W is supplied to the exposure apparatus 10 according to the coating processing status output from the C / D apparatus 50 side, and sets the exposure apparatus 10 side. Output to the main controller 120. Then, main controller 120 causes the above-described related processing to be performed based on the idle time output (feed forward) from host computer 90. Further, the host computer 90 predicts the idle time until the wafer W is supplied to the exposure apparatus 10 each time the coating process is performed in the C / D apparatus 50, and the idle time information output to the main controller 120. Are corrected sequentially. As a result, the main control device 120 can always select the related process accurately based on more accurate idle time information. Similarly, the host computer 90 may be configured to predict the idle time according to the exposure processing status output from the exposure apparatus 10 side (main control apparatus 120) and output it to the main control apparatus 120. Also in this case, it becomes possible to accurately grasp the idle time that varies depending on the exposure processing status, and the related processing described above can be accurately selected and executed.

  The host computer 90 can also cause the main control device 120 to select a related process to be performed in the idle time based on the result of measuring a wafer processed by the lithography system 100 (feedback). For example, when the overlay accuracy of the pattern formed on the wafer is less than or equal to a predetermined value, the host computer 90 makes the main control device 120 perform different related processes to perform alignment calibration. An instruction to preferentially select and execute, or an instruction to preferentially select and execute focus calibration to the main control device 120 when the pattern line width deviates from a specified value. It is good also as a structure to take out.

(Third embodiment)
Subsequently, a third embodiment of the present invention will be described.
In the above embodiment, the procedure for starting the related process is performed using the time corresponding to (corresponding to) the free time or the free time. However, in the present embodiment, the time corresponding to the free time or the free time is used. A case where the processing time is extended will be described.

  For example, when the exposure process for the wafer W is the exposure process for the second and subsequent layers, an EGA measurement using an alignment system ALG is used to form a circuit pattern with good overlay accuracy with a pattern that has already been formed (Japanese Patent Application Laid-Open (JP-A)). The so-called enhanced global alignment (disclosed in Japanese Patent Application Laid-Open No. 61-44429) or the like can detect the array coordinates of the shot area on the wafer W with high accuracy. In this EGA measurement, the coordinates of all shot areas on the wafer W are calculated by statistically processing the coordinates of a plurality of (for example, eight) wafer marks in a predetermined arrangement on the wafer W. When the vacant times T1 and T2 are notified, the number of wafer marks (for example, 12 locations) that can be measured in the vacant time is obtained, and when performing EGA measurement, the time corresponding to the vacant time is obtained. Extend and perform 12 measurement / calculation processes.

In this way, by utilizing the idle time and extending the processing time of related processing, it is possible to improve exposure accuracy such as pattern transfer accuracy without increasing the total processing time for the wafer. Become.
In addition to the above-mentioned EGA measurement, for example, a temperature adjustment process in the cooling unit 80 can be cited as a related process that contributes to improving accuracy by extending the processing time.
In this case, by using the above-described vacant time, the cooling time for the wafer after resist coating can be lengthened to bring it closer to the temperature in the exposure chamber 12A, and the wafer W is distorted due to the temperature difference. It is possible to prevent the wafer holder 25 from expanding and to contribute to the improvement of exposure accuracy.

  As described above, the preferred embodiments according to the present invention have been described with reference to the accompanying drawings, but the present invention is not limited to the examples. Various shapes, combinations, and the like of the constituent members shown in the above-described examples are examples, and various modifications can be made based on design requirements and the like without departing from the gist of the present invention.

  For example, in the first embodiment, the first mode and the second mode are selected and implemented. However, only the second mode in which the related process and the adjustment process can be performed for a long time is continuously performed. It is also possible to implement. However, especially when using a laser light source, taking into consideration the fact that the photosensitive property of the resist is kept constant by keeping the time from the completion of the exposure processing to the wafer until the development processing is performed constant. Normally, the first mode is selected, and it is preferable to select the second mode when the related processing is performed for a relatively long time.

  In the above embodiment, the present invention is applied to a system in which an exposure apparatus and a C / D apparatus are connected. However, the present invention is not limited to this. For example, an inspection apparatus that inspects a substrate (wafer). Using a plurality of processing devices such as a system in which a C / D apparatus is connected, a system in which the inspection apparatus and the exposure apparatus are connected, and a system in which the substrate transport apparatus and the exposure apparatus are connected. It can be widely applied to systems for manufacturing parts.

  In addition to using the idle time due to the difference in capacity between the two processing devices, there are three or more processing devices such as a first processing device, a second processing device, a third processing device,. In this case, the processing capacity of the predetermined processing apparatus (for example, the third processing apparatus) and the processing capacities of the plurality of processing apparatuses that perform pre-processing than the predetermined processing apparatus (for example, the first processing apparatus and the second processing apparatus) It is also possible to use the idle time due to the difference in processing capacity with the processing capacity combined with the above.

  The substrate (object) in each of the above embodiments is not limited to a semiconductor wafer for manufacturing a semiconductor device, but a glass substrate for a display device, a ceramic wafer for a thin film magnetic head, or a mask or reticle used in an exposure apparatus. The original plate (synthetic quartz, silicon wafer) or the like is applied.

  As the exposure apparatus 10, in addition to a step-and-scan type scanning exposure apparatus (scanning stepper) that scans and exposes the pattern of the reticle R by synchronously moving the reticle R and the wafer W, the reticle R and the wafer W It can also be applied to a step-and-repeat projection exposure apparatus (stepper) in which the pattern of the reticle R is collectively exposed while the wafer is stationary and the wafer W is sequentially moved stepwise. The present invention can also be applied to a step-and-stitch type exposure apparatus that partially transfers at least two patterns on the wafer W.

  The type of the exposure apparatus 10 is not limited to an exposure apparatus for manufacturing a semiconductor element that exposes a semiconductor element pattern onto the wafer W, but an exposure apparatus for manufacturing a liquid crystal display element or a display, a thin film magnetic head, an image sensor (CCD). ) Or an exposure apparatus for manufacturing reticles or masks.

The light source of the exposure apparatus to which the present invention is applied includes not only KrF excimer laser (248 nm), ArF excimer laser (193 nm), F ₂ laser (157 nm), but also g-line (436 nm) and i-line (365 nm). ) Can be used. Further, the magnification of the projection optical system may be not only a reduction system but also an equal magnification or an enlargement system. In the above embodiment, the catadioptric projection optical system is exemplified, but the present invention is not limited to this, and the optical axis (reticle center) of the projection optical system and the center of the projection area are set at different positions. It can also be applied to a refraction type projection optical system.

  Further, the present invention is applied to a so-called immersion exposure apparatus in which a liquid is locally filled between the projection optical system and the substrate, and the substrate is exposed through the liquid. It is disclosed in the publication No. 99/49504 pamphlet. Further, in the present invention, the entire surface of the substrate to be exposed as disclosed in JP-A-6-124873, JP-A-10-303114, US Pat. No. 5,825,043 and the like is in the liquid. The present invention is also applicable to an immersion exposure apparatus that performs exposure while being immersed.

  The present invention can also be applied to a twin stage type exposure apparatus provided with a plurality of substrate stages (wafer stages). The structure and exposure operation of a twin stage type exposure apparatus are described in, for example, Japanese Patent Laid-Open Nos. 10-163099 and 10-214783 (corresponding US Pat. Nos. 6,341,007, 6,400,441, 6,549). , 269 and 6,590,634), JP 2000-505958 (corresponding US Pat. No. 5,969,441) or US Pat. No. 6,208,407. Furthermore, the present invention may be applied to the wafer stage disclosed in Japanese Patent Application No. 2004-168482 filed earlier by the present applicant.

  An exposure apparatus to which the present invention is applied assembles various subsystems including the constituent elements recited in the claims of the present application so as to maintain predetermined mechanical accuracy, electrical accuracy, and optical accuracy. It is manufactured by. In order to ensure these various accuracies, before and after assembly, various optical systems are adjusted to achieve optical accuracy, various mechanical systems are adjusted to achieve mechanical accuracy, and various electrical systems are Adjustments are made to achieve electrical accuracy. The assembly process from the various subsystems to the exposure apparatus includes mechanical connection, electrical circuit wiring connection, pneumatic circuit piping connection and the like between the various subsystems. Needless to say, there is an assembly process for each subsystem before the assembly process from the various subsystems to the exposure apparatus. When the assembly process of the various subsystems to the exposure apparatus is completed, comprehensive adjustment is performed to ensure various accuracies as the entire exposure apparatus. The exposure apparatus is preferably manufactured in a clean room where the temperature, cleanliness, etc. are controlled.

Next, an embodiment of a manufacturing method of a micro device using the exposure apparatus and the exposure method according to the embodiment of the present invention in the lithography process will be described. FIG. 7 is a flowchart showing a manufacturing example of a micro device (a semiconductor chip such as an IC or LSI, a liquid crystal panel, a CCD, a thin film magnetic head, a micro machine, etc.).
First, in step S10 (design step), function / performance design (for example, circuit design of a semiconductor device) of a micro device is performed, and pattern design for realizing the function is performed. Subsequently, in step S11 (mask manufacturing step), a mask (reticle) on which the designed circuit pattern is formed is manufactured. On the other hand, in step S12 (wafer manufacturing step), a wafer is manufactured using a material such as silicon.
Next, in step S13 (wafer processing step), using the mask and wafer prepared in steps S10 to S12, an actual circuit or the like is formed on the wafer by lithography or the like, as will be described later. Next, in step S14 (device assembly step), device assembly is performed using the wafer processed in step S13. This step S14 includes processes such as a dicing process, a bonding process, and a packaging process (chip encapsulation) as necessary. Finally, in step S15 (inspection step), inspections such as an operation confirmation test and a durability test of the microdevice manufactured in step S14 are performed. After these steps, the microdevice is completed and shipped.

FIG. 8 is a diagram illustrating an example of a detailed process of step S13 in the case of a semiconductor device.
In step S21 (oxidation step), the surface of the wafer is oxidized. In step S22 (CVD step), an insulating film is formed on the wafer surface. In step S23 (electrode formation step), an electrode is formed on the wafer by vapor deposition. In step S24 (ion implantation step), ions are implanted into the wafer. Each of the above steps S21 to S24 constitutes a pre-processing process at each stage of the wafer processing, and is selected and executed according to a necessary process at each stage.
At each stage of the wafer process, when the above pre-process is completed, the post-process is executed as follows. In this post-processing process, first, in step S25 (resist formation step), a photosensitive agent is applied to the wafer. Subsequently, in step S26 (exposure step), the circuit pattern of the mask is transferred to the wafer by the lithography system (exposure apparatus) and the exposure method described above. Next, in step S27 (development step), the exposed wafer is developed, and in step S28 (etching step), exposed members other than the portion where the resist remains are removed by etching. In step S29 (resist removal step), the resist that has become unnecessary after the etching is removed. By repeatedly performing these pre-processing steps and post-processing steps, multiple circuit patterns are formed on the wafer.

  Further, in order to manufacture reticles or masks used in not only microdevices such as semiconductor elements but also light exposure apparatuses, EUV exposure apparatuses, X-ray exposure apparatuses, electron beam exposure apparatuses, etc., from mother reticles to glass substrates and The present invention can also be applied to an exposure apparatus that transfers a circuit pattern to a silicon wafer or the like. Here, in an exposure apparatus using DUV (deep ultraviolet), VUV (vacuum ultraviolet) light, or the like, a transmission type reticle is generally used. As a reticle substrate, quartz glass, fluorine-doped quartz glass, fluorite, Magnesium fluoride or quartz is used. In proximity-type X-ray exposure apparatuses, electron beam exposure apparatuses, and the like, a transmissive mask (stencil mask, membrane mask) is used, and a silicon wafer or the like is used as a mask substrate. Such an exposure apparatus is disclosed in WO99 / 34255, WO99 / 50712, WO99 / 66370, JP-A-11-194479, JP-A2000-12453, JP-A-2000-29202, and the like. .

1 is a plan view schematically showing a configuration of a lithography system according to a first embodiment of the present invention. It is a figure which shows the structure of the exposure apparatus of FIG. FIG. 2 is a block diagram schematically showing a configuration of a control system of the lithography system of FIG. 1. It is a graph which shows an example of the process relevant to an exposure process. 6 is a time chart showing idle time and exposure processing time in the exposure apparatus. It is a block diagram which shows roughly the structure of the control system of the lithography system which concerns on 2nd Embodiment. It is a flowchart figure which shows an example of the manufacturing process of a microdevice. It is a figure which shows an example of the detailed process of step S13 in FIG.

Explanation of symbols

  ALG: alignment system (related processing apparatus), R: reticle (mask), W: wafer (substrate, object), 1 ... laser apparatus (utility supply apparatus, related processing apparatus), 10: exposure apparatus (second processing apparatus) ), 50... C / D apparatus (first processing apparatus), 90... Host computer (adjustment apparatus), 100... Lithography system (electronic component manufacturing system), 120.

Claims (21)

A method of manufacturing an electronic component in which a second processing device performs a second processing on an object that has been subjected to a first processing by a first processing device,
A plurality of related processes related to at least one of the first process and the second process in a free time caused by a difference between the processing capacity of the first processing apparatus and the processing capacity of the second processing apparatus. A selection process for selecting a related process with a high priority from
An adjustment process for adjusting the selected high priority related processing ;
Performing the adjusted high priority related processing;
A method for manufacturing an electronic component, comprising: A method of manufacturing an electronic component in which a second processing device performs a second processing on an object that has been subjected to a first processing by a first processing device,
Adjustment of related processing related to at least one of the first processing and the second processing in a free time caused by the difference between the processing capability of the first processing device and the processing capability of the second processing device An adjustment process to perform
In the adjustment step, the related process is adjusted so as to extend the processing time of the related process according to the idle time and improve the accuracy of the related process . Production method. In the manufacturing method of the electronic component of Claim 1,
In the adjusting step, the related process is adjusted so that a plurality of related processes according to the priority order are selected and executed according to the idle time. In the manufacturing method of the electronic component of Claim 3,
The method of manufacturing an electronic component, wherein the plurality of related processes are processes different from each other. In the manufacturing method of the electronic component of Claim 3 or 4,
A method of manufacturing an electronic component , wherein the adjustment is performed so as to change the related processing to be performed based on a result of performing the second processing on the object. In the manufacturing method of the electronic component in any one of Claim 1 to 5,
Predicting the idle time based on the result of performing the second process on the object;
A method of manufacturing an electronic component, wherein the related processing is adjusted according to the predicted free time. In the manufacturing method of the electronic component in any one of Claim 1 to 5,
Predicting the idle time based on information obtained by performing the first processing on the object;
A method of manufacturing an electronic component, wherein the related processing is adjusted according to the predicted free time. In the manufacturing method of the electronic component in any one of Claim 1 to 7,
After performing the adjustment process so that the related process is performed within a time obtained by adding a predetermined free time set for each object in the second process according to the number of the plurality of objects. A method for manufacturing an electronic component, comprising: a first step of continuously performing the second process on the plurality of objects. In the manufacturing method of the electronic component of Claim 8,
The object subjected to the first process is selected and executed by selecting a plurality of second processes for performing the second process and the first process at predetermined intervals. Manufacturing method of electronic components. In the manufacturing method of the electronic component in any one of Claim 1 to 9,
The related process is at least one of a measurement process related to the second process, a calibration process of the measurement process, and a replacement process of a material used for the second process. In the manufacturing method of the electronic component in any one of Claim 1 to 10,
The method of manufacturing an electronic component, wherein the second process performed by the second processing apparatus is an exposure process performed by an exposure apparatus.   A device manufacturing method using the method for manufacturing an electronic component according to claim 1. An electronic component manufacturing system comprising: a first processing device that performs a first process on an object; and a second processing device that performs a second process on the object that has been subjected to the first process,
A plurality of related processing devices that perform related processing related to at least one of the first processing and the second processing;
A related processing device that performs high-priority related processing processing is selected from among the plurality of related processing devices during a free time caused by the difference between the processing capability of the first processing device and the processing capability of the second processing device. And an adjusting device for adjusting the selected related processing device. An electronic component manufacturing system comprising: a first processing device that performs a first process on an object; and a second processing device that performs a second process on the object that has been subjected to the first process,
A related processing device that performs related processing related to at least one of the first processing and the second processing;
The processing time of the related processing device is extended in accordance with the idle time caused by the difference between the processing capability of the first processing device and the processing capability of the second processing device, and the accuracy of the related processing is improved. as an adjustment device for performing the adjustment of the associated processor,
An electronic component manufacturing system comprising: The electronic component manufacturing system according to claim 13,
The said adjustment apparatus adjusts so that the said related processing apparatus may be selected and implemented according to the said idle time, The manufacturing system of the electronic component characterized by the above-mentioned . In the electronic component manufacturing system according to claim 15,
The system for manufacturing an electronic component, wherein the plurality of related processing devices perform different related processes. The electronic component manufacturing system according to claim 15 or 16,
The adjusting device, based on a result of said second processing to said object, the electronic component manufacturing system, characterized in that to adjust to change the associated processing device to be selected. In the electronic component manufacturing system according to any one of claims 13 to 17,
The adjusting device predicts the idle time based on a result of performing the second process on the object;
An electronic component manufacturing system, wherein the related processing device is adjusted according to a predicted free time. In the electronic component manufacturing system according to any one of claims 13 to 17,
The adjusting device predicts the idle time based on a result of performing the first process on the object;
An electronic component manufacturing system, wherein the related processing device is adjusted according to a predicted free time. In the electronic component manufacturing system according to any one of claims 13 to 19,
The related processing device is at least one of a measurement device that performs measurement processing related to the second processing and a material replacement device that replaces a material used for the second processing. The electronic component manufacturing system according to any one of claims 13 to 20,
The second processing apparatus is an exposure apparatus that performs an exposure process.

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