JP5079278B2 - SIMULATION METHOD USING TRANSISTOR MODEL AND METHOD FOR CONTROLLING CIRCUIT OF FIELD EFFECT TRANSISTOR BASED ON SIMULATION METHOD USING TRANSISTOR MODEL - Google Patents

Description

  The present invention relates to a simulation method using a transistor model for performing an operation analysis by reflecting a change in threshold voltage caused by a change in potential distribution in a channel formation region of a field effect transistor, and a simulation using the transistor model The present invention relates to an operation control method for a circuit composed of a field effect transistor based on the method.

  It is known that a threshold voltage of a field effect transistor, in particular, a polysilicon thin film transistor or an amorphous silicon thin film transistor used for a liquid crystal device or the like, varies transiently depending on operating conditions. Conventionally, there has been proposed a method for improving the accuracy of operation analysis of a field effect transistor by reflecting a phenomenon in which a threshold voltage of a transistor fluctuates transiently in a simulation using a transistor model.

  Japanese Laid-Open Patent Publication No. 10-326295 (Patent Document 1) discloses that local levels in the forbidden band (forbidden band) are closely involved in the electrical conduction of amorphous silicon thin film transistors, and bias conditions and history during operation. , The threshold voltage varies. Further, in the above-mentioned Patent Document 1, by using a threshold voltage model in which a drain current model is connected to a circuit model in which a pair of a resistance model and a capacitance model connected in parallel is connected in series, An analysis method for correcting the value of the threshold voltage based on the value of the current flowing through the transistor model is disclosed.

JP 10-326295 A (page 2-4, FIG. 3)

  In the method disclosed in Japanese Patent Laid-Open No. 10-326295, the threshold voltage value does not change when no current flows between the drain terminal and the source terminal of the transistor model. However, in an actual transistor, the threshold voltage changes even when no current flows between the drain electrode and the source electrode. For example, disclosed by “Shigenobu Maeda, Low Power Consumption / High-Speed MOSFET Technology, Polycrystalline Silicon TFT Load SRAM and SOI Device, Cypec, June 2002, p. 37-38, FIG. 2-17 (1)”. As shown, when a so-called band-to-band trap is present, carriers are trapped and the threshold voltage fluctuates when the potential distribution in the channel formation region is changed by applying a voltage to the gate electrode of the transistor. For example, as shown in FIG. 9, when a drain electrode and a source electrode of a transistor are short-circuited and a voltage is applied to the gate electrode, electrons are trapped (captured) at the localized level of the channel formation region, and the threshold value of the transistor is fluctuate. In the method disclosed in Japanese Patent Laid-Open No. 10-326295 described above, the value of the threshold voltage does not vary unless a current flows between the drain terminal and the source terminal of the transistor model. Thus, it cannot be said that the above-described method sufficiently reflects the mechanism of threshold fluctuation in an actual transistor, and the accuracy of simulation is lowered.

  Accordingly, a first object of the present invention is to provide a simulation method using a transistor model for performing an operation analysis by reflecting a change in threshold voltage caused by a change in potential distribution in a channel formation region of a field effect transistor. There is to do. A second object of the present invention is based on a simulation method using a transistor model for performing an operation analysis by reflecting a change in threshold voltage caused by a change in potential distribution in a channel formation region of a field effect transistor. Another object of the present invention is to provide a method for controlling the operation of a circuit comprising a field effect transistor.

The simulation method of the present invention for achieving the first object described above is a transistor model for performing an operation analysis reflecting a change in threshold voltage caused by a change in potential distribution in a channel formation region of a field effect transistor. A simulation method using
(1) Based on the value obtained by the threshold voltage calculation model defined to reflect the relationship between the potential distribution change in the channel formation region and the carriers captured / released by the localized levels in the channel formation region. Calculate the threshold voltage change amount,
(2) Correcting the threshold voltage value based on the threshold voltage variation,
(3) Analyzing the operation of a circuit model composed of a transistor model based on the corrected threshold voltage value . The threshold voltage calculation model may be one independent integration circuit model or a plurality of mutually independent integration circuit models. of which is constituted by an integrating circuit model, the value of the potential difference between the gate terminal and the source terminal of the transistor model V _gs, the value of the predetermined voltage _V gslim (where, _V gslim> 0) when the, the V _gs When the absolute value is less than or equal to V _gslim , a voltage having a value of V _gs is applied to each of the integration circuit models, and when the absolute value of V _gs exceeds the value of V _gslim , the integration circuit model A voltage having a value of V _gslim ² / V _gs is applied to each.

An operation control method for a circuit comprising a field effect transistor to achieve the second object described above is an operation analysis reflecting a change in threshold voltage caused by a change in potential distribution in a channel formation region of the field effect transistor. A method for controlling the operation of a circuit composed of a field effect transistor based on a simulation method using a transistor model for performing
By the simulation method,
(1) Based on the value obtained by the threshold voltage calculation model defined to reflect the relationship between the potential distribution change in the channel formation region and the carriers captured / released by the localized levels in the channel formation region. Calculate the threshold voltage change amount,
(2) Correcting the threshold voltage value based on the threshold voltage variation,
(3) Analyzing the operation of the circuit model composed of the transistor model based on the corrected threshold voltage value;
(4) Based on the analysis result of the operation of the circuit model, the signal input to the circuit composed of the field effect transistor is corrected, and the threshold voltage calculation model is an independent integration circuit model or It is composed of a plurality of mutually independent integration circuit models, and the potential difference value between the gate terminal and the source terminal of the transistor model is V _gs , and the predetermined voltage value is V _gslim (where V _gslim > 0). When the absolute value of V _gs is less than or equal to the value of V _gslim , a voltage having a value of V _gs is applied to each integration circuit model, and when the absolute value of V _gs exceeds the value of V _gslim. A voltage having a value of V _gslim ² / V _gs is applied to each of the integration circuit models .

  The simulation method of the present invention and the simulation method used in the operation control method of a circuit comprising the field effect transistor of the present invention (hereinafter, these may be collectively referred to simply as the simulation method of the present invention). In this case, it reflects the relationship between the change in potential distribution in the channel formation region of a field effect transistor (hereinafter sometimes referred to simply as FET) and the carriers that are captured / released by the localized levels in the channel formation region. A model for calculating a threshold voltage is used. Here, the “channel formation region” means a region where a channel can be formed, and does not mean only a region where a channel is formed. For example, in a thin film transistor, a portion of a semiconductor layer located opposite to a gate electrode corresponds to a “channel formation region”. According to the present invention, even in a state where no current flows between the drain terminal and the source terminal of the transistor model, the value of the threshold voltage varies as in the case of the actual transistor. Thereby, the threshold fluctuation in the actual transistor can be schematically reflected. A circuit comprising a transistor model that calculates a threshold voltage change amount based on a value obtained by a threshold voltage calculation model, corrects the threshold voltage value based on the threshold voltage change amount, and based on the corrected threshold voltage value By analyzing the behavior of the model, it is possible to perform accurate simulation analysis. Simulation analysis can be performed on a circuit composed of discrete elements, or simulation analysis can be performed on a circuit comprising an LSI, or a thin film transistor formed on a glass substrate, a plastic substrate, or the like. You can also. In the simulation method of the present invention, a widely known transistor model can be used. “A circuit model including a transistor model” widely means a circuit model including a transistor model. That is, it may be a circuit model composed of only one or a plurality of transistor models, or a circuit model composed of a transistor model and an element model other than the transistor model. In addition, according to the operation control method for a circuit including a field effect transistor according to the present invention, the field effect is corrected by correcting a signal input to the circuit including the field effect transistor based on an accurate simulation analysis result. A circuit composed of a type transistor can be operated satisfactorily. For example, by performing a simulation based on a circuit model so as to precede the operation of a circuit composed of an actual field effect transistor, it is possible to dynamically grasp a malfunction due to a delay in the operation of the circuit. When a malfunction is confirmed by simulation, the actual circuit can be operated at an appropriate timing by correcting the phase and the like of the signal input to the circuit composed of the actual field effect transistor. As simulation means used in the simulation method of the present invention and the operation control method of a circuit comprising the field effect transistor of the present invention (hereinafter, these may be collectively referred to simply as the present invention), for example, Known simulators such as SPICE (Simulation Program with Integrated Circuit Emphasis) can be widely used. By a simulator executed by a computer having a storage means and a CPU, the threshold voltage change amount, the correction of the threshold voltage value based on the threshold voltage change amount, and the operation of the circuit model including the transistor model based on the corrected threshold voltage value are performed. Can be analyzed.

  In the simulation method of the present invention, the threshold voltage calculation model can be constituted by one independent integration circuit model or a plurality of mutually independent integration circuit models. The number of integrating circuit models is not particularly limited as long as it is 1 or more, but may be appropriately set according to the driving frequency of the transistor model in the simulation. As a guideline, the number of integrating circuit models may be increased by one every time the driving frequency of the transistor model is increased 10 times. The integration circuit model can be configured by connecting a capacitance model and a resistance model in series. As will be described later, when a certain potential level continues for a time t in the channel formation region of the FET, the amount of charge trapped in the localized level in the channel formation region is approximately proportional to ln (t). The same applies to the amount of charge released from the localized level when the potential level decreases by a certain value and continues for time t. Since the value of the electric charge accumulated in the capacitance model constituting the single integration circuit model changes exponentially, there is a case where the logarithmic change cannot be expressed sufficiently. In this case, in a plurality of integration circuit models having different time constants, a logarithmic change can be simulated in a circuit by considering the value of the sum of charges accumulated in each capacitance model. As described above, the state where carriers are trapped / released in the channel formation region can be schematically represented by charge accumulation / discharge in the integration circuit model.

In the simulation method of the present invention including the various preferable modes and configurations described above, the resistance value in the resistance model constituting the integration circuit model can be changed depending on the operation of the transistor model. For example, a constant value R _OFF in, a certain value R _ON is when a relation R _OFF> R _ON, the value of resistance in the resistance model and R _ON in the transistor model is turned on, the transistor model is turned off In FIG. 5, the resistance value in the resistance model is set as R _OFF , and a simulation can be performed. When the threshold voltage calculation model is composed of a plurality of integration circuit models, the above-described constant values R _OFF and R _ON are individually set for each integration circuit model. In the configuration described above, depending on the operating state of the transistor model, the resistance value in the resistance model constituting each integrating circuit model is one of two different values, but is not limited thereto. . For example, in the simulation, the value of the channel resistance can be virtually calculated based on the current value and the voltage value between the drain terminal and the source terminal in the transistor model. Based on the channel resistance value obtained in this way, the resistance value in the resistance model constituting the integrating circuit model can be changed. The degree of carrier capture / release in an actual transistor varies depending on the operating state of the transistor. By changing the resistance value in the resistance model constituting the integration circuit model depending on the operating state of the transistor model, it is possible to schematically reflect the change in the degree of carrier capture / release in the actual transistor.

In the simulation method of the present invention including the various preferred modes and configurations described above, a voltage based on the value of the potential difference between the gate terminal and the source terminal of the transistor model is applied to each of the integration circuit models. It can be configured. In this case, when the value of the potential difference between the gate terminal and the source terminal of the transistor model is V _gs and the value of the predetermined voltage is V _gslim , the absolute value of V _gs is less than the value of V _{gslim. Applies} a voltage of V _gs to each integrating circuit model, and when the absolute value of V _gs exceeds the value of V _gslim , the voltage of V _gslim ² / V _gs is applied to each integrating circuit model. It can be set as the structure which applies. That is, when the absolute value of V _gs exceeds the value of V _gslim , a voltage having a smaller value is applied to each integrating circuit model as the absolute value of V _gs increases. In general, in a FET, the degree of change in potential distribution in a channel formation region and the voltage between a gate electrode and a source electrode are not simply proportional. That is, after the strong inversion, the potential distribution hardly changes even if the voltage between the gate electrode and the source electrode changes. In addition, for example, in a polysilicon thin film transistor, it is known that the height of the potential barrier at the grain boundary portion of the polysilicon layer is lowered due to the influence of inversion charges after strong inversion (for example, The electrical properties of dense silicon films, John YWSeto, J. Appl. Phys. 46 (12), December 1975, 5247-5254). According to the above-described configuration, when the absolute value of V _gs exceeds the value of V _gslim , a voltage having a value of V _gslim ² / V _gs is applied to each integrating circuit model, so that after the strong inversion described above. It is possible to reflect the tendency of potential change at.

但し、α、βは定数、Ｃ_OXはトランジスタモデルにおける単位面積あたりのゲート絶縁膜容量の値である。尚、上述した閾値電圧の基準値Ｖ_{th_ref}は、実際のトランジスタにおいて直流電圧を印加したときの電流−電圧特性（Ｖ_gs−Ｉ_ds特性）に基づいて決定することができる。基準値Ｖ_{th_ref}は、実際のトランジスタにおいて充分にキャリアが局在準位に捕獲された状態における閾値電圧の値に対応する。 In the simulation method of the present invention including the various preferable modes and configurations described above, the threshold voltage change amount may be calculated based on the charge value in the capacitance model that constitutes each integration circuit model. it can. In this case, (A) the reference value of the threshold voltage is V _{th_ref} , (B) the number of integration circuit models is N, and the n-th integration circuit model (where n = 1, 2,..., N) is configured. When the charge value in the capacitance model is Q _n and the threshold voltage change amount is ΔV _th , ΔV _th is calculated based on the following formula (1), and then ΔV _th is added to V _{th_ref} to set the threshold value. The voltage value can be corrected.

Here, α and β are constants, and C _OX is the value of the gate insulating film capacitance per unit area in the transistor model. The threshold voltage reference value V _{th_ref} described above can be determined based on current-voltage characteristics (V _gs -I _ds characteristics) when a DC voltage is applied to an actual transistor. The reference value V _{th_ref} corresponds to the value of the threshold voltage in a state where carriers are sufficiently trapped in the localized level in an actual transistor.

In this case, (A) the capacitance value in the capacitance model constituting the nth integration circuit model is applied to C _n , and (B) is applied to the nth integration circuit model at a certain time t. V _n (t) is the voltage value, Q _n (t) is the charge value in the capacitance model constituting the nth integration circuit model, and resistance in the resistance model constituting the nth integration circuit model When the value of R _n (t) is R _n (t), the charge value Q _n (t + Δt) in the capacitance model constituting the nth integration circuit model when time Δt has elapsed from time t is expressed by the following equation: The calculation can be made based on (2), and the threshold voltage change amount ΔV _th can be calculated based on the following equation (1) ′.

Values of various parameters such as the above-described predetermined voltage value V _gslim , constants α and β shown in Equation (1), a capacitance value in the capacitance model constituting the integration circuit model, and a resistance value in the resistance model Can be determined by fitting so that the characteristics of the circuit composed of the actual field effect transistor to be simulated and the characteristics obtained by the simulation of the circuit model composed of the transistor model are substantially matched. For example, in an actual inverter chain circuit, a relationship between operating voltage / frequency-delay time is obtained in advance. Thereafter, the operation of the circuit model composed of the transistor model corresponding to the inverter chain circuit is analyzed by simulation. Then, each of the above parameters may be determined so that the relationship between the operating voltage, frequency, and delay time obtained by the simulation follows the actual measurement result of the inverter chain circuit.

  In the simulation method of the present invention, even when no current flows between the drain terminal and the source terminal of the transistor model, the value of the threshold voltage varies in the same manner as in the actual transistor. Thereby, a highly accurate simulation becomes possible. In addition, according to the operation control method for a circuit including a field effect transistor according to the present invention, the field effect is corrected by correcting a signal input to the circuit including the field effect transistor based on an accurate simulation analysis result. A circuit composed of a type transistor can be operated satisfactorily.

  First, in order to help understanding of the present invention, the relationship between carriers captured / released by the localized levels in the channel formation region of the FET will be described.

  FIG. 1A is a schematic structural diagram of a polysilicon thin film transistor (hereinafter sometimes simply referred to as TFT). For convenience of explanation, it is assumed that the TFT1 is an N-channel type. Between the gate electrode 2 and the polysilicon thin film 6, a gate insulating film 3 made of, for example, a silicon oxide film is formed. Reference numeral 4 is a source electrode, and reference numeral 5 is a drain electrode.

  There are crystal grain boundaries 7 in the polysilicon thin film 6. In the vicinity of the crystal grain boundary 7, the periodicity of the crystal is broken. For this reason, a localized level is generated between the bands. Localized levels are divided into two types based on electrical properties. In other words, it is neutral before emitting electrons, and is a positively charged donor level when emitting electrons, and is an acceptor level that is neutral before capturing electrons and negatively charged when electrons are captured. .

  FIG. 1B shows an energy band and carriers trapped in localized levels in the channel formation region in the vicinity of the crystal grain boundary 7 in the channel formation region in the TFT 1 shown in FIG. Specifically, it is a diagram schematically showing a relationship with electrons). The gate electrode 2 is in a higher potential state in the upper diagram than in the lower diagram in FIG. By setting the gate electrode 2 to a higher potential, electrons are trapped in the localized level (mainly the localized level that is the acceptor level). It should be noted that the localized level is not only the surface (more specifically, the interface between the gate insulating film and the channel formation region), but also in the depth direction (-Z in FIGS. 1A and 1B). In other words, the higher the potential of the gate electrode 2, the faster the number of electrons trapped in the localized level increases.

When electrons are captured at the localized level, the channel formation region is negatively charged by a fixed negative charge. For this reason, when the operation of the TFT 1 in a state where electrons are not captured in the localized level and the operation of the TFT 1 in a state where electrons are captured in the localized level are compared, in the latter case, the operation of the TFT 1 is compared. If the gate electrode 2 is not set to a higher potential, the same operation as the former cannot be obtained. In other words, the threshold value shifts in the positive direction qualitatively by trapping electrons in the localized levels. On the other hand, when the gate electrode 2 becomes a relatively negative potential, electrons trapped in the localized level are emitted, and qualitatively, the threshold value shifts in a relatively negative direction. This relationship is shown in FIG. FIG. 2 is a schematic diagram for explaining the relative change of the threshold due to the capture / release of electrons by the localized levels. In FIG. 2, E _C , E _V , E _i , and E _f indicate the energy level at the conduction band edge, the energy level at the valence band edge (full band edge), the intrinsic Fermi level, and the Fermi level, respectively.

  It is known that threshold shifts in TFT do not occur instantaneously, but actually change over time as long as a few seconds (for example, Characterization of Switching Transient Behaviors in Polycrystalline-Silicon Thin-Film Transistors, Hiroyuki Ikeda, Japanese Journal of Applied Physics Vol. 43, No. 2, 2004, pp. 477-484). As described above, the cause of the shift of the threshold value is a carrier that is captured / released by a localized level. This carrier capture / emission process is performed in a state where the source electrode and the drain electrode are short-circuited (hereinafter, for convenience, the short-circuited source electrode and drain electrode are simply referred to as a short-circuit electrode). It is known that it can be observed as a transient current flowing between the gate electrode and the short-circuit electrode when a rectangular wave is applied to the gate electrode (for example, Characterization of trapping states in reactive-silicon thin film transistors by deeplevel transient spectroscopy , J. FL Ayres, J. Appl. Phys. 74 (3), 1 August 1993, 1787-1792).

  The time dependence of the transient current is calculated as follows based on the theory of recombination / generation process (SRH theory) via a general mediation center. (For the theory of SRH, see, for example, Statistics of the Recombinations of Holes and Electrons, W. Shockley, WTRead, Jr., Physical Review Vol. 87 (1952) pp. 835-842, or Electron-Hole Recombination in Germanium. RNHall, Physical Review Letters (1952) pp.387 etc.).

ここで、ｑは電気素量、Ｗはゲート幅、Ｌはゲート長、l_gはグレインサイズ、ｅ_nはあるエネルギーレベルＥでの電子の放出確率、Ｄ_s（Ｅ）はエネルギーレベルＥでの結晶粒界面での単位体積あたりの局在準位密度である。電子の放出確率ｅ_nは、ＳＲＨの理論により、以下の式（４）のように表される。

ここで、σ、ν、Ｎ_cはそれぞれ電子の捕獲断面積、熱速度、伝導帯端の状態密度を示す。ｋはボルツマン定数、Ｔは絶対温度、Ｅ_Cは伝導帯端におけるエネルギーレベルである。 In FIG. 1B, the depth from the interface between the gate insulating film and the channel formation region where the localized level is filled with carriers (specifically, electrons) at a certain energy level E (in the −Z direction in the figure). Is χ (E). For convenience, the Fermi distribution function is treated as a step function (a form in which the temperature is absolutely zero degrees). At this time, in a state where the source electrode 4 and the drain electrode 5 are short-circuited, between the gate electrode 2 and the short-circuit electrode (which is constituted by the short-circuited source electrode 4 and drain electrode 5 as described above). The flowing transient current I (t) is expressed by the following equation (3). The integration range of Equation (3) is from the intrinsic Fermi level E _i to the energy level E _C at the conduction band edge.

Here, q is the elementary charge, W is the gate width, L is the gate length, l _g is the grain size, the electron emission probability in e _n is the energy level E, D _s (E) is in the energy level E It is the density of localized states per unit volume at the crystal grain interface. Emission probability e _n electrons, the theory of SRH, is represented by the following formula (4).

Here, σ, ν, and N _c indicate the electron capture cross section, the heat speed, and the density of states of the conduction band edge, respectively. k is the Boltzmann constant, T is the absolute temperature, and E _C is the energy level at the conduction band edge.

式（５）によれば、ゲート電極２と短絡電極との間に流れる過渡電流Ｉ（ｔ）は１／ｔに比例する。電荷量は電流を積分することにより得ることができる。従って、局在準位に捕獲されるキャリアの数はｌｎ（ｔ）に比例することがわかる。 It is known that the term e _n exp (−e _n t) in Equation (3) has a value in a limited energy level range at a constant temperature (for example, the Characterization of trapping states in the above-mentioned). (See Fig. 5 in -silicon thin film transistors by deep level transient spectroscopy, J. FL Ayres, J. Appl. Phys. 74 (3), 1 August 1993, 1787-1792). In the above equation (3), the value of the integrand can be treated as zero outside this limited range. The energy level of this limited range is represented by a constant value of E _0, the integration variable is converted from E to e _n, is integrated in the interval ∞ 0, it is possible to obtain the following equation (5) .

According to Equation (5), the transient current I (t) flowing between the gate electrode 2 and the short-circuit electrode is proportional to 1 / t. The amount of charge can be obtained by integrating the current. Therefore, it can be seen that the number of carriers trapped in the localized level is proportional to ln (t).

  In view of the above points, in the present invention, the capture / release of carriers is schematically reflected by the charge accumulation / discharge in the capacitance model constituting the integration circuit model. In the embodiment, a plurality of integration circuit models having different time constants are used to express a logarithmic change when carriers are captured / released. Furthermore, by changing the resistance value in the resistance model constituting the integration circuit model depending on the operating state of the transistor model, the change in the degree of carrier capture / release in the actual transistor is schematically reflected.

  The relationship between carriers captured / released by the localized levels in the channel formation region has been described above. Hereinafter, the present invention will be described based on examples with reference to the drawings.

  Example 1 relates to a simulation method of the present invention. Example 1 is a simulation method using a transistor model, and is defined to reflect the relationship between the change in potential distribution in the channel formation region and the carriers captured / released by the localized levels in the channel formation region. The threshold voltage change amount is calculated based on the value obtained by the threshold voltage calculation model. Then, the threshold voltage value is corrected based on the threshold voltage change amount, and the operation of the circuit model including the transistor model is analyzed based on the corrected threshold voltage value.

  In the first embodiment, the operation of a circuit model including a transistor model is analyzed using a simulator such as SPICE. First, the configuration of a transistor model and a threshold voltage calculation model used in the simulator will be described.

A transistor model used in Embodiment 1 will be described. FIG. 3A shows the transistor model 10 used in the first embodiment. This transistor model 10 is a transistor model including a current model. Such a transistor model is, for example, a model of a polysilicon thin film transistor, such as Unified model for short-channel poly-Si TFTs, Benjamin Iniguez, Zheng Xua, Tor A. Fjeldlya, Michael S. Shur, Solid-State Electronics 43 (1999 1821-1831, and is generally used to calculate DC characteristics and the like. For convenience of explanation, the transistor model 10 will be described as being an N-channel type. The transistor model 10 includes a current model 11 and capacitance models 12 and 13. The current model 11 is connected between the source terminal 14 and the drain terminal 16. The capacitance model 12 is connected between the gate terminal 15 and the source terminal 14 and corresponds to the gate-source capacitance C _gs . The capacitance model 13 is connected between the gate terminal 15 and the drain terminal 16 and corresponds to the gate-drain capacitance C _gd .

Next, the threshold voltage calculation model will be described. In the first embodiment, the threshold voltage calculation model is composed of a plurality of independent integration circuit models. FIG. 3B shows a plurality of integration circuit models 21 (21 _{1 to} 21 _N ) constituting the threshold voltage calculation model 20. Each integrating circuit model 21 is formed by connecting a capacitance model 22 and a resistance model 23 in series. In the first embodiment, the threshold voltage calculation model 20 is configured by the five integration circuit models 21 (that is, N = 5). However, the present invention is not limited to this. In the first embodiment, the capacitance value of the capacitance model 22 is set to the same value in each integrating circuit model 21, but the present invention is not limited to this. As will be described later, the resistance value of the resistance model 23 is individually adjusted for each integrating circuit model 21. Hereinafter, when the nth integration circuit model is specified, it is expressed as an integration circuit model 21 _n, and when it is not necessary to distinguish, it is simply expressed as an integration circuit model 21. The same applies to the capacitance model 22 and the resistance model 23. As will be described later, a voltage based on the potential difference between the gate terminal and the source terminal of the transistor model 10 (that is, the gate-source voltage) is applied to the integrating circuit model 21. The integrating circuit model 21 and the transistor model 10 described above are independent of each other. In other words, the integration circuit model 21 is not a circuit load of the transistor model 10.

  The configuration of the transistor model 10 and the threshold voltage calculation model 20 has been described above. When the operation of the circuit comprising the transistor model 10 is analyzed by a simulator such as SPICE, the threshold voltage change amount of the transistor model 10 is calculated from the value obtained by the threshold voltage calculation model 20 in the operation process of the simulator as described below. Then, the simulator may be set so that the threshold voltage is corrected and the circuit analysis including the transistor model 10 is performed based on the corrected threshold voltage value.

  First, the voltage applied to the threshold voltage calculation model 20 in the simulator operation process will be described in detail.

The voltage applied to the plurality of integration circuit models 21 constituting the threshold voltage calculation model 20 will be described. A voltage based on the value of the potential difference between the gate terminal 15 and the source terminal 14 of the transistor model 10 is applied to each of the integrating circuit models 21. Specifically, the value of the potential difference V _gs between the gate terminal 15 and source terminal 14 of transistor model, when the V _Gslim the value of the predetermined voltage, the absolute value of V _gs is equal to or less than the value of V _Gslim In some cases, a voltage having a value of V _gs is applied to each integrating circuit model, and when the absolute value of V _gs exceeds the value of V _gslim , each integrating circuit model 21 has V _gslim ² / V _gs. Apply a voltage of. The setting of the predetermined voltage value V _gslim will be described later.

The resistance value in the resistance model 23 constituting the integrating circuit model 21 will be described. In order to reflect schematically that the degree of carrier capture / release in the actual transistor changes according to the operating state of the transistor, the resistance value in the resistance model 23 constituting the integration circuit model 21 is expressed by the transistor model 10. Change depending on the operation. In the first embodiment, for the sake of simplicity, when the transistor model 10 is turned off (that is, when the voltage between the gate terminal and the source terminal is equal to or lower than the threshold value), the resistance value in the resistance model 23 _n is set to a certain constant value, for example. and R _{N_OFF,} when transistor model 10 is turned on (i.e., the gate terminal - when the voltage between the source terminals exceeds a threshold), the predetermined value R _{N_ON} that the value of resistance in the resistance model 23 _n (Here, R _{n_OFF} > _{Rn_ON} ). The constant values R _{n_OFF} and R _{n_ON} described above are individually set for each integration circuit model 21 and will be described later.

  In the foregoing, the voltage applied to the threshold voltage calculation model in the operation process of the simulator has been described.

  Next, in the operation process of the simulator, a method for calculating the threshold voltage change amount based on the value obtained by the threshold voltage calculation model 20, correction of the threshold voltage value based on the threshold voltage change amount, and the like will be described.

In the first embodiment, the threshold voltage change amount is calculated based on the charge value in the capacitance model 22 that constitutes each integration circuit model 21. Specifically, the number of integration circuit models 21 is N (where N = 5 in the first embodiment as described above), and the nth (where n = 1, 2,..., N). When the charge value in the capacitance model 22 _n constituting the integrating circuit model 21 _n is Q _n and the threshold voltage change amount is ΔV _th , ΔV _th is calculated based on the following equation (1). Here, α and β are constants, and C _OX is the value of the gate insulating film capacitance per unit area in the transistor model 10. The setting of the constants α and β will be described later.

Then, when the threshold voltage reference value is V _{th_ref} , the threshold voltage value is corrected by adding ΔV _th to V _{th_ref} . Then, based on the corrected threshold voltage value, the operation of the circuit model including the transistor model 10 may be analyzed by a simulator such as SPICE. As described above, the threshold voltage reference value V _{th_ref} can be determined based on current-voltage characteristics (V _gs -I _ds characteristics) when a DC voltage is applied to an actual transistor. The reference value V _{th_ref} corresponds to the value of the threshold voltage in a state where carriers are sufficiently trapped in the localized level in an actual transistor.

  As described above, the calculation method of the threshold voltage change amount in the operation process of the simulator, the outline of the correction of the threshold voltage value based on the threshold voltage change amount, and the circuit model including the transistor model 10 based on the corrected threshold voltage value The analysis of the operation of was explained.

When analyzing the operation of the circuit comprising the transistor model 10 by a simulator such as SPICE, the operation is usually analyzed at a predetermined time step. For this reason, in the operation analysis using an actual simulator, it is necessary to repeat the above steps as appropriate until the analysis is completed. That is, for each time step, the value of electric charge in the capacitance model 22 constituting each integrating circuit model 21 is obtained, the threshold voltage change amount is calculated based on the value, and ΔV _{th is added} to the threshold voltage reference value V _{th_ref.} To correct the threshold voltage value and repeat the process of analyzing the operation of the circuit model composed of the transistor model 10 based on the corrected threshold voltage value. In Example 1, the value of charge in the capacitance model 22 was obtained for each time step by solving the value of charge in the capacitance model 22 by discretizing the differential equation. The contents will be described below.

Here, the capacitance value in the capacitance model 22 _n constituting the _nth integration circuit model 21 _n is C _n . Further, the value of the voltage applied to the _nth integration circuit model 21 _n at a certain time t is V _n (t), and the capacitance model 22 _n constituting the _nth integration circuit model 21 _n It is assumed that the charge value is Q _n (t), and the resistance value in the resistance model 23 _n constituting the _nth integration circuit model 21 _n is R _n (t). As described above, in the first embodiment, the capacitance value of the capacitance model 22 in each integration circuit model 21 is the same, and the value of the voltage applied to each integration circuit model 21 is also the same. Value.

Here, in the nth integration circuit model 21 _n , the following expression (6) is established.

When the time step of the simulation is time Δt, the charge value Q _n (t + Δt) in the capacitance model 22 _n constituting the _nth integration circuit model 21 _n when time Δt has elapsed from time t is The following equation (2) obtained by discretizing equation (6) can be obtained.

Accordingly, the threshold change amount ΔV _{th at} time t + Δt can be calculated based on the following equation (1) ′.

In the simulation at the next time step (that is, the simulation at time t + Δt), ΔV _th obtained by the equation (1) ′ is added to the threshold voltage reference value V _{th_ref} to correct the threshold voltage value. Then, the operation of the circuit model composed of the transistor model 10 may be analyzed based on the corrected threshold voltage value.

  Also for the simulation after time t + 2Δt, the threshold voltage value is corrected by the same process as that performed for time t → time t + Δt described above, and the circuit model composed of the transistor model 10 is based on the corrected threshold voltage value. What is necessary is just to analyze the operation.

  The simulation method of Example 1 has been described above. As described above, according to the simulation method of the first embodiment, the threshold voltage change amount of the transistor model 10 is calculated from the value obtained by the threshold voltage calculation model 20, the threshold voltage is corrected, and the corrected threshold voltage is calculated. Based on the value, the analysis result of the circuit composed of the transistor model 10 can be obtained.

Next, a method of setting various parameters such as the predetermined voltage value V _gslim and the constants α and β shown in the equation (1) will be briefly described.

Various parameters such as a predetermined voltage value V _gslim , constants α and β shown in Expression (1), a capacitance value in the capacitance model 22 constituting the integration circuit model 21, and a resistance value in the resistance model 23 are as follows: Various parameters may be fitted so that the characteristics of the circuit composed of the actual FET to be simulated and the characteristics obtained by the simulation of the circuit model composed of the transistor model 10 substantially coincide.

  In Example 1, the operating voltage / frequency-delay time was measured for an actual inverter chain circuit. Then, the operation of the circuit model composed of the transistor model corresponding to the inverter chain circuit is analyzed by simulation, and the relationship between the operating voltage / frequency-delay time obtained by the simulation follows the measurement result of the actual inverter chain circuit. Thus, the above parameters were fitted.

  Hereinafter, a method for fitting various parameters will be described with reference to the drawings. First, the relationship between the operating voltage / frequency-delay time for an actual inverter chain circuit will be described.

4A shows a circuit diagram of an actual inverter chain circuit 30. FIG. The inverter chain circuit 30 is configured by connecting a plurality of FETs 31 and resistors 32 connected in series in a ladder shape (10 in the first embodiment). The gate electrode of the FET 31 in the first stage (left side in FIG. 4A) is connected to the input terminal 33. The gate electrode of the FET 31 in the second and subsequent stages is connected to the previous stage so that the voltage at the connection portion between the resistor 32 and the FET 31 in the previous stage is applied. A connection site between the tenth-stage resistor 32 and the FET 31 is connected to the output terminal 34. A voltage V _ss is applied to the terminal 35, and a voltage V _dd (where V _dd > V _ss ) is applied to the terminal 36. The voltage applied to the input terminal 33 is V _in , and the voltage output from the output terminal 34 is V _out .

FIG. 4B schematically shows the state of an input waveform and an output waveform when a square wave is input to the inverter chain circuit 30. Due to the delay of the signal transmitted through the inverter chain circuit 30, the output waveform is delayed with respect to the input waveform. The delay time of the output waveform varies depending on the operating voltage (specifically, the potential difference between the terminal 36 and the terminal 35, that is, V _dd −V _ss ), the frequency of the input waveform, and the like. FIG. 5 schematically shows the relationship between the operating voltage / frequency / delay time measured for the inverter chain circuit 30. In FIG. 5, the relationship between the frequency and the delay time is shown for _six operating voltages (V ₁ <V ₂ <... V ₅ <V ₆ ). The delay time was normalized and displayed. The upper peak voltage of the input waveform is the voltage V _dd , and the lower peak voltage is the voltage V _ss . As can be seen from FIG. 5, the delay time tends to increase as the frequency of the input waveform increases. It can also be seen that the correlation between the frequency of the input waveform and the delay time tends to increase as the operating voltage decreases.

  The relationship between the operating voltage / frequency and the delay time in the actual inverter chain circuit 30 has been described above.

In Example 1, the operation of the netlist corresponding to the inverter chain circuit 30 shown in FIG. 4A was analyzed by a simulator such as SPICE. In the operation process of the simulator, the transistor model 10 and the threshold voltage calculation model 20 are used when analyzing the operation of the portion corresponding to the FET 31 in FIG. According to the procedure described above, the threshold voltage change amount of the transistor model 10 is calculated from the value obtained by the threshold voltage calculation model 20, the threshold voltage is corrected, and the circuit including the transistor model 10 is based on the corrected threshold voltage value. Analysis is performed. Then, a predetermined voltage value V _gslim , constants α and β shown in Expression (1), and an integration circuit model 21 are configured so that the obtained analysis result and the measurement result shown in FIG. By determining various parameters such as the capacitance value in the capacitance model 22 and the resistance value in the resistance model, the fitting of the above various parameters can be completed.

  Hereinafter, specific procedures for fitting the various parameters will be described with reference to FIGS. 5 and 6.

[Step-100]
First, as a preparation for simulation, various characteristic parameters in the transistor model 10 are set by a known method. Specifically, various parameters in the transistor model 10 are reflected so as to reflect a V _gs -I _ds characteristic, a V _ds -I _ds characteristic, a capacitance-voltage characteristic (CV characteristic), and the like obtained by actually measuring the FET 31. Should be set. As described above, for the reference value V _{Th_ref} threshold voltage can be set based on V _gs -I _ds characteristics of FET 31.

[Step-110]
Next, the netlist corresponding to the inverter chain circuit 30 is operated by simulation under the condition of the first operating voltage (for example, the condition corresponding to V _dd −V _ss = V ₁ (V) shown in FIG. 5). To analyze. Specifically, a predetermined voltage value V _gslim , constants α and β shown in Expression (1), a capacitance value in the capacitance model 22 constituting the integrating circuit model 21, and a resistance value in the resistance model 23. The operation of the netlist corresponding to the inverter chain circuit 30 is analyzed in a state where appropriate initial values are given to various parameters such as.

[Step-120]
Thereafter, the analysis result (more specifically, the frequency-delay time) obtained by the simulation is compared with the result of FIG. 5, and various parameters are readjusted in consideration of the following relationship.

FIG. 6 schematically shows a comparison result between an analysis result obtained by simulation and an actual measurement value. First, the relationship between the resistance value in the resistance model 23 constituting the integrating circuit model 21 and the analysis result obtained by the simulation will be described. As described above, in the first embodiment, the resistance value in the resistance model 23 _n constituting the _nth integration circuit model 21 _n is a certain constant value R _{n —} ON when the transistor model 10 is in the ON operation, and the transistor model 10 When is turned off, a certain value R _{n — OFF} is given. When the value of the constant value R _{n_OFF} described above is changed, the degree of change in the amount of charge released from the capacitance model 22 _n in the integration circuit model 21 _n (in other words, the nth when the transistor model 10 is in the off operation). The time constant of the integration circuit model 21 _n changes. As a result, the frequency dependence of the delay time can be finely adjusted to some extent (in other words, the curve shape of the analysis result graph obtained by the simulation shown in FIG. 6 can be adjusted).

  The relationship between the constant α and the analysis result obtained by the simulation will be described. Qualitatively, when the constant α is increased, the delay time tends to be generally longer (that is, the graph of the calculated values by the simulation shown in FIG. 6 moves in the + Y direction). When the constant α is made smaller, the tendency opposite to that described above is shown.

  The relationship between the constant β and the analysis result obtained by the simulation will be described. Qualitatively, when the constant β is increased, there is a tendency that the frequency dependence of the delay time generally increases (that is, in FIG. 6, the right-side spread in the figure is further expanded). When the constant β is decreased, the tendency reverse to that described above is exhibited.

[Step-130]
Using various readjusted parameters, the operation of the netlist corresponding to the inverter chain circuit 30 is analyzed.

[Step-140]
The analysis result obtained by the simulation and the result of FIG. 5 are compared. When the difference between the two is large, [Step-120] to [Step-130] are repeated. If it is determined that the difference between the two is within the allowable range, the process proceeds to the next step [Step-150].

[Step-150]
The inverter chain circuit 30 is used under the condition of the second operating voltage (for example, the condition corresponding to V _dd −V _ss = V ₂ (V) shown in FIG. 5) using the various readjusted parameters described above. Analyzes the behavior of the netlist corresponding to.

[Step-160]
Thereafter, the analysis result obtained by the simulation is compared with the result of FIG.

[Step-170]
When the difference between the two is large under the condition of the second operating voltage, the value of the predetermined voltage value V _gslim is adjusted. As described above, in FIG. 5, the correlation between the frequency of the input waveform and the delay time tends to increase as the operating voltage decreases. In the simulation, the dependency of the correlation between the frequency of the input waveform and the delay time on the operating voltage can be adjusted by changing the value V _gslim of the predetermined voltage. After re-adjusting the predetermined voltage value V _gslim , the same steps as [Step-150] to [Step-160] are repeated again. If it is determined that the difference between the two is within the allowable range, the process proceeds to the next step [Step-180].

[Step-180]
Then, if necessary, under the condition of the third operating voltage (for example, the condition corresponding to V _dd −V _ss = V ₃ (V) shown in FIG. 5), [Step-150] to [Step- 170]. The same applies to the conditions of the fourth to sixth operating voltages (for example, the conditions corresponding to V ₄ (V), V ₅ (V), and V ₆ (V) shown in FIG. 5).

  The fitting of various parameters can be completed by the above [Step-100] to [Step-180].

  The second embodiment relates to a method for controlling the operation of a circuit comprising a field effect transistor according to the present invention.

  In the second embodiment, based on a simulation method using a transistor model for performing an operation analysis reflecting a change in threshold voltage caused by a change in potential distribution in a channel formation region of the field effect transistor, a field effect transistor is used. Control the operation of the circuit consisting of Specifically, the threshold voltage calculation defined by the simulation method so as to reflect the relationship between (1) the change in potential distribution in the channel formation region and the carriers captured / released by the localized levels in the channel formation region. A threshold voltage change amount is calculated on the basis of a value obtained by the model, (2) the threshold voltage value is corrected on the basis of the threshold voltage change amount, and (3) on the basis of the corrected threshold voltage value. The operation of the circuit model composed of the transistor model is analyzed, and (4) a signal input to the circuit composed of the field effect transistor is corrected based on the analysis result of the operation of the circuit model.

  In the second embodiment, a description will be given assuming that the circuit composed of a field effect transistor to be controlled is an edge trigger flip-flop circuit (hereinafter simply referred to as a D-type flip-flop circuit) composed of TFTs. This is not a limitation.

  First, problems of the D-type flip-flop circuit composed of TFTs will be briefly described.

  FIG. 7A is a schematic connection diagram for explaining the operation of the D-type flip-flop circuit. FIG. 7B is a schematic waveform diagram for explaining the operation of the D-type flip-flop circuit. The D-type flip-flop circuit 40 receives a data waveform from the data circuit 41 and a clock waveform from the clock circuit 42. As shown in FIG. 7B, in the D-type flip-flop circuit 40, the data input when the clock waveform rises is sampled and appears in the data output of the D-type flip-flop circuit 40. As shown in FIG. 7B, in order to correctly sample the data input waveform, the setup time and hold time need to be equal to or greater than a certain value. However, as described above, in the TFT, the threshold value changes due to the influence of the band-to-band trap. For this reason, the signal delay time in the TFT constituting the D-type flip-flop circuit 40 varies depending on the history of the applied voltage. As a result, the timings of the data waveform and the clock waveform are shifted in the D-type flip-flop circuit 40, the setup time and the hold time are insufficient, and a malfunction may occur in which desired data cannot be sampled.

  Hereinafter, a method for controlling the operation of a circuit including a field effect transistor according to the second embodiment will be described with reference to the drawings. The simulation method used in the second embodiment is the same as that described in the first embodiment. Therefore, a detailed description of the simulation method is omitted.

  FIG. 8 is a block diagram of a device 60 in which the operation control method for a circuit comprising a field effect transistor according to the present invention is used. In the device 60, the control unit 50 is formed of a computer including a storage unit and a CPU, for example. The calculation unit 51 includes a simulator such as SPICE and a control program for issuing a command to a phase adjustment circuit 44 described later according to the calculation result of the simulator. A net list corresponding to the D-type flip-flop circuit 40 is stored in the net list storage unit 52 constituted by the storage means of the control unit 50. In the model storage unit 53, the transistor model 10 described in the first embodiment, a plurality of integration circuit models 21 constituting the threshold voltage calculation model 20, the capacitance model 22 and the resistance model 23 constituting the integration circuit model 21, etc. Is stored. For convenience of explanation, it is assumed that the plurality of TFTs constituting the D-type flip-flop circuit 40 all have the same specifications, and the fitting of various parameters described in the first embodiment is completed in advance.

  The delay circuit 43 is a circuit that delays input signals from the data circuit 41 and the clock circuit 42 by, for example, one clock. The phase adjustment circuit 44 is a circuit that adjusts the phase between the signal from the data circuit 41 and the signal from the clock circuit 42 based on the command from the arithmetic unit 51 described above. A signal that has passed through the delay circuit 43 and the phase adjustment circuit 44 is input to the D-type flip-flop circuit 40.

  The signal values of the data circuit 41 and the clock circuit 42 are sequentially input to the calculation unit 51 via an input unit (not shown). The calculation unit 51 is a transistor corresponding to the D-type flip-flop circuit 40 based on the data stored in the net list storage unit 52 and the model storage unit 53 and the input data circuit 41 signal and clock circuit 42 signal. Analyzes the behavior of a circuit model consisting of models in real time. Since a signal is input to the D-type flip-flop circuit 40 via the delay circuit 43, the analysis by the simulation is performed prior to the operation of the D-type flip-flop circuit 40.

  When it is confirmed that a malfunction occurs due to the analysis result of the simulation, the arithmetic unit 51 issues a command to the phase adjustment circuit 44 and corrects the signal input to the D-type flip-flop circuit 40. Specifically, if a malfunction due to the simulation analysis result is caused by an insufficient setup time, a command is issued to the phase adjustment circuit 44 so as to lengthen the setup time. Similarly, if a malfunction due to simulation analysis occurs due to an insufficient hold time, a command is issued to the phase adjustment circuit 44 to increase the hold time. As a result, the D-type flip-flop circuit 40 can be operated at an appropriate timing.

  As mentioned above, although this invention was demonstrated based on the Example of invention, this invention is not limited to these, It can change suitably.

  In the embodiment, one type of transistor model is used, but the present invention is not limited to this. For example, when analyzing a circuit composed of an N-channel FET and a P-channel FET, an N-channel FET transistor model / threshold voltage calculation model and a P-channel FET transistor are analyzed. A model / threshold voltage calculation model may be prepared individually.

  In the embodiment, a software simulator such as SPICE is used as a simulator, but the present invention is not limited to this. The simulator may be implemented in hardware. Further, in FIG. 8, the control unit 50 and the D-type flip-flop circuit 40 that is the control target are illustrated in a separated form, but the control target circuit and the control unit are configured integrally. You can also. For example, in a liquid crystal display or the like, a glass substrate having a TFT formed on the surface is used. In this case, a mode in which a TFT, a driving circuit for driving the TFT, and a simulator for the driving circuit are both formed on a glass substrate or the like can be employed.

FIG. 1A is a schematic structural diagram of a polysilicon thin film transistor. FIG. 1B shows the carrier trapped in the energy band and the localized level in the channel formation region in the polysilicon thin film transistor shown in FIG. Specifically, it is a diagram schematically showing a relationship with electrons). FIG. 2 is a schematic diagram for explaining the relative change of the threshold due to the capture / release of electrons by the localized levels. FIG. 3A shows a transistor model used in the embodiment. FIG. 3B shows a plurality of integration circuit models constituting the threshold voltage calculation model. FIG. 4A shows a circuit diagram of an actual inverter chain circuit. FIG. 4B schematically shows an input waveform and an output waveform when a square wave is input to the inverter chain circuit. FIG. 5 shows the relationship between the operating voltage / frequency / delay time measured for the inverter chain circuit. FIG. 6 schematically shows a comparison result between an analysis result obtained by simulation and an actual measurement value. FIG. 7A is a schematic connection diagram for explaining the operation of the D-type flip-flop circuit. FIG. 7B is a schematic waveform diagram for explaining the operation of the D-type flip-flop circuit. FIG. 8 is a block diagram of an apparatus in which the operation control method of the present invention is used. FIG. 9 is a circuit diagram showing a state in which a voltage is applied to the gate by short-circuiting between the drain electrode and the source electrode of the transistor.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... TFT, 2 ... Gate electrode, 3 ... Gate insulating film, 4 ... Source electrode, 5 ... Drain electrode, 6 ... Polysilicon thin film, 7 ... Grain boundary DESCRIPTION OF SYMBOLS 10 ... Transistor model, 11 ... Current model, 12 ... Capacitance model, 13 ... Capacitance model, 14 ... Source terminal, 15 ... Gate terminal, 16 ... Drain terminal, 20... Threshold voltage calculation model, 21, 21 _{1 to} 21 _N ... Integration circuit model, 22, 22 _{1 to} 22 _N ... Capacitance model, 23, 23 ₁ to 23 _N ... Resistance model, 30 ... Inverter chain circuit, 31 ... FET, 32 ... Resistance, 33 ... Input terminal, 34 ... Output terminal, 35 ... Terminal, 36 ... Terminal, 40 ... D-type flip-flop circuit, 41 ... Data circuit 42 ... Clock circuit, 43 ... Delay circuit, 44 ... Phase adjustment circuit, 50 ... Control unit, 51 ... Calculation unit, 52 ... Netlist storage unit, 53 ... Model Storage unit, 60... Device

Claims (7)

A simulation method using a transistor model for performing an operation analysis reflecting a change in threshold voltage caused by a change in potential distribution in a channel formation region of a field effect transistor,
(1) Based on the value obtained by the threshold voltage calculation model defined to reflect the relationship between the potential distribution change in the channel formation region and the carriers captured / released by the localized levels in the channel formation region. Calculate the threshold voltage change amount,
(2) correcting the value of the threshold voltage based on the threshold voltage variation,
(3) analyzing the operation of the circuit model consisting of the transistor model based on the value of the corrected the threshold voltage, it consists,
The threshold voltage calculation model is constituted by one independent integration circuit model or a plurality of independent integration circuit models,
When the value of the potential difference between the gate terminal and the source terminal of the transistor model is V _gs and the value of the predetermined voltage is V _gslim (where V _gslim > 0),
When the absolute value of V _gs is less than or equal to the value of V _gslim , a voltage having a value of V _gs is applied to each of the integration circuit models ,
When the absolute value of V _gs exceeds the value of V _gslim , a voltage having a value of V _gslim ² / V _gs is applied to each of the integration circuit models .
Simulation method.   The simulation method according to claim 1, wherein the integration circuit model includes a capacitance model and a resistance model connected in series.   The simulation method according to claim 2, wherein a resistance value in the resistance model constituting the integration circuit model is changed depending on an operation of the transistor model.   The simulation method according to claim 2 or 3, wherein the threshold voltage change amount is calculated based on a charge value in the capacitance model constituting the integration circuit model. (A) A reference value of the threshold voltage is V _{th # ref} ,
(B) The number of the integration circuit models is N, the charge value in the capacitance model constituting the nth (where n = 1, 2,..., N) integration circuit model is Q _n , 5. The threshold voltage value is corrected by calculating ΔV _{th based} on the following equation (1) when ΔV _th is the threshold voltage change amount , and then adding ΔV _th to V _{th # ref.} The simulation method described in 1.

Here, α and β are constants, and C _OX is the value of the gate insulating film capacitance per unit area in the transistor model. (A) The capacitance value in the capacitance model constituting the nth integration circuit model is represented by C _n ,
(B) The value of the voltage applied to the nth integration circuit model at a certain time t is V _n (t), and the charge in the capacitance model constituting the nth integration circuit model When the value is Q _n (t) and the resistance value in the resistance model constituting the n th integration circuit model is R _n (t), the n th time when the time Δt has elapsed from time t. The charge value Q _n (t + Δt) in the capacitance model constituting the integration circuit model is calculated based on the following equation (2), and the threshold voltage change amount ΔV _th is further calculated by the following equation ( The simulation method according to claim 5, wherein the calculation is performed based on 1) ′.

  Operation control of a circuit composed of field-effect transistors based on a simulation method using a transistor model to reflect changes in threshold voltage caused by changes in potential distribution in the channel formation region of field-effect transistors A method,
  By the simulation method,
  (1) Based on the value obtained by the threshold voltage calculation model defined to reflect the relationship between the potential distribution change in the channel formation region and the carriers captured / released by the localized levels in the channel formation region. Calculate the threshold voltage change amount,
  (2) correcting the value of the threshold voltage based on the threshold voltage change amount;
  (3) Analyzing the operation of the circuit model comprising the transistor model based on the corrected value of the threshold voltage,
  (4) based on the analysis result of the operation of the circuit model, correcting a signal input to a circuit composed of a field effect transistor;
  The threshold voltage calculation model is constituted by one independent integration circuit model or a plurality of independent integration circuit models,
  The value of the potential difference between the gate terminal and the source terminal of the transistor model is expressed as V _gs , The value of the predetermined voltage is V _gslim (However, V _gslim > 0)
  V _gs The absolute value of V is V _gslim Each of the integration circuit models, V _gs Apply a voltage of
  V _gs The absolute value of V is V _gslim When the value exceeds the value of V, _gslim ² / V _gs Applying a voltage of
  An operation control method for a circuit comprising a field effect transistor.

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