JP5075168B2 - Power semiconductor device and method for manufacturing power semiconductor device - Google Patents

Power semiconductor device and method for manufacturing power semiconductor device Download PDF

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Publication number
JP5075168B2
JP5075168B2 JP2009163786A JP2009163786A JP5075168B2 JP 5075168 B2 JP5075168 B2 JP 5075168B2 JP 2009163786 A JP2009163786 A JP 2009163786A JP 2009163786 A JP2009163786 A JP 2009163786A JP 5075168 B2 JP5075168 B2 JP 5075168B2
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metal
source electrode
semiconductor device
bonding
power semiconductor
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JP2011018841A (en
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修平 中田
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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Description

本発明は、電力用半導体スイッチング素子及びダイオードからなる電力用半導体装置に関し、とくに短絡事故時に発生する大電流に対する耐量（短絡耐量）を向上させるための構造およびその製造方法に関するものである。   The present invention relates to a power semiconductor device including a power semiconductor switching element and a diode, and more particularly to a structure for improving a resistance against a large current (short-circuit resistance) generated in a short-circuit accident and a manufacturing method thereof.

インバーターなどのパワーエレクトロニクス機器の省エネのためには、これらの機器に使用されるスイッチング素子（ＩＧＢＴ、ＭＯＳＦＥＴ等）での電力損失を低減する必要がある。電力損失は、素子のいわゆるＯＮ抵抗により決定され、ＯＮ抵抗を低減するためにＳｉＣなどの新しい半導体材料を用いる開発が進められている。一方、事故時（負荷短絡時）に素子に流れる電流値は、ＯＮ抵抗値に反比例して大きくなるので、ＯＮ抵抗値の小さい素子ほど、自己発熱により破損しやすくなる（短絡時の耐量の低下）。つまり、トレードオフの関係にある損失低減と短絡時の耐量向上を両立させることが、低ＯＮ抵抗素子の実用化に求められている技術課題である。   In order to save power electronics devices such as inverters, it is necessary to reduce power loss in switching elements (IGBT, MOSFET, etc.) used in these devices. The power loss is determined by the so-called ON resistance of the device, and development using a new semiconductor material such as SiC is underway to reduce the ON resistance. On the other hand, the value of the current that flows through the element at the time of an accident (when the load is short-circuited) increases in inverse proportion to the ON resistance value. Therefore, the smaller the ON resistance value, the easier it is to break due to self-heating (decrease in withstand capability during short circuit) ). That is, it is a technical problem required for the practical use of a low ON resistance element to achieve both a reduction in loss that is in a trade-off relationship and an improvement in withstand capability at the time of a short circuit.

例えば、ＳｉＣのようなワイドバンドギャップ半導体の場合、Ｓｉと異なり、温度上昇による半導体自体の性能劣化はほとんどなく、高温に対しての耐性は高い。しかし、回路との接続には金属電極が使用され、例えば、金属電極にアルミニウムを用いる場合、半導体と金属電極の境界面の温度がアルミニウムの融点（６６０℃）を超えると、金属電極の溶融が起こり、電極の信頼性に重大な問題を生じる。従って、ワイドバンドギャップ半導体を用いる場合には、Ｓｉを用いる場合とは異なる放熱設計や損失制御を行う必要があり、金属電極と半導体の境界面がある一定の温度以下になるように、負荷短絡時の発生損失と放熱条件を設定しなければならない。   For example, in the case of a wide band gap semiconductor such as SiC, unlike Si, there is almost no performance degradation of the semiconductor itself due to temperature rise, and resistance to high temperatures is high. However, a metal electrode is used for connection to the circuit. For example, when aluminum is used for the metal electrode, if the temperature at the interface between the semiconductor and the metal electrode exceeds the melting point of aluminum (660 ° C.), the metal electrode melts. Occurs and causes significant problems in electrode reliability. Therefore, when using a wide bandgap semiconductor, it is necessary to perform heat dissipation design and loss control different from the case of using Si, and load short-circuiting so that the interface between the metal electrode and the semiconductor is below a certain temperature. Loss of time and heat dissipation conditions must be set.

そこで、ワイドバンドギャップ半導体よりなる半導体素子部の表側の面（ソース電極面に相当）に５０μｍ以上の厚さの金属電極を形成し、放熱効果を高めて短絡時の温度上昇を抑制する半導体装置が提案されている（例えば、特許文献１参照）。   Therefore, a semiconductor device in which a metal electrode having a thickness of 50 μm or more is formed on the front side surface (corresponding to the source electrode surface) of the semiconductor element portion made of a wide band gap semiconductor, thereby enhancing the heat dissipation effect and suppressing the temperature rise during short circuit Has been proposed (see, for example, Patent Document 1).

特開２００６−３１９２１３号公報（段落００３２、図３）JP 2006-319213 A (paragraph 0032, FIG. 3)

しかしながら、半導体素子本体（半導体材料）と金属電極（金属）とでは、線膨張率が異なるので、金属電極全体が厚くなっていると、使用時のヒートサイクルのたびに金属電極と半導体素子本体との間に発生する応力によって金属電極の剥離が発生し、長期的な信頼性が低下するおそれがあった。   However, since the linear expansion coefficient differs between the semiconductor element body (semiconductor material) and the metal electrode (metal), if the entire metal electrode is thick, the metal electrode and the semiconductor element body each time the heat cycle is used. There was a possibility that peeling of the metal electrode occurred due to the stress generated during this period, and long-term reliability was lowered.

本発明は、上記のような課題を解決するためになされたもので、信頼性が高く、損失低減と短絡時の耐量向上を両立させた電力用半導体装置を得ることを目的とする。   The present invention has been made to solve the above-described problems, and an object of the present invention is to obtain a power semiconductor device that has high reliability and achieves both a reduction in loss and an improvement in withstand capability during short-circuiting.

本発明の電力用半導体装置は、絶縁性の基板と、前記絶縁性の基板の主面に形成された複数の配線と、前記複数の配線のうちの第１の配線に接合されたワイドバンドギャップ半導体材料を用いた半導体素子と、前記半導体素子の前記第１の配線との接合面と反対側にアルミニウムを用いて形成されたソース電極の一部と、前記複数の配線のうち第２の配線とを電気的に接続するワイヤと、を備え、前記ソース電極には、複数の金属塊が分散して接合され、前記複数の金属塊のそれぞれは、前記ソース電極との接合面以外が絶縁物で覆われていることを特徴とする。 A power semiconductor device according to the present invention includes an insulating substrate, a plurality of wirings formed on a main surface of the insulating substrate, and a wide band gap bonded to a first wiring of the plurality of wirings. A part of a source electrode formed using aluminum on a side opposite to a bonding surface between a semiconductor element using a semiconductor material and the first wiring of the semiconductor element, and a second wiring among the plurality of wirings A plurality of metal lumps are dispersed and joined to the source electrode, and each of the plurality of metal lumps is an insulator except for a joint surface with the source electrode. It is covered with.

本発明の電力用半導体装置の製造方法は、絶縁性の基板の主面に複数の配線を形成し、前記複数の配線のうちの第１の配線にワイドバンドギャップ半導体材料を用いた半導体素子を接合し、ボンディング用ワイヤを前記半導体素子のアルミニウムを用いて形成されたソース電極の一部に第１ボンドによりボンディングし、前記複数の配線のうちの第２の配線に第２ボンドによりボンディングすることにより前記ソース電極と前記第２の配線とを電気的に接続し、前記ソース電極においてそれぞれ異なる位置に、前記ボンディング用ワイヤを第１ボンドによりボンディングし、当該ボンディングにより形成された圧縮根を残して切り離すことにより、前記ソース電極上に複数の金属塊を形成する、ことを特徴とする。 A method for manufacturing a power semiconductor device according to the present invention includes: forming a plurality of wirings on a main surface of an insulating substrate; and a semiconductor element using a wide band gap semiconductor material for a first wiring among the plurality of wirings. Bonding, bonding a bonding wire to a part of a source electrode formed using aluminum of the semiconductor element by a first bond, and bonding to a second wiring of the plurality of wirings by a second bond. Electrically connecting the source electrode and the second wiring, bonding the bonding wire by a first bond at different positions in the source electrode, leaving a compression root formed by the bonding A plurality of metal lumps are formed on the source electrode by separating them.

本発明の電力用半導体装置および電力用半導体装置の製造方法によれば、半導体素子のソース電極の表面に、複数の金属塊を接合させたので、負荷短絡時の熱を金属塊が吸収して温度上昇を抑制するとともに、金属塊がソース電極との接合面以外が絶縁物で覆われているので、ヒートサイクルを受けても信頼性が高く、損失低減と短絡時の耐量向上を両立させた電力用半導体装置を得ることができる。   According to the power semiconductor device and the method for manufacturing the power semiconductor device of the present invention, a plurality of metal lumps are bonded to the surface of the source electrode of the semiconductor element. In addition to suppressing the temperature rise, the metal lump is covered with an insulator other than the joint surface with the source electrode, so it is highly reliable even when subjected to a heat cycle, and both reduction in loss and improvement in resistance during short-circuiting are achieved. A power semiconductor device can be obtained.

本発明の実施の形態１にかかる電力用半導体装置の半導体素子の構成を示す図である。It is a figure which shows the structure of the semiconductor element of the power semiconductor device concerning Embodiment 1 of this invention. 本発明の実施の形態１にかかる電力用半導体装置の構成を示す図である。It is a figure which shows the structure of the semiconductor device for electric power concerning Embodiment 1 of this invention. 本発明の実施の形態２にかかる電力用半導体装置の構成を示す図である。It is a figure which shows the structure of the semiconductor device for electric power concerning Embodiment 2 of this invention. 本発明の実施の形態２にかかる電力用半導体装置における温度上昇低減効果を示す図である。It is a figure which shows the temperature rise reduction effect in the semiconductor device for electric power concerning Embodiment 2 of this invention. 本発明の実施の形態２にかかる電力用半導体装置の構成を示す図である。It is a figure which shows the structure of the semiconductor device for electric power concerning Embodiment 2 of this invention. 本発明の実施の形態２にかかる電力用半導体装置における構成を最適化するための試験データを示す図である。It is a figure which shows the test data for optimizing the structure in the power semiconductor device concerning Embodiment 2 of this invention. 本発明の実施の形態２の変形例にかかる電力用半導体装置の構成を示す図である。It is a figure which shows the structure of the semiconductor device for electric power concerning the modification of Embodiment 2 of this invention.

実施の形態１．
本発明の実施の形態１にかかる電力用半導体装置について、図に基づいて説明する。図１と図２は、本発明にかかる実施の形態１にかかる電力用半導体装置を説明するためのもので、図１は、電力用半導体装置のうち、半導体素子部分の平面構成を示す図であり、図２は、電力用半導体装置を半導体素子のソース電極部分との関連で説明するため平面図と断面図である。 Embodiment 1 FIG.
A power semiconductor device according to a first embodiment of the present invention will be described with reference to the drawings. 1 and 2 are diagrams for explaining a power semiconductor device according to a first embodiment of the present invention. FIG. 1 is a diagram showing a planar configuration of a semiconductor element portion of the power semiconductor device. FIG. 2 is a plan view and a cross-sectional view for explaining the power semiconductor device in relation to the source electrode portion of the semiconductor element.

本実施の形態１にかかる電力用半導体装置に用いる半導体素子は、炭化ケイ素（ＳｉＣ）や窒化ガリウム（ＧａＮ）を用いたワイドバンドギャップ半導体であり、種類としては、ＩＧＢＴ（Insulated Gate Bipolar Transistor）、またはＭＯＳＦＥＴ（Metal Oxide Semiconductor Field-Effect-Transistor）のようないわゆるスイッチング素子である。半導体素子３の表側の面には、図１に示すように、図における上端中央部には、外部の制御回路（図示せず。）からゲート電圧が印加されるゲートパッド3GPが形成されている。又、ＭＯＳＦＥＴのセルの集合体領域であるセル領域内に、ＭＯＳＦＥＴの各セルのソース電極3Sが形成されている。そして、ソース電極3Sの周囲を全体的に取り囲むゲートフィンガー電極3GFが、ゲートパッド3GPと構造的に繋がった状態で、半導体素子３の外周部に沿って形成されている。 The semiconductor element used in the power semiconductor device according to the first embodiment is a wide bandgap semiconductor using silicon carbide (SiC) or gallium nitride (GaN), and the type is IGBT (Insulated Gate Bipolar Transistor), Or it is what is called a switching element like MOSFET (Metal Oxide Semiconductor Field-Effect-Transistor). The front surface of the semiconductor element 3, as shown in FIG. 1, the upper central portion of the figure, an external control circuit (not shown.) The gate pad 3G P gate voltage is applied from the is formed Yes. In addition, a source electrode 3 S of each cell of the MOSFET is formed in a cell region which is an aggregate region of the MOSFET cell. The gate finger electrode 3 GF surrounding the source electrode 3 S Overall is in a state that is connected to the gate pad 3G P structurally, it is formed along the outer periphery of the semiconductor element 3.

図２（ａ）は、本発明の特徴を説明するために電力用半導体装置のソース電極部分を抽出して簡略化した図である。なお、半導体素子全体の構成を示す図１においてはソース電極を3Sと表示しているが、ソース電極3Sは、半導体素子３における発熱を伴う代表的な面であるので、以降、半導体素子のうちの他の部分の記載を省略し、ソース電極（の主面）を３ｆと表記する。図２（ｂ）は図２（ａ）のIIb−IIb線で切断した断面図である。図において、電力用半導体装置は、絶縁性のパッケージ基板１と、基板１の主面１ｆの異なる位置に形成された複数の配線２と、複数の配線２のうちの第１の配線２ａに接合された半導体素子３と、半導体素子３の第１の配線２ａとの接合面と反対側になるソース電極３ｆの一部と、複数の配線２のうちの（第１の配線２ａと異なる）第２の配線２ｂとを電気的に接続するため、ボンディング用ワイヤ（図示せず）をソース電極３ｆの一部に第１ボンドによりボンディングし、第２の配線２ｂに第２ボンドによりボンディングすることにより形成されたワイヤ４と、を備え、半導体素子のソース電極３ｆには、複数の金属塊５ｂが分散して接合されている。 FIG. 2A is a simplified view of the source electrode portion of the power semiconductor device extracted in order to explain the characteristics of the present invention. In FIG. 1 showing the configuration of the entire semiconductor element, the source electrode is indicated as 3 S. However, since the source electrode 3 S is a representative surface with heat generation in the semiconductor element 3, the semiconductor element is hereinafter referred to. The description of the other part is omitted, and the source electrode (the main surface thereof) is denoted as 3f. FIG. 2B is a cross-sectional view taken along the line IIb-IIb in FIG. In the figure, a power semiconductor device is bonded to an insulating package substrate 1, a plurality of wirings 2 formed at different positions on the main surface 1 f of the substrate 1, and a first wiring 2 a among the plurality of wirings 2. A part of the source electrode 3f on the opposite side to the bonding surface of the semiconductor element 3 and the first wiring 2a of the semiconductor element 3, and the second of the plurality of wirings 2 (different from the first wiring 2a) In order to electrically connect the second wiring 2b, a bonding wire (not shown) is bonded to a part of the source electrode 3f by a first bond, and is bonded to the second wiring 2b by a second bond. And a plurality of metal masses 5b are dispersed and bonded to the source electrode 3f of the semiconductor element.

なお、ソース電極３ｆの表面には、接続を良くするための図示しない厚さ数μｍの薄いアルミニウムの下地が形成されており、上述したワイヤ４や金属塊５ｂは、アルミニウムの下地を介してソース電極３ｆに接続されており、各金属塊５ｂは同電位となっている。なお、厚み数μｍ程度の金属の下地は、特許文献１に示すような厚い金属電極と異なり、ヒートサイクル時に応力を及ぼすものではないので、以降下地部分も半導体材料とみなし、ソース電極３ｆ上にワイヤ４や金属塊５ｂが接合されているとして説明する。   A thin aluminum base (not shown) having a thickness of several μm (not shown) for improving the connection is formed on the surface of the source electrode 3f. The wire 4 and the metal block 5b described above are connected to the source via the aluminum base. It is connected to the electrode 3f, and each metal block 5b has the same potential. Note that, unlike a thick metal electrode as shown in Patent Document 1, a metal base having a thickness of about several μm does not exert stress during a heat cycle, and hence the base part is regarded as a semiconductor material and is placed on the source electrode 3f. A description will be given assuming that the wire 4 and the metal block 5b are joined.

そして、複数の金属塊５ｂのそれぞれは、ソース電極３ｆにおいてそれぞれ異なる位置に、ワイヤ４を形成する時と同様にボンディング用ワイヤを第１ボンドによりボンディングし、当該ボンディングにより形成された圧縮根を残してボンディングワイヤを切り離すことにより形成する。最終的に、ソース電極３ｆや配線２ｂ等を含め、半導体装置の表面は絶縁物７で覆われており、金属塊５ｂもソース電極３ｆとの接合面以外は絶縁物７で覆われている。図では、ソース電極３ｆ部分を覆う絶縁物７の一部分のみ示しているが、実際には電力用半導体装置のほぼ全面が絶縁物７により覆われている。なお、金属塊５ｂのソース電極３ｆとの接合面以外は、全て「もの」としての絶縁物７により覆われている必要はなく、空隙（真空または電気的に不活性なガス雰囲気）であってもよく、その場合も絶縁物で覆われているとみなして説明する。   Then, each of the plurality of metal blocks 5b is bonded to the bonding wire by the first bond at the different positions in the source electrode 3f in the same manner as when the wire 4 is formed, and the compressed root formed by the bonding is left. Then, it is formed by cutting the bonding wire. Finally, the surface of the semiconductor device including the source electrode 3f and the wiring 2b is covered with the insulator 7, and the metal block 5b is also covered with the insulator 7 except for the joint surface with the source electrode 3f. In the figure, only a part of the insulator 7 covering the source electrode 3 f is shown, but in practice, almost the entire surface of the power semiconductor device is covered with the insulator 7. It should be noted that everything except the joint surface of the metal block 5b with the source electrode 3f does not need to be covered with the insulator 7 as "thing", and is a void (vacuum or electrically inert gas atmosphere). In this case, it is assumed that it is covered with an insulator.

ボンディングワイヤとしては、直径３００μｍのアルミニウム（Ａｌ）を用い、バードピークボンディングにより接続している。これにより、金属塊５ｂやワイヤ４のソース電極３ｆとの接合面を広くとることができるとともに、ボンディングワイヤの切断を連続的に行うことができるので、多数の金属塊５ｂを容易に形成することができる。   As a bonding wire, aluminum (Al) having a diameter of 300 μm is used and connected by bird peak bonding. As a result, it is possible to widen the joining surface of the metal lump 5b and the source electrode 3f of the wire 4 and to continuously cut the bonding wire, so that a large number of metal lumps 5b can be easily formed. Can do.

なお、本実施の形態１では、直径３００μｍのアルミニウムを用いていたが、直径３００μｍ以外のアルミニウムを用いたとしても同様の効果が期待できる。また、ワイヤ以外の材料を用いたボンディング（例えばリボンボンディング）を用いても同様の効果を得ることができる。また、ボンディングワイヤに金（Ａｕ）を用いてもよく、その場合は第１ボンドを接合強度の高いネイルヘッドボンディングで行ってもよい。   In Embodiment 1, aluminum having a diameter of 300 μm is used, but the same effect can be expected even if aluminum having a diameter other than 300 μm is used. The same effect can be obtained by using bonding (for example, ribbon bonding) using a material other than a wire. Further, gold (Au) may be used for the bonding wire, and in that case, the first bond may be performed by nail head bonding with high bonding strength.

次に動作について説明する。
通常使用時の動作については、従来の電力用半導体装置と同様なので、ここでは、負荷短絡（異常）が発生した時の動作について説明する。負荷短絡が発生した場合、半導体素子３には電源電圧が加わった状態で負荷が短絡されるので、半導体素子３には素子抵抗及び負荷抵抗（この場合は殆ど０になる）及び電源電圧で決まる電流が流れることになる。その電流値は、通常電流値より１桁以上大きく、その結果、素子の内部抵抗と電流値で半導体素子３の内部（主にソース電極）で発熱が発生し、素子温度が上昇する。素子温度が上昇して金属電極の溶融が起こると、電力用半導体装置が破損する。 Next, the operation will be described.
Since the operation during normal use is the same as that of a conventional power semiconductor device, the operation when a load short circuit (abnormality) occurs will be described here. When a load short-circuit occurs, the load is short-circuited with the power supply voltage applied to the semiconductor element 3, so that the semiconductor element 3 is determined by the element resistance, the load resistance (in this case, almost zero) and the power supply voltage. Current will flow. The current value is larger by one digit or more than the normal current value. As a result, heat is generated inside the semiconductor element 3 (mainly the source electrode) due to the internal resistance and current value of the element, and the element temperature rises. When the element temperature rises and the metal electrode melts, the power semiconductor device is damaged.

ここで、短絡が長期間にわたって継続する場合、発生した熱を継続して放出する必要があり、特許文献１に示されるような外部との効率的な熱伝導経路を形成する必要がある。しかし、通常のインバーター制御システムにおいては、外部制御回路系に保護回路を設け、負荷電流値が一定電流以上になるとゲート電圧を低減してソース電極に流れる電流値を抑制し、発生熱量を制限するようにしている。したがって、ＩＧＢＴやＭＯＳＦＥＴのような電力用半導体装置は、負荷短絡時に保護回路が動作するまでの短い期間において、高電圧、大電流のストレス状態に耐えられるようにすればよい。電力用半導体装置に求められる負荷短絡耐量の規格としては、素子の絶対定格の２／３の電源電圧において、通常オン状態のゲート電圧が印加されたときに、１０μ秒以内に素子が破壊しないこと、となっている。   Here, when the short circuit continues for a long period of time, it is necessary to continuously release the generated heat, and it is necessary to form an efficient heat conduction path with the outside as disclosed in Patent Document 1. However, in a normal inverter control system, a protection circuit is provided in the external control circuit system, and when the load current value exceeds a certain value, the gate voltage is reduced to suppress the current value flowing through the source electrode, thereby limiting the amount of heat generated. I am doing so. Therefore, a power semiconductor device such as an IGBT or a MOSFET may be able to withstand a high voltage and large current stress state in a short period until the protection circuit operates when a load is short-circuited. The standard for the load short-circuit withstand capability required for power semiconductor devices is that the device does not break within 10 μs when a normally on-state gate voltage is applied at a power supply voltage of 2/3 of the absolute rating of the device. It has become.

そこで、本発明の実施の形態１にかかる電力用半導体装置では、半導体素子３のソース電極３ｆ上に配線２ａとの電気接続に用いるワイヤ４以外に、複数の金属塊５ｂを設け、短絡が始まってから保護回路が動作するまでの１０μＳの間の発熱を複数の金属塊５ｂ（の熱容量により）に吸収させて、半導体素子３の温度上昇を抑制する。金属塊５ｂは、ワイヤボンディングに通常用いられるアルミニウムないしは金などの熱伝導度が良好で熱容量も大きい金属体で形成されているので、発熱部であるソース電極３ｆの直上に（短期間機能する）ヒートシンクを構成していることと同等の状況を形成できる。このように発熱部の近傍に保護回路が動作するまで実質的にヒートシンクとして機能する金属塊５ｂを分散して配置したことにより短絡による発熱量が大きくなったとしても温度上昇を低減することが可能である。つまり、通常のシステムでは１０μｓ程度で保護回路が動作することになるので、このように限られた時間内（瞬間的な）の温度上昇を抑制することにより、電力用半導体装置の破損を防止することができる。   Therefore, in the power semiconductor device according to the first embodiment of the present invention, a plurality of metal blocks 5b are provided on the source electrode 3f of the semiconductor element 3 in addition to the wire 4 used for electrical connection with the wiring 2a, and a short circuit starts. The heat generated for 10 μS from when the protection circuit operates until the plurality of metal blocks 5b (due to the heat capacity) is absorbed, and the temperature rise of the semiconductor element 3 is suppressed. Since the metal block 5b is formed of a metal body having a good thermal conductivity and a large heat capacity such as aluminum or gold, which is usually used for wire bonding, the metal block 5b is directly above the source electrode 3f which is a heat generating part (functions for a short period of time). A situation equivalent to configuring a heat sink can be formed. As described above, the metal mass 5b that substantially functions as a heat sink is dispersedly arranged in the vicinity of the heat generating portion until the protection circuit operates, so that the temperature rise can be reduced even if the amount of heat generated by the short circuit increases. It is. In other words, since the protection circuit operates in about 10 μs in a normal system, the power semiconductor device is prevented from being damaged by suppressing the temperature rise within a limited time (instantaneous) in this way. be able to.

しかも、それぞれの金属塊５ｂはアイランド状に配置されており、ソース電極３ｆとの接合面以外は絶縁物７（空隙も含めて）で覆われている。ここで、金属塊の表面を覆っている絶縁物７は、もともとソース電極３ｆ上を全面的に覆った場合でも、ヒートサークルのたびにソース電極３ｆに対して応力を与えてしまわないような性質を有している。したがって、複数の金属塊５ｂのそれぞれは、ヒートサイクルの際、ソース電極３ｆ全体の面積に対してソース電極３ｆに対して応力をかけることはない。しかも、各金属塊５ｂとソース電極３ｆとの接合面は小さいので、ヒートサイクル時にそれぞれの金属塊５ｂとソース電極３ｆとの接合面間にかかる応力は小さく、接合面の剥離を誘発することはない。   In addition, each metal block 5b is arranged in an island shape, and is covered with an insulator 7 (including a gap) except for the joint surface with the source electrode 3f. Here, the insulator 7 covering the surface of the metal block does not give stress to the source electrode 3f at every heat circle even when the entire surface of the source electrode 3f is originally covered. have. Therefore, each of the plurality of metal blocks 5b does not apply stress to the source electrode 3f with respect to the entire area of the source electrode 3f during the heat cycle. In addition, since the joining surface between each metal lump 5b and the source electrode 3f is small, the stress applied between the joining surfaces between each metal lump 5b and the source electrode 3f during the heat cycle is small, and the peeling of the joining surface is not induced. Absent.

したがって、ヒートサイクル時に線膨張率の差により歪が生ずる領域が、それぞれの金属塊５ｂの接合面というごく小さな領域に限定されるとともに、金属塊５ｂの膨張収縮等による機械的変形も金属塊５ｂの周りの絶縁物７により吸収される。これは、各金属塊５ｂに、それぞれヒートサイクル時のストレスに対する遊びが設けられていることになり、各金属塊５ｂのそれぞれにかかった力が他の金属塊５ｂに影響することがない。そのため、使用時のヒートサイクルのたびに接合面にかかる応力が無視できる程度に小さくなり、接合面の剥離の発生が抑制され、長期的な信頼性が向上する。   Therefore, the region where distortion occurs due to the difference in linear expansion coefficient during the heat cycle is limited to a very small region called the joint surface of each metal lump 5b, and mechanical deformation due to expansion / contraction of the metal lump 5b is also caused by the metal lump 5b. It is absorbed by the insulator 7 around. This means that each metal lump 5b is provided with play against stress during the heat cycle, and the force applied to each metal lump 5b does not affect the other metal lump 5b. Therefore, the stress applied to the joint surface is reduced to a level that can be ignored at each heat cycle during use, the occurrence of peeling of the joint surface is suppressed, and long-term reliability is improved.

また、半導体素子３と配線２ｂとを電気接続するワイヤ４を形成するときに用いたワイヤボンディング工程の一部を金属塊５ｂの形成に応用したので、複雑な製造工程を追加する必要がなく、電気接続配線を形成する際の連続した工程の中で金属塊５ｂを形成することができる。つまり、スループットが向上し、製造コストや製造時間を大きく増大させることなく、負荷短絡耐量を向上させることができる。   In addition, since a part of the wire bonding process used when forming the wire 4 that electrically connects the semiconductor element 3 and the wiring 2b is applied to the formation of the metal lump 5b, there is no need to add a complicated manufacturing process, The metal block 5b can be formed in a continuous process when forming the electrical connection wiring. That is, the throughput is improved, and the load short-circuit tolerance can be improved without greatly increasing the manufacturing cost and the manufacturing time.

一方、金属塊５ｂに配線との電気接続を担わせようと、例えば、特開２００５−５０９６１号公報（段落００５３、図１２））のように、バンプ電極と半導体素子の表面を導電性の接着材で覆うようにした場合、上面から電気接続を行うために圧力をかける必要がある。また、電流を流すための導電性接着材の場合、導電材料を密に充填する必要があるため、接着剤自体が金属と同様の性質を持つことになり、各バンプ電極がつながった１枚の板のように作用して、特許文献１と同様にヒートサイクル時に接合面に応力がかかり、剥離等を起こす可能性がある。   On the other hand, in order to allow the metal block 5b to be electrically connected to the wiring, for example, as disclosed in JP-A-2005-50961 (paragraph 0053, FIG. 12), the bump electrode and the surface of the semiconductor element are electrically bonded. When covered with a material, it is necessary to apply pressure to make an electrical connection from the upper surface. In addition, in the case of a conductive adhesive for passing an electric current, it is necessary to densely fill the conductive material. Therefore, the adhesive itself has the same property as that of a metal, and one bump electrode is connected to each other. As in the case of Patent Document 1, it acts like a plate, and stress is applied to the joint surface during the heat cycle, which may cause peeling.

しかし、本発明の実施の形態１にかかる電力用半導体装置では、金属塊５ｂのそれぞれが、ソース電極３ｆとの接合面以外を絶縁物で覆うようにしたので、ヒートサイクル時に実質的に各金属塊５ｂが機械的な拘束を受けることがないので、ヒートサイクル時に接合面にかかる応力が小さくなり、剥離の発生を抑制することができる。   However, in the power semiconductor device according to the first embodiment of the present invention, each of the metal lumps 5b is covered with an insulator except for the joint surface with the source electrode 3f. Since the lump 5b is not mechanically restrained, the stress applied to the joint surface during the heat cycle is reduced, and the occurrence of peeling can be suppressed.

また、金属塊５ｂやソース電極３ｆに直接触れる絶縁物として、例えばゲル状のエポキシ材料のように流動性のある絶縁物を用いれば、各金属塊５ｂのソース電極３ｆとの接合面以外は機械的に解放されることになるので、ヒートサイクル時に接合面にかかる応力がさらに小さくなり、剥離の発生を効果的に抑制することができる。   Further, as an insulator that directly touches the metal block 5b and the source electrode 3f, for example, if a fluid insulating material such as a gel-like epoxy material is used, a part other than the joint surface with the source electrode 3f of each metal block 5b is mechanical. Therefore, the stress applied to the joint surface during the heat cycle is further reduced, and the occurrence of peeling can be effectively suppressed.

以上のように、本発明の実施の形態１にかかる電力用半導体装置によれば、絶縁性の基板１と、絶縁性の基板１の主面１ｆの異なる位置に形成された複数の配線２と、複数の配線２のうちの第１の配線２ａに接合された半導体素子３と、半導体素子３の第１の配線２ａとの接合面と反対側になるソース電極３ｆの一部と、複数の配線２のうちの第２の配線２ｂとを電気的に接続するワイヤ４と、を備え、ソース電極３ｆには、複数の金属塊５ｂが分散して接合され、複数の金属塊５ｂのそれぞれは、ソース電極３ｆとの接合面以外を絶縁物で覆うように構成したので、信頼性が高く、損失低減と短絡時の耐量向上を両立させた電力用半導体装置を得ることができる。   As described above, according to the power semiconductor device of the first embodiment of the present invention, the insulating substrate 1 and the plurality of wirings 2 formed at different positions on the main surface 1f of the insulating substrate 1 The semiconductor element 3 bonded to the first wiring 2a of the plurality of wirings 2, a part of the source electrode 3f on the opposite side to the bonding surface of the semiconductor element 3 to the first wiring 2a, A wire 4 that electrically connects the second wire 2b of the wires 2, and a plurality of metal lumps 5b are dispersed and joined to the source electrode 3f, and each of the plurality of metal lumps 5b is In addition, since the structure other than the joint surface with the source electrode 3f is covered with an insulator, it is possible to obtain a power semiconductor device that has high reliability and achieves both a reduction in loss and an improvement in resistance against short circuit.

とくに、絶縁物７としてゲル状の絶縁物を用いたので、より信頼性が高く、損失低減と短絡時の耐量向上を両立させた電力用半導体装置を得ることができる。   In particular, since a gel-like insulator is used as the insulator 7, it is possible to obtain a power semiconductor device that is more reliable and that achieves both a reduction in loss and an improvement in resistance against short circuit.

また、本発明の実施の形態１にかかる電力用半導体装置の製造方法によれば、絶縁性の基板１の主面１ｆに複数の配線２を形成し、複数の配線２のうちの第１の配線２ａに半導体素子３を接合し、ボンディング用ワイヤを半導体素子３のソース電極３ｆの一部に第１ボンドによりボンディングし、複数の配線２のうちの第２の配線２ｂに第２ボンドによりボンディングすることによりソース電極３ｆと第２の配線２ｂとを電気的に接続し、ソース電極３ｆにおいてそれぞれ異なる位置に、前記ボンディング用ワイヤを第１ボンドによりボンディングし、当該ボンディングにより形成された圧縮根５ｂを残して切り離すことにより、ソース電極３ｆ上に複数の金属塊５ｂを形成する、ように構成した。つまり、ワイヤ４は、ボンディング用ワイヤをソース電極３ｆの一部に第１ボンド４ａによりボンディングし、第２の配線２ｂに第２ボンド４ｂによりボンディングすることにより形成し、複数の金属塊５ｂは、ソース電極３ｆにおいてそれぞれ異なる位置に、前記ボンディング用ワイヤをワイヤ４と同様に第１ボンドによりボンディングし、当該ボンディングにより形成された圧縮根を残して切り離すことにより形成するように構成したので、スループットが向上し、製造コストや製造時間を大きく増大させることなく、負荷短絡耐量を向上させることができる。   In addition, according to the method for manufacturing the power semiconductor device according to the first embodiment of the present invention, the plurality of wirings 2 are formed on the main surface 1f of the insulating substrate 1, and the first of the plurality of wirings 2 is formed. The semiconductor element 3 is bonded to the wiring 2a, the bonding wire is bonded to a part of the source electrode 3f of the semiconductor element 3 by the first bond, and the second wiring 2b of the plurality of wirings 2 is bonded by the second bond. By doing so, the source electrode 3f and the second wiring 2b are electrically connected, and the bonding wire is bonded to the source electrode 3f at different positions by the first bond, and the compressed root 5b formed by the bonding is used. A plurality of metal lumps 5b are formed on the source electrode 3f by separating the metal electrode 5f. That is, the wire 4 is formed by bonding a bonding wire to a part of the source electrode 3f by the first bond 4a and bonding to the second wiring 2b by the second bond 4b. Since the bonding wire is bonded to the source electrode 3f at different positions by the first bond in the same manner as the wire 4, and is formed by cutting off the compression root formed by the bonding, the throughput is increased. It is possible to improve the load short-circuit tolerance without greatly increasing the manufacturing cost and the manufacturing time.

なお、本実施の形態１ではワイヤ４を1本設けた場合の例を示しているが、ワイヤ４を複数本設けても同様の効果が得られる。また副次的な効果としては、本構成をとることにより、通常のソース電極３ｆのように表面が下地のＡｌ膜（厚み数μｍ程度）のみの場合に対して、第１ボンドにより形成した金属塊５ｂ（圧縮根）が面内に多数存在することにより、ソース電極３ｆの表面を流れる電流の経路の抵抗値が低減し素子の動作特性が改善される。従来はこの点を改善するために複数本のワイヤを形成する必要があった。   Although the first embodiment shows an example in which one wire 4 is provided, the same effect can be obtained even if a plurality of wires 4 are provided. Further, as a secondary effect, by adopting this configuration, the metal formed by the first bond with respect to the case where the surface is only the base Al film (thickness of about several μm) like the normal source electrode 3f. Since there are a large number of masses 5b (compression roots) in the plane, the resistance value of the path of the current flowing through the surface of the source electrode 3f is reduced, and the operating characteristics of the element are improved. Conventionally, it has been necessary to form a plurality of wires in order to improve this point.

実施の形態２．
本実施の形態２にかかる電力用半導体装置では、金属塊として実施の形態１において用いたワイヤボンディングの第１ボンドの圧縮根５ｂの代わりに、金属膜５ｍを使用するようにした。図３は、本実施の形態２にかかる電力用半導体装置の構成を示す図で、図３（ａ）は電力用半導体装置の平面図、図３（ｂ）は図３（ａ）のIIIb−IIIb線で切断した断面図である。図において、電力用半導体装置は、半導体素子３の第１の配線２ａとの接合面と反対側になるソース電極３ｆ上には、金属塊としての厚み３０μｍの複数のアルミニウムによる金属膜５ｍが、面内に分散するように形成されている。そして、半導体素子３と第２の配線２ｂとを電気的に接続するために金属膜５ｍのひとつと、第２の配線２ｂとをワイヤボンディングにより接続したワイヤ４と、を備えている。なお、説明の簡略化のため、図３では絶縁物７の記載を省略しているが、各金属膜５ｍのソース電極３ｆとの接合面以外は実施の形態１と同様に絶縁物７で覆われており、以降の図でも同様である。 Embodiment 2. FIG.
In the power semiconductor device according to the second embodiment, the metal film 5m is used in place of the compression bond 5b of the first bond of the wire bonding used in the first embodiment as the metal lump. 3A and 3B are diagrams showing the configuration of the power semiconductor device according to the second embodiment. FIG. 3A is a plan view of the power semiconductor device, and FIG. 3B is a cross-sectional view taken along line IIIb- in FIG. It is sectional drawing cut | disconnected by the IIIb line. In the figure, in the power semiconductor device, a metal film 5m made of a plurality of aluminum having a thickness of 30 μm as a metal lump is formed on the source electrode 3f on the opposite side to the joint surface of the semiconductor element 3 with the first wiring 2a. It is formed so as to be dispersed in the plane. And in order to electrically connect the semiconductor element 3 and the 2nd wiring 2b, one of the metal films 5m and the wire 4 which connected the 2nd wiring 2b by wire bonding are provided. For simplification of description, the illustration of the insulator 7 is omitted in FIG. 3, but the metal film 5m is covered with the insulator 7 in the same manner as in the first embodiment except for the joint surface with the source electrode 3f. The same applies to the following figures.

本実施の形態２では、ソース電極３ｆ上に分散し、それぞれ接合面以外が絶縁物で覆われている金属塊として、図示しないマスキングを用いて、厚さ３０μｍの複数（図では２０個）のアルミニウムの金属膜５ｍをアイランド状に形成した。各金属膜５ｍを微細なアイランド状に形成することにより、半導体素子３が高温状態と低温状態を繰り返すヒートサイクルにさらされた場合でも、熱膨張率の差により金属膜５ｍと半導体素子３のソース電極（ソース電極面）に加わる熱応力を低減することができる。この結果として熱応力に強い電力用半導体装置を得ることができる。つまり、本実施の形態２のように金属塊として金属膜５ｍを用いた場合でも、熱サイクルによる膜はがれの問題を生じさせることなく、短絡時の温度上昇を低減することができる。   In the second embodiment, a plurality (20 in the figure) of 30 μm in thickness is used as a metal lump that is dispersed on the source electrode 3f and is covered with an insulator except for the bonding surface, using masking (not shown). An aluminum metal film 5m was formed in an island shape. By forming each metal film 5m into a fine island shape, even when the semiconductor element 3 is exposed to a heat cycle in which a high temperature state and a low temperature state are repeated, the metal film 5m and the source of the semiconductor element 3 are caused by the difference in thermal expansion coefficient. Thermal stress applied to the electrode (source electrode surface) can be reduced. As a result, a power semiconductor device resistant to thermal stress can be obtained. That is, even when the metal film 5m is used as a metal lump as in the second embodiment, the temperature rise at the time of short circuit can be reduced without causing the problem of film peeling due to thermal cycling.

なお、本実施の形態２として厚さ３０μｍのアルミニウムの膜を用いているが、本実施の形態２のような金属膜５により金属塊を形成する場合では、マスクを用いてスパッタ―ないしは蒸着方法によりアイランド状の金属膜を形成することが可能であり、信頼性が高く、損失低減と短絡時の耐量向上を両立させる電力用半導体装置を得ることができるという効果を有する。また、マスクを通してアルミニウムの金属塊を形成しているが、前述の方法もしくは印刷法、ディッピング、メッキ法等により一様な膜を形成後にエッチングにより膜をアイランド状に形成したとしても、信頼性が高く、損失低減と短絡時の耐量向上を両立させる電力用半導体装置を得ることができ、更に、印刷法により直接的にパターンを形成しても、信頼性が高く、損失低減と短絡時の耐量向上を両立させる電力用半導体装置を得ることができる。   Although the aluminum film having a thickness of 30 μm is used as the second embodiment, when a metal lump is formed by the metal film 5 as in the second embodiment, a sputtering or vapor deposition method using a mask is used. Thus, an island-like metal film can be formed, and there is an effect that it is possible to obtain a power semiconductor device that has high reliability and can achieve both reduction in loss and improvement in withstand capability during short-circuiting. In addition, although the aluminum metal lump is formed through the mask, even if the film is formed in an island shape by etching after forming a uniform film by the above-mentioned method or printing method, dipping, plating method, etc., the reliability is high. High power semiconductor device that achieves both low loss and improved short-circuit withstand capability can be obtained, and even if the pattern is formed directly by printing, it is highly reliable, with low loss and short-circuit withstand capability. It is possible to obtain a power semiconductor device that achieves both improvements.

なお、本実施の形態２においては、ワイヤ４を金属膜５ｍの一部の上にボンディングするようにしたが、ワイヤ４をボンディングする部分には金属膜５ｍを形成せず、ソース電極３ｆの露出面（下地のＡｌ膜）にボンディングするようにしてもよい。この場合、金属膜５ｍの材料としてワイヤよりも融点の低い材料を用い、ワイヤ４よりも先に金属膜５ｍを融解させるようにして、金属膜５ｍの融解熱により温度上昇を抑制するようにしてもよい。   In the second embodiment, the wire 4 is bonded onto a part of the metal film 5m. However, the metal film 5m is not formed on the portion where the wire 4 is bonded, and the source electrode 3f is exposed. Bonding to a surface (underlying Al film) may also be possible. In this case, a material having a melting point lower than that of the wire is used as the material of the metal film 5m, the metal film 5m is melted before the wire 4, and the temperature rise is suppressed by the heat of fusion of the metal film 5m. Also good.

つぎに、上述した実施の形態１や実施の形態２における金属塊の形状等の好適範囲について検討を行った。   Next, a suitable range such as the shape of the metal block in the first embodiment and the second embodiment described above was examined.

＜金属塊の厚みの最適化＞
図４は、短絡を１０μＳ間生じさせたときのＡｌ面の温度上昇（金属膜５ｍの膜断面内の最大温度上昇：縦軸）と金属膜５ｍ（Ａｌ）の膜厚（横軸）の関係を示している。基本的に膜厚みを厚くするほど、Ａｌ層の温度上昇を低く抑えることができるが、膜厚みを３０μｍ以上にしたとしても温度上昇を抑える効果は少なくなる。また、Ａｌ膜厚を３μｍにした場合、６５０Ｋ程度の温度上昇が予想されるが、膜厚みを１０μｍ以上にすることで上昇を１００Ｋ程度抑制することが可能となる。このとき使用雰囲気を２００℃とすると最大温度は７５０℃となる。 <Optimization of metal lump thickness>
FIG. 4 shows the relationship between the Al surface temperature rise (maximum temperature rise in the cross section of the metal film 5m: vertical axis) and the metal film 5m (Al) film thickness (horizontal axis) when a short circuit occurs for 10 μS. Is shown. Basically, the thicker the film thickness, the lower the temperature rise of the Al layer, but the effect of suppressing the temperature rise is reduced even if the film thickness is 30 μm or more. Further, when the Al film thickness is 3 μm, a temperature increase of about 650 K is expected, but by increasing the film thickness to 10 μm or more, the increase can be suppressed by about 100 K. At this time, if the use atmosphere is 200 ° C., the maximum temperature is 750 ° C.

なお、特許文献１においては、「アルミニウム（Ａｌ）を用いる場合、半導体とアルミニウム電極の境界面の温度がアルミニウムの融点、すなわち６６０℃を超えないようにしなければならない。６６０℃を超えると、素子破壊が生じなくても、アルミニウム電極の溶融が起こり、電極の信頼性に重大な問題を生じる」と記載されている。しかし、図４に示す上昇温度は、膜の断面内の最も温度が高い点の温度上昇を示しているのであって、短絡が発生してから１０μｓ以内に短絡状態が解除されれば、最高点の温度は周辺への熱拡散により急速に冷却される。このことを考慮すると、最高点の温度が７５０℃（上所温度５５０Ｋ）になったとしても先行技術に示されるように電極の溶融が発生することはない。つまり、保護回路の動作が開始されるまでの１０μｓという期間での温度分布およびその後の温度分布の変化を考慮すると、最高点の温度は融点より１００Ｋ程度高い値まで許容できることになる。したがって、膜厚みを１０μｍ以上にすることにより、実用上は金属電極の溶融を引き起こすことなく、電力用半導体装置の信頼性を保つことができる。   In Patent Document 1, “when aluminum (Al) is used, the temperature of the interface between the semiconductor and the aluminum electrode must not exceed the melting point of aluminum, that is, 660 ° C. If the temperature exceeds 660 ° C., the element Even if no breakdown occurs, the aluminum electrode melts, causing a serious problem in the reliability of the electrode. However, the rising temperature shown in FIG. 4 indicates the temperature rise at the highest temperature in the cross section of the film, and the highest point is achieved if the short circuit state is released within 10 μs after the short circuit occurs. The temperature of is rapidly cooled by thermal diffusion to the surroundings. Considering this, even if the maximum temperature reaches 750 ° C. (upper temperature 550 K), melting of the electrode does not occur as shown in the prior art. That is, in consideration of the temperature distribution in the period of 10 μs until the operation of the protection circuit and the change in the subsequent temperature distribution are taken into consideration, the maximum temperature can be allowed to be about 100K higher than the melting point. Therefore, by setting the film thickness to 10 μm or more, the reliability of the power semiconductor device can be kept practically without causing melting of the metal electrode.

つまり、金属塊５の厚みを１０μｍ以上としたので、短絡が発生して保護回路が動作するまでの間の発熱による電力用半導体装置の故障を確実に防止することができる。   That is, since the thickness of the metal block 5 is set to 10 μm or more, it is possible to reliably prevent failure of the power semiconductor device due to heat generation until a short circuit occurs and the protection circuit operates.

また、金属塊５の厚みを３０μｍ以下としたので、金属塊５（とくに金属膜５ｍ）を形成する工程を短く抑えることができ、安価で迅速に電力用半導体装置を製造することができる。そのため、低コストで、しかも短絡が発生して保護回路が動作するまでの間の発熱による電力用半導体装置の故障を確実に防止することができる。   In addition, since the thickness of the metal block 5 is 30 μm or less, the process of forming the metal block 5 (particularly the metal film 5 m) can be kept short, and a power semiconductor device can be manufactured quickly and inexpensively. Therefore, it is possible to reliably prevent a failure of the power semiconductor device due to heat generation at a low cost until the short circuit occurs and the protection circuit operates.

なお、金属塊として圧縮根５ｂを使用する場合でも、ボンディング用ワイヤの径を調整することで厚みを調整することはできる。   Even when the compression root 5b is used as the metal lump, the thickness can be adjusted by adjusting the diameter of the bonding wire.

＜金属塊の配置の最適化＞
つづいて、金属塊の配置について検討を行った。図５は、図３における円V部分の拡大図で、図５（ａ）は平面図、図５（ｂ）は断面図である。配置について図３及び図５を用いて説明する。図３で示しているのは、各金属膜５ｍが方形であり、縦横に整列配置している例である。実際の配置は後述するように様々な配置が考えられるが、ここでは、説明のしやすい図３の配置で説明する。また、金属塊としては形状がはっきりしている実施の形態２における金属膜５ｍの図を用いているが、実施の形態１における第１ボンドの圧縮根５ｂでも同様の考え方ができるので、金属膜５ｍや圧縮根５ｂを総称して金属塊５として説明する。 <Optimization of metal lump arrangement>
Subsequently, the arrangement of metal blocks was examined. FIG. 5 is an enlarged view of a circle V portion in FIG. 3, FIG. 5 (a) is a plan view, and FIG. 5 (b) is a cross-sectional view. The arrangement will be described with reference to FIGS. FIG. 3 shows an example in which each metal film 5m is square and aligned in the vertical and horizontal directions. Although various arrangements can be considered as will be described later, here, the arrangement shown in FIG. Moreover, although the figure of the metal film 5m in Embodiment 2 in which the shape is clear is used as the metal lump, since the same idea can be applied to the compressed root 5b of the first bond in Embodiment 1, the metal film 5m and the compressed root 5b will be collectively referred to as a metal lump 5.

図５（ａ）にてわかるように、各金属塊５を格子状に配置した場合、半導体素子３のソース電極３ｆ上で、金属塊５が接合されていない露出部分が碁盤目のように存在する。露出部分のうち、金属塊５が接合されている部分と最も距離を有する部分は、碁盤目の中央にあたる位置Pfとなる。この位置Pfから金属塊５との最短距離をDPfとすると、本実施の形態では、DPfが５０μｍ以下になるように、金属塊５の間隔D55（図５（ｂ）に示すようにソース電極３ｆとの接合部分での間隔）を７０μｍ（≒５０×２／２0.5：（DPFの最大値）×（対角と辺の換算））に設定した。 As can be seen from FIG. 5A, when each metal block 5 is arranged in a lattice pattern, an exposed portion where the metal block 5 is not joined exists on the source electrode 3f of the semiconductor element 3 like a grid. To do. Of the exposed portion, the portion having the longest distance from the portion to which the metal block 5 is joined is the position Pf corresponding to the center of the grid. Assuming that the shortest distance from this position Pf to the metal block 5 is D Pf , in this embodiment, the distance D 55 between the metal blocks 5 (as shown in FIG. 5B) so that D Pf is 50 μm or less. The distance at the junction with the source electrode 3f was set to 70 μm (≈50 × 2/2 0.5 : (maximum value of DPF ) × (conversion of diagonal and side)).

図６は、先ほどの最短距離DPfを求めるために行った試験結果を示している。図６下部は、短絡試験を行った素子表面状態の写真で、上部は写真の各領域を説明するための模式図である。試験は半導体素子の一部に電流を流し（図中１３ｆ（模式図の網掛部に相当する））、それ以外の部分（図中１５の領域（２点鎖線VIa-VIaより右上側で、模式図の網
掛を行っていない部分））には電流を流していない。ここで、電流を流した部分１３ｆは半導体素子３の第1主面３ｆでの露出領域とみなし、電流の流れていない部分１５はヒートシンクとして作用するので、半導体素子３の第1主面３ｆでの金属塊５が接合されている部分と同様の部分であるとみなすことができる。 FIG. 6 shows the result of the test performed to obtain the shortest distance D Pf as described above. The lower part of FIG. 6 is a photograph of the surface state of the element subjected to the short circuit test, and the upper part is a schematic diagram for explaining each region of the photograph. In the test, a current was passed through a part of the semiconductor element (13f in the figure (corresponding to the shaded area in the schematic diagram)), and the other parts (15 regions in the figure (upper right of the two-dot chain line VIa-VIa In the figure, no shade is applied)). Here, the portion 13 f through which current flows is regarded as an exposed region on the first main surface 3 f of the semiconductor element 3, and the portion 15 through which no current flows functions as a heat sink, and therefore the first main surface 3 f of the semiconductor element 3. It can be considered that it is a part similar to the part to which the metal lump 5 is joined.

試験の結果、図中に示される一点鎖線VIb-VIbの左下側は発熱によるダメージを受けて、表面に形成されているＡｌ面（本試験では厚みは３μｍ）が熱のため変色している。このとき、電流の流れていない領域１５からダメージを受けずに済んだ領域の幅（２点鎖線VIa-VIaと一点鎖線VIb-VIbとの間隔）が５０μｍであった。   As a result of the test, the lower left side of the alternate long and short dash line VIb-VIb shown in the figure is damaged by heat generation, and the Al surface (thickness of 3 μm in this test) formed on the surface is discolored due to heat. At this time, the width (interval between the two-dot chain line VIa-VIa and the one-dot chain line VIb-VIb) of the region that did not receive damage from the region 15 where no current flows was 50 μm.

したがって、ヒートシンク（金属塊５）がある場合、そこ（接合部分）から５０μｍの範囲はヒートシンクの熱吸収効果により素子温度の上昇が抑制されていることが判る。したがって、ソース電極３ｆの露出部分における金属塊５との最短距離DPfが５０μｍ以下になるように、例えば、本実施の形態では金属塊５同士の間隔D55を７０μｍとした。しかし、間隔D55を１００μｍとしても、高温になるのは碁盤の目の中央部のごくわずかな
領域のみとなるので、金属塊５を密に形成することが困難な場合、実用的には、金属塊５同士の間隔D55を１００μｍ以下と設定してもよい。あるいは、どのような配置パターンを用いても最短距離DPfが５０μｍ以下となるように、金属塊５同士の間隔D55を５０μｍ以下と設定するようにしてもよい。 Therefore, when there is a heat sink (metal lump 5), it can be seen that the rise of the element temperature is suppressed by the heat absorption effect of the heat sink in the range of 50 μm from that (joint portion). Thus, as the shortest distance D Pf of the metal block 5 in the exposed portion of the source electrode 3f becomes 50μm or less, for example, in this embodiment it was 70μm metal ingot 5 between distance D 55 of the. However, even if the distance D 55 is set to 100 μm, only a very small area at the center of the grid is high, so that it is practically difficult to form the metal block 5 densely, the metal block 5 spacing D 55 between may be set as 100μm or less. Alternatively, using any arrangement pattern as the shortest distance D Pf also becomes 50μm or less, the metal block 5 between distance D 55 of the may be set to 50μm or less.

上記のように、露出部分における金属塊５との最短距離DPfが所定値以下に保たれるのであれば、各金属塊の接合部分の形状が方形である必要はなく、円形や六角形など、様々な形状でもその効果に差異はない。さらに、配置パターンも千鳥状であったり、亀甲状であったり、あるいはランダム形状でもよい。また、本実施の形態では金属塊５を２０個のアイランドに分割しているが、熱応力によりＡｌ膜が破損(剥離)する事象の発生は、素子の動作温度、冷却方法、膜の製造方法、積層構造（バリアメタルの配置等）に依存する。従って使用環境によって、分割個数は適宜調整すればよいが、いずれの個数に分割しようと、分割しない場合（面全体を接合）に対して、ヒートサイクル時の剥離の発生を抑制して信頼性を向上させる効果を有する。 As described above, if the shortest distance D Pf with the metal lump 5 in the exposed portion is kept below a predetermined value, the shape of the joint portion of each metal lump need not be a square, but a circle, a hexagon, etc. There are no differences in the effect of various shapes. Furthermore, the arrangement pattern may be a staggered pattern, a turtle shell pattern, or a random pattern. Further, in this embodiment, the metal block 5 is divided into 20 islands, but the occurrence of an event that the Al film is damaged (peeled) due to thermal stress depends on the operating temperature of the element, the cooling method, and the film manufacturing method. Depends on the laminated structure (arrangement of barrier metal, etc.). Therefore, the number of divisions may be adjusted as appropriate depending on the use environment. However, regardless of the number of divisions, when not divided (joining the entire surface), the occurrence of peeling during heat cycle is suppressed and reliability is improved. Has the effect of improving.

実施の形態３．
上記各実施の形態では、発熱パターンに関係なく、金属塊５をソース電極３ｆ内で、ほぼ均等に分散配置した例を示したが、本実施の形態３では、発熱分布に応じて金属塊５の配置を変化させるようにした。例えば、図７に示すように電流経路からの大きな電流が流れ、発熱が大きくなるワイヤ４の接続部分４ａ近傍で金属膜５ｍの形状を大きな形状5mL
とし、４ａから離れるに従って中間の形状の金属膜5mM、小さな形状の金属膜5mSと発熱部からの距離が近いほど金属塊５の熱容量が大きくなるように配置した。 Embodiment 3 FIG.
In each of the above-described embodiments, an example in which the metal block 5 is distributed almost uniformly in the source electrode 3f regardless of the heat generation pattern has been described. However, in the present embodiment 3, the metal block 5 is set according to the heat generation distribution. The arrangement of was changed. For example, the flow a large current from the current path as shown in FIG. 7, the heat generation becomes large wire 4 of the connecting portion 4a larger shape 5m the shape of the metal film 5m in the vicinity L
As the distance from 4a is increased, the heat capacity of the metal mass 5 is increased as the distance from the heat generating portion to the intermediate metal film 5m M and the small metal film 5m S is decreased.

なお、本実施の形態３では、説明が容易になるように金属膜５ｍの大きさで熱容量を変化させた場合を示したが、例えば、圧縮根５ｂを用いる場合、ボンディングを行う位置を調整することにより、発熱量の多いところほど、金属塊５の個数密度を上げるようにしてもよい。   In the third embodiment, the case where the heat capacity is changed depending on the size of the metal film 5m is shown for easy explanation. However, for example, when the compression root 5b is used, the bonding position is adjusted. Accordingly, the number density of the metal blocks 5 may be increased as the amount of heat generation increases.

１：絶縁性の基板、 ２：配線、 ２ａ：第１の配線、２ｂ：第２の配線、 ３：（ワイドバンドギャップ）電力用半導体素子、 3S（３ｆ，１３ｆ）：ソース電極、 ４：ワイヤ、 ５：金属塊（5b：ワイヤボンドの第１ボンドによる圧縮根、 5m：金属膜）、 ７：絶縁物、
Pf：ソース電極の露出部分において、金属塊またはワイヤが接している部分からの距離が最も遠くなる位置、 DPf：位置Pfから金属塊またはワイヤが接している部分との最短距離。 1: insulating substrate, 2: wiring, 2a: first wiring, 2b: second wiring, 3: (wide band gap) power semiconductor element, 3 S (3f, 13f): source electrode, 4: Wire, 5: metal block (5b: compression root by the first bond of wire bond, 5m: metal film), 7: insulator
P f : The position where the distance from the portion where the metal block or wire is in contact is the farthest in the exposed portion of the source electrode, D Pf : The shortest distance from the position P f to the portion where the metal block or wire is in contact.

Claims (5)

絶縁性の基板と、
前記絶縁性の基板の主面に形成された複数の配線と、
前記複数の配線のうちの第１の配線に接合されたワイドバンドギャップ半導体材料を用いた半導体素子と、
前記半導体素子の前記第１の配線との接合面と反対側にアルミニウムを用いて形成されたソース電極の一部と、前記複数の配線のうちの第２の配線とを電気的に接続するワイヤと、を備え、
前記ソース電極には、複数の金属塊が分散して接合され、前記複数の金属塊のそれぞれは、前記ソース電極との接合面以外が絶縁物で覆われていることを特徴とする電力用半導体装置。 An insulating substrate;
A plurality of wirings formed on the main surface of the insulating substrate;
A semiconductor element using a wide band gap semiconductor material bonded to a first wiring of the plurality of wirings;
A wire for electrically connecting a part of the source electrode formed using aluminum on the opposite side of the bonding surface of the semiconductor element to the first wiring and the second wiring of the plurality of wirings And comprising
A plurality of metal lumps are dispersed and joined to the source electrode, and each of the plurality of metal lumps is covered with an insulator except for a joint surface with the source electrode. apparatus. 前記複数の金属塊同士の間隔が５０μｍ以下であることを特徴とする請求項１に記載の電力用半導体装置。   The power semiconductor device according to claim 1, wherein an interval between the plurality of metal lumps is 50 μm or less. 前記複数の金属塊の厚みは、１０μｍ以上であることを特徴とする請求項１または２に記載の電力用半導体装置。 The thickness of the plurality of metal mass, power semiconductor device according to claim 1 or 2, characterized in that at 10μm or more. 前記ワイドバンドギャップ半導体材料が、炭化珪素または窒化ガリウムであることを特徴とする請求項１ないし３のいずれか１項に記載の電力用半導体装置。4. The power semiconductor device according to claim 1, wherein the wide band gap semiconductor material is silicon carbide or gallium nitride. 5. 絶縁性の基板の主面に複数の配線を形成し、
前記複数の配線のうちの第１の配線にワイドバンドギャップ半導体材料を用いた半導体素子を接合し、
ボンディング用ワイヤを前記半導体素子のアルミニウムを用いて形成されたソース電極の一部に第１ボンドによりボンディングし、前記複数の配線のうちの第２の配線に第２ボンドによりボンディングすることにより前記ソース電極と前記第２の配線とを電気的に接続し、
前記ソース電極においてそれぞれ異なる位置に、前記ボンディング用ワイヤを第１ボンドによりボンディングし、当該ボンディングにより形成された圧縮根を残して切り離すことにより、前記ソース電極上に複数の金属塊を形成する、
ことを特徴とする電力用半導体装置の製造方法。 Form multiple wirings on the main surface of the insulating substrate,
Bonding a semiconductor element using a wide band gap semiconductor material to a first wiring of the plurality of wirings;
Bonding a bonding wire to a part of a source electrode formed using aluminum of the semiconductor element by a first bond, and bonding to a second wiring of the plurality of wirings by a second bond. Electrically connecting the electrode and the second wiring;
Bonding the bonding wire with a first bond at different positions in the source electrode, and leaving a compressed root formed by the bonding to form a plurality of metal masses on the source electrode,
A method of manufacturing a power semiconductor device.
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