JP5074922B2 - Method for producing porous semiconductor film on substrate - Google Patents

Description

  The present invention relates to a method for producing a porous semiconductor film and a film obtained from such production. Furthermore, it relates to electronic devices incorporating such membranes and possible uses of such membranes.

Single crystal solar cells (solar cells) exhibit energy conversion efficiencies as high as ˜25%. Si-based crystals are no longer single crystals but polycrystalline, with the highest efficiency in the range of ˜18% and with amorphous Si the efficiency is ˜12%. However, even Si-based solar cells are rather expensive to manufacture even an amorphous Si plate. Accordingly, alternatives have been developed based on organic materials and / or mixtures of organic and inorganic materials, the latter type of solar cells often being referred to as hybrid solar cells. Organic and hybrid solar cells have been proven to be cheaper to manufacture, but appear to be equally low in efficiency, even compared to amorphous Si cells. Due to their possible inherent advantages such as lightweight, large area, low cost manufacturing, environmentally friendly materials, or flexible substrate manufacturing, efficient organic devices are technically and commercially available May prove to be a useful "plastic solar cell". Recent developments in solar cells based on dye-sensitized nanocrystalline titanium oxide (porous TiO ₂ ) semiconductors and liquid redox electrolytes demonstrate high energy conversion efficiency in organic materials (Non-Patent Document 1).

Photoelectrochemical cells (dye-sensitized solar cells, DSSC) based on nanocrystals of TiO ₂ sensitized with molecular dyes have attracted attention since its first announcement as an efficient photovoltaic device (Non-Patent Document 1, see above; Patent Document 1). Part of the ongoing work is the possible application of such cells on flexible substrates and the possibility of manufacturing flexible solar cells using them. One of the major challenges to be solved prior to the successful introduction of such flexible DSSCs is the limited temperature range applicable to plastic substrates. Primarily, the TiO ₂ nanoparticles used are brought into good electrical contact by application of a temperature as high as 450 ° C. Such a process is not applicable to flexible plastic substrates that limit the efficiency of cells using these substrates. Regarding other sintering methods, the most promising manufacturing method of flexible DSSC has so far applied high pressure to the TiO ₂ layer (Non-patent document 2; Patent document 2; Non-patent document 3; Non-patent document). 4). Furthermore, chemical sintering has been applied with little success (Non-Patent Document 5; Non-Patent Document 6). The combination of both methods, namely temperature sintering and chemical sintering, also leads to only minor improvements (Non-Patent Document 7).

  The disadvantages of the state of the art of manufacturing flexible solar cells can be summarized as follows:

  High temperature sintering is used to provide good electrical contact between the semiconductor particles. However, the temperature required for good electrical contact between the nanoparticles is more flexible than that which is acceptable for most substrates, e.g. made of polymer and on which plastic solar cell elements are formed. Much higher. Thus, due to the inherent limitations of the material, process parameters need to be compromised, which effectively limits the performance of solar cells thus manufactured effectively from the beginning.

  On the other hand, if a low temperature is used for sintering (around 200 ° C.), or if sintering occurs additionally or instead due to the application of high pressure, an organic binder cannot be used for the initial material. Usually, these organic binders are used to control the porosity of the layer containing semiconductor particles. Subsequently, in a high temperature method, the organic binder simply does not burn, leaving behind a hollow space. However, in a low temperature sintering process, these binders cannot be used because they only have to burn. Thus, porosity and concomitantly the transport of ions through the void is effectively reduced. Furthermore, the electrical contact between the particles does not reach a quality comparable to a hot sintered layer. Although the combination of low temperature sintering and pressure application improves electrical contact to some extent, the problem of low porosity remains unresolved.

In chemical sintering, the chemical reaction activated or not at low temperature that occurs in the oxide layer is used to coat the nanoparticles in the porous layer. They form a conductive outer layer, which improves the electrical conductivity of the porous membrane. However, these films are expected to have a high defect concentration. Furthermore, it is not clear if transport occurs only with a thin outer membrane. In both cases, this leads to lower performance at higher light intensity, which is reported in Non-Patent Document 7 (see above). This strongly limits the applicability of these cells.
WO91 / 16719 pamphlet H. Lindstroem, et al, Method for producing nanostructured thin film electrodes, WO 00/72373 pamphlet B. O-Regan, and M. Graetzel, Nature 353 (1991, 737) H. Lindstroem, et al, New manufacturing method for nanostructured electrodes on plastic substrates, Nano Lett, 1, 97 (2001) H. Lindstroem, et al, A new method for forming dye-sensitized nanocrystalline solar cells at room temperature, J. Photochem. Photobiol. A 145, 107 (2001) G. Boschloo, et al, Optimization of dye-sensitized solar cells formed by compression method, J. Photochem. Photobiol. A 148, 11 (2002) D. Zhang, et al, Efficient Porous Titania Photoelectrode Production by Hydrothermal Crystallization at the Solid-Air Interface, Adv. Master. 15, 814 (2003) D. Zhang, et al, Low temperature synthesis of porous nanocrystalline TiO2 thin films for dye-sensitized solar cells by hydrothermal crystallization, Chem. Lett. 9, 874 (2002) SA Hague, at al, Flexible dye-sensitized nanocrystal solar cell, Chem. Comm. 24, 3008 (2003)

  Accordingly, it was an object of the present invention to provide a manufacturing method that makes it possible to utilize the benefits of a high temperature sintering process in combination with a flexible substrate that cannot withstand such a high temperature sintering process. Furthermore, it was an object of the present invention to provide a plastic solar cell that can be manufactured by an inexpensive method. Furthermore, it was an object of the present invention to provide a plastic solar cell with an efficiency comparable to that reported in the literature.

All these purposes
a) forming on the first substrate an adhesive layer capable of providing electrical and mechanical contact between the porous semiconductor layer attached to the adhesive layer and the first substrate;
b) forming a porous semiconductor layer on the second substrate;
c) transferring the porous semiconductor layer onto the adhesive layer;
Optionally, after step b) or c), n is an integer from 2 to 100, preferably 2 to 20, more preferably 2 to 10, and the third, fourth, fifth,. forming a second, third, fourth,..., n-th porous semiconductor film on the n, n + 1th substrate, and the second, third, fourth, fifth,. A step of transferring the porous semiconductor film onto each of the first, second, third, fourth,..., N-1th porous semiconductor films, and optionally, one, several, or second. , 3rd, 4th, 5th, ... on the substrate, having a step of forming a further adhesive layer on each of the nth porous semiconductor layers, onto which the next semiconductor layer is transferred. It is solved by a method for producing a porous semiconductor film.

  As an example, when a second porous semiconductor layer is formed on a third substrate, it is transferred onto the first porous semiconductor layer which is itself transferred onto the adhesive layer. Furthermore, an additional adhesive layer may be present between the first and second porous semiconductor layers. In a preferred embodiment, the porous semiconductor films on the substrate are stacked on top of each other and are described above in steps a) to c) and possibly substeps ba), bb), bc). , Ca), cb) and cc) (see below for these sub-steps) with an alternating sequence of adhesion and porous semiconductor layers.

  In one embodiment, the adhesive layer is transparent, translucent, or opaque. Preferably it is transparent. In another embodiment it is opaque and thus more light scattering.

  In one embodiment, the porous semiconductor layer is transparent, translucent, or opaque.

  In one embodiment, the second, third, fourth, etc. semiconductor layers are transparent, translucent, or opaque. In certain embodiments, subsequent semiconductor layers become increasingly opaque, thus causing greater scattering. In certain embodiments, the opacity of individual porous semiconductor layers varies and preferably increases over the thickness of each individual layer. This can be applied to a film having only one porous semiconductor layer or a film having several porous semiconductor layers.

In certain embodiments, step c) comprises
ca) separating the porous semiconductor layer from the second substrate;
cb) optionally coloring the porous semiconductor layer, preferably using a dye effective for a dye-sensitized solar cell;
cc) transferring the porous semiconductor layer onto the adhesive layer without the second substrate.

Preferably, step b)
ba) A step of forming the porous semiconductor layer on the second substrate by a printing method, particularly a screen printing method, a doctor blade method, a drop cast method, a spin coating method, an ink jet method, and a spray method. When,
bb) sintering the porous semiconductor layer, and optionally,
bc) Preferably, the step of coloring the porous semiconductor layer using a dye effective for the dye-sensitized solar cell.

  In one embodiment, in step a), the adhesive layer is formed by a printing method, in particular a screen printing method, and / or an ink jet method, a doctor blade method, a drop cast method, a spin coating method, a sputtering method, a sol-gel method, and a spray. The adhesive layer is formed on the first substrate by a method selected from methods.

  In a further embodiment, the adhesive layer also has a function of being a block layer for preventing direct contact between the first substrate and an electrolyte applied later. In order to perform such a function, the adhesive layer may be composed of two sublayers, and one of the sublayers, preferably the lower sublayer is a block layer, and the other sublayer. The layer is an adhesive layer. The lower part (blocking layer) may be formed by a sputtering method or a sol-gel method particularly suitable for a plastic substrate.

  Preferably, step ca) comprises the step of lifting-off the porous semiconductor layer from the second substrate, preferably the lift-off is the porous semiconductor of the second substrate or a part thereof. It is done by removal from the layer, more preferably the removal is done by physical methods such as peeling and / or chemical methods such as etching and / or oxidation.

  In certain embodiments, the transfer of step c) is made while the porous semiconductor layer is wet or dry, preferably the transfer is achieved by a roll-to-roll technique. Is done.

In certain embodiments, the method according to the invention additionally comprises:
d) sintering and / or pressing a composite having the first substrate, the adhesive layer, and the porous semiconductor layer as an upper layer in that order.

  In certain embodiments, the sintering of step bb) is done at a temperature in the range of 300 ° C. to 500 ° C., preferably higher than 350 ° C., more preferably higher than 380 ° C., and most preferably higher than 400 degrees.

In certain embodiments, the sintering of step d) is performed at a temperature range of 50 ° C. to 200 ° C. and / or the pressing is performed at a pressure in the range of 0-12 × 10 ⁴ N / cm ^2. .

Preferably, the adhesive layer, semiconductor particles, a layer of preferably oxide particles, more preferably TiO ₂ particles, in particular anatase (anatase) -TiO ₂ particles.

It will be apparent to those skilled in the art that many types of semiconductor particles can be used to implement in the present invention. Examples of these include, but are not limited to: TiO ₂ , SnO ₂ , ZnO, Nb ₂ O ₅ , ZrO ₂ , CeO ₂ , WO ₃ , SiO ₂ , Al ₂ O ₃ , CuAlO ₂ , SrTiO ₃ , and SrCuO _2. Alternatively, it is a composite oxide containing some of these oxides.

In one embodiment, the porous semiconductor layer is a layer of semiconductor particles, preferably oxide particles, more preferably TiO ₂ particles, in particular anatase-TiO ₂ particles, wherein preferably the porous semiconductor layer is , Having semiconductor particles having a size in the range of about 10 nm to 1000 nm, preferably 10 nm to 500 nm.

  In one embodiment, the porous semiconductor layer has a porosity ranging from 30% to 80% as measured by a nitrogen adsorption technique. In this background, and as used herein, a film having a porosity of X% indicates that X% of the total volume occupied by the film is void.

  In one embodiment, the porous semiconductor layer is a composite layer having a first sublayer and a second sublayer adjacent to the first sublayer, and the first sublayer includes spherical nanoparticles, The second sublayer has elongated rod-like nanoparticles. Preferably, the nanoparticles are semiconductor particles. Preferably, the spherical nanoparticles have a size ranging from about 10 nm to about 500 nm, more preferably from about 10 to about 250 nm. Preferably, the elongated rod-like particles have an average length of 10 nm to 500 nm, preferably more than 50 nm to 200 nm along the longest aspect. In one embodiment, the ratio of the longest axis to the shortest axis of the elongated rod-like particles is 2 or more. In a preferred embodiment, the ratio of longest axis to shortest axis is between 2 and 10.

  In another embodiment, the rod-shaped nanoparticle is a fiber having a ratio of the longest axis to the shortest axis between 20 and 1000.

  In some embodiments, the content of rod-like particles in the first layer is less than the content of rod-like particles in the second layer, and the content of spherical nanoparticles in the second layer is contained in the spherical particles of the first layer. Although less than the amount, the first sub-layer of spherical nanoparticles also includes rod-shaped nanoparticles, and the second sub-layer of rod-shaped nanoparticles also includes spherical nanoparticles. In this application, whenever a sub-layer is referred to as a “sub-layer containing spherical nanoparticles” or “a sub-layer containing stretched rod-like particles”, these terms also contain “other” types of nanoparticles. Including the aforementioned possibilities of each sub-layer.

  In certain embodiments, the first sub-layer of spherical nanoparticles contains exclusively spherical nanoparticles, and the second sub-layer of elongated rod-shaped nanoparticles is exclusively elongated rod-shaped nanoparticles. Contains particles.

  In one embodiment, the porous semiconductor layer consists of a mixture of spherical and elongated rod-shaped nanoparticles, with the content of rod-shaped nanoparticles gradually increasing from the bottom of the layer to the top of the layer, or vice versa.

  In certain embodiments, the rod-shaped nanoparticles are nanotubes.

  In one embodiment, in the porous semiconductor film on the substrate, the first sub layer faces the adhesive layer, and the second sub layer is further removed from the adhesive layer. In another embodiment, in the porous semiconductor layer on the substrate, the second sublayer faces the adhesive layer, and the first sublayer is further removed from the adhesive layer.

  Preferably, the first and second sub-layers each have a thickness in the range of 1 μm to 20 μm.

  Preferably, the substrate is a substrate capable of withstanding a temperature of 350 ° C. or higher, preferably 400 ° C. or higher. Here, preferably, the second substrate is glass or metal, preferably steel, or one in an upper layer. Alternatively, it is formed from glass with several additional layers.

  In one embodiment, the second substrate further includes a spacer layer, and the porous semiconductor layer is provided thereon, wherein the spacer layer is preferably removed by a chemical and / or physical method. That can be lifted off of the porous semiconductor layer.

  In one embodiment, the spacer layer is organic, inorganic, metal, preferably gold, or a combination thereof, wherein preferably the spacer layer is formed from gold and its removal can be, for example, an oxidizing agent. For example by oxidation by treatment of strong acids or redox couples, such as iodine / iodide.

  Preferably, the porous semiconductor layer has a thickness in the range of about 1 μm to about 50 μm.

  In one embodiment, the adhesive layer is a layer of semiconductor particles having a size in the range of about 10 nm to about 100 nm, preferably 10 nm to 50 nm, more preferably 10 nm to 20 nm.

  Preferably, the adhesive layer has a thickness in the range of 10 nm to 1 μm, preferably less than 500 nm, more preferably 100 nm or less.

  In an embodiment, the first substrate is formed from a flexible material, which preferably cannot withstand a sintering process at a temperature above 250 ° C.

  The object of the present invention is also solved by a porous semiconductor film produced by the method according to the present invention.

The purpose is on the substrate,
A series of adhesive layers and porous semiconductor layers that are alternately positioned on top of each other, wherein the layers are defined as above, preferably the porous semiconductor layer is dyed, or one or Due to the presence of the respective dyes, the subsequent porous semiconductor layer is dye-sensitized with several dyes, and the absorption of the absorption shifted to the longer wavelength side from the previous porous semiconductor layer closer to the substrate. An adhesion layer and a porous semiconductor layer having a center of mass;
This is further solved by a porous semiconductor film, preferably produced by the method according to the invention.
As used herein, the terms “dyed” and “dye sensitized” are used interchangeably.

  In certain embodiments, the porous layer is colored prior to transfer onto the corresponding adhesive layer. The absorption range of the colored porous layer can vary. Preferably, the first porous layer absorbs in the region on the shorter wavelength side, and the center of mass of absorption in the subsequent layer is subsequently shifted to the longer wavelength side.

They are,
A first substrate, preferably a flexible substrate, more preferably not capable of withstanding sintering temperatures above 250 ° C;
The adhesive layer capable of providing electrical and mechanical contact between the porous semiconductor layer attached to the adhesive layer and the first substrate, preferably 10 nm to 100 nm, more preferably 10 nm to 50 nm, most preferably An adhesion layer, which is a layer of semiconductor particles, in the range of 10 nm to 20 nm, the porosity is 30% to 80%, and the average pore size is in the range of 1 μm to about 100 μm;
A porous semiconductor layer having semiconductor particles having a pore size ranging from about 10 nm to about 1000 nm and having a pore size ranging from about 3 nm to about 500 nm, and having a thickness ranging from about 1 μm to about 50 μm A porous semiconductor layer, in that order, having a porosity in the range of 30% to 80% as measured by a nitrogen adsorption technique, preferably manufactured by a method according to the present invention. Solved.

The object of the present invention is also solved by an electronic device having a porous semiconductor film according to the present invention, wherein preferably the electronic device is a solar cell, more preferably the solar cell is greater than 5%. Has power conversion efficiency. In a preferred embodiment, the solar cell is 75% or more after a pressure of up to 6 × 10 ⁴ N / cm ² , preferably up to 10 × 10 ⁴ N / cm ² is applied to the porous semiconductor film, Preferably, it has a relative porosity defined for an unpressurized membrane of 80% or more. In another embodiment, the electronic device is a sensor device.

  The object of the invention is further solved by the use of the method according to the invention for the manufacture of electronic devices, in particular solar cells.

  They are also solved by the use of the porous semiconductor film according to the invention in electronic devices, preferably solar cells.

  The object of the present invention is also solved by a porous semiconductor layer having a first sub-layer having spherical nanoparticles and a second sub-layer having elongated rod-shaped nanoparticles adjacent to said first sub-layer. Preferably, the nanoparticles are semiconductor particles. Such a semiconductor layer having a first sub-layer with spherical nanoparticles and a second sub-layer with elongated rod-shaped nanoparticles adjacent to said first sub-layer is sometimes referred to herein as a “composite layer”. Is also called.

  Preferably, such composite layers of spherical and rod-like nanoparticles exhibit a difference in coefficient of thermal expansion between two different sub-layers.

  Such composite layers are sometimes also referred to herein as “sphere-rod composite layers” or “SRCL”. As used herein, the term “sphere-bar composite layer” refers to any layer having a sub-layer of spherical nanoparticles and another sub-layer of elongated rod-shaped nanoparticles adjacent to it. Is intended. For those skilled in the art, the terms “spherical” and “stretched rod” are merely approximate terms, and their appearance is still adequately represented by these terms, but in a strict geometric sense, It is clear that can also be used to represent particles that are not spherical or not completely rod-shaped.

  The term “adjacent to” is intended to indicate the spatial arrangement of two entities next to each other. In some embodiments, two adjacent sublayers are in direct contact with each other. In other embodiments, two adjacent sub-layers are separated by an intermediate spacer layer, whose dimensions may be very thin compared to the thickness of each sub-layer. However, in a preferred embodiment, two adjacent sublayers are in direct contact with each other.

  In certain embodiments, the spherical nanoparticles have a size in the range of about 10 nm to about 500 nm, more preferably 10 to about 250 nm. Preferably, the elongated rod-like particles have an average length of 10 nm to 500 nm, preferably more than 50 nm to 200 nm along the longest aspect. In a preferred embodiment, the ratio of the longest axis to the shortest axis of the elongated rod-like particles is 2 or more. In a more preferred embodiment, the ratio of the longest axis to the shortest axis is between 2 and 10.

  In one embodiment, the composite layer of spherical and rod-like particles has a thickness in the range of about 2 μm to 50 μm, preferably about 2 μm to about 40 μm.

Preferably, the semiconductor particles are oxide particles. Examples of these include, but are not limited to: TiO ₂ , SnO ₂ , ZnO, Nb ₂ O ₅ , ZrO ₂ , CeO ₂ , WO ₃ , SiO ₂ , Al ₂ O ₃ , CuAlO ₂ , SrTiO ₃ , and SrCuO _2. It is.

More preferably, the semiconductor particles are TiO ₂ particles, especially anatase-TiO ₂ particles.

  In certain embodiments, the ball-bar composite layer has a porosity ranging from 30% to 80% as measured by a nitrogen adsorption technique. In this context, and as used herein, a film or layer having a porosity of X% indicates that X% of the total volume occupied by the film or layer is void.

  The inventors have surprisingly found that such SRCL can be lifted off the substrate more easily compared to non-composite layers. Thus, such SRCL can be used and applied in any manner involving lift-off of a layer, preferably a semiconductor layer, from a substrate.

The inventors have also surprisingly found that the above disadvantages in the production of flexible DSSCs can generally be overcome by applying a method of transferring a porous TiO ₂ layer. This method applies the benefits of high temperature sintering of an active porous layer (good electrical contact, good porosity, good mechanical stability), such a porous layer on a flexible plastic substrate Combined with the possibility of making them in good electrical contact. It ensures complete freedom in selecting the parameters of the porous layer to be transferred and also in selecting the optimal electrical and optical properties of the layer. The principle is based on the formation of layers and the separation of contact with the substrate. That means that the active porous layer is formed on a substrate that can withstand high temperatures (spare substrate). After successful formation of this layer, it is removed from the spare substrate and transferred to another substrate (eg, unable to withstand high temperature sintering processes). Porous with the spacer or adhesive layer transferred to the flexible substrate, making it in good mechanical and electrical contact with this other substrate (“first” substrate according to the terms of the appended claims) Between the layers, a spacer or adhesive layer can provide electrical and mechanical contact between the flexible substrate and the transferred porous layer. As used herein, the term “adhesion layer” is used between a substrate (which may itself be coated with a TCO layer, for example) and another layer applied to the substrate, preferably a porous semiconductor layer. Any layer that provides adhesion is intended to be shown, or it provides adhesion between two adjacent layers, preferably two subsequent porous semiconductor layers. It has been found that good results are obtained when this spacer layer or adhesion layer consists of a very thin layer of nanoporous semiconductor particles, preferably TiO ₂ particles. To bring the transferred porous layer (sometimes also referred to herein as the “transfer layer”), the nanoporous adhesive layer and the substrate into good electrical contact, for example, only heating to 200 ° C., pressurization, and / or Or a different low temperature sintering process, such as chemical sintering, is sufficient and can be applied. Since the adhesive layer is much thinner than the standard porous layer employed in DSSC, the above disadvantages of these methods are much less important than when applied to the active porous layer. For example, pressurization does not affect the good properties of the transfer layer, but enhances the electrical contact between the nanoparticles of the adhesive layer and the contact between the electrode, adhesive layer and transfer layer. So far, the best results have been found for a combination of heating and pressing.

  Unless the semiconductor particles used in the porous semiconductor layer (sometimes also referred to herein as the “transfer layer”) and / or the adhesive layer are clearly specified as in SRCL, what shape is very good Will be apparent to those skilled in the art. They may be, for example, spheres, rods, tubes. They can take any aspect ratio and different diameters and shapes may be mixed. Similarly, mixed multilayer structures may be applied. In certain embodiments, the subsequent layers, ie, the adhesive layer and the subsequent semiconductor layer, may be increasingly scattered, ie, less permeable than the immediately adjacent layer. The effect of this stepwise scattering is due to the different composition of each subsequent layer having particles of different sizes and / or shapes, and the average size of the particles increasing from layer to layer. sell. Preferably, the surface roughness of each layer should not be substantially greater than the smaller particle size, preferably the smaller particle size of each layer. This ensures a smooth surface transition and good contact between the two layers. Furthermore, it is possible to add fibers to the porous semiconductor layer for better stability of this layer. The preferred thickness of the porous semiconductor layer is about 1 μm to about 50 μm. The porous semiconductor layer is preferably preferably flat and temperature resistant, that is, withstands high temperature sintering processes such as those used to sinter semiconductor layers (eg, in the temperature range of 350 ° C. to 500 ° C.). It can be formed on any kind of substrate. Alternatively, the substrate may have a shape that is simply similar or the same as the substrate on which the adhesive layer is formed. The preferred substrate material is glass or steel, although others can be used. The porous semiconductor layer may be formed by any suitable means including, but not limited to, printing methods, particularly inkjet printing methods, screen printing methods, doctor blade methods, drop cast methods, spin coating methods and spray methods. . One preferred method for forming a porous semiconductor layer is ink jet printing, because this method allows precise control over the thickness of the applied layer, and if desired, one single layer can be Very thin layers corresponding to about 1-5 monolayers corresponding to the thickness of one particle can be produced. However, ink jet printing is also perfectly compatible with the formation of thick layers in the range of μm, for example 2 μm to 50 μm. Another particularly preferred method for forming the porous semiconductor layer is screen printing. In one method of transferring a porous semiconductor layer from a substrate on which it is formed to an adhesive layer, a spacer layer is present on the substrate, and a semiconductor layer is formed thereon. The spacer layer facilitates removal of the porous semiconductor layer from the substrate on which it has been formed after the porous semiconductor layer has been sintered. Such a spacer layer may comprise an organic or inorganic material, which may comprise a metal, in particular gold. The spacer layer may be removed chemically, physically, or otherwise, as will be apparent to those skilled in the art. For example, gold can be oxidized by treatment with a redox couple such as a strong acid and / or iodine / iodide, for example. As a result of such removal, the porous semiconductor layer can be lifted off from the substrate on which it is formed and transferred onto the adhesive layer. A porous semiconductor layer is a layer that is the main “active” layer of an electronic device, meaning that the steps of light absorption, charge separation, and migration are mainly performed.

  In a preferred embodiment, the semiconductor layer is a composite layer of two different sublayers of spherical and rod-shaped semiconductor nanoparticles, respectively. Such SRCL (ball-bar composite layer) can be lifted off from the substrate much more easily, thus facilitating any process required to lift off the semiconductor film from the substrate.

  The inventors have found that the lift-off process described above is clearly facilitated by the application of a composite layer (SRCL) having a sphere-rod as shown in FIG. Without wishing to be bound by any theory, the effect can be described as follows:

First, we have the following SRCL, homogeneous porous layer, porous layer with two sublayers (the latter is the same geometric shape (diameter 10 to 10) in both sublayers. Mechanical force except gravity for small particles (20 nm), or smaller particles in the lower sublayer and larger particles of the same geometry in the upper sublayer (diameter 300 nm) The time required to remove the porous layer from the spare substrate in the iodine / iodide electrolyte was measured. The average time for all reference layers was at least an order of magnitude larger than the average time for SRCL. A comparison of the data for SRCL and a double layer of two nanospherical sublayers is shown in FIG. The inventors do not wish to be bound by any theory, and the most appropriate explanation for these observations is SRCL due to different expansion / contraction during layer formation and subsequent cooling in the high temperature sintering process. It is proposed that the internal stress of this causes easier removal from the spare substrate. However, in the particular embodiment used for illustration, both spheres and rods are anatase TiO ₂ single crystals as confirmed by X-ray diffraction, so the effect is different in the two layers. It cannot be purely attributed to crystallographic properties, and must instead be related to the nano-morphology of the membrane. Indeed, it is expected that a close-packed structure consisting of either randomly placed bulk polycrystalline material, single crystal rods, or single crystal spheres will exhibit the same average coefficient of thermal expansion. Thus, the nanoporous structure is allowed to deviate depending on the shape of the nanoscale structural block, which is explained as follows. TiO ₂ nanorods are grown by a template method. Based on selective adsorption of surfactants on surfaces of selected crystallographic orientation. In the case of diethylenetriamine, adsorption takes place selectively in the [001] direction or in a plane parallel to the c-axis of the anatase lattice, as used here for the synthesis of nanorods (see FIG. 7 for axis and direction nomenclature). See also). Surfactants retard crystal growth along the direction perpendicular to these planes, so it is expected that the long axis of the nanorods will coincide (within some deviation) in the [001] direction, which is indeed transmissive It was verified by electron microscopy. On the other hand, it is known that the thermal expansion coefficient α for anatase TiO ₂ has a negative expansion even along the a-axis, ie, the direction perpendicular to the [001] direction, and is strongly dependent on the crystalline orientation ( α _a = −2.88 × 10 ⁻⁶ , α _c = 6.6424 × 10 ⁻⁶ , both at room temperature). In the one-dimensional model of FIG. 7 (one-dimensional in the sense that the model just accounts for the different expansion coefficients along the nanoparticle chain), the c-axis of a spherical or rod-like particle is randomly oriented in all three directions. The major axis of the rod-shaped body contributes more than the minor axis to the total length of the nanoparticle chains shown in FIG. 7, so there is a difference in the macroscopic thermal expansion coefficient. Although this model oversimplifies the situation of nanoporous networks, based on these ideas, macroscopic thermal expansion coefficient differences are expected for porous layers consisting of either spheres or rods . Furthermore, since the layer structure is formed during the sintering cycle at 450 ° C., even small differences in α are sufficient to account for the internal stress observed at room temperature. Indeed, when the inventors measured the thickness of the porous layer between room temperature and 300 ° C. by optical interferometry, they found a different reaction between the standard layer and SRCL. For the standard layer, a decreasing thickness was observed with increasing temperature. This is attributed to layer shrinkage due to stronger lateral expansion of the glass substrate compared to the film itself. However, no reduction is observed for the nanorod layer, which can be interpreted as a larger expansion coefficient of the nanorod layer. In short, the nanometer-scale TiO ₂ shape is associated with macroscopic differences in the mechanical properties of the layer, combined with the nanoporous arrangement of particles in the layer, leading to optimization of the lift-off process. .

As far as the adhesive layer is concerned, it is not necessary for itself to participate in the active process of an electronic device in which a porous semiconductor film is used, and this adhesive layer is formed into a thin permeable layer, which is a Any material that can provide good electrical and mechanical contact between, eg, the electrodes) may be included. The material of the adhesive layer may be nanoporous, which means that the average pore size in the adhesive layer is in the range of 1 nm to 100 nm. In a preferred embodiment, the nanoporous particles of the adhesive layer are semiconductor particles, preferably oxide particles, more preferably TiO ₂ particles. It will be apparent to those skilled in the art that these particles may take any shape, for example, spherical, rod-shaped, or tube-shaped. Their preferred sizes range from about 10 nm to about 100 nm, but preferably the surface roughness of the individual layers is substantially smaller particle sizes, preferably smaller particle sizes of the individual layers. It must be emphasized that it is bigger than that. Also, at the interface between the adhesive layer and the porous semiconductor layer, the particles of the adhesive layer are relatively small to ensure good contact between the smooth surface and the two layers. The preferred thickness of the adhesive layer is from about 10 nm to about 1 μm, but embodiments with a thickness less than 500 nm are preferred. An embodiment having a thickness of 100 nm or less is more preferable. The adhesive layer may be applied by any means including, but not limited to, printing methods, particularly inkjet printing methods, screen printing methods, doctor blade methods, drop cast methods, spin coating methods, and spraying methods. . One preferred method of applying the adhesive layer is an ink jet printing method, because this method provides precise control over the thickness of the applied layer, so that one single layer can be reduced to one particle thickness. Corresponding very thin layers corresponding to about 1 to 5 monolayers can be produced. In principle, any substrate for the adhesive layer is possible, but for the purposes of manufacturing plastic solar cells, of course, relatively flexible substrates are preferred. It will be apparent to those skilled in the art that many materials can be used for such flexible substrates, including but not limited to polymeric materials. Also, the substrate can be flat or take any other shape. In a preferred embodiment, when the substrate is a flexible polymer substrate, it can only withstand some limits, for example up to 200 ° C.

For transferring the porous semiconductor layer from the first substrate on which the porous semiconductor layer is formed to the second substrate to be used in the electronic device, any technique for the purpose can be applied. Such techniques are known to those skilled in the art and include, but are not limited to, roll-to-roll techniques. During the transfer, the porous semiconductor layer may be wet or dry. After the porous semiconductor layer is transferred to the adhesive layer, low temperature sintering and / or pressure application may follow. A preferred temperature value for low temperature sintering is 200 ° C. or less. A preferred pressure is in the range of 2 × 10 ⁴ N / cm ^{2 to} 12 × 10 ⁴ N / cm ² . It will be apparent to those skilled in the art that the present invention is not limited to one adhesive layer and one porous semiconductor layer. We also envision other composites of one or more semiconductor layers and / or one or more adhesive layers.

Once a composite having at least a substrate, a transparent adhesive layer and a porous semiconductor layer is produced, it can be used, for example, in the production of solar cells. Solar cells and their other elements are known to those skilled in the art, i.e. it comprises an electrolyte and the porous semiconductor layer is treated with a dye to dye-sensitize it. As electrode materials, those materials that are not temperature resistant can be used because they do not need to be exposed to a high temperature sintering process. Materials for forming such electrodes are known to those skilled in the art and include metals, organic materials, highly doped poly (3,4-ethylenedioxidethiophene) (PEDOT or PEDT) and derivatives, and TCO layers. Including (transparent conductive oxide), but not limited. The same applies to the counter electrode, which may be an organic material, a TCO material, and / or a metal such as platinum. Exemplary TCO materials are, but not limited to, FTO, ITO, ZnO, SnO ₂ and combinations thereof.

  It will also be apparent to those skilled in the art that there are a wide variety of flexible substrates. For example, but not limited to, polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyethersulfone (PES), polyimide (Kapton), polyetheretherketone (PEEK), polyetherimide (PEI), stainless steel, OHP Flexible, predominantly polymeric (except steel) substrates such as (overhead transparencies) may be used.

Reference is made to the drawings.
The invention will be further described with reference to the following examples, which are present to illustrate the invention but are not intended to limit the invention.

Example 1
A schematic diagram of a DSSC formed by the lift-off technique described above is shown in FIG. In a typical cell produced by the method of the present invention, the substrate is coated with a transparent conductive oxide layer (TCO, about 100 nm). An active porous layer (porous) on which a thin adhesive layer of about 100 nm thickness consisting of TiO ₂ nanoparticles with a diameter of about 14 nm is transferred onto the substrate after sintering on the TCO and another substrate. Guarantees contact between the semiconductor layer or the transfer layer). The active porous layer is a dual structure of approximately 8 μm thick sublayer consisting of 20 nm particles (Part I in FIG. 1) and 2 μm thick sublayer consisting of a mixture of 20 nm and 300 nm particles (Part II in FIG. 1). Consists of. One possibility to remove the active layer from the spare substrate is to sinter it on a thin gold layer. After sintering, the gold is dissolved, for example with an iodine / iodide mixture, and the active layer is transferred from the preliminary to the true substrate in a solvent. After drying of the transfer and adhesive layers at 85 ° C. and low temperature sintering of the adhesive layer at 200 ° C. and 60 kN / cm ² , red dye molecules (= cis-bis (isothiocyanate) bis (2,2′- Bipyridyl-4,4′-dicarboxylic acid) ruthenium (II)) is attached to TiO ₂ as a monolayer by self-assembly from a solution in ethanol (0.3 mM). A dye-sensitized porous layer is filled with a polymer electrolyte solution (PEO in PC / EC) containing iodine / iodide (0.015 M) that serves as a redox couple. A 6 μm thick bulk layer of the same polymer electrolyte bridges the gap between the porous layer and a flat and smooth platinum film (50 nm) applied on any kind of substrate. In order to avoid direct contact between the TiO ₂ layer and the platinum counter electrode, an inert spacer, for example a glass ball or spacer foil, is introduced between the two electrodes.

Current to illumination with 100 mW / cm ² solar (AM 1.5) simulated in such a solar cell - voltage characteristic is shown in FIG. The maximum power conversion efficiency of 7% can be extracted from the data. FIG. 3 shows the efficiency and short circuit current density as a function of applied pressure. Previously reported results for the membranes under pressure which has not been formed by lift-off technique (Lindstroem et al., 2001, see above) and in contrast, efficiency and _{J SC} in 50 kN · cm ² or more pressure both saturated . For the non-lift-off layer, the best value is reported for a much lower pressure of about 5 kN / cm ² . One reason for this difference may be found in the pressure dependence of the porosity and efficiency of previously sintered (450 ° C.) but not transferred layers as shown in FIG. Neither porosity nor efficiency shows a strong dependence on the applied pressure and keeps their good properties in pressurization. However, for membranes that have not been pre-sintered, the porosity is greatly reduced with pressure, and the thicker, unsintered but pressurized membranes have worse performance and early time at high pressures. Can be one reason for the saturation of efficiency (Lindstrom et al., 2001, see above). The importance of a thin adhesive layer is demonstrated in FIG. 5, where the efficiency of the lift-off cell is shown as a function of the number of printing cycles when each cycle is inkjet printed equal to a layer thickness of about 100 nm. A large reduction in efficiency can be found for a large number of print cycles.

Example 2
In addition, experiments were conducted on a porous transfer layer that was dye-sensitized before the transfer layer was lifted off from the first substrate. The formation follows a path similar to that described for the first example, but this time with two adhesive layers and two transfer layers on top of each other in an alternating fashion, the transfer layer being dye-enhanced. The felt cell is manufactured. The order of the layers is: substrate-adhesive layer 1-porous semiconductor layer 1 (colored) -adhesive layer 2-porous semiconductor layer 2 (colored). The transfer layer is only about 5 μm thick and consists of a porous TiO ₂ layer with only particles having a diameter of about 20 nm. The transfer layer is sintered on a thin (approximately 20 nm) gold layer, and after sintering, red dye molecules are attached to TiO ₂ as a monolayer by self-assembly from a solution in ethanol (0.3 mM). It was. The gold layer was then dissolved with an iodine / iodide mixture. The first porous layer (porous semiconductor layer 1) was transferred onto a substrate coated with a 100 nm thick thin layer (adhesive layer 1) consisting of TCO (100 nm) and TiO ₂ nanoparticles with a diameter of about 14 nm. The adhesive layer 1 was applied by ink jet printing technology. After drying the first adhesive transfer layer at room temperature, a second thin adhesive layer (adhesive layer 2) is applied by ink jet printing and a second dye-sensitized porous layer (porous semiconductor layer 2) Was transferred onto the second adhesive layer. After the second drying at room temperature, all layers were sintered together by applying 60 kN / cm ² at room temperature. A power conversion efficiency of up to about 4% (with 100 mW / cm ² irradiation) was observed for cells made by transfer of such pre-colored porous layers. In another experiment, tri (isothiocyanate) (2,2 ′) in which the dye molecule of the second porous layer transferred onto the substrate is not a red dye molecule and the maximum absorption is shifted to the longer wavelength side. : 6 ′, 2 ″ -terpyridyl-4,4 ′, 4 ″ -tricarboxylic acid) ruthenium (II) molecule, black pigment.

Example 3
Further, an experiment was conducted on a porous transfer layer composed of a double layer of a sphere in the lower part and a rod-shaped particle in the upper part. These composite layers were produced as follows: On a thin gold layer on a glass substrate, a porous layer of about 5 μm thickness consisting of 20 nm spheres was first applied by screen printing. After drying at 80 ° C., a porous layer having a thickness of about 5 μm composed of a rod-like body having a length of about 100 nm and a diameter of about 20 nm (longest axis: shortest axis ratio = 5) is formed on the spherical layer. Applied. All layers were then sintered at 450 ° C. Those SRCLs could be lifted off for further use in the DSSCs produced by the lift-off techniques described above, for example, removal of the gold layer by immersion in a gold soluble electrolyte. They were also used in the experiment shown in FIG. 8 (b). In these experiments, the lift-off of the sphere-bar composite layer was compared to a standard double layer consisting of spheres in both the upper and lower sublayers. The relative membrane area removed from the various spare substrates is shown as a function of the duration of the layer immersion in the gold soluble electrolyte, and the removal of the sphere-bar composite layer is the layer removal at 1 minute relative to SRCL. Is much easier than the standard layer, as shown without onset and removal within the time scale of the experiment without additional force on the standard layer.

  The features of the invention disclosed in the description, the claims and / or the accompanying drawings, both alone and in combination, can affect the implementation of the invention in their various forms.

FIG. 1 shows a schematic diagram of a cell formed by the transfer / lift-off technique described by the present invention. FIG. 2 shows the IV characteristics of a DSSC manufactured with lift-off, ie manufactured according to the present invention. The applied temperature for sintering of the adhesive layer was 200 ° C., the applied pressure was 60 kN / cm ² , measured with simulated 100 mW / cm ² AM1.5 sunlight. 3, the DSSC according to the present invention, as a function of the applied pressure, the current density _{J SC} efficiency and short circuit (short Circuit) shown. The pressurization temperature was room temperature and measured with white light of 100 mW / cm ² using a sulfur lamp. FIG. 4 shows the efficiency and relative porosity of the DSSC according to the present invention as a function of applied pressure. The pressurizing temperature was room temperature. A relative porosity of 100% means the porosity of the cell before any external pressure is applied. FIG. 5 shows the efficiency of the loft-off cell according to the invention as a function of the adhesive layer thickness. The cell was only sintered at 200 ° C. and no pressure was applied. FIG. 6 is a schematic diagram and a scanning electron micrograph of SRCL according to the present invention. Figure 7 shows a schematic of a chain of TiO ₂ nanospheres chains and TiO ₂ nano rod-shaped body. In the nanorod state, the [001] direction contributes more. FIG. 8 (a) shows an overview of the improved lift-off in the nanorod sublayer, possibly due to different thermal expansion, compared to the nanosphere sublayer, and FIG. A comparison of the time required to lift off a heavy layer (having differently sized particles of the same shape) and a sphere-bar composite layer according to the present invention is shown.

Claims (35)

a) forming on the first substrate an adhesive layer capable of providing electrical and mechanical contact between the porous semiconductor layer attached to the adhesive layer and the first substrate;
b) forming a porous semiconductor layer on the second substrate;
c) transferring the porous semiconductor layer onto the adhesive layer;
The adhesive layer is a layer of semiconductor particles. A method for producing a porous semiconductor film on a substrate. After step b) or c), n is an integer from 2 to 100, and on the third, fourth, fifth,... Nth, n + 1th substrate, the second, third, fourth. ... forming the nth porous semiconductor layer; and the second, third, fourth, fifth, ... nth porous semiconductor layers in the first, second, third, The manufacturing method of the porous semiconductor film on the board | substrate of Claim 1. It has the process of transcribe | transferring on 4, n-1th porous semiconductor layer, respectively. After step b) or c), one, some, or second, third, fourth, fifth,... Each of the next semiconductor layers on top of each of the nth porous semiconductor layers The method for producing a porous semiconductor film on a substrate according to claim 2, further comprising the step of forming a further adhesive layer to which each of the above is transferred. Step c)
ca) separating the porous semiconductor layer from the second substrate;
The method according to any one of claims 1 to 3, further comprising: cc) transferring the porous semiconductor layer onto the adhesive layer without the second substrate.   5. The method of claim 4, wherein step c) comprises the step of cb) coloring the porous semiconductor layer between step ca) and step cc). Step b)
ba) printing method, de compactors blading, drop casting, spin coating method, an inkjet method, and by a process selected from spraying, a step of forming the porous semiconductor layer on the second substrate,
bb) sintering the porous semiconductor layer. The method according to any one of claims 1 to 5. The method according to claim 6, wherein step b) comprises after step bb): bc) coloring the porous semiconductor layer. 2. In step a), the adhesive layer is formed on the first substrate by a method selected from a printing method, a doctor blade method, a drop cast method, a spin coating method, and a spray method. The method in any one of -7. The method according to claim 4, wherein step ca) includes a step of lifting off the porous semiconductor layer from the second substrate. The method according to claim 9, wherein the lift-off is performed by removing the second substrate or a part thereof from the porous semiconductor layer. The method according to claim 10, wherein the removal is performed by at least a physical method or a chemical method. The method according to claim 1, wherein the transfer of step c) is performed while the porous semiconductor layer is in a wet or dry state. The method of claim 12, wherein the transfer is accomplished by a roll-to-roll technique. In addition,
The step of d) sintering or pressing at least a composite having the first substrate, the adhesive layer, and the porous semiconductor layer as an upper layer in that order. Method. The method according to any one of claims 6 to 14, wherein the sintering of step bb) is performed at a temperature in the range of 300C to 500C. 16. At least the sintering in step d) is performed in a temperature range of 50 ° C. to 200 ° C., or the pressurization is performed in a pressure range of 0 to 12 × 10 ⁴ N / cm ² . The method according to any one. The method according to claim 1, wherein the adhesive layer is a layer of oxide particles. The method according to claim 1, wherein the porous semiconductor layer is a layer of semiconductor particles. The method according to claim 1, wherein the porous semiconductor layer has semiconductor particles having a size in a range of 10 nm to 1000 nm. The method according to claim 1, wherein the porous semiconductor layer has a porosity ranging from 30% to 80% as measured by a nitrogen adsorption technique. The porous semiconductor layer is a composite layer having a first sublayer and a second sublayer adjacent to the first sublayer, the first sublayer includes spherical nanoparticles, and the second sublayer includes: The method according to claim 1, comprising stretched rod-shaped nanoparticles. The method of claim 21, wherein the spherical nanoparticles have a size in the range of 10 nm to 500 nm, and the elongated rod-like particles have an average length of 10 nm to 500 nm along the longest aspect. The method according to claim 21, wherein in the porous semiconductor film on the substrate, the first sub layer faces the adhesive layer, and the second sub layer is further removed from the adhesive layer. 24. A method according to any of claims 21 to 23, wherein the first and second sub-layers each have a thickness in the range of 1 [mu] m to 20 [mu] m. The method according to claim 1, wherein the substrate is a substrate that can withstand a temperature of 350 ° C. or higher. The method according to claim 25, wherein the second substrate is made of glass or metal. The method according to any one of claims 25 to 26, wherein the second substrate further includes a spacer layer, and the porous semiconductor layer is provided thereon. 28. The method of claim 27, wherein the spacer layer can be removed at least by chemical or physical methods, thereby allowing lift-off of the porous semiconductor layer. The method according to any one of claims 27 to 28, wherein the spacer layer is organic, inorganic, metal, or a combination thereof. 30. The method of claim 29, wherein the spacer layer is formed from metal and removal is performed by oxidation. The method according to claim 1, wherein the porous semiconductor layer has a thickness in the range of 1 μm to 50 μm. The method according to claim 1, wherein the adhesive layer is a layer of semiconductor particles having a size in a range of 10 nm to 100 nm. The method according to claim 1, wherein the adhesive layer has a thickness in the range of 10 nm to 1 μm. The method according to claim 1, wherein the first substrate is made of a flexible material.   35. Use of the method according to any of claims 1 to 34 for the manufacture of an electronic device.