JP5055142B2 - Memory test circuit - Google Patents

Description

  The present invention relates to a memory test circuit for testing the storage contents of a ROM (read only memory) in which a unique ID (identification code) is assigned to each semiconductor memory.

FIG. 2 is a test configuration diagram of a conventional ROM.
In this test configuration, a single ROM tester 10 is used to simultaneously test a plurality of ROMs 1a, 1b,..., 1n storing the same data.

  The ROM testing machine 10 includes an address generation unit 11 that generates an address signal ADR that increases one by one in order from address 0, a data memory 12 that holds correct data to be read from the ROM to be tested, and ROMs 1a and 1b to be tested. ,..., 13n that are determined every 1n and compare the data read from the corresponding ROM with the data from the data memory 12 to determine pass / fail.

  In this test configuration, the address generation unit 11 of the ROM tester 10 generates an address signal ADR that increases one by one from address 0 in order, and provides it as an address signal to the data memory 12, and also the ROMs 1a, 1b,. , 1n are commonly applied to the address terminals.

  Expected value data DT0 is output from the data memory 12, and stored data DTa, DTb,..., DTn are read from the ROMs 1a, 1b,. The data DTa, DTb,..., DTn are given to the determination units 13a, 13b,..., 13n of the ROM tester 10, respectively, and are compared with the expected value data DT0. Then, determination result signals RESa, RESb,..., RESn are output from the determination units 13a, 13b,.

JP-A-5-157802

  The test configuration of the ROM is based on the premise that the same data is stored in the ROMs 1a, 1b,. However, in applications where security functions that have become important in recent years and applications that require individual systems to be identified, it is necessary to assign unique IDs to individual ROMs.

  FIG. 3 is a diagram showing an example of a memory map of such an ID-added ROM. For example, in hexadecimal display, addresses 000 to FEF are allocated to the user data area, and 15 bytes from FF0 to FFE are It is assigned to the ID area, and the FFF address is assigned to the checksum area. The checksum is a lower 8-bit value as a result of accumulating 15-byte data in the ID area in units of bytes.

  When testing such a ROM with the test configuration of FIG. 2, the user data area in which the same data is stored can be tested simultaneously, but the ID area or check in which individual IDs or checksums are stored The thumb area cannot be tested at the same time. For this reason, it is necessary to individually test these ID areas and checksum areas, and there is a problem that the production efficiency cannot be increased and it is not suitable for mass production.

  An object of the present invention is to provide a memory test circuit capable of collectively testing a ROM having an ID area and a checksum area.

  According to the present invention, a memory test circuit for collectively testing the stored contents of a plurality of ROMs storing individual identification codes and check data in addition to common user data is configured as follows.

  That is, in this memory test circuit, an address determination unit for determining whether an address signal given to a ROM to be tested is a user data area, an ID area, or a check data area, and an ID area is specified by the address signal. When the check data area is specified by the address signal, the check sum calculation unit that calculates the check data according to the ID data sequentially read from the ROM, and the check data read from the ROM A first determination unit that determines whether the check data calculated by the checksum calculation unit is normal or not, and when the user data area is specified by the address signal, is read from the ROM User data is selected and output, and the ID area or When Ekkudeta region is specified, a selector for selecting and outputting a signal outputted from the first determination unit.

  Further, the memory test circuit reads data from the data memory in accordance with the address signal and a data memory storing expected value data to be output from the selector when the storage contents of the ROM to be tested are normal. A second determination unit that compares the expected value data and the signal output from the selector according to the storage content read from the ROM to determine whether the storage content of the ROM is good or bad.

  In the present invention, when an ID area is specified by an address signal given to a ROM to be tested, a checksum calculation unit that calculates check data according to ID data sequentially read from the ROM, and a check data area by the address signal Is specified, the check data read from the ROM is compared with the check data calculated by the checksum calculation unit to determine whether the data is normal. Thus, even if each ROM has a different ID, the first determination unit can determine whether the ID is normal or not based on the check data. Therefore, the second determination unit can determine the pass / fail of the test target ROM ID and its check data only by examining the determination result of the first determination unit. As a result, in addition to the common data area, it is possible to collectively test ROMs having individual ID areas and checksum areas.

  The above and other objects and novel features of the present invention will become more fully apparent when the following description of the preferred embodiment is read in conjunction with the accompanying drawings. However, the drawings are for explanation only, and do not limit the scope of the present invention.

  FIG. 1 is a test configuration diagram of a ROM showing an embodiment of the present invention. Elements common to those in FIG. 2 are denoted by common reference numerals.

  In this test configuration, the same user data is stored, and a plurality of ROMs 1a, 1b,..., 1n to be tested in which individual IDs and corresponding checksums are stored are stored in the same ROM testing machine 10 as in the past. Is used to test all at once.

  In this test configuration, test circuits 20a, 20b,..., 20n are inserted between the output side of each ROM 1a, 1b,. These test circuits 20a, 20b,..., 20n have the same configuration, and include an address determination unit 21, a checksum calculation unit 22, a determination unit 23, and a selector (SEL) 24, for example, as described in the test circuit 20a. ing.

  The address determination unit 21 determines which region of the ROM 1a to be tested is specified by the address signal ADR output from the address generation unit 11 of the ROM tester 10, and the control signals C1 and C2 are determined according to the region. , C3. For example, when the address signal ADR designates the user data area, the address determination unit 21 sets the control signal C1 to the level “H” and outputs it. Further, the control signal C2 is output in the ID area, and the control signal C3 in the checksum area is set to “H”. All control signals other than “H” are set to have a level “L”.

  The checksum calculation unit 22 cumulatively adds the data DTa read from the corresponding test target ROM 1a when the control signal C2 designates the ID area (that is, when the control signal C2 is “H”). Is. The added 1-byte value is given to the determination unit 23.

  When it is specified by the control signal C3 that it is a checksum area (that is, when the control signal C3 is “H”), the determination unit 23 is a ROM 1a to be tested corresponding to the cumulative addition result of the checksum calculation unit 22. Is compared with data DTa read out from. If they match, the determination unit 23 outputs all “1” data, for example, and outputs all “0” data if they do not match. Further, when it is outside the checksum area (that is, when the control signal C3 is “L”), the determination unit 23 outputs data of all “0”.

  When the control signal C1 designates the user data area (that is, when the control signal C1 is “H”), the selector 24 selects the data DTa read from the ROM 1a to be tested, and other than the user data area In this case, the output data of the determination unit 23 is selected. Data output from the selector 23 is provided to the corresponding determination unit 13a of the ROM tester 10.

  The ROM testing machine 10 includes an address generation unit 11, a data memory 12, and a plurality of determination units 13a, 13b,. The address generation unit 11 generates an address signal ADR that increases by 1 sequentially from address 0, as in FIG.

  On the other hand, the data memory 12 stores an expected value to be output from the test circuit 20a or the like according to the address signal ADR, and correct user data to be stored in the ROM 1a or the like is stored at an address corresponding to the user data area. It is remembered. Also, the data of the address corresponding to the ID area is set to all “0”, and the data of the address corresponding to the checksum area is set to all “1”. The determination units 13a, 13b,..., 13n compare the data output from the corresponding test circuits 20a, 20b,..., 20n with the data DT0 output from the data memory 12 to determine pass / fail. Resulting signals RESa, RESb,..., RESn are output.

Next, the operation will be described.
When the test is started, the address generation unit 11 of the ROM tester 10 outputs an address signal ADR that increases by 1 sequentially from address 0. The address signal ADR is given to the data memory 12, and is commonly given to the ROMs 1a, 1b,..., 1n to be tested and the test circuits 20a, 20b,.

  When the user data area is specified by the address signal ADR (for example, in the case of the ROM having the memory map of FIG. 3, addresses 000 to FEF), a control signal output from the address determination unit 21 of the test circuit 20a C1, C2, and C3 are “H”, “L”, and “L”, respectively. As a result, the operations of the checksum calculation unit 22 and the determination unit 23 are stopped, and the selector 24 selects the data DTa in the user data area read from the ROM 1a to be tested. The data DTa output from the selector 24 of the test circuit 20a is given to the determination unit 13a of the ROM tester 10 and compared with the data DT0 read from the data memory 12. Then, the determination unit 13a outputs a determination result signal RESa. The operation in this user data area is the same as the test configuration of FIG.

  Next, when the ID area is specified by the address signal ADR (for example, in the case of the ROM having the memory map of FIG. 3, addresses FF0 to FFE), the control output from the address determination unit 21 of the test circuit 20a. The signals C1, C2, and C3 are “L”, “H”, and “L”, respectively. As a result, the checksum calculation unit 22 enters the operating state, the operation of the determination unit 23 is stopped, and the output signal of the determination unit 23 is selected by the selector 24.

  The ID region data DTa sequentially read from the ROM 1 a according to the address signal ADR is sequentially accumulated and added by the checksum calculation unit 22, and the addition result is output to the determination unit 23. However, since the operation of the determination unit 23 is stopped at this time, the output signal of the determination unit 23 is all “0”. As a result, all “0” is output from the selector 24 and provided to the determination unit 13 a of the ROM tester 10. On the other hand, since the data DT0 read from the data memory 12 is also all “0”, the determination unit 13a outputs a signal RESa indicating a normal determination result.

  Thereafter, when the checksum area is designated by the address signal ADR (for example, in the case of the ROM having the memory map of FIG. 3, at the FFF address), the control signal C1, which is output from the address determination unit 21 of the test circuit 20a. C2 and C3 are “L”, “L”, and “H”, respectively. As a result, the operation of the checksum calculation unit 22 is stopped, the determination unit 23 enters an operating state, and the selector 24 selects the output signal of the determination unit 23.

  In the determination unit 23, the checksum of the data in the ID area calculated by the checksum calculation unit 22 is compared with the checksum area data DTa read from the ROM 1a to be tested. If the two data match (that is, if the checksum is normal), the output signal of the determination unit 23 is all “1”, and if they do not match (that is, if the checksum is not normal). The output signal of the determination unit 23 is all “0”.

  In the selector 24, the output signal of the determination unit 23 is selected and supplied to the determination unit 13a of the ROM tester 10. On the other hand, the data DT0 read from the data memory 12 corresponding to the address of the checksum area is all “1”. Therefore, if the output signal of the determination unit 23 of the test circuit 20a is all “1”, the determination unit 13a of the ROM tester 10 outputs a signal RESa indicating a determination result indicating normality.

  If the signal RESa of the determination result indicating that all the addresses of the ROM 1a to be tested are normal is obtained, it is determined that the content stored in the ROM 1a is normal. If the determination result signal RESa is output even once, there is defective data in the ROM 1a. The test operation for the ROM 1a to be tested has been described above, but the same test operation is simultaneously performed on the other ROMs 1b,.

  As described above, in the test configuration of the ROM of this embodiment, in the user data area of the ROMs 1a to 1n to be tested, the data DTa to DTn read from the ROMs 1a to 1n are output to the ROM tester 10 as they are, and the ID area In the checksum area, test circuits 20a to 20n for comparing the read checksum with the calculated checksum and outputting the determination result to the ROM tester 10 are provided for each ROM to be tested. ing. As a result, even if different IDs are assigned to the individual ROMs, it is possible to share the expected value data of the ROM tester 10 and test the ROMs having the ID area and the checksum area collectively. There is an advantage that can be.

In addition, this invention is not limited to the said Example, A various deformation | transformation is possible. Examples of this modification include the following.
(A) The data sizes of the user data area, ID area, and checksum area in the ROM to be tested are not limited to those illustrated.
(B) The checksum (check data) calculation method is not limited to the exemplified one. That is, the calculation method in the checksum calculation unit 22 in the test circuit 20 needs to match the calculation method of the check data in the ROM to be tested.
(C) In the addresses corresponding to the ID area and the checksum area, the value of the signal output from the determination unit 23 is not limited to that illustrated. In other words, when the address corresponds to the ID area and the checksum area, the value of the data DT0 read from the data memory 12 of the ROM tester 10 is set to the expected value of the signal output from the determination unit 23. good.
(D) In the test configuration diagram of FIG. 1, each test circuit 20a to 20n is described as having an address determination unit 21, but the address determination unit 21 can be shared. In other words, the test circuits 20b to 20n can be configured by the checksum calculation unit 22, the determination unit 23, and the selector 24, respectively.

It is a test block diagram of ROM which shows the Example of this invention. It is a test block diagram of the conventional ROM. It is a figure which shows an example of the memory map of ROM with ID.

Explanation of symbols

1a ~ 1n ROM
DESCRIPTION OF SYMBOLS 10 ROM test machine 11 Address generation part 12 Data memory 13a-13n, 23 Determination part 20a-20n Test circuit 21 Address determination part 22 Checksum calculation part 24 Selector

Claims (1)

A memory test circuit for collectively testing the storage contents of a plurality of read-only memories in which individual identification codes and check data are stored in addition to common user data,
An address determination unit that determines whether an address signal to be given to the read-only memory to be tested is a user data area, an identification code area, or a check data area;
When an identification code area is specified by the address signal, a checksum calculation unit that calculates check data according to an identification code sequentially read from the read-only memory;
When a check data area is specified by the address signal, the check data read from the read-only memory is compared with the check data calculated by the checksum calculation unit to determine whether the check data area is normal. A first determination unit;
When a user data area is designated by the address signal, user data read from the read-only memory is selected and output.When an identification code area or a check data area is designated by the address signal, A selector that selects and outputs a signal output from the first determination unit;
A data memory storing expected value data to be output from the selector when the stored content of the read-only memory to be tested is normal;
The expected value data read from the data memory in response to the address signal is compared with the signal output from the selector according to the storage content read from the read-only memory, and the quality of the storage content of the read-only memory is determined. A second determination unit that
A memory test circuit comprising:

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