JP5054064B2 - Hold circuit - Google Patents

Description

  The present invention relates to a hold circuit. In particular, the present invention relates to a hold circuit that suppresses a temporal drift of an output voltage during a hold operation.

  A hold circuit that holds and outputs a voltage of an input signal at a specific timing is known. Typical hold circuits include a peak hold circuit that holds the peak voltage of the input signal, a bottom hold circuit that holds the bottom voltage of the input signal, and a sample hold circuit that holds the input signal based on the sample / hold signal. Hereinafter, an input signal input to the hold circuit may be referred to as an input voltage, and an output signal output from the hold circuit may be referred to as an output voltage. In addition, the hold circuit holding and outputting an input voltage at a specific timing is referred to as a hold operation.

  The hold circuit includes a hold capacitor, a switching MOS transistor that switches between conduction and cutoff between the input terminal and the hold capacitor, and a buffer amplifier provided between the hold capacitor and the output terminal. Conduction between two points of the MOS transistor is referred to as “the MOS transistor is turned on”, and disconnection between the two points is referred to as “the MOS transistor is turned off”. The buffer amplifier outputs the voltage of the hold capacitor with low impedance. The buffer amplifier is sometimes called an impedance conversion circuit or a voltage follower.

  It is known that a slight current flows through the main electrode (source and drain) even when the MOS transistor is OFF. The current that flows when OFF is called a leakage current. Since the amount of charge charged in the hold capacitor is fluctuated by a leak current generated in the switching MOS transistor, the output voltage during the hold operation drifts.

  For example, Patent Literature 1 discloses a technique for reducing output voltage drift during a hold operation caused by a leak current. FIG. 7 shows an equivalent circuit of the sample and hold circuit disclosed in FIG. The hold circuit 700 includes a hold capacitor 712, a switching MOS transistor 708, and a buffer amplifier 709. The hold capacitor 712 stores electric charge according to the input signal supplied to the input terminal 706. The switching MOS transistor 708 conducts (ON) and shuts off (OFF) between the input terminal 706 and the hold capacitor 712 in accordance with the sample / hold signal input to the S / H terminal (sample / hold terminal) 704. Switch. The voltage of the hold capacitor 712 is output from the output terminal 714 via the buffer amplifier 709. The buffer amplifier 709 includes an operational amplifier 710 in which an inverting input terminal 710a and an output terminal 710c are connected. The non-inverting input terminal 710 b of the operational amplifier 710 corresponds to the input terminal of the buffer amplifier 709, and the output terminal 710 c of the operational amplifier 710 corresponds to the output terminal of the buffer amplifier 709.

  Reference numeral 720 in FIG. 7 indicates a parasitic diode of the switching MOS transistor 708. The parasitic diode is not intentionally inserted and is inevitably generated from the structure of the MOS transistor. Leakage current flows due to this parasitic diode. In FIG. 7, the leak current flowing from the back gate BG to the drain D is indicated by the symbol IL.

  In the technique of Patent Document 1, the back gate BG of the switching MOS transistor 708 is connected to the output terminal 710c of the operational amplifier 710 (buffer amplifier 709). In addition, a switching element 724 is provided for electrically connecting the source S of the switching MOS transistor 708 and the output terminal 710c of the operational amplifier 710 (buffer amplifier 709) when the switching MOS transistor 708 is OFF. The switch element 724 blocks between the source S and the output terminal 710c when the switching MOS transistor 708 is ON. When the switch element 724 is ON, the source S, the drain D, and the back gate BG of the switching MOS transistor 708 have substantially the same potential. With this configuration, the potential difference between the two main electrode electrodes (source / drain) of the switching MOS transistor 708 and between the back gate / drain is reduced, and leakage current flowing through the drain is suppressed.

JP-A-11-213687

  A buffer amplifier for outputting the voltage of the hold capacitor may cause a potential difference between its input end and output end due to its characteristics. A potential difference generated between the input terminal and the output terminal of the buffer amplifier is referred to as an offset voltage. In FIG. 7, the symbol Vos indicates the offset voltage of the buffer amplifier 709 (that is, the offset voltage of the operational amplifier 710). In the hold circuit 700 shown in FIG. 7, the offset voltage Vos is applied to the back gate BG of the switching MOS transistor 708. That is, a potential difference of Vos is generated between the drain D of the switching MOS transistor and the back gate BG. The hold capacitor 712 is charged by the offset voltage Vos and the voltage at the input terminal 710b of the buffer amplifier 709 rises. As a result, the voltage at the output terminal 710c of the buffer amplifier 709 also rises, and the amount of charge charged in the hold capacitor 712 further increases. Thus, even during the hold operation, the voltage of the output terminal 710c of the buffer amplifier 709, that is, the output voltage of the hold circuit 700 drifts. In other words, a positive feedback loop of the offset voltage Vos is formed in the buffer amplifier 709, and the output voltage of the hold circuit drifts with time.

  A timing chart of signals in the hold circuit 700 is shown in FIG. FIG. 8A shows a timing chart of the sample / hold signal, and FIG. 8B shows a timing chart of the output voltage. As shown in FIG. 8, during the period in which the sample / hold signal indicates “hold”, the output voltage Vout gradually drifts without maintaining a constant value.

  The present invention solves the above problems. That is, an object of the present invention is to provide a hold circuit that can suppress a time-dependent drift of an output voltage during a hold operation.

  The present invention is embodied in a hold circuit having an input terminal and an output terminal. The hold circuit includes a hold capacitor, a switching MOS transistor, and a buffer amplifier. One end of the hold capacitor is connected to a constant voltage terminal. The constant voltage may be a ground voltage in the case of a sample hold circuit or a peak hold circuit, and may be a power supply voltage in the case of a bottom hold circuit. A switching MOS transistor is interposed between the input terminal and the other end of the hold capacitor. The switching MOS transistor switches between conduction (ON) and cutoff (OFF) between the input terminal and the other end of the hold capacitor. In the case of the peak hold circuit or the bottom hold circuit, the switching MOS transistor switches between ON and OFF according to the magnitude relationship between the voltage at the input terminal and the voltage at the output terminal. Specifically, in the case of the peak hold circuit or the bottom hold circuit, the two main electrodes (source and drain) of the switching MOS transistor are connected to the input terminal and the other end of the hold capacitor, respectively. The output of the comparator that compares the voltage between them is connected to the gate. In the case of a sample and hold circuit, the switching MOS transistor switches between ON and OFF based on a sample and hold signal given from the outside. Specifically, in the case of a sample hold circuit, the two main electrodes (source and drain) of the switching MOS transistor are connected to the input terminal and the other end of the hold capacitor, respectively, and the sample hold signal terminal is connected to the gate. Yes. The buffer amplifier is interposed between the hold capacitor and the output terminal, and outputs the same voltage as the voltage at the other end of the hold capacitor with low impedance.

  In the hold circuit of the present invention, the buffer amplifier is constituted by a chopper amplifier. Here, the non-inverting input terminal of the chopper amplifier is connected to the hold capacitor, and the inverting input terminal is connected to the output terminal of the chopper amplifier. Further, the output terminal of the chopper amplifier is connected to the back gate of the switching MOS transistor. In this hold circuit, the non-inverting input terminal of the chopper amplifier corresponds to the buffer-up input terminal, and the output terminal of the chopper amplifier corresponds to the output terminal of the buffer amplifier (that is, the output terminal of the hold circuit).

  The effect of the hold circuit of the present invention will be described. In the parasitic diode of the MOS transistor, current can flow in the reverse direction at a high temperature. That is, the parasitic diode behaves as a non-linear characteristic resistance at high temperatures. The hold circuit of the present invention utilizes the fact that the parasitic diode of the switching MOS transistor behaves as a resistor at a high temperature. In the chopper amplifier, the direction (positive / negative) of the offset voltage generated between the non-inverting input terminal and the output terminal is inverted according to the chopper control clock signal. In the hold circuit of the present invention, the potential of the back gate BG of the switching MOS transistor is higher than the potential of the drain D when the offset voltage is positive, and vice versa when the offset voltage is negative. That is, when the offset voltage is positive, a leak current flows from the back gate BG of the switching MOS transistor to the drain D, and when the offset voltage is negative, the leak current flows in reverse. As a result, the amount of charge charged in the hold capacitor during the hold operation is maintained substantially constant, and the drift over time is suppressed.

  A typical chopper amplifier includes a cross switch and an operational amplifier. In the operational amplifier, an operational amplifier input side MOS transistor is connected to each of two input terminals (a non-inverting input terminal and an inverting input terminal). The cross switch periodically and alternately switches the connection between the two input terminals (non-inverting input terminal and inverting input terminal) of the chopper amplifier and the gates of the two operational amplifier input-side MOS transistors. In this case, a chopper amplifier having the following technical features is suitable for the hold circuit of the present invention. That is, the cross switch is composed of a plurality of cross switch MOS transistors. The back gate of each cross switch MOS transistor is connected to the output terminal of the operational amplifier.

  In the chopper amplifier having the above technical features, a leakage current flows in both directions according to the chopper control clock signal even between the back gate and the drain of the cross switch MOS transistor. Therefore, the hold circuit having such a configuration can suppress the drift of the output voltage due to the leakage current inside the chopper amplifier.

  In a switching MOS transistor or a cross-switch MOS transistor of the hold circuit, the magnitude of the leak current flowing from the back gate to the drain may be different from the magnitude of the leak current flowing from the drain to the back gate. In order to cope with such a case, the hold circuit of the present invention preferably includes a duty ratio adjustment circuit for adjusting the duty ratio of the chopper control clock signal. By adjusting the duty ratio, it is possible to cancel out the bias of the leakage current depending on the flowing direction, and it is possible to more effectively suppress the drift of the output voltage during the hold operation.

  According to the hold circuit of the present invention, it is possible to suppress the time drift of the output voltage during the hold operation.

The circuit diagram of the hold circuit of 1st Example is shown. An example of a timing chart of each signal is shown. The circuit diagram of a chopper amplifier is shown. The circuit diagram of the operational amplifier in a chopper amplifier is shown. An example of the timing chart of each signal when adjusting a duty ratio is shown. The circuit diagram of the hold circuit of 2nd Example is shown. The circuit diagram of the conventional hold circuit is shown. An example of the timing chart of the output voltage in the conventional hold circuit is shown.

Some of the main features of the embodiments described below are listed.
(Feature 1) A switching MOS transistor that switches between conduction and interruption between an input terminal and a hold capacitor is an nMOS transistor. The nMOS transistor conducts between the two main electrodes when the voltage applied to the gate is HIGH, and blocks between the two main electrodes when the voltage is LOW. One of the main electrodes (source or drain) of the nMOS transistor is connected to the input terminal of the hold circuit, and the other is connected to the other end of the hold capacitor. When the hold circuit is a sample hold, a sample / hold signal is input to the gate of the nMOS transistor. In the case of the peak hold circuit or the bottom hold circuit, the output terminal of the comparator that compares the input voltage and the output voltage is connected to the gate of the nMOS transistor.

  FIG. 1 shows a circuit diagram of the hold circuit of this embodiment. The hold circuit of this embodiment is a sample hold circuit 100 that holds an input voltage in accordance with a sample hold signal. In FIG. 1, the letters “S”, “D”, “G”, and “BG” indicate the source, drain, gate, and back gate of the MOS transistor, respectively. In the MOS transistor, there is no difference between the source and the drain. Therefore, even if the word “source” is replaced with the word “drain”, the following explanation is valid. “SC” indicates a chopper control clock signal supplied to the chopper amplifier 110. “S / H” indicates a sample / hold signal supplied to the sample / hold circuit 100. “Vin” and “Vout” indicate an input voltage and an output voltage, respectively. “Vos” indicates an offset voltage generated between the input terminal and the output terminal of the buffer amplifier 109. The offset voltage Vos corresponds to an offset voltage generated between the non-inverting input terminal 110b and the output terminal 110c of the chopper amplifier 110. “GND” in FIG. 1 indicates a ground terminal.

  The sample and hold circuit 100 includes a switching MOS transistor 108, a hold capacitor 112, and a buffer amplifier 109.

  The switching MOS transistor 108 is an nMOS transistor that conducts between the source and drain when the gate voltage is HIGH and shuts off between the source and drain when the gate voltage is LOW. Hereinafter, the time when the source / drain is conducted is referred to as “the MOS transistor is ON”, and the time when the source / drain is disconnected is sometimes referred to as “the MOS transistor is OFF”. Hereinafter, the switching MOS transistor 108 is simply referred to as “MOS 108”.

  The source S of the MOS 108 is connected to the input terminal 106 of the sample and hold circuit 100. The drain D of the MOS 108 is connected to one end P of the hold capacitor 112. The other end of the hold capacitor 112 is connected to a ground terminal (GND). The other end of the hold capacitor 112 may be connected to the constant voltage terminal. The gate G of the MOS 108 is connected to the S / H terminal 104 to which the sample / hold signal is input. The back gate BG of the MOS 108 is connected to an output terminal 110c of a chopper amplifier 110 described later.

  Reference numeral 120 denotes a parasitic diode between the source S of the MOS 108 and the back gate BG, and reference numeral 122 denotes a parasitic diode between the drain D of the MOS 108 and the back gate BG. The parasitic diodes 120 and 122 are not elements intentionally inserted by design, but are elements that are formed due to the structure of the MOS transistor. Parasitic diodes 120 and 122 generally do not pass current in the reverse direction at 100 ° C. or lower. However, when the temperature exceeds 100 ° C., particularly 150 ° C. or higher, the parasitic diodes 120 and 122 behave as resistors having nonlinear characteristics, and current flows in both directions. It has been known.

  The drain D of the MOS 108 is connected to one end P of the hold capacitor 112. One end P of the hold capacitor 112 is also connected to the non-inverting input terminal 110 b of the chopper amplifier 110. The output terminal 110c of the chopper amplifier 110 is connected to the inverting input terminal 110a. The chopper amplifier 110 to which the output terminal 110c and the inverting input terminal 110a are connected constitutes a buffer amplifier 109 having a gain of “1” between the non-inverting input terminal 110b and the output terminal 110c. The buffer amplifier 109 outputs a voltage having the same magnitude as the voltage at one end P of the hold capacitor 112 with a low impedance. The buffer amplifier 109 may be called an impedance conversion circuit or a voltage follower.

  The output terminal 110 c of the chopper amplifier 110 corresponds to the output terminal of the buffer amplifier 109 and also corresponds to the output terminal 114 of the sample hold circuit 100.

  The operation of the sample and hold circuit 100 will be outlined. When the sample / hold signal is HIGH, the output voltage of the sample / hold circuit 100 follows the change of the input voltage. When the sample / hold signal is LOW, the sample hold circuit 100 maintains and outputs the input voltage at the HIGH / LOW switching timing of the sample / hold signal.

  The operation of the chopper amplifier 110 will be outlined. Since the chopper amplifier itself is well known, a detailed description of its operation is omitted. An example of a specific configuration of the chopper amplifier will be described later. A chopper control clock signal is input to the chopper amplifier 110 via the S / H terminal 102. When the voltage V0 is applied to the non-inverting input terminal 110b of the chopper amplifier 110, a voltage of V0 ± Vos is output from the output terminal 110c. Here, the voltage Vos is an offset voltage generated between the non-inverting input terminal 110b and the output terminal 110c of the chopper amplifier 110. The offset voltage Vos is a potential difference generated between the non-inverting input terminal and the output terminal due to the internal structure of the chopper amplifier 110. The offset voltage varies depending on individual products. The offset voltage is generated not only in the chopper amplifier but in almost all amplifiers.

  A feature of the chopper amplifier is that the positive / negative of the offset voltage Vos is inverted in response to HIGH / LOW switching of the chopper control clock. FIG. 2 shows an example of a timing chart of each signal. 2A shows a timing chart of the sample / hold signal, and FIG. 2B shows a timing chart of the chopper control clock signal SC. FIG. 2C shows a change with time of the offset voltage Vos. FIG. 2D shows the change over time of the output voltage Vout.

  As shown in FIGS. 2B and 2C, the offset voltage Vos is inverted between positive and negative in response to the chopper clock signal. When the offset voltage Vos is positive, the potential of the output terminal 110c of the chopper amplifier 110 (that is, the back gate potential of the MOS 108) becomes higher than the potential of the non-inverting input terminal 110b (that is, the drain potential of the MOS 108). As a result, a current flows from the back gate BG to the drain D through the parasitic diode 122. In this case, since a leak current flows into the hold capacitor 112, the output voltage Vout increases.

  On the other hand, when the offset voltage Vos is inverted negatively, the potential of the output terminal 110c of the chopper amplifier 110 (that is, the back gate potential of the MOS 108) becomes lower than the potential of the non-inverting input terminal 110b (that is, the drain potential of the MOS 108). Here, as described above, the parasitic diodes 120 and 122 of the MOS 108 behave as resistors when the temperature becomes high. Therefore, at a high temperature, a current flows from the drain D to the back gate BG through the path of the parasitic diode 122. As a result, the charge of the hold capacitor 112 is released to the back gate BG, and the output voltage Vout decreases. During the hold period, the charge of the hold capacitor 112 repeatedly increases and decreases in response to the chopper control clock signal, so that the output voltage also repeatedly increases and decreases and the drift that increases (or decreases) in one direction is suppressed (FIG. 2D). ).

  As described above, the sample-and-hold circuit 100 can suppress the time-dependent drift of the output voltage during the hold operation on the assumption that the sample-and-hold circuit 100 operates at a high temperature (approximately 100 ° C. or higher). In other words, the sample hold circuit 100 is a hold circuit that suppresses the drift of the output voltage with time under a high temperature environment.

  Next, the configuration of the chopper amplifier 110 will be described. FIG. 3 shows a circuit diagram of the chopper amplifier 110. The chopper amplifier 110 includes a cross switch 322 and an operational amplifier 324. The operational amplifier 324 includes a pair of operational amplifier input side MOS transistors 316 and 318 and an amplifier circuit 320. Hereinafter, for the sake of simplicity, the operational amplifier input side MOS transistors 316 and 318 are simply referred to as input side MOSs. The input-side MOSs 316 and 318 are nMOS transistors that conduct between the source and the drain when the gate voltage is HIGH. Although not shown, the back gates of the input side MOSs 316 and 318 are grounded. The circuit of the amplifier circuit 320 will be described later with reference to FIG. Reference numeral 324 a represents an inverting input terminal of the operational amplifier 324, and reference numeral 324 b represents a non-inverting input terminal of the operational amplifier 324. The two input terminals of the operational amplifier 324 are connected to the gates of the input side MOSs 316 and 318, respectively. Reference numeral 110 c indicates an output terminal of the chopper amplifier 110. The output terminal 110 c of the chopper amplifier 110 also corresponds to the output terminal of the operational amplifier 324.

  The cross switch 322 includes four cross switch nMOS transistors 308, 310, 312, and 314. The cross switch 322 includes two input terminals (an inverting input terminal 110a and a non-inverting input terminal 110b) of the chopper amplifier, and two input terminals 324a and 324b of the operational amplifier 324 (that is, gates of the pair of input side MOSs 316 and 318). ) Is connected. The cross switch 322 alternately switches the connection relationship between the two input terminals of the chopper amplifier and the input side MOSs 316 and 318 in response to HIGH / LOW inversion of the chopper control clock signal SC. Hereinafter, the “cross-switch nMOS transistor 308” is simply referred to as “nMOS transistor 308”. The other cross switch nMOS transistors 310, 312, and 314 are also simply referred to as nMOS transistors 310, 312, and 314 while omitting the expression “for cross switch”.

  The circuit of the cross switch 322 will be specifically described. Two nMOS transistors 308 and 310 are connected in parallel to the inverting input terminal 110a. The inverting input terminal 110 a is connected to the sources of the two nMOS transistors 308 and 310. The drain of the nMOS transistor 308 is connected to the gate of one input side MOS 318 (one input terminal 324b of the operational amplifier 324). The drain of the nMOS transistor 310 is connected to the gate of the other input side MOS 316 (the other input terminal 324a of the operational amplifier 324). The back gates of the nMOS transistors 308 and 310 are connected to the output terminal of the amplifier circuit 320, that is, the output terminal 110 c of the chopper amplifier 110. A chopper control clock signal is input to the gate of the nMOS transistor 308. A chopper control clock signal is input to the gate of the nMOS transistor 310 via the inverter 306. Note that reference numeral 304 in FIG. 3 denotes a duty ratio adjustment circuit that changes the duty ratio of the chopper control clock signal. The duty ratio adjustment circuit 304 will be described later.

  Two nMOS transistors 312 and 314 are connected in parallel to the non-inverting input terminal 110b. The non-inverting input terminal 110 b is connected to the sources of the two nMOS transistors 312 and 314. The drain of the nMOS transistor 312 is connected to the gate of one input side MOS 316 (one input terminal 324a of the operational amplifier 324). The drain of the nMOS transistor 314 is connected to the gate of the other input side MOS 318 (the other input terminal 324b of the operational amplifier 324). The back gates of the nMOS transistors 312 and 314 are connected to the output terminal of the amplifier circuit 320, that is, the output terminal 110 c of the chopper amplifier 110. A chopper control clock signal is input to the gate of the nMOS transistor 312. A chopper control clock signal is input to the gate of the nMOS transistor 314 via the inverter 306.

  The cross switch 322 operates as follows. The cross switch 322 connects the inverting input terminal 110 a to one of the pair of input MOS transistors 316 and 318 of the operational amplifier 324 and connects the non-inverting input terminal 110 b to the other of the pair of input MOS transistors 316 and 318. The cross switch 322 switches the connection of the inverting input terminal 110a to the other input MOS transistor and switches the connection of the non-inverting input terminal 110b to the one input MOS transistor together with HIGH / LOW inversion of the chopper control clock signal.

  In the cross switch 322, the back gates of the nMOS transistors 312 and 314 connected in parallel to the non-inverting input terminal 110b are connected to the output terminal 110c of the chopper amplifier 110. As described above, when the voltage V0 is applied to the non-inverting input terminal 110b of the chopper amplifier 110, the output voltage of the chopper amplifier 110 becomes V0 ± Vos. Therefore, the back gate voltages of the nMOS transistors 312 and 314 vary by ± Vos with respect to the drain voltage. In response to fluctuations in the offset voltage Vos, a leakage current reciprocates between the back gates / drains of the nMOS transistors 312 and 314. As a result, voltage drift in the chopper amplifier 110 is suppressed.

  The amplifier circuit 320 will be described with reference to FIG. The letters “A”, “B”, “C”, “D”, “E” in FIG. 4 are the letters “A”, “B”, “C”, “D”, “E” in FIG. E ". A signal indicated by the letter “A” is referred to as a “chopper control clock signal”, and a signal indicated by the letter “B” is referred to as a “chopper control clock inverted signal”. The signal indicated by the letter “C” is referred to as “op-amp first input signal”, and the signal indicated by the letter “D” is referred to as “op-amp second input signal”. The signal indicated by the letter “E” is referred to as “op-amp reference signal”. In FIG. 4, “VDD” means a power supply voltage, and “GND” means a ground voltage.

  The sources of the pMOS transistors 402, 404, and 414 are connected to a constant voltage terminal that is maintained at the power supply voltage VDD. Although not shown in FIG. 4, the back gates of the nMOS transistors 406, 408, 410, 412, 422, 424, and 426 are grounded. The back gates of the pMOS transistors 402, 404, and 414 are connected to a constant voltage terminal maintained at the power supply voltage VDD.

  A constant operational amplifier reference signal (E) is generated by the signal current source 420, the pair of nMOS transistors 424 and 426, and the nMOS transistor 422.

  A cross switch 430 is formed by the four nMOSs 406, 408, 410, and 412. The cross switch 430 alternately switches the connection between the two inputs and the two outputs according to the chopper control clock signal (A) and the chopper control clock inverted signal (B). By this cross switch 430, the operational amplifier first input signal (C) and the operational amplifier second input signal (D) are alternately switched in synchronization with the chopper control clock signal. As shown in FIG. 4, the potential difference between the operational amplifier first input signal (C) and the operational amplifier second input signal (D) by the cross switch 430, the pair of pMOS transistors 402 and 404, the pMOS transistor 414, and the resistor 416. Is output from the output terminal 110c. Note that the resistor 416 and the capacitor 418 are elements for phase compensation, and their values are set according to the characteristics required for the amplifier circuit 320.

  The function of the duty ratio adjustment circuit 304 will be described with reference to FIG. FIG. 5A shows a timing chart of the chopper control clock signal SC adjusted by the duty ratio adjustment circuit 304. In FIG. 5A, the symbol T0 indicates the clock cycle, and the symbol T1 indicates the pulse width of the clock signal. The duty ratio adjustment circuit 304 adjusts the pulse width T1. The duty ratio D is represented by T1 / T0. FIG. 5A shows a chopper control clock signal adjusted to a duty ratio greater than 50%.

  FIG. 5B shows a change with time of the offset voltage Vos that repeats inversion by the adjusted chopper control clock signal. FIG. 5C shows a change with time of the output voltage Vout. When the duty ratio D increases, the period in which the offset voltage Vos is positive becomes longer than the period in which it is negative. Since the output voltage Vout corresponds to time integration of the offset voltage, the output voltage Vout increases with time as the duty ratio increases (FIG. 5C). The duty ratio adjustment function is useful when the asymmetry of the forward and reverse characteristics of the parasitic diode is large, or when the absolute value of the positive offset voltage is different from the absolute value of the negative offset voltage. That is, when the forward current of the parasitic diode is larger than the reverse current, or when the positive offset voltage is larger than the negative offset voltage, the output voltage during the hold operation can be reduced by making the duty ratio smaller than 50%. Can be suppressed. On the contrary, when the forward voltage current is smaller than the reverse current or when the positive offset voltage is smaller than the negative offset voltage, the duty ratio is set larger than 50% to increase the output voltage during the hold operation. Drift can be suppressed.

  The second embodiment is an example in which the present invention is applied to a peak hold circuit. FIG. 6 shows a circuit diagram of the peak hold circuit 600. In the peak hold circuit 600, components having the same functions as those of the sample hold circuit 100 of the first embodiment are denoted by the same reference numerals as in FIG.

  In the peak hold circuit 600, an operational amplifier 630 is connected between the input terminal 106 and the switching MOS transistor 208 (MOS 208). The MOS 208 is a pMOS transistor. The gate G of the MOS 208 is connected to the drain D. The MOS 208 connected in this way has a rectification that prevents current from flowing from the source to the drain when the source voltage is higher than the drain voltage, and prevents current from flowing from the drain to the source when the source voltage is lower than the drain voltage. Functions as an element. The parasitic diodes 220 and 222 of the pMOS are generated in a direction in which a leak current flows from the source S and drain D to the back gate BG. However, as in the first embodiment, the parasitic diodes 220 and 222 act as resistors at high temperatures (approximately 100 ° C. or higher).

  The operational amplifier 630 will be described. The non-inverting input terminal 630 b of the operational amplifier 630 is connected to the input terminal 106. The inverting input terminal 630 a of the operational amplifier 630 is connected to the output terminal 110 c of the chopper amplifier 110. The output terminal 630 c of the operational amplifier 630 is connected to the source S of the MOS 208. The other configuration of the peak hold circuit 600 is the same as that of the sample hold circuit 100 of the first embodiment.

  In the peak hold circuit 600, while the input voltage is increasing, the output of the operational amplifier 630 becomes a high voltage, and the source voltage becomes higher than the drain voltage. At this time, a current flows from the source S to the drain D. As a result, the output voltage follows changes in the input voltage. When the input voltage decreases, the output of the operational amplifier 630 becomes a low voltage, and the source voltage becomes lower than the drain voltage. Since the MOS 208 prevents a current from flowing from the drain D to the source S, the drain voltage is maintained. As a result, the voltage at the other end P of the hold capacitor 112 is maintained, and the output voltage maintains the peak value of the input voltage. The buffer amplifier 109 of the peak hold circuit 600 is composed of a chopper amplifier 110 as in the first embodiment. Accordingly, the peak hold circuit 600 suppresses the drift of the output voltage during the hold, similarly to the sample hold circuit 100 of the first embodiment. If the MOS 208 is replaced with an nMOS transistor and one end of the hold capacitor 102 is connected to a stable constant potential terminal such as a ground terminal or a power supply terminal, the circuit 600 becomes a bottom hold circuit.

  Several preferred modifications of the embodiment described above will be described. In the first embodiment, the cross switch 322 is constituted by four nMOS transistors 308, 310, 312, and 314. The cross switch 322 may be formed of a pMOS transistor instead of the nMOS transistor. In this case, the back gates of the two pMOS transistors connected in parallel to the inverting input terminal 110a are pulled up to the power supply voltage. The back gates of the two pMOS transistors connected in parallel to the non-inverting input terminal 110b are connected to the output terminal of the chopper amplifier as in the first embodiment.

  It is also preferable to replace each of the four nMOS transistors constituting the cross switch 322 with a complementary configuration in which an nMOS transistor and a pMOS transistor are connected in parallel.

  As mentioned above, although embodiment of this invention was described in detail, these are only illustrations and do not limit a claim. The technology described in the claims includes various modifications and changes of the specific examples illustrated above. The technical elements described in this specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. The technology illustrated in this specification or the drawings achieves a plurality of objects at the same time, and has technical usefulness by achieving one of the objects.

100: sample hold circuit 106: input terminal 108, 208: switching MOS transistor 109: buffer amplifier 110: chopper amplifier 110a: inverting input terminal 110b: non-inverting input terminal 110c: output terminal 112: hold capacitor 114: output terminal 120: Parasitic diode 304: Duty ratio adjustment circuit 306: Inverter 320: Amplifier circuit 322: Cross switch 324: Operational amplifier 430: Cross switch 600: Peak hold circuit 630: Operational amplifier 700: Sample hold circuit 706: Input terminal 708: Switching MOS transistor 708 : Hold capacitor 709: buffer amplifier 710: operational amplifier 710 a: inverting input terminal 710 b: non-inverting input terminal 710 c: output terminal 712: hold capacitor

Claims (3)

A hold circuit having an input terminal and an output terminal,
A hold capacitor with one end connected to the constant voltage terminal;
A switching MOS transistor that switches between conduction and cutoff between the input terminal and the other end of the hold capacitor;
A buffer amplifier that is provided between the other end of the hold capacitor and the output terminal, and that outputs the voltage at the other end of the hold capacitor with a low impedance;
The buffer amplifier is composed of a chopper amplifier whose non-inverting input terminal is connected to the other end of the hold capacitor and whose inverting input terminal is connected to the output terminal. The output terminal of the chopper amplifier is the output of the hold circuit. A hold circuit which is connected to a terminal and connected to a back gate of a switching MOS transistor. Chopper amplifier
An operational amplifier in which an input side MOS transistor is connected to each of the two input ends;
A cross switch that periodically and alternately switches the connection between the two input terminals of the chopper amplifier and the gates of the two input side MOS transistors,
The hold switch according to claim 1, wherein the cross switch includes a plurality of cross switch MOS transistors, and back gates of the plurality of cross switch MOS transistors are connected to an output terminal of an operational amplifier. circuit.   The hold circuit according to claim 1, further comprising a duty ratio adjustment circuit that adjusts a duty ratio of the chopper control clock signal.

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