JP5043700B2 - Differential signal transmission method - Google Patents

Description

  The present invention relates to a differential signal transmission method in a semiconductor integrated circuit, and more particularly to a transmission method of a differential signal having a small amplitude.

  In a transmission between a driver unit that drives a display device such as a liquid crystal display panel and a timing control unit that transmits data to the driver unit, a differential driving method such as RSDS (Reduced Swing Differential Signaling) is used.

  Such a differential drive method is a method of transmitting a pair of differential signals having opposite polarities to one signal through two signal lines. Since the signal is recognized by the level difference between the pair of differential signals in the receiving unit, it can be recognized as a signal having an amplitude twice that of each signal line. For this reason, the amplitude of each signal line can be reduced. In this way, the amplitude of the signal line can be reduced, the electromagnetic wave energy generated from the signal line is small, and the differential signals are paired so that they cancel each other out and reduce EMI (Electro Magnetic Interference). Is done. Further, since the signal is recognized by the potential difference of the differential signal, it is resistant to noise to some extent.

  FIG. 13 is a diagram showing signal forms of clock and data in the above-described conventional differential signal transmission. As shown in FIG. 13, at least two differential transmission lines of clock and data are required. In addition, when the interface level of the transmission unit and the reception unit are different, or when the GND level is different, there are many cases where the connection is made by AC coupling via a capacitor. Since AC coupling is connected via a capacitor, no DC component is transmitted. In order to transmit a signal correctly by AC coupling, it is necessary to use a DC-balanced signal (equal number of 0 and 1). For this reason, it is generally necessary to use an encoding such as 8B10B.

A conventional technique for multiplexing signal transmission in a differential signal transmission method is proposed by, for example, Patent Document 1. If the method disclosed in Patent Document 1 is adopted, the signal transmission rate is doubled, but data encoding is required to realize AC coupling and the like. Further, there is no specific disclosure regarding the clock signal transmission method.
JP 2005-338863 A

  As described above, in the conventional differential signal transmission system as shown in FIG. 13, at least two pairs of signal lines of the data signal D and the clock CK are necessary. However, in recent systems, it is necessary to transmit a larger amount of data, and the conventional differential signal transmission method has a problem that the number of signal lines becomes very large.

  Further, as a source of EMI, radiation from a connector or a cable in transmission wiring can be considered, but the noise that is the basis of these depends on the signal to be transmitted. The clock signal has many switching times, and has a large spectral component in the frequency and harmonics of the clock signal. Such energy is radiated from a connector, a cable, a board, or the like, which can be a problem to be solved.

  In addition, the multiplexing method shown in Patent Document 1 does not describe a clock signal multiplexing method, and is basically a system that requires clock transmission. Furthermore, in the case of AC coupling connection, encoding (8B10B or the like) that maintains DC balance is required, which causes a problem that the circuit configuration becomes complicated.

  In order to solve the above-described problems, the present invention multiplexes a clock signal and a data signal, can easily reproduce the clock, and realizes signal transmission with good DC balance without encoding even in AC coupled transmission, and is particularly a noise source. The purpose is to enable easy transmission of a clock signal as a transmission signal having a low noise peak.

  In order to solve the above problems, the present invention mainly adopts the following configuration.

  In a signal transmission method for transmitting logical data using two differential signals, positive and negative, the clock signal and the data signal are transmitted as differential signals using different signal line pairs, and the data signal is transmitted as two differential signals. The clock signal is configured to transmit a signal of exclusive OR with the data signal as a differential signal.

Further, in the signal transmission configuration described above, two or more continuous data of 0 or 1 is added for every N signals of the data signal . Further , in the signal transmission method, a skew control circuit that outputs a sampling clock signal based on the regenerated clock signal is provided on the receiving side in the transmission of the differential signal, and the data is obtained by the sampling clock signal from the skew control circuit. The sampling is performed at a stable point of the signal.

  According to the present invention, a clock signal and a data signal can be easily multiplexed, and the number of signal lines can be reduced. The multiplexed clock signal and data signal can be reproduced with a simple circuit. Further, by adding at least 2 bits of 0 or 1 code to the beginning or end of the data signal, DC balance (balance of transmission data 0 and 1) is achieved, and transmission is possible even when connected by AC coupling. This is useful for data transfer between devices, particularly for signal transmission between a driver that drives a liquid crystal panel and a timing controller that sends a signal to the driver.

  In recent years, liquid crystal panels have become larger and more precise, and the number of signal transmissions has become a major issue, which is also a problem of power consumption, and the panel frame is designed to be narrow. The tendency to reduce the number of wirings described above can have an effect on narrowing the frame.

A signal transmission system according to an embodiment of the present invention will be described in detail below with reference to FIGS. FIG. 1 is a diagram illustrating a configuration example of a signal transmission method according to an embodiment of the present invention. In FIG. 1, 1 and 6 are exclusive ORs, 2 and 3 are differential signal output circuits, 4 and 5 are differential signal reception circuits, CK is a clock signal, D is a data signal, CD is an internal signal, S ₀ and S ₁ are differential signals.

  In the present embodiment, the data D is output as a differential signal S 1 by the differential output circuit 3. The clock signal CK is exclusive ORed with the data D by the exclusive OR circuit 1. The calculation result signal is an internal signal CD. The internal signal CD is output as a differential signal S0 by the differential output circuit 2.

  On the other hand, on the receiving side, the differential signal S1 is reproduced as a single-ended signal by the differential signal receiving circuit 5. The dynamic signal S0 is converted into a single-ended signal by the differential signal receiving circuit 4, and is input to the exclusive OR 6 together with the signal subjected to the single-ended conversion by the receiving circuit 5, and the result of the exclusive OR operation is output. The Here, as the differential signal output circuits 2 and 3 and the differential signal receiving circuits 4 and 5, conventionally known circuits may be employed.

FIG. 2 is a diagram showing the signal timing and the waveform of the differential output signal of the transmission system shown in FIG. 1, and the timing chart of each signal when the data signal (D) shown in the uppermost stage of FIG. And shows the waveform of the differential output signal. As described above, the CD signal is an exclusive OR signal of D and CK, and when sending the data series as shown, it becomes a signal like the CD shown in FIG. 2 (the third-stage waveform in FIG. 2). See). Differential signals to be sent out, S ₁ is a differential signal of the data signal itself, the data signal is converted into a single-ended signal is reproduced by the differential signal receiving circuit 5. S ₀ is a differential signal of the signal CD described above, and single-ended conversion is performed by the differential signal receiving circuit 4 to reproduce the signal CD. When the reproduced CD and the reproduced data are subjected to an exclusive OR operation with the exclusive OR 6, the clock signal CK is reproduced.

  By adopting the configuration shown in FIG. 1, the differential signal is not a clock signal in which EMI noise energy tends to be large (see the description in the section of the problem to be solved by the invention), but a signal that is not uniform with the data signal. As a result, a specific spectrum component is increased and a signal which becomes an EMI generation source is suppressed.

  FIG. 3 is a diagram showing another configuration example of the signal transmission method according to the embodiment of the present invention. This configuration example is an example adapted to a multilevel differential signal. 3, 7 and 10 are exclusive ORs, 8 is a binary (amplitude) differential signal output circuit, 9 is a binary differential signal receiving circuit, and other reference numerals are the same as those in FIG. It plays the function of.

  In this configuration example (another configuration example shown in FIG. 3), the data signal D is input to one of the binary differential signal output circuits 8. The clock signal CK is subjected to an exclusive OR operation with the data signal D by the exclusive OR circuit 7. The calculation result signal is an internal signal CD. The internal signal CD is input to the other side of the binary differential signal output circuit 8. The binary differential signal output circuit 8 uniquely determines the output amplitude based on the combination of the input data signal D and the internal signal CD and outputs it. An example of the output amplitude determination table is shown in FIG. The amplitude allocation of this table is not limited to the illustrated example, and the allocation of binary amplitude conversion in the present embodiment is not limited to the table shown in FIG.

  A binary differential output signal based on the data signal D and the internal signal CD determined as described above is output from the binary differential signal output circuit 8 as a differential signal S. FIG. 5 is a diagram illustrating the signal timing and the waveform of the binary differential output signal of the transmission method illustrated in FIG. As can be seen from FIG. 5, a differential signal having a binary amplitude that is not a fixed pattern, such as the clock signal CK, is an advantageous signal for an EMI generation source. Further, the number of signals is reduced by half in comparison with the configuration example shown in FIG. 1, which is very useful for reducing the area, the number of pins, and the total EMI energy.

  In the present embodiment, each amplitude of the multi-value amplitude modulation is not defined. The essence of this embodiment is that the signals D and CK as described above are transmitted in multiple values, and the amplitude can be set to an appropriate value depending on the design of the transmission path, receiving circuit, etc. to be realized. Thus, the implementation of this embodiment does not require any restrictions.

  The transmitted differential signal S is inversely converted by the binary differential signal receiving circuit 9 from the amplitude according to the table of FIG. The inversely converted data signal D is the transmitted data signal D itself. Further, the inversely converted signal D and the internal signal CD are calculated by the exclusive OR circuit 10, and as a result, the transmission clock signal CK is reproduced.

  In this way, according to the configuration example shown in FIG. 3, the two signals D and CK of the data and the clock can be transmitted as a pair of differential signals, and the spectrum peak is not a regular signal such as the clock signal CK. And a reduction in the number of signals.

FIG. 6 is a diagram illustrating another configuration example of the signal transmission method according to the embodiment of the present invention. Another configuration example of this embodiment shown in FIG. 6 superimposes a clock signal and data signals of a plurality of data signals (in this configuration example, three of D ₀ , D ₁ , and D ₂ ), This is a configuration example in which transmission is performed with multiple values (binary in this configuration example).

In FIG. 6, 11, 12, 13, 18, 19, and 20 are exclusive ORs, 14 and 15 are binary (amplitude) differential signal output circuits, and 16 and 17 are binary differential signal reception circuits. S ₀ and S ₁ are differential signals.

In this configuration example, the data signal D ₀ is input to one of the binary differential signal output circuits 15. The clock signal CK is subjected to an exclusive OR operation with the data signal D ₀ by the exclusive OR circuit 13. The calculation result signal is CD. This CD is input to the other side of the binary differential output circuit 15. Binary differential signal output circuit 15 is uniquely determines the output amplitude by a combination of the input data signal D ₀ and the operation result signal CD signals, and outputs a differential multilevel signal S _0.

The data signal D ₁ is exclusively ORed with the clock signal CK by the exclusive OR circuit 12. The calculation result signal is CD1. This CD 1 is input to one of the binary differential signal output circuits 14. Data signal D ₂ is exclusive ORed with the clock signal CK by the exclusive OR circuit 11. The calculation result signal is CD2. This CD 2 is input to the other side of the binary differential output circuit 14.

Further, the binary differential signal output circuit 14 uniquely determines the output amplitude by a combination of CD1 and CD2 of the signals input, and outputs a differential multilevel signal S _1. An example of a table for determining the output amplitude is shown in FIG. FIG. 8 is a diagram showing a table for explaining multi-value signal conversion of the transmission method shown in FIG. The amplitude allocation of this table is not limited to the example shown in FIG. 8, and the allocation of binary amplitude conversion in this embodiment is not limited to this table.

  FIG. 7 shows a signal transmission time table determined in this way. FIG. 7 is a diagram showing the signal timing and the waveform of the binary differential output signal of the transmission method shown in FIG. As can be seen from FIG. 7, this is a binary amplitude differential signal that is not a fixed pattern such as the clock signal CK, and this differential signal is advantageous for an EMI generation source. Further, the number of signals is reduced by half from the configuration example shown in FIG. 3, which is very useful for saving area, number of pins, and total EMI energy. That is, in the configuration example shown in FIG. 6, a total of four signals, one clock signal and three data signals, are transmitted as two pairs of differential signals.

Signals S0 and S1 which is transmitted, CD than the amplitude according to a table shown in FIG. 8 described above, CD1, signals CD2 and _{D 0} is the inverse transform by the reception circuit 16, 17. The inversely converted signal D ₀ is the transmitted signal D ₀ itself. The inverse transformed signal _{D 0} and CD, CD1, CD2 is calculated by the exclusive OR circuit 18, 19, 20 As a result, the transmitted clock signal CK and the data D1, D2 are reproduced.

In this way, according to another configuration example (configuration example shown in FIG. 6) of the present embodiment, the clock signal CK and the plurality of data signals D ₀ , D ₁ , D ₂ are transmitted by several pairs of differential signals. This is not a regular signal such as the clock signal CK, but reduces the spectrum peak and the number of signals. Here, the number of signals can be realized by a differential signal pair that is half the total number of signals to be transmitted.

  Next, an example of a DC balance improvement technique for AC coupled transmission in the signal transmission system according to the embodiment of the present invention will be described. FIG. 11 is an explanatory diagram showing an example in which the DC balance improvement technique is applied to the configuration example shown in FIG. 1 of the signal transmission method according to the present embodiment. As described so far, according to this embodiment, since the transmission of the clock signal itself is eliminated, an effect of reducing EMI can be expected. Data is basically a random signal. However, in the present embodiment, the transmission signal is based on the generation of transmission data by exclusive OR operation of the clock and data. Therefore, when the same data pattern of “0” and “1” as the clock signal continues ( In the meantime, the transmission signal is a DC output (see the pattern similarity between D and CK in FIG. 11 (1)). The pattern at this time is illustrated in FIG. There is no problem when transmission and reception are directly connected, but it is a problem when adapting to AC coupling.

Therefore, in the present embodiment, a signal transmission method that allows AC coupling even in such a case is shown. An example adapted to the case of FIG. 11 (1) is shown in FIG. 11 (2). This application example is a case where 2 bits of “0” data are inserted for every 4 bits of data for explanation. As shown in FIG. 11 (2), (see _{S 0} in FIG. 11 (2)) by inserting a successive "0" data of 2bit, since always data inversion of 1bit is inserted, at least DC pattern Can be suppressed to 5 bits or less. The same operation can be achieved by inserting 2-bit continuous “1” data.

  FIG. 12 is an explanatory diagram showing an example in which the DC balance improvement technique is applied to the other configuration example shown in FIG. 3 in the signal transmission method according to the present embodiment. The signal timing and signal waveform shown in FIG. 12 (1) are the cases where no data is inserted. Similar to the example of FIG. 11A, the intermediate signal CD becomes a continuous pattern (DC signal) of “0”. When this is converted into a multi-value differential transmission signal by multi-value conversion as shown in FIG. 4, the signal waveform shown by the solid line and broken line of S in FIG. The transmission signal is not a DC signal. However, in the case of transmission by AC coupling, if such a pattern continues for a long time, the level is balanced and a waveform as shown by S (AC) in FIG. As a result, the multi-value (amplitude) information of the signal is lost, and there is a problem that correct information cannot be transmitted.

  Even in such a case, by adopting the configuration shown in the example of the DC balance improvement method relating to the present embodiment (adding two or more continuous data of 0 or 1 for every N signals of the data signal). This problem can be solved. As in the case of FIG. 11, 2-bit continuous “0” data is inserted every 4 bits of data. As a result, the transmitted signal has a waveform as shown in FIG. 12 (2) (see waveform S). The signal transmitted by the inserted data changes from a simple binary amplitude continuous pattern to a signal pattern having a plurality of amplitude values, and it is possible to suppress level fluctuations when AC coupling is used.

  Next, a skew control circuit installed for stable reception on the receiving side of the signal transmission method according to the embodiment of the present invention will be described below with reference to FIGS. FIG. 9 is a diagram showing the timing and waveform of each signal in a configuration example including a skew control circuit installed for stable reception on the receiving side of the signal transmission method according to the present embodiment. FIG. 10 is a diagram showing a configuration example including a skew control circuit installed for stable reception on the receiving side of the signal transmission method according to the present embodiment.

  The configuration example shown in FIG. 10 is obtained by applying a skew control circuit to the other configuration example of the present embodiment shown in FIG. The configuration example illustrated in FIG. 10 illustrates a portion after the receiving unit of the transmission circuit in FIG. 3.

  In FIG. 10, reference numeral 21 denotes a skew control circuit, and various proposals have been generally made. In this embodiment, such a skew control circuit is applied to ensure a skew margin of the reproduced clock signal CK and to ensure It is to be able to capture various data. For example, as an example of the skew control circuit 21, a PLL that locks to the multiplication in synchronization with the reproduced clock signal is used, and a sampling timing corresponding to the multiplication is generated in one period of the reproduction clock to determine the data. There is a method of securing a skew margin by sampling. In FIG. 10, a sampling clock 22 is generated as an output of the skew control circuit 21, and this clock 22 is applied to the D / FF circuit 23.

  The clock, data recovery, and skew adjustment of this embodiment will be described with reference to the timing chart of each signal shown in FIG. As described above, the data signal D and the clock signal CK are superimposed on the multilevel differential signal S, and a signal as shown in the uppermost stage of FIG. 9 is transmitted. Since the amplitude is transmitted as multi-value information, the signal is determined based on the levels of VrefU, VrefC, and VrefD as shown in FIG. In the present embodiment, when the signal is higher than VrefU, D and CD (internal signals) are set to “1”. When VrefC is between VrefU, D is “1”, CD is “0”, between VrefC and VrefD, D is “0”, CD is “1”, and when below VrefU, both D and CD Set to “0”.

  The D and CD signals decoded in this way are as shown in the timing chart (see FIG. 5). As described above, D is a transmitted data signal. The clock signal CK is output by an exclusive OR operation of D and CD. The calculation result is shown in FIG. As can be seen from FIG. 9, a periodic clock signal is reproduced (see FIGS. 3, 4 and 5).

  The reproduced data signal D is sampled by the reproduced clock signal CK. For this reason, data can be reliably sampled by sampling at a stable point of the data signal D (sampling by the sampling clock 22) by the skew control circuit 21 as described above. The timing explanation is as shown in the figure. Data is sampled by a sampling clock 22 (see the waveform diagram at the bottom of FIG. 9) whose skew is adjusted from the reproduction clock CK.

  As described above, the gist of the embodiment of the present invention is intended to solve the following problem, and presents a problem solving means for that purpose, and is characterized by its effects. In other words, the bandwidth of signals to be transmitted tends to increase with the improvement of digital TV image quality, and the current system is approaching the limits of the number of signals, clock skew, etc. LSI power consumption, chip surface properties Both increase and become a cause of noise generation such as EMI. Therefore, in the present embodiment, an attempt is made to realize a differential signal transmission system that generates less EMI noise while securing an increased digital video signal transmission with a smaller number of signal lines and a skew margin.

  To solve this problem, the clock signal is randomized by taking an EXOR of the signal to be transmitted and the clock signal is randomized, and the EMI is reduced by the transmission of converted data that can be easily recovered by the inverse conversion by EXOR on the receiving side. To do. Further, the data signal and clock signal obtained by this conversion method are amplitude multiplexed and transmitted. Similarly, in the case of a plurality of signal lines and one clock, an EXOR signal is generated by one data signal, the remaining data signal, and the clock, and one data signal and an EXOR generated difference having a binary amplitude is generated. In addition, a differential signal having a binary amplitude is generated by combining two EXOR-generated signals with the remaining signals, and the generated differential signals are transmitted.

  By adopting such a solution, it is possible to configure clock superimposition with a simple logical operation, and redundant data for encoding is not required. Also, the clock recovery circuit can be configured with simple logic operations, and the circuit scale and power consumption can be reduced. In addition, by superimposing the clock with such a simple configuration, the clock signal becomes a random pattern, and the spectrum having a peak in the characteristic frequency that causes EMI noise can be reduced. In addition, the number of signals can be reduced by using a multiplexed differential signal with binary amplitude, and a small area and low power consumption can be realized.

It is a figure which shows the structural example of the signal transmission system which concerns on embodiment of this invention. It is a figure which shows the signal timing of the transmission system shown in FIG. 1, and the waveform of a differential output signal. It is a figure which shows the other structural example of the signal transmission system which concerns on embodiment of this invention. It is a figure which shows the table explaining the multi-value signal conversion of the transmission system shown in FIG. It is a figure which shows the signal timing of the transmission system shown in FIG. 3, and the waveform of a binary differential output signal. It is a figure which shows another structural example of the signal transmission system which concerns on embodiment of this invention. It is a figure which shows the signal timing of the transmission system shown in FIG. 6, and the waveform of a binary differential output signal. It is a figure which shows the table explaining the multi-value signal conversion of the transmission system shown in FIG. It is a figure which shows the timing and waveform of each signal in the structural example containing the skew control circuit installed in order to receive stably in the receiving side of the signal transmission system which concerns on this embodiment. It is a figure which shows the structural example containing the skew control circuit installed in order to receive stably in the receiving side of the signal transmission system which concerns on this embodiment. It is explanatory drawing which shows an example which applied the DC balance improvement method with respect to the structural example shown in FIG. 1 in the signal transmission system which concerns on this embodiment. It is explanatory drawing which shows an example which applied the DC balance improvement method with respect to the other structural example shown in FIG. 3 in the signal transmission system which concerns on this embodiment. It is a figure explaining the signal transmission in the structural example of the differential signal transmission system regarding a prior art.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Exclusive OR 2,3 Differential signal output circuit 4,5 Differential signal receiving circuit 6 Exclusive OR 7 Exclusive OR 8 Binary (amplitude) differential signal output circuit 9 Binary differential signal receiving circuit 10, 11, 12, 13 Exclusive logical sum 14,15 Binary (amplitude) differential signal output circuit 16,17 Binary differential signal receiving circuit 18,19,20 Exclusive logical sum 21 Skew control circuit 22 Sampling clock 23 D / FF circuit CK Clock signal CD Internal signal S, S0, S1 Differential signal D0, D1, D2 Data signal VrefU, VrefC, VrefD Amplitude threshold level

Claims (3)

In a signal transmission system that transmits logical data by two differential signals, positive and negative,
The clock signal and data signal are each transmitted as a differential signal using different signal line pairs,
The data signal is transmitted as two differential signals, positive and negative, and the clock signal is transmitted as an exclusive OR signal with the data signal as a differential signal. In claim 1 ,
2. A signal transmission system characterized by adding two or more continuous data of 0 or 1 for every N number of data signals . In claim 1 ,
A skew control circuit that outputs a sampling clock signal based on the recovered clock signal is provided on the receiving side in the transmission of the differential signal,
A signal transmission system characterized in that sampling is performed at a stable point of the data signal by a sampling clock signal from the skew control circuit .

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