JP5043058B2 - Power supply - Google Patents

Description

  The present invention relates to a power supply device that converts an input voltage into a desired voltage and outputs the desired voltage.

  In recent years, in consideration of the environment, in power supply devices, low power consumption during standby (so-called low power consumption operation) has been regarded as important as much as satisfying operation specifications during normal operation. .

  Conventionally, in the above power supply apparatus, a single power supply apparatus is provided with a plurality of power supply circuits having mutually different characteristics in order to satisfy the operation specifications during normal operation and to realize low power consumption during standby. A configuration is known in which the plurality of power supply circuits are switched depending on whether the operation is normal operation or standby (see Patent Document 1).

  Specifically, particularly in the field of mobile devices such as mobile phone terminals, in order to reduce the power consumption of the devices, the operating specifications required during standby have become very strict. Yes. The reason for this is that high power supply capability and high-speed response are required to execute various applications during normal operation, while in standby mode when low power consumption operation is performed, it is contrary to normal operation. Depending on the specifications required.

  Here, the power supply device 100 disclosed in Patent Document 1 includes two voltage conversion circuits 110 for both satisfying the operation specifications during normal operation and reducing the power consumption during standby. And 120 (see FIG. 6). One of the voltage conversion circuits 110 and 120 satisfies the above operating specifications during normal operation. The other of the voltage conversion circuits 110 and 120 can achieve low power consumption by satisfying the minimum necessary operation specifications that can support low power consumption operation with respect to the output voltage and power supply capability. The power supply apparatus 100 has a configuration in which the voltage conversion circuits 110 and 120 can be switched by a selection circuit 150.

  However, the power supply apparatus 100 is merely a configuration in which the voltage conversion circuits 110 and 120 having different characteristics are integrated into one chip. In the power supply apparatus 100 having the configuration, the output voltage offset There arises a problem such as the occurrence of variations.

  Therefore, in order to solve the above problems such as variations in the offset of the output voltage, Patent Document 2 discloses a configuration in which the differential input portion of each amplifier constituting the differential circuit is shared. Yes.

  In the power supply device disclosed in Patent Document 2, the control circuit to the differential circuit and the circuit from the differential circuit to the subsequent circuit are switched by switching the first and second amplifiers that share the differential input unit. Therefore, the transistors constituting the input stage of the differential circuit can be used for both normal operation and standby. As a result, compared to the conventional technology in which a plurality of power supply circuits are simply switched, the circuit constituting the differential input unit is shared both during normal operation and during standby, thereby reducing variations in output voltage offset. It becomes feasible.

  Specifically, the power supply device disclosed in Patent Document 2 is a technique that achieves high-speed response during transmission and reception, high ripple rejection, and low current consumption during standby. This will be described with reference to FIG.

  FIG. 7 is a diagram illustrating a circuit configuration of the power supply device disclosed in Patent Document 2. In FIG.

  Hereinafter, for convenience, a p-channel MOS (Metal Oxide Semiconductor) transistor is referred to as a p-transistor, and an n-channel MOS transistor is referred to as an n-transistor.

  In the power supply device 10 shown in FIG. 7, the n transistors M <b> 1 to M <b> 3 constituting the differential input unit are shared by the first amplifier 21 and the second amplifier 22. In the control operation of the power supply device 10 having such a configuration, there are two operation modes, a normal operation and a low power consumption operation (standby operation).

  First, the control operation of the power supply device 10 during normal operation will be described.

  The polarities of the switches SW1 to SW3 during normal operation are SW1 = ON, SW2 = OFF, and SW3 = OFF, respectively. Note that one end of the switch SW1 is commonly connected to the source terminals of the p-transistors M11 to M14, and the other end is connected to a power supply line to which the input voltage Vin is applied. In addition, one end of the switch SW2 is commonly connected to the source terminals of the p transistors M21 to M23, and the other end is connected to the power supply line. Furthermore, one end of the switch SW3 is connected to the control circuit 25 via the inverter 26, and the other end is connected to the gate terminal of the n transistor M24.

  A reference voltage source 23 is connected to the gate terminal of the n transistor M1. An output voltage monitor point is connected to the gate terminal of the n-transistor M2, and the potential of the output voltage monitor point is the detection voltage Vs. Note that the detection voltage Vs is obtained by setting the output voltage VOUT so that it becomes equal to the reference voltage Vr from the reference voltage source 23 when the output voltage VOUT reaches the target voltage (resistance value of the resistor R1): (resistance This is a voltage obtained as a result of voltage division by the resistance value of R2. The source terminals of the n transistors M1 and M2 are commonly connected to the drain terminal of the n transistor M3. The n-transistor M3 has a gate terminal connected to the bias power supply 24 and operates as a constant current source.

  The p-transistor M11 has a drain terminal connected to the drain terminal of the n-transistor M1, and the p-transistor M13 has a drain terminal connected to the drain-terminal of the n-transistor M2. Also, it has a so-called diode connection configuration in which its gate terminal and drain terminal are connected. Further, the gate terminal of the p transistor M11 is connected to the gate terminal of the p transistor M12, and the gate terminal of the p transistor M13 is connected to the gate terminal of the p transistor M14.

  That is, the p-transistors M11 and M12 and the p-transistors M13 and M14 each have a current mirror structure. When the current mirror ratio in each current mirror structure is 1: 1, each p-transistor The current values flowing through M11 and p-transistor M12 are equal to each other, and the current values flowing through p-transistor M13 and p-transistor M14 are equal to each other. With this configuration, the current flowing through the n-transistor M1 constituting the differential input section flows through the p-transistor M11 and the p-transistor M12 and the n-transistor M15 whose drain terminal is connected to the drain terminal of the p-transistor M12. .

  The n-transistor M15 has the above diode-connected configuration in which its gate terminal and drain terminal are connected in the same manner as the p-transistors M11 and M13, and the gate terminal of the n-transistor M15 is connected to the n-transistor M16. Connected to the gate terminal. Therefore, the n transistors M15 and M16 have a current mirror structure, and when the current mirror ratio in the current mirror structure is 1: 1, the current value flowing through the n transistor M15 and the n transistor M16 is still the same. Become equal to each other. Further, when the current mirror ratio in the n transistors M15 and M16 is 1: 1, the current values flowing in the n transistor M1 and the n transistor M16 are equal to each other, and the current flowing in the n transistor M2 is the p transistor. It flows to the p-transistor M14 via M13. The drain terminals of the p-transistor M14 and the n-transistor M16 are connected to the gate terminal of the p-transistor M0 that is an output control transistor, and power is supplied from the n-transistor M16 to the output terminal Tout via the p-transistor M0. Is called.

  Here, in the power supply device 10, when the output voltage VOUT becomes low during normal operation, the gate voltage (detection voltage Vs) of the n transistor M2 becomes lower than the gate voltage (reference voltage Vr) of the n transistor M1. For this reason, the current flowing through the n transistor M2 is smaller than the current flowing through the n transistor M1. As a result, the current flowing through the n transistor M16 is larger than the current flowing through the p transistor M14. Then, the potential of the node drops so that the node to which the p transistor M14 and the n transistor M16 and the gate terminal of the p transistor M0 are connected approaches the ground level (potential). As a result, the p-transistor M0 becomes conductive and compensates for the shortage of the low output voltage VOUT (that is, increases the output voltage VOUT).

  On the other hand, when the output voltage VOUT applied to the output terminal Tout during the normal operation reaches the target voltage and becomes higher than the target voltage, the operation principle is opposite to the case where the output voltage VOUT becomes low. . That is, since the current flowing through the n transistor M1 is smaller than the current flowing through the n transistor M2, the current flowing through the n transistor M16 is smaller than the current flowing through the p transistor M14. Then, the potential of the node rises so that the node to which the p-transistor M14 and the n-transistor M16 are connected to the gate terminal of the p-transistor M0 approaches the input voltage Vin in the power supply device 10. As a result, the p-transistor M0 is rendered non-conductive, and an excess of the output voltage VOUT that is increased is compensated by a current flowing through the load and feedback resistor (not shown) (that is, the output voltage VOUT is lowered).

  As described above, in the power supply device 10, during normal operation, feedback control is performed so that the output voltage VOUT becomes the target voltage, whereby the input voltage Vin is converted into a desired voltage, and the desired voltage is not shown. It can be supplied to the load.

  Next, the control operation of the power supply device 10 during the low power consumption operation will be described.

  The polarities of the switches SW1 to SW3 during the low power consumption operation are SW1 = OFF, SW2 = ON, and SW3 = ON, respectively.

  During the low power consumption operation, unlike the normal operation, the p transistors M11 and M13 do not function, but the p transistor M21 whose drain terminal is connected to the drain terminal of the n transistor M1, and the drain terminal is the drain of the n transistor M2. The p-transistor M22 connected to the terminal functions. The p-transistors M21 and M22 have the current mirror structure in which the gate terminals are connected to each other, and the gate terminal and the drain terminal are connected to each other, and therefore flow into the n-transistor M1. A current flows to the p-transistor M22 via the p-transistor M21. Therefore, a current corresponding to the potential difference between the gate terminals of the n transistors M1 and M2 flows through the node to which the drain terminals of the p transistor M22 and the n transistor M2 are connected. The node is connected to the gate terminal of the p-transistor M23, the drain terminal of the p-transistor M23 and the drain terminal of the n-transistor M24 are connected, and each drain of the p-transistor M23 and the n-transistor M24 is connected. The node to which the terminal is connected is connected to the gate terminal of the p-transistor M0. Since the switch SW3 is conductive, the gate terminal of the n transistor M24 is connected to the control circuit 25 via the inverter 26. Finally, as in the normal operation state, power is supplied to the output terminal Tout via the p-transistor M0.

  Here, in the power supply device 10, when the output voltage VOUT becomes low during the low power consumption operation, the gate voltage of the n transistor M2 becomes lower than the gate voltage of the n transistor M1 as in the normal operation. For this reason, the current flowing through the n transistor M2 is smaller than the current flowing through the n transistor M1. As a result, the current flowing through the p-transistor M22 is larger than the current flowing through the n-transistor M2. A node to which the p-transistor M22 and the n-transistor M2 are connected becomes the input voltage Vin. Then, the p-transistor M23 becomes non-conductive, the gate voltage of the p-transistor M0 becomes the ground potential by the n-transistor M24 which is a constant current source, the p-transistor M0 becomes conductive, and the shortage of the low output voltage VOUT is reduced. Compensate (that is, increase the output voltage VOUT). When the output voltage VOUT becomes high during the low power consumption operation, the p-transistor M0 becomes non-conductive as in the normal operation, and the output is increased due to the current flowing through the load (not shown) and the feedback resistor. The excess of the voltage VOUT is compensated (that is, the output voltage VOUT is lowered).

  As described above, the power supply apparatus 10 converts the input voltage Vin into a desired voltage by performing feedback control so that the output voltage VOUT becomes the target voltage during the low power consumption operation, and loads the desired voltage to the load. It is the structure which can be supplied to.

Japanese Patent Laid-Open No. 11-353040 (released on December 24, 1999) JP 2005-242704 A (published September 8, 2005)

  However, in the power supply device disclosed in Patent Document 2, it is necessary to operate separate transistors during normal operation and during low power consumption driving. For this reason, in the power supply device, due to the manufacturing variation for each transistor, the output voltage offset also varies, which causes a problem that it is difficult to stably supply power.

  That is, in the power supply device disclosed in Patent Document 2, the p-transistors M11 and M13 and the p-transistor M21 are connected to the n-transistors M1 and M2 constituting the input differential unit, and the p-transistors M11 and M13 constitute different differential circuits. And M22 are physically switched using the switches SW1 and SW2.

  Here, the p-transistors M11, M13, M21, and M22, each of which is a component of the differential circuit, have the same characteristics of each transistor (hereinafter referred to as “ensuring pairing”). Required. If the securing of the pair is incomplete, the differential circuit composed of the p transistors M11 and M13 and the differential circuit composed of the p transistors M21 and M22 have different characteristics. For this reason, variations in the offset of the output voltage occur, and it becomes difficult for the power supply device to obtain desired characteristics. Therefore, in particular, when mass-producing the power supply device, there is a high possibility that a large variation in process parameters occurs for each power supply device, and the power supply device supplies stable power with the occurrence of the variation. It becomes difficult.

  Of the transistors to be connected to the drain terminals of the n transistors M1 and M2, the p-transistor M22 connected to the n transistor M2 does not have the diode connection configuration during the low power consumption operation. For this reason, the gate terminal of the p-transistor M22 becomes a terminal where the bias voltage (bias point) fluctuates greatly. The fluctuation of the gate bias voltage also causes variations in the offset of the output voltage.

  The present invention has been made in view of the above-described problems, and an object of the present invention is to provide a power supply device that can further suppress variations in offset of the output voltage and can stably supply power. There is.

  In order to solve the above-described problem, the power supply device according to the present invention outputs an output circuit that generates an output voltage according to a difference voltage between a detection voltage obtained from the output voltage and a predetermined reference voltage. And a differential circuit that generates and outputs a drive voltage for driving the output circuit so that the voltage has a desired voltage value, the drain terminal being connected to the output circuit. A first transistor having a drain terminal connected to the drain terminal of the first transistor and a gate terminal connected to a driving voltage output line from which the differential circuit outputs the driving voltage. And a switching circuit provided between the gate terminal of the first transistor and the drive voltage output line, and the switching circuit connects the gate terminal of the first transistor to the driving circuit. A pressure output line, whether or not to connect, and characterized in that for switching in accordance with the operating conditions of the power supply.

  According to the above configuration, in the power supply device, whether the gate terminal of the first transistor is connected to the drive voltage output line according to the operation state (whether the operation is normal operation or low power consumption operation). Whether or not is switched by a switching circuit. Specifically, when the gate terminal of the first transistor is connected to the drive voltage output line, both the first and second transistors function, and at this time, a high level drive voltage and a large current can be handled. Therefore, it is suitable for the normal operation where high power supply capability and high-speed response are required. In addition, when the gate terminal of the first transistor is not connected to the drive voltage output line, the second transistor functions, while the first transistor does not function, and at this time, the current flowing to the output circuit can be reduced. It is suitable for the low power consumption operation.

  That is, the power supply device can be switched between the normal operation and the low power consumption operation by the first and second transistors and the switching circuit, and thus, in the differential circuit and the output circuit, There is no need to operate separate transistors to perform the switching. Therefore, in the power supply apparatus, it is possible to suppress the variation in the offset of the output voltage and perform stable power supply more than the power supply apparatus disclosed in Patent Document 2.

  In addition, this power supply device is the structure which switches whether the 1st transistor is made to function, with the 2nd transistor functioned. According to this structure, both the 1st transistor and the 2nd transistor function. There is no period during which the operation of the power supply device becomes discontinuous due to switching by the switching circuit. In this case, in this power supply device, a stable power supply is performed at the timing at which the operation of the first transistor handling the drive voltage and current is stabilized, that is, at the timing before the operation status is switched and after the operation status is switched. An effect can be obtained.

  Further, in order to solve the above problem, the power supply device according to the present invention, according to the output circuit that generates the output voltage, and the difference voltage between the detection voltage obtained from the output voltage and a predetermined reference voltage, And a differential circuit that generates and outputs a drive voltage for driving the output circuit so that the output voltage has a desired voltage value, and a drain terminal is connected to the output circuit. The first transistor being connected, the second transistor having a drain terminal connected to the drain terminal of the first transistor, the gate terminal of the first transistor, and the driving for the differential circuit to output the driving voltage. A first switching circuit provided between the voltage output lines, a second switching circuit provided between the gate terminal of the second transistor and the drive voltage output line, and 1 cut The circuit switches whether to connect the gate terminal of the first transistor to the drive voltage output line according to the operating state of the power supply device. The second switching circuit includes the second transistor. Whether to connect the gate terminal to the drive voltage output line is switched according to the operating condition of the power supply device.

  According to the above configuration, in the power supply device, in addition to the switching by the first switching circuit having the same function as the switching circuit, the gate terminal of the second transistor is connected to the drive voltage output according to the operating situation. Whether or not to connect to the line is switched by the second switching circuit. Specifically, when the gate terminal of the second transistor is not connected to the drive voltage output line, a configuration in which the second transistor does not function can be realized. This power supply device is configured to switch whether or not the first and second transistors are to function. According to this configuration, the operation of the power supply device is discontinuous due to the switching by the switching circuit described above. A period occurs. In this case, since the power supply device can sufficiently reduce the drive voltage and current once at the timing of the switching, a large effect of stably supplying power at the timing of the switching is obtained. be able to.

  In the power supply device according to the present invention, the first and second switching circuits connect only one of the gate terminal of the first transistor and the gate terminal of the second transistor to the drive voltage output line. As described above, the switching is controlled.

  According to said structure, the said power supply device is a structure which switches whether a 1st transistor is functioned, or a 2nd transistor is functioned, According to this structure, a 1st transistor and a 2nd transistor are substantially set. Therefore, there is no period in which neither of the above functions, so that it is possible to obtain a great effect of supplying stable power.

  The power supply apparatus according to the present invention further includes a third transistor having a drain terminal connected to the drain terminal of the first transistor and a gate terminal connected to the drive voltage output line. It is said.

  When only one of the gate terminals of the first and second transistors is connected to the drive voltage output line, the period in which both the first and second transistors do not function, that is, the period in which there is no transistor that handles the drive voltage May occur. Here, in many cases, the period is not assumed in the power supply apparatus. Therefore, when the period occurs, an unexpected malfunction may occur in the power supply apparatus.

  Therefore, according to the above configuration, the drain terminal is connected to the output circuit from the drain terminal of the first transistor separately from the first and second transistors, and the gate terminal is connected to the drive voltage output line. A third transistor. Since the third transistor handles the drive voltage regardless of the operating state, the generation of the period that is theoretically not assumed in the power supply device is avoided by further including the third transistor. It becomes possible.

  The power supply device according to the present invention is characterized in that a maximum current value that can be output is limited by supplying at least one of the first and second transistors to which a constant current is supplied. It is said.

  According to the above configuration, in the transistor in which the maximum current value that can be output is limited, the current value is limited to be small with respect to the gate voltage, so that the gain of the transistor in the high-frequency band is reduced. The output voltage can be stabilized.

  Also, the power supply device according to the present invention is characterized in that the first transistor has a maximum output current value larger than that of the second transistor.

  According to the above configuration, a desired output voltage can be generated using the first transistor even when the second transistor is not used. However, in this configuration, it is not essential not to use the second transistor.

  The power supply device according to the present invention further includes a phase adjustment circuit that adjusts a phase of the output voltage, and the phase adjustment circuit is provided between the drain terminal of the first transistor and the drive voltage output line. It is characterized by being connected.

  According to the above configuration, since the phase adjustment circuit adjusts the phase of the output voltage, the output voltage can be further stabilized.

  The power supply device according to the present invention further includes a load connected to the output circuit, and the load is separable from the output circuit according to an operation state of the power supply device. It is said.

  According to said structure, the output voltage from the said output circuit can be further stabilized by connecting the load separable with respect to an output circuit to an output circuit by the said normal operation especially.

  As described above, the power supply device according to the present invention includes an output circuit that generates an output voltage, and the output voltage is a desired voltage according to a difference voltage between a detection voltage obtained from the output voltage and a predetermined reference voltage. A differential circuit that generates and outputs a drive voltage for driving the output circuit so as to be a value, and a first transistor whose drain terminal is connected to the output circuit; The drain terminal is connected to the drain terminal of the first transistor, and the gate terminal is connected to the driving voltage output line from which the differential circuit outputs the driving voltage; and the first transistor A switching circuit provided between a gate terminal of the transistor and the drive voltage output line, and the switching circuit connects the gate terminal of the first transistor to the drive voltage output line, Whether connection to, those for switching in accordance with the operating conditions of the power supply.

  Further, the power supply device according to the present invention includes an output circuit that generates an output voltage, and the output voltage has a desired voltage value according to a difference voltage between a detection voltage obtained from the output voltage and a predetermined reference voltage. And a differential circuit that generates and outputs a drive voltage for driving the output circuit, the drain terminal having a first transistor connected to the output circuit, and a drain The terminal is provided between the second transistor connected to the drain terminal of the first transistor, the gate terminal of the first transistor, and the drive voltage output line from which the differential circuit outputs the drive voltage. And a second switching circuit provided between the gate terminal of the second transistor and the drive voltage output line, wherein the first switching circuit includes the first transistor. The second switching circuit switches whether the gate terminal of the second transistor is connected to the driving voltage output line according to the operating state of the power supply device. Whether to connect to the voltage output line is switched according to the operation status of the power supply device.

  Therefore, it is possible to further suppress the variation in the offset of the output voltage and to perform stable power supply.

It is a circuit diagram which shows the structure of the power supply device which concerns on one embodiment of this invention. It is a circuit diagram which shows the structure of the phase compensation circuit which concerns on this invention. It is a circuit diagram which shows the structure of the load concerning this invention. It is a circuit diagram which shows the structure of the power supply device which concerns on another embodiment of this invention. It is a circuit diagram which shows the structure of the power supply device which concerns on another embodiment of this invention. It is a circuit diagram which shows the structure of the power supply device which concerns on a prior art. It is a circuit diagram which shows the structure of the power supply device which concerns on another prior art.

  The form for implementing this invention is demonstrated with reference to FIGS.

  In order to solve the above-described problem, the power supply device of the present invention shown in FIG. 1, FIG. 4, and FIG. 5 is a transistor that constitutes the differential circuit 107 and is connected to the p-transistor M108. With respect to the n-transistor M111 connected to the transistor M110 and the p-transistor M109, during normal operation where high power supply capability and high-speed response are required, and during low-power consumption operation where low power consumption is required The same transistor is used. Specifically, in the power supply device of the present invention, the gate terminal of the n-transistor M103 of the drive circuit 108 to be used in normal operation is connected to the drive voltage output line L101 for the differential circuit 107 to output the drive voltage Vd. Depending on whether or not they are connected, the power supply capability in the power supply device (the conduction period of the p-transistors M101 and M102) is determined. The offset of the output voltage Vo resulting from switching whether or not to connect the gate terminal of the n transistor M103 to the drive voltage output line L101, that is, whether or not to make the n transistor M103 function, ensures the pairing. The required transistor is not switched, and a sufficiently high gain is originally obtained in the entire power supply device (at this time, the offset of the output voltage Vo is negligibly small with respect to the gain), and more , It is small enough to be ignored and does not need to be substantially considered. Here, securing the pair means that a plurality of transistors (for example, n-transistors M110 and M111) have the same characteristics, and in particular, a plurality of transistors having a current mirror structure. In the differential circuit 107 that is driven in accordance with the relative ratio between them, the theoretical characteristics can be obtained only after the pairing of the plurality of transistors is ensured. When securing the pair characteristics, even if the same type of transistors are used, the voltage value (threshold value) at which conduction and non-conduction are switched according to the W / L ratio (ratio of channel width to length), etc. ) And IV (current-voltage) characteristics are different from each other. When the current mirror structure is configured by combining the transistors for which the pairing is not ensured and the differential circuit 107 is configured, it is difficult to obtain a desired characteristic regarding the offset of the output voltage Vo. In securing the pair property, it is necessary to make the W / L ratio, the voltage dependence characteristic, the operating temperature range, the layout arrangement relationship, and the like equal for each transistor. In the differential circuit 107 and further in the output circuit 109, the transistors required to ensure pairing are not switched. The power supply device of the present invention is the same in normal operation and low power consumption operation. Since the characteristics of the differential circuit 107 and the output circuit 109 can be obtained, the offset of the output voltage Vo can be suppressed. In the power supply device of the present invention, since the n-transistor M111 has the above-described diode connection configuration, fluctuations in the bias voltage (bias point) applied to the gate terminals of the n-transistors M110 and M111 can be suppressed. It is possible to suppress the offset (circuit offset) of the output voltage Vo due to the fluctuation. Further, the power supply device of the present invention is a circuit for improving the stability of the power supply device according to the operation state of the power supply device, which is during normal operation or low power consumption operation. By adding 101 and / or the phase compensation circuit 102, a wide circuit characteristic can be realized.

  Hereinafter, the power supply device of the present invention will be described in detail in the order of the power supply device 510 shown in FIG. 1, the power supply device 540 shown in FIG. 4, and the power supply device 550 shown in FIG.

  FIG. 1 is a circuit diagram showing a configuration of a power supply device according to an embodiment of the present invention.

  1 includes a load 101, a phase compensation circuit (phase adjustment circuit) 102, a switch (switching circuit, first switching circuit) 103, a reference voltage generation circuit 104, a mode switching circuit 105, a bias generation circuit 106, And resistors R101 and R102.

  The power supply device 510 includes twelve MOS transistors M101 to M112. Of these, M101, M102, and M106 to M109 are p-channel types (that is, p transistors), and M103 to M105, M110 M112 is an n-channel type (that is, an n-transistor).

  Further, in the power supply device 510, the p transistors M106, M108, M109 and the n transistors M110, M111 constitute a differential circuit 107. The n transistors M103 to M105, the phase compensation circuit 102, and the switch 103 constitute a drive circuit 108. The p transistors M101 and M102 constitute an output circuit 109.

  An input voltage Vi (for example, 5 V) from a power supply (not shown) is applied (supplied) to the power supply device 510 through the power supply line Lh. Note that the source terminals of the p-transistors M101, M102, M106, and M107 are connected to the power supply line Lh. The voltage applied to the drain terminal of the p-transistor M101 is an output voltage Vo (eg, 3V) that the power supply device 510 should output.

  The reference voltage generation circuit 104 is a known reference voltage source, and generates and outputs a predetermined reference voltage Vref. Since the reference voltage generation circuit 104 is connected to the gate terminal of the p transistor M109, the reference voltage Vref is applied to the gate terminal of the p transistor M109.

  The mode switching circuit 105 generates and outputs a mode switching signal (not shown) that indicates each operation status of the power supply device 510, whether the power supply device 510 is in a normal operation or a low power consumption operation. Since the mode switching circuit 105 is connected to the load 101, the phase compensation circuit 102, and the switch 103, the mode switching signal is supplied to the load 101, the phase compensation circuit 102, and the switch 103. When the mode switching signal is supplied, the load 101, the phase compensation circuit 102, and the switch 103 perform each operation according to the operation status of the power supply device 510 indicated by the mode switching signal. Details of each operation will be described later.

  Here, when the operation state of the power supply device 510 is defined by two types of normal operation and low power consumption operation, the mode switching circuit 105 uses the Low level (low level) and the mode switching signal as the mode switching signal. Any configuration that can output two types of signals, such as a logic signal composed of binary signals of high level (high level), is sufficient. The mode switching circuit 105 capable of outputting two types of signals using the logic signal can be realized with a simple and simple configuration using a logic circuit (inverter or the like), without needing to be specifically described. Therefore, detailed description is omitted. However, the mode switching circuit 105 is not limited to the configuration that outputs the binary logic signal as the mode switching signal, and an output circuit of any two types of signals that is configured to output two types of signals. Can be applied. Further, the mode switching signal may be directly supplied from the outside to the load 101, the phase compensation circuit 102, and the switch 103. In this case, the mode switching circuit 105 itself is unnecessary.

  The bias generation circuit 106 is a known bias voltage generation circuit (bias circuit), and generates and outputs a predetermined bias voltage Vb. Since the bias generation circuit 106 is connected to the gate terminals of the n transistors M105 and M112, the bias voltage Vb is applied to the gate terminals of the n transistors M105 and M112. Both of the n transistors M105 and M112 are continuously conducted (all periods in which the bias voltage Vb is supplied to the gate terminal) by continuously applying the bias voltage Vb to the gate terminal.

  Furthermore, the power supply device 510 is provided with a power supply line Ll connected to the ground (ground) potential GND inside or outside. Note that the source terminals of the n transistors M103, M105, and M110 to M112, the load 101, one end of the resistor R102, and the terminal 103c of the switch 103 are connected to the power supply line Ll.

  The gate terminals of the p-transistor M106 and the p-transistor M107 are connected to each other. The p-transistor M107 has a gate terminal, specifically, a node to which the gate terminals of the p-transistors M106 and M107 are connected, and a drain terminal. That is, the p transistors M106 and M107 have the above-described current mirror structure, and a current proportional to the current flowing through the p transistor M107 flows through the p transistor M106. Note that the ratio between the current value flowing through the p-transistor M106 and the current value flowing through the p-transistor M107 can be set to an arbitrary ratio according to the value of the input voltage Vi, for example.

  The drain terminal of the n transistor M112 is connected to the drain terminal of the p transistor M107. As described above, the bias voltage Vb from the bias generation circuit 106 is applied to the gate terminal of the n transistor M112, whereby the n transistor M112 is continuously turned on. Here, a current having a preset magnitude flows from the drain terminal of the p-transistor M107 to the conducting n-transistor M112. As a result, the p-transistor M107 supplies an arbitrary constant current to the p-transistor M106 constituting the differential circuit 107. That is, the n-transistor M112 has a function of supplying a constant current to the p-transistor M107, whereby an arbitrary constant current is output from the p-transistor M106 through the p-transistor M107.

  The differential circuit 107 specifically has the following configuration. That is, the drain terminal of the p-transistor M106 is connected to the source terminals of the p-transistors M108 and M109. The drain terminal of the p transistor M108 is connected to the drain terminal of the n transistor M110, and the drain terminal of the p transistor M109 is connected to the drain terminal of the n transistor M111. The gate terminal of the p-transistor M108 is connected to a node where the other end of the resistor R102 and one end of the resistor R101 are connected. The gate terminals of the n transistor M110 and the n transistor M111 are connected to each other. The n transistor M111 has a gate terminal, specifically, a node to which the gate terminals of the n transistors M110 and M111 are connected, and a drain terminal. That is, the n transistors M110 and M111 have the above-described current mirror structure, and a current proportional to the current flowing through the n transistor M111 flows through the n transistor M110. Note that the ratio between the value of the current flowing through the n transistor M110 and the value of the current flowing through the n transistor M111 can be set to an arbitrary ratio according to the value of the input voltage Vi, for example. Furthermore, one end of the drive voltage output line L101 is connected to a node to which the drain terminals of the p transistor M108 and the n transistor M110 are connected.

  Specifically, the drive circuit 108 has the following configuration. That is, the other end of the drive voltage output line L101 is connected to the terminal 103b of the switch 103. The gate terminal of the n transistor (second transistor) M104 is connected to the drive voltage output line L101 in parallel to the switch 103. The source terminal of the n transistor M104 is connected to the drain terminal of the n transistor M105. The drain terminal of the n transistor M104 is connected to the drain terminals of the p transistor M102 and the n transistor (first transistor) M103. The gate terminal of the n transistor M103 is connected to the terminal 103a of the switch 103. The drain terminal of the n transistor M103 is connected to the drain terminal of the p transistor M102 of the output circuit 109. The phase compensation circuit 102 is connected to the drive voltage output line L101 in parallel to the switch 103 and the n transistor M104 and at a subsequent stage from the node to which the drive voltage output line L101 and the gate terminal of the n transistor M104 are connected. In addition, each drain terminal of the p-transistor M102 and the n-transistors M103 and M104 is connected to a node to which the drain terminal is connected.

  The switch 103 is a well-known switch circuit that has three terminals 103a to 103c and performs a c-contact operation. When the terminal 103a and the terminal 103b are connected, the terminal 103a and the terminal 103c are connected. A function to switch between and according to the operation status of the power supply device 510 according to the above-described mode switching signal, that is, during normal operation or during low power consumption operation, It is a switching circuit.

  Further, as described above, the bias voltage Vb from the bias generation circuit 106 is applied to the gate terminal of the n transistor M105, whereby the n transistor M105 is continuously turned on. Here, in the n transistor M105, a current having a preset magnitude flows from the source terminal of the n transistor M104. As a result, the n-transistor M104 supplies an arbitrary constant current to the p-transistor M102 constituting the output circuit 109. That is, the n-transistor M105 has a function of supplying a constant current to the n-transistor M104, whereby the maximum current that can be output from the n-transistor M104 to the p-transistor M102 can be output. The value is limited.

  The output circuit 109 specifically has the following configuration. That is, the gate terminals of the p transistor M101 and the p transistor M102 are connected to each other. The p-transistor M102 has a gate terminal, specifically, a node to which the gate terminals of the p-transistors M101 and M102 are connected, and a drain terminal. That is, the p transistors M101 and M102 have the above-described current mirror structure, and a current proportional to the current flowing through the p transistor M102 flows through the p transistor M101. Note that the ratio between the current value flowing through the p-transistor M101 and the current value flowing through the p-transistor M102 can be set to an arbitrary ratio, for example, according to the value of the input voltage Vi.

  A load 101 and a series circuit of resistors R101 and R102 are connected in parallel between the drain terminal of the p-transistor M101 and the power supply line Ll. The other end of the resistor R101 is connected to the drain terminal of the p-transistor M101, and the load 101 is connected to the node to which the drain terminal of the p-transistor M101 and the other end of the resistor R101 are connected. .

  Here, in power supply device 510, output voltage Vo is divided by resistors R101 and R102, which are feedback resistors. The divided output voltage Vo is generated as a detection voltage Vk at a node where the resistors R101 and R102 are connected, and the detection voltage Vk is applied to the gate terminal of the p-transistor M108 connected to the node. The On the other hand, as described above, the reference voltage Vref from the reference voltage generation circuit 104 is continuously applied to the gate terminal of the p-transistor M109. Although details will be described later, according to this configuration, the differential circuit 107 generates the drive voltage Vd for setting the output voltage Vo to a desired voltage value in accordance with the detection voltage Vk. The drive voltage Vd is output from the drain terminal of the p-transistor M108 to the drive circuit 108 through the drive voltage output line L101. The voltage value of the detection voltage Vk is determined according to the resistance value ratio (feedback resistance ratio) between the resistor R101 and the resistor R102. This resistance value ratio may be set as appropriate so that the resistance values of the resistors R101 and R102 are such that the voltage value of the output voltage Vo that has reached a desired voltage value is equal to the reference voltage Vref.

  FIG. 2 is a diagram illustrating an example of a specific circuit configuration of the phase compensation circuit 102.

  2 is a series circuit of a capacitor 201, a resistor R201, and a resistor R202. The source terminal and the drain terminal of an n-transistor M201 are connected in parallel to the resistor R202 at both ends of the resistor R202. It is the composition which is. The gate terminal of the n transistor M201 is connected to the mode switching circuit 105, and the end of the resistor R202 opposite to the resistor R201 is connected to the drive voltage output line L101 (that is, the gate terminal of the n transistor M104 and the gate terminal of the n transistor M103). The end of the capacitor 201 opposite to the resistor R201 is connected to the node to which the drain terminals of the p-transistor M102 and the n-transistors M103 and M104 are connected.

  In the phase compensation circuit 102, the capacitor 201 and the resistors R201 and R202 are connected in series, and the power supply apparatus 510 is inserted so as to be connected to a circuit element having a high gain, thereby improving the stability of the power supply apparatus 510. This is a general phase compensation circuit for the purpose of achieving the above.

  Here, power supply device 510 assumes two types of operating conditions, that is, normal operation and low power consumption operation. In order to cope with the phase compensation (phase adjustment) in each of these two types of operating conditions, the phase compensation circuit 102 includes an n transistor M201 that switches between conduction and non-conduction in response to a mode switching signal from the mode switching circuit 105. By connecting in parallel with any one of the capacitor 201, the resistor R201, and the resistor R202 (here, the resistor R202), the phase compensation constant (the degree of phase adjustment) can be set in two stages, that is, one and the other described later. The phase compensation constant can be set.

  The phase compensation circuit 102 having the above-described configuration is a general phase compensation circuit that can be realized by a well-known technique, and the procedure for phase compensation (phase adjustment) using the phase compensation circuit 102 is as follows. Can be carried out by those skilled in the art using a well-known technique, and a detailed description thereof will be omitted.

  Note that the n-transistor M201 may be turned on when the power supply device 510 is in a normal operation or may be turned on when the power supply device 510 is in a low power consumption operation. Further, the drive voltage output line L101 (the gate terminal of the n-transistor M104) and the node to which the drain terminals of the p-transistor M102 and the n-transistors M103 and M104 are connected are connected to the phase compensation circuit 102. It may be replaced. Furthermore, the phase compensation circuit 102 may be configured to use two transistors in place of the resistors R201 and R202 and realize phase compensation (phase adjustment) by using the on-resistance of each of the transistors. . In the phase compensation circuit 102, the n transistor M103 is connected in parallel with the resistor R202. However, the present invention is not limited to this, and the n transistor M103 may be connected in parallel with the resistor R201, or in parallel with the capacitor 201. Needless to say, they may be connected.

  FIG. 3 is a diagram illustrating an example of a specific circuit configuration of the load 101.

  The load 101 has a configuration in which the drain terminal of the n-transistor M301 is connected to the other end of the resistor R301, and the source terminal of the n-transistor M301 is grounded (connected to the power supply line Ll). The gate terminal of the n transistor M301 is connected to the mode switching circuit 105, and one end of the resistor R301 is connected to the output circuit 109 (the drain terminal of the p transistor M101).

  The load 101 is intended to improve the operational stability of the output circuit 109 by increasing the bias current supplied between the source terminal and the drain terminal of the p-transistor M101 (see FIG. 1) during normal operation. It is a circuit provided. In other words, since it is sufficient for the load 101 to be connected to the power supply device 510 during normal operation, an n transistor is used as shown in FIG. 3 in view of further reduction in power consumption of the power supply device 510. It is preferable that the power supply device 510 is configured to be attachable and detachable by switching between M301 conduction (during normal operation) and non-conduction (during low power consumption operation) according to a mode switching signal.

  Here, in the load 101, a transistor may be used instead of the resistor R301, and the load may be configured by the on-resistance of the transistor. In the load 101, the source terminal of the n transistor M301 is connected to one end of the resistor R301, the other end of the resistor R301 is grounded (connected to the power supply line Ll), and the drain terminal of the n transistor M301 is connected. May be connected to the output circuit 109 (the drain terminal of the p-transistor M101). That is, the n transistor M301 may be provided at any part of the load 101. Furthermore, the load 101 does not need to be disconnected during the low power consumption operation as long as the current flows so that the current value can be ignored during the low power consumption operation.

  Returning to FIG. 1, the operation of the power supply device 510 in each of the normal operation and the low power consumption operation according to the operation status of the power supply device 510 will be described in detail.

  First, the operation of the power supply device 510 during normal operation will be described. In this case, the terminal 103a and the terminal 103b of the switch 103 are connected by the mode switching signal from the mode switching circuit 105, whereby the gate terminal of the n-transistor M103 is connected to the drive voltage output line L101, and the load 101 is The n transistor M301 (see FIG. 3) is connected to the power supply device 510 when the n transistor M301 (see FIG. 3) is turned on, and the phase compensation circuit 102 is set to one phase compensation constant when the n transistor M201 (see FIG. 2) is turned off. The

  When the output voltage Vo is lower than a desired voltage value during normal operation, the detection voltage Vk applied to the gate terminal of the p-transistor M108 in the differential circuit 107 is applied to the gate terminal of the p-transistor M109. It becomes a level lower than the reference voltage Vref. At this time, the current flowing through the p-transistor M109 becomes smaller than the current flowing through the p-transistor M108, and the value of the current flowing through the n-transistors M110 and M111 having the current mirror structure is lowered. As a result, the voltage level at the node to which the drain terminals of the p-transistor M108 and the n-transistor M110 are connected increases, and as a result, the level of the drive voltage Vd output from the node increases to a level close to the input voltage Vi. Retained. Since the gate terminal of the n transistor M103 is connected to the drive voltage output line L101, the drive voltage Vd is applied to the gate terminals of the n transistors M103 and M104 and the phase compensation circuit 102.

  Here, due to the above-described function of the n-transistor M105, a constant current is supplied to the n-transistor M104, and the maximum current value that can be output from the n-transistor M104 is limited. Therefore, the maximum current value corresponding to the drive voltage Vd supplied from the drive circuit 108 to the output circuit 109 is determined according to the characteristics of the n transistor M103.

  The n-transistor M103 repeats conduction and non-conduction in accordance with the drive voltage Vd supplied to the gate terminal, but is held at a high level when the output voltage Vo is lower than a desired voltage value. The n-transistor M103 is continuously turned on by the drive voltage Vd (all periods during which the drive voltage Vd is held at a high level), and the level of the output voltage Vo increases accordingly.

  Thus, in the power supply device 510, when the output voltage Vo is lower than the desired voltage value during normal operation, the level of the output voltage Vo is increased to increase the output voltage Vo to the desired voltage value. Each of the above operations is performed.

  On the other hand, when the output voltage Vo is higher than a desired voltage value during normal operation, the detection voltage Vk applied to the gate terminal of the p-transistor M108 in the differential circuit 107 is applied to the gate terminal of the p-transistor M109. The level becomes higher than the applied reference voltage Vref. The current flowing through the p-transistor M109 becomes larger than the current flowing through the p-transistor M108, and the current value flowing through the n-transistors M110 and M111 increases. The voltage level at the node to which the drain terminals of p-transistor M108 and n-transistor M110 are connected drops, and as a result, the level of drive voltage Vd output from the node drops to a level close to the ground potential and is held. Since the gate terminal of the n transistor M103 is connected to the drive voltage output line L101, the drive voltage Vd is applied to the gate terminals of the n transistors M103 and M104 and the phase compensation circuit 102. When the output voltage Vo is higher than a desired voltage value, the n-transistor M103 is continuously (all periods during which the drive voltage Vd is held at a low level) by the drive voltage Vd held at a low level. As a result, the level of the output voltage Vo decreases.

  Thus, in the power supply device 510, when the output voltage Vo is higher than the desired voltage value during normal operation, the level of the output voltage Vo is lowered to reduce the output voltage Vo to the desired voltage value. Each of the above operations is performed.

  Although the load 101 functions during normal operation, the stability of the operation of the output circuit 109 is improved by increasing the bias current supplied between the source terminal and the drain terminal of the p-transistor. ing.

  Further, during normal operation, the phase compensation circuit 102 applies the phase defined by one of the two phase compensation constants set to the phase compensation constant to the voltage output from the drive circuit 108, thereby causing the phase deviation. To compensate.

  Examples of the phase shift include each phase difference of the drain voltage with respect to the gate voltage in n transistors M103 and M104, variation in characteristics of each transistor, and the like. By connecting the phase compensation circuit 102 shown in FIG. 2 between each gate terminal and each drain terminal of the n-transistors M103 and M104, the phase shift in the voltage output from the drive circuit 108 is simple and easy. Can compensate. As a result, the voltage output from the drive circuit 108, and hence the output voltage Vo, can be further stabilized. The same applies to the low power consumption operation described later.

  Next, the operation of the power supply device 510 during the low power consumption operation will be described. In this case, the gate terminal of the n-transistor M103 is disconnected from the drive voltage output line L101 by connecting the terminal 103a and the terminal 103c of the switch 103 by the mode switching signal from the mode switching circuit 105 (power supply line Ll). The load 101 is disconnected from the power supply device 510 when the n-transistor M301 (see FIG. 3) is turned off, and the phase compensation circuit 102 is turned off when the n-transistor M201 (see FIG. 2) is turned on. The other phase compensation constant is set.

  When the output voltage Vo is lower than a desired voltage value during the low power consumption operation, the voltage at the node to which the drain terminals of the p-transistor M108 and the n-transistor M110 are connected is the same as in the normal operation. The level rises, and as a result, the level of the drive voltage Vd output from the node rises to a level close to the input voltage Vi and is held.

  Here, since the gate terminal of the n transistor M103 is disconnected from the drive voltage output line L101, the drive voltage Vd is applied to the gate terminal of the n transistor M104 and the phase compensation circuit 102, while the n transistor M103 has Not applied to the gate terminal.

  The n-transistor M104 repeats conduction and non-conduction according to the drive voltage Vd supplied to the gate terminal, but is held at a high level when the output voltage Vo is lower than a desired voltage value. The n-transistor M104 is continuously turned on by the drive voltage Vd (all periods in which the drive voltage Vd is held at a high level), and accordingly, the level of the output voltage Vo rises.

  Thus, in the power supply device 510, when the output voltage Vo is lower than the desired voltage value during the low power consumption operation, the output voltage Vo is set to the desired voltage value by increasing the level of the output voltage Vo. For each of the above operations.

  On the other hand, when the output voltage Vo is higher than a desired voltage value during the low power consumption operation, the node to which the drain terminals of the p-transistor M108 and the n-transistor M110 are connected is the same as in the normal operation. As a result, the level of the drive voltage Vd output from the node falls to a level close to the ground potential and is held. Since the gate terminal of the n transistor M103 is disconnected from the drive voltage output line L101, the drive voltage Vd is applied to the gate terminal of the n transistor M104 and the phase compensation circuit 102, while being applied to the gate terminal of the n transistor M103. Not applied. When the output voltage Vo is higher than a desired voltage value, the n-transistor M104 is continuously (all periods during which the drive voltage Vd is held at a low level) by the drive voltage Vd held at a low level. As a result, the level of the output voltage Vo decreases.

  Thus, in the power supply device 510, when the output voltage Vo is higher than the desired voltage value during the low power consumption operation, the output voltage Vo is lowered to the desired voltage value by lowering the level of the output voltage Vo. For each of the above operations.

  The load 101 does not function during the low power consumption operation, but may function. Further, during the low power consumption operation, the phase compensation circuit 102 gives the voltage defined by the other phase compensation constant among the phase compensation constants set in two stages to the voltage output from the drive circuit 108, Compensate for phase shift. As a result, the voltage output from the drive circuit 108, and hence the output voltage Vo, can be further stabilized.

  Here, the n-transistor M104 has a constant current supplied by the n-transistor M105, so that the maximum current value that can be output is limited, and the n-transistor M103 has a gate terminal at the time of low power consumption operation. It is grounded and practically does not handle the drive voltage Vd.

  Note that the maximum current value that can be output by the n-transistor M104 is the constant current value flowing through the n-transistor M105 and the current mirror ratio (p-transistor M101 in the p-transistors M101 and M102 having the current mirror structure). The ratio of the current value flowing through the p transistor M102 and the current value flowing through the p-transistor M102).

As an example, the current value of the constant current flowing through the n-transistor M105 is a (μA), and the current mirror ratio is expressed by the following formula (1),
(Current value flowing in the p-transistor M101): (Current value flowing in the p-transistor M102) = b: 1 (1)
In this case, the maximum current value that can be output by the n-transistor M104 is a × b (μA). Since the maximum current value is limited and there is no need to increase the bias when there is no load, the power supply device 510 can achieve a low power consumption operation.

  In each of the normal operation and the low power consumption operation, the power supply device 510 performs the above-described operation in each of the case where the output voltage Vo is lower than the desired voltage value and the case where the output voltage Vo is higher than the desired voltage value. The detection voltage Vk is made constant so that the output voltage Vo is stabilized at a desired voltage value, and the output voltage Vo is set to the desired voltage value according to the difference voltage between the detection voltage Vk and the reference voltage Vref. It is said.

  The power supply device 510 that performs the above-described operations for setting the output voltage Vo to a desired voltage value using the n transistors M103 and M104 is immediately before switching between the normal operation and the low power consumption operation. Since there is no possibility that both n-transistors M103 and M104 will not be connected at the timing immediately thereafter, the stability of the output voltage can be improved.

  FIG. 4 is a circuit diagram showing a configuration of a power supply apparatus according to another embodiment of the present invention.

  A power supply device 540 illustrated in FIG. 4 includes the drive circuit 408 in place of the drive circuit 108 in the power supply device 510 illustrated in FIG. The drive circuit 408 is configured to further include a switch (second switching circuit) 403 in addition to the configuration of the drive circuit 108.

  Since the switch 403 is connected to the mode switching circuit 105, a mode switching signal is supplied. The switch 403 is a well-known switch circuit having three terminals 403a to 403c and performing a c contact operation. When the terminals 403a and 403b are connected, the terminals 403a and 403c are connected. Are switched according to the mode switching signal, that is, during normal operation or during low power consumption operation, according to the operation status of the power supply device 540. .

  The terminal 403a is connected to the gate terminal of the n-transistor M104, the terminal 403b is connected to the drive voltage output line L101, and the terminal 403c is connected to the power supply line Ll. Specifically, the terminal 403b is phase compensation between the node of the drive voltage output line L101 to which the phase compensation circuit 102 is connected and the node to which the drain terminals of the p-transistor M108 and the n-transistor M110 are connected. The circuit 102 and the switch 103 are connected in parallel. In other words, the switch 403 is provided between the gate terminal of the n transistor M104 and the drive voltage output line L101.

  The power supply device 540 is different from the power supply device 510 in that the power supply device 540 is further connected to the terminal 403a and the terminal 403c of the switch 403 by a mode switching signal from the mode switching circuit 105 in normal operation. Thus, the gate terminal of the n-transistor M104 is disconnected from the drive voltage output line L101 (connected to the power supply line Ll).

  Thus, the operation of power supply device 540 during normal operation differs from the operation of power supply device 510 during normal operation as follows.

  That is, when the output voltage Vo is lower than a desired voltage value during normal operation, the voltage at the node to which the drain terminals of the p-transistor M108 and the n-transistor M110 are connected is the same as in the power supply device 510. The level rises, and as a result, the level of the drive voltage Vd output from the node rises to a level close to the input voltage Vi and is held.

  Here, since the gate terminal of the n-transistor M104 is disconnected from the drive voltage output line L101, the drive voltage Vd is applied to the gate terminal of the n-transistor M103 and the phase compensation circuit 102. Not applied to the gate terminal.

  The n-transistor M103 repeats conduction and non-conduction in accordance with the drive voltage Vd supplied to the gate terminal, but is held at a high level when the output voltage Vo is lower than a desired voltage value. The n-transistor M103 is continuously turned on by the drive voltage Vd (all periods during which the drive voltage Vd is held at a high level), and the level of the output voltage Vo increases accordingly.

  Thus, in the power supply device 540, when the output voltage Vo is lower than the desired voltage value during normal operation, the level of the output voltage Vo is raised to increase the output voltage Vo to the desired voltage value. Each of the above operations is performed.

  On the other hand, when the output voltage Vo is higher than a desired voltage value during normal operation, the voltage at the node to which the drain terminals of the p-transistor M108 and the n-transistor M110 are connected is the same as in the power supply device 510. The level decreases, and as a result, the level of the drive voltage Vd output from the node decreases to a level close to the ground potential and is held. Since the gate terminal of the n transistor M104 is disconnected from the drive voltage output line L101, the drive voltage Vd is applied to the gate terminal of the n transistor M103 and the phase compensation circuit 102, while being applied to the gate terminal of the n transistor M104. Not applied. When the output voltage Vo is higher than a desired voltage value, the n-transistor M103 is continuously (all periods during which the drive voltage Vd is held at a low level) by the drive voltage Vd held at a low level. As a result, the level of the output voltage Vo decreases.

  Thus, in the power supply device 540, when the output voltage Vo is higher than the desired voltage value during normal operation, the output voltage Vo is set to the desired voltage value by lowering the level of the output voltage Vo. Each of the above operations is performed.

  On the other hand, in the power supply device 540, in the case of low power consumption operation, the terminal 403a and the terminal 403b of the switch 403 are further connected by the mode switching signal from the mode switching circuit 105, whereby the gate terminal of the n transistor M104 is Connected to the drive voltage output line L101. However, in this case, the operation of the power supply apparatus 540 is the same as the operation of the power supply apparatus 510 during the low power consumption operation described above, and thus the description thereof is omitted.

  That is, the power supply device 540 is different from the power supply device 510 in that the gate terminal of the n-transistor M104 is disconnected from the drive voltage output line L101 during normal operation, so that the n-transistor M104 does not handle the drive voltage Vd. The M104 does not affect the above-described operations for setting the output voltage Vo to a desired voltage value.

  In the power supply device 540, the switching using the switch 403 described above is combined with the switching using the switch 103 similar to that of the power supply device 510, and the switches 103 and 403 are configured so that the power supply device 540 is in normal operation or has low power consumption. Switching is controlled so that only one of the gate terminals of the n-transistors M103 and M104 is connected to the drive voltage output line L101 depending on whether it is in operation. Thereby, in the power supply device 540, it is possible to suppress the variation in the offset of the output voltage Vo during the normal operation and to stably supply power more than in the power supply device 510 using only the switch 103.

  That is, the same can be said for the power supply devices 510, 540, and 550. Normally, the n-transistor M103 has a maximum output current value larger than that of the n-transistor M104. Note that, as described above, the maximum current value that can be output from the n transistor M104 is limited by the n transistor M105, while the maximum current value that can be output from the n transistor M103 is the minimum value Rm of its own on-resistance. If the applied voltage is Vm, it can be increased to Vm / Rm (A). For this reason, during normal operation, a sufficiently large power driving capability can be obtained by using only the n transistor M103 without using the n transistor M104. The power supply device 540 is configured to switch the conduction and non-conduction of the n-transistor M103 in accordance with the drive voltage Vd from the differential circuit 107 and to set the output voltage Vo to a desired voltage value. When the output voltage Vo becomes stable after switching between conduction and non-conduction, the output voltage Vo at substantially the same level as the output voltage Vo during normal operation of the power supply device 510 can be obtained. The power supply device 540 that performs each of the above-described operations for setting the output voltage Vo to a desired voltage value using only one of the n-transistors M103 and M104 is a normal operation and a low power consumption operation. Since there is no possibility that both n-transistors M103 and M104 are connected at the instant of switching to the hour, the stability of the output voltage can be improved.

  FIG. 5 is a circuit diagram showing a configuration of a power supply device according to still another embodiment of the present invention.

  A power supply device 550 illustrated in FIG. 5 includes a drive circuit 508 instead of the drive circuit 408 in the power supply device 540 illustrated in FIG. 4. In addition to the configuration of the drive circuit 408, the drive circuit 508 further includes n transistors M401 and M402.

  The n transistor (third transistor) M401 has a gate terminal connected to the drive voltage output line L101, a drain terminal connected to each drain terminal of the n transistors M103 and M104, and a source terminal connected to the drain of the n transistor M402. Connected to the terminal. Specifically, the gate terminal of the n transistor M401 is between the node of the drive voltage output line L101 to which the terminal 403b is connected and the node to which the drain terminals of the p transistor M108 and the n transistor M110 are connected. The phase compensation circuit 102 and the switch 103 are connected in parallel.

  The n transistor M402 has a gate terminal connected to the bias generation circuit 106 and a source terminal connected to the power supply line Ll. The bias voltage Vb of the bias generation circuit 106 is continuously applied to the gate terminal of the n-transistor M402, whereby the n-transistor M402 is continuously applied (all periods during which the bias voltage Vb is supplied to the gate terminal). ). A current having a preset magnitude flows through the n transistor M402 from the source terminal of the n transistor M401. As a result, the n-transistor M401 supplies an arbitrary constant current to the p-transistor M102 constituting the output circuit 109. That is, the n-transistor M402 has a function of supplying a constant current to the n-transistor M401, whereby the maximum current that can be output from the n-transistor M401 to the p-transistor M102 can be output. The value is limited.

  Note that no switching circuit is connected to the gate terminal of the n-transistor M401, and the n-transistor M401 outputs a drive voltage regardless of whether the power supply device 550 is in normal operation or in low power consumption operation. According to the drive voltage Vd applied from the line L101, it switches between conduction and non-conduction.

  When only one of the gate terminals of the n transistors M103 and M104 is connected to the drive voltage output line L101 as in the power supply device 540 shown in FIG. 4, both the n transistors M103 and M104 are driven by the drive voltage Vd. There is a possibility that a period of not handling will occur. Here, in the power supply device 540, there is no transistor handling the drive voltage Vd in the drive circuit 108 in the period, and such a period is often not assumed in the power supply apparatus of the present invention. If this occurs, there is a risk that an unexpected failure may occur in the power supply device of the present invention.

  Therefore, the power supply device 550 switches between conduction and non-conduction in accordance with the drive voltage Vd applied from the drive voltage output line L101 regardless of whether it is during normal operation or low power consumption operation. It further includes an n-transistor M401 that handles the drive voltage Vd. By further including the n-transistor M401, the power supply device 550 can theoretically avoid the occurrence of the above period that is not assumed in the power supply device of the present invention.

  In the power supply device of the present invention, the gate terminal is connected to the bias generation circuit 106, the drain terminal is connected to the source terminal of the n-transistor M103, and the source terminal is connected to the power supply line Ll. The n-transistor further includes an n-transistor that has a function of supplying a constant current to the n-transistor M103, similarly to the n-transistors M105 and M402, and thereby the n-transistor M103 to the p-transistor M102. The maximum current value that can be output by the n-transistor M103 may be limited. That is, it is preferable that at least one of the n transistors M103, M104, and M401 has a maximum current value that can be output by being supplied with a constant current.

  The maximum current value is limited by inserting a resistor (not shown) between at least one of the corresponding n transistors M103, M104, and M401 and the power supply line Ll. In this case, the restriction may not necessarily use a constant current.

  The present invention is not limited to the above-described embodiments, and various modifications can be made within the scope shown in the claims. That is, embodiments obtained by combining technical means appropriately modified within the scope of the claims are also included in the technical scope of the present invention.

  The present invention relates to a power supply device that converts an input voltage into a desired voltage and outputs the desired voltage, in particular, an output circuit that generates an output voltage, a detection voltage obtained from the output voltage, and a predetermined reference voltage. And a differential circuit that generates and outputs a drive voltage for driving the output circuit so that the output voltage becomes a desired voltage value in accordance with the difference voltage between the two. An example of this type of power supply device is a power supply device for portable equipment such as a mobile phone terminal.

101 Load 102 Phase compensation circuit (phase adjustment circuit)
103 switch (switching circuit, first switching circuit)
107 differential circuit 109 output circuit 403 switch (second switching circuit)
510, 540, 550 Power supply device L101 Drive voltage output line M103 n-channel MOS transistor (first transistor)
M104 n-channel MOS transistor (second transistor)
M401 n-channel MOS transistor (third transistor)
Vd Drive voltage Vo Output voltage Vref Reference voltage Vk Detection voltage

Claims (9)

An output circuit for generating an output voltage;
Generate and output a drive voltage for driving the output circuit so that the output voltage becomes a desired voltage value according to a difference voltage between a detection voltage obtained from the output voltage and a predetermined reference voltage. A power supply device comprising a differential circuit,
A first transistor having a drain terminal connected to the output circuit;
A second transistor having a drain terminal connected to the drain terminal of the first transistor and a gate terminal connected to a drive voltage output line from which the differential circuit outputs the drive voltage;
A switching circuit provided between the gate terminal of the first transistor and the drive voltage output line,
The power supply apparatus according to claim 1, wherein the switching circuit is configured to switch whether to connect the gate terminal of the first transistor to the drive voltage output line according to an operating state of the power supply apparatus. An output circuit for generating an output voltage;
Generate and output a drive voltage for driving the output circuit so that the output voltage becomes a desired voltage value according to a difference voltage between a detection voltage obtained from the output voltage and a predetermined reference voltage. A power supply device comprising a differential circuit,
A first transistor having a drain terminal connected to the output circuit;
A second transistor having a drain terminal connected to the drain terminal of the first transistor;
A first switching circuit provided between a gate terminal of the first transistor and a drive voltage output line from which the differential circuit outputs the drive voltage;
A second switching circuit provided between the gate terminal of the second transistor and the drive voltage output line;
The first switching circuit switches whether or not to connect the gate terminal of the first transistor to the drive voltage output line according to the operating state of the power supply device,
The second switching circuit is configured to switch whether to connect the gate terminal of the second transistor to the drive voltage output line according to the operating state of the power supply device. The first and second switching circuits are
The switching is controlled so that only one of the gate terminal of the first transistor and the gate terminal of the second transistor is connected to the drive voltage output line. Power supply.   4. The power supply device according to claim 3, further comprising a third transistor having a drain terminal connected to the drain terminal of the first transistor and a gate terminal connected to the drive voltage output line. .   5. The power supply device according to claim 4, wherein a maximum current value that can be output is limited by supplying a constant current to the third transistor.   6. The power supply device according to claim 1, wherein the first transistor has a maximum output current value larger than that of the second transistor. A phase adjustment circuit for adjusting the phase of the output voltage;
The power supply device according to claim 1, wherein the phase adjustment circuit is connected between a drain terminal of the first transistor and the drive voltage output line.   The at least one of the first and second transistors is limited in a maximum current value that can be output by being supplied with a constant current. The power supply described. A load connected to the output circuit;
The power supply apparatus according to any one of claims 1 to 8, wherein the load is separable from the output circuit according to an operation state of the power supply apparatus.

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