JP5029160B2 - Image display device, driving method of image display device, and driving device of image display device - Google Patents

Description

The present invention relates to an image display apparatus , an image display apparatus driving method, and an image display apparatus driving apparatus .

 2. Description of the Related Art In recent years, a laser scan display that displays an image by raster scanning beam-shaped light such as laser light on a projection surface has attracted attention as one form of an image display device. Since such a laser scan display can express complete black by stopping the supply of laser light, for example, the contrast is very high compared to a projector using a liquid crystal light valve, and the laser light is single. Because of its wavelength, its color purity is high, and its high coherence makes it easy to shape the beam (easy to squeeze), so it is expected as a high-quality display that realizes high contrast, high color reproducibility, and high resolution. Has been.

In a laser scan display that requires high-speed scanning and a large deflection angle, a resonant MEMS (Micro Electro Mechanical System) scanner is often used as a laser scanner (see Patent Document 1 below). A MEMS scanner is a reflection mirror that is formed by finely processing a semiconductor material such as single crystal silicon and supported by a torsion spring or the like. The reflection mirror is driven by electrostatic force or Lorentz force, and these external forces and torsion are driven. The laser beam is scanned by rotating the reflection mirror within a predetermined angle range by interaction with the restoring force of the spring. Since such a MEMS scanner is a resonance type scanner, there is a characteristic that the rotation angle of the reflection mirror changes sinusoidally. For this reason, for example, when focusing on the horizontal scanning direction, a phenomenon occurs in which the scanning speed of the laser light is the fastest at the center of the screen and the scanning speed of the laser light decreases toward the edge of the screen.
JP 2007-47354 A

  By the way, when analog modulation is used as the gradation expression means of the laser scan display, for example, assuming that an image of 60 frames per second is displayed with a resolution VGA, the pixel synchronization clock frequency is 18.4 (MHz). Considering that the horizontal scanning speed of the laser beam fluctuates as in the case of using the MEMS scanner of this type and that the entire time for which the rotating mirror rotates cannot be used for scanning, the maximum pixel synchronization clock frequency at the center of the screen is 50. (MHz) and so on. In other words, the laser driver that supplies the drive current to the laser diode that is the light source of the laser light needs to generate the drive current according to the gradation data that is input in synchronization with the high-speed pixel synchronization clock as described above There is.

  As a configuration of such a laser driver, a current source corresponding to each gradation is prepared, and an operation state and a non-operation state of each current source are switched at high speed according to gradation data, and a current generated in the operation state Is conceivable to output to the laser diode. However, the current source cannot switch between the operating state and the non-operating state at high speed, and a time lag occurs until the current is actually generated by switching from the non-operating state to the operating state. For this reason, conventionally, as a laser driver configuration, a configuration is adopted in which a switch controlled by gradation data is used to select whether the current of each current source maintained in the operating state is supplied to a dummy load or a laser diode. It was. However, with such a configuration, there is a problem in that power consumption increases because a current always flows through each current source.

   The present invention has been made in view of the above-described circumstances, and in the case where an image is displayed by scanning light on a projection surface, an image that can achieve low power consumption while satisfying the requirement for high-speed operation. It is an object to provide a display device, a drive signal generation circuit, and a method for driving an image display device.

In order to achieve the above object, an image display device according to the present invention includes a scanning unit that scans light generated from a light source on a projection surface, and a light irradiation position on the projection surface that receives a video signal as an input. Video signal processing means for generating a gradation signal that defines the gradation value of the corresponding pixel, a drive signal source for generating a drive signal corresponding to the gradation signal, a dummy load, and an output destination of the drive signal An image display device comprising drive signal generation means having an output changeover switch for switching to either the dummy load or the light source in accordance with an adjustment signal, while storing the video signal input from the outside A video signal storage means for outputting a video signal of a display target pixel corresponding to a current light irradiation position on the projection surface to the video signal processing means; and a video signal stored in the video signal storage means. An operation determining unit that determines whether or not the drive signal source needs to be operated after a predetermined number of pixels from the display target pixel based on the signal, and outputs a signal source operation enable / disable signal indicating the determination result; The drive signal generation means includes operation switching means for switching operation / non-operation of the drive signal source based on the signal source operation availability signal.
According to the image display device having such characteristics, it is determined whether or not the drive signal source needs to be operated after a predetermined number of pixels from the display target pixel based on the accumulated video signal that is the source of the gradation signal. Judgment is made, and the operation / non-operation of the drive signal source is switched based on the signal source operation availability signal indicating the determination result. That is, when the drive signal source needs to be operated after a predetermined number of pixels from the display target pixel in consideration of the time lag until the drive signal is actually generated by switching the drive signal source from the non-operating state to the operating state. Since the drive signal source is operated in advance and the drive signal source is switched to the non-operating state when it is not necessary to operate, it is possible to reduce the power consumption while satisfying the demand for high-speed operation.

In the image display device described above, the video signal is a digital video signal having N bits, and the video signal storage means is provided corresponding to each bit data of the digital video signal, and corresponds to each. It has first to Nth shift registers having a configuration in which bit data is input and a plurality of flip-flops are connected in series.
Provided corresponding to each of the first to Nth shift registers, and outputs a logical sum signal of the output signals of all flip-flops in the corresponding shift register as the first to Nth signal source operation enable / disable signals. And the video signal processing means inputs the output signal of the flip-flop at the final stage in the first to Nth shift registers as a digital video signal of the display target pixel. And generating a digital gradation signal of bit number N that defines the gradation value of the display target pixel based on the digital video signal, and the drive signal generation means generates a current corresponding to the maximum gradation value. The first terminal of the two terminals excluding the control terminal is connected to the first current source, the second terminal is connected to the first common potential line, and the control terminal is Connected to the first terminal And a second terminal of the two terminals excluding the control terminal is connected to the first common potential line, and is provided corresponding to each bit of the digital gradation signal. A terminal is provided corresponding to each of the first to Nth output side transistor elements connected to the control terminal of the input side transistor element and the first to Nth signal source operation enable / disable signals, and has two terminals. One of the terminals is connected to the first terminal of each of the first to Nth output side transistor elements corresponding to each, and between the two terminals according to the first to Nth signal source operation enable / disable signals corresponding to each First to Nth operation switching means for switching connection / disconnection, a second current source for generating a threshold current of the light source, and a bit corresponding to each bit of the digital gradation signal, one end being 1st to Nth connected to two common potential lines A dummy load is provided corresponding to each bit of the digital gradation signal, and the other terminals of the first to Nth operation switching means corresponding to the bit data corresponding to the dummy load are connected to the first terminal. To first to Nth output changeover switches for switching between connecting to the other end of the Nth dummy load or connecting to one end of the second current source, and to one end of the second current source A current mirror circuit that outputs a drive current having substantially the same current value as the drive signal, and the electrical characteristics of the first to Nth output side transistor elements are bit data corresponding to each of the current characteristics. It is desirable that it is set so as to generate a current corresponding to.
When the video signal is a digital video signal with N bits and a digital gradation signal with N bits that defines the gradation value of the display target pixel corresponding to the light irradiation position is used as the gradation signal, By adopting the configuration, it is possible to easily and inexpensively realize the video signal storage unit, the operation determination unit, and the drive signal generation unit.

In the image display device described above, the video signal is a digital video signal having N bits, and the video signal storage means is provided corresponding to each bit data of the digital video signal, and corresponds to each. It has first to Nth shift registers having a configuration in which bit data is input and a plurality of flip-flops are connected in series.
A logical sum circuit that outputs a logical sum signal of output signals of all flip-flops in the first to Nth shift registers as the signal source operation enable / disable signal;
The PWM (which defines the gradation value of the display target pixel based on the digital video signal by inputting the output signal of the flip-flop at the last stage in the first to Nth shift registers as the digital video signal of the display target pixel. Pulse Width Modulation) gradation signal is generated, and the drive signal generation means includes a first current source for generating a current corresponding to the maximum gradation value, and a first terminal of two terminals excluding the control terminal. The input side transistor element connected to the first current source, the second terminal connected to the first common potential line, the control terminal connected to the first terminal of itself, and the control terminal are excluded. A second terminal of two terminals is connected to the first common potential line, an output side transistor element in which the control terminal is connected to a control terminal of the input side transistor element, and one of the two terminals Is the output side An operation switching means that is connected to the first terminal of the star element and switches connection / disconnection between the two terminals according to the signal source operation availability signal; a second current source that generates a threshold current of the light source; A dummy load having one end connected to a second common potential line and the other terminal of the operation switching means is connected to the other end of the dummy load according to the PWM gradation signal, or the second current An output changeover switch that switches whether to connect to one end of the source, and a current mirror circuit that outputs, as the drive signal, a drive current having a current value substantially the same as a current flowing through one end of the second current source. Is desirable.
When the video signal is a digital video signal with N bits and a PWM gray scale signal that defines the gray scale value of the display target pixel corresponding to the light irradiation position is used as the gray scale signal, the configuration as described above is employed. Thus, it is possible to realize the video signal storage unit, the operation determination unit, and the drive signal generation unit easily and inexpensively.

In the above-described image display device, the scanning unit includes a reflection mirror that reflects the light, and a first rotation for rotating the reflection mirror about a first axis along a reflection surface of the reflection mirror. A MEMS (Micro Electro Mechanical System) scanner including a support unit, and an irradiation position detection unit that detects a rotation angle of the reflection mirror around the first axis as an irradiation position of light on the projection surface; Pixel synchronization clock generation means for generating a pixel synchronization clock signal that defines the output timing of the gradation signal to the drive signal generation means according to the light irradiation position detected by the irradiation position detection means, and A pixel synchronization clock signal is used as a clock signal of the flip-flop in the video signal storage means, and the video signal processing means is the image synchronization clock. Tsu synchronization with the click signal to output a tone signal to be displayed pixel to the drive signal generating means, it is desirable.
Thus, by using the MEMS scanner as the scanning means, it is possible to reduce the power consumption while taking advantage of the high speed scanning and the large deviation scanning which are the advantages of the MEMS scanner. Further, the pixel synchronization clock signal generated based on the rotation angle about the first axis of the reflection mirror of the MEMS scanner is used as a clock of the flip-flop in the video signal storage means and the video signal processing means, so that it is accurately covered. The gradation signal of the display target pixel corresponding to the current light irradiation position on the projection surface can be supplied to the drive signal generating means.

On the other hand, the drive signal generation circuit according to the present invention receives a grayscale signal that defines a grayscale value of a display target pixel, a drive signal source that generates a drive signal according to the grayscale signal, a dummy load, A drive signal generation circuit comprising an output changeover switch for switching the output destination of the drive signal to either the dummy load or an external light source according to the gradation signal, and a signal source operation input from the outside It is characterized by comprising an operation switching means for switching operation / non-operation of the drive signal source based on the availability signal.
According to the drive signal generation circuit having such a feature, a time lag from when the drive signal source is switched from the non-operating state to the operating state and actually generating the drive signal is taken into account, and a predetermined number of pixels after the display target pixel When it is necessary to operate the drive signal source, the drive signal source is operated in advance, and when it is not necessary to operate, the drive signal source is switched to the non-operating state. Electricity can be achieved.

In the above-described drive signal generation circuit, a digital gradation signal having N bits that defines the gradation value of the display target pixel, and first to Nth signal sources corresponding to each bit data of the digital gradation signal. A first current source that generates an electric current corresponding to the maximum gradation value, and a first terminal of two terminals excluding the control terminal is connected to the first current source; The second terminal is connected to the first common potential line, the control terminal is provided corresponding to each bit of the digital gradation signal, and the input side transistor element connected to its own first terminal. A first terminal to an Nth output side in which a second terminal of the two terminals excluding the control terminal is connected to the first common potential line, and the control terminal is connected to a control terminal of the input side transistor element. Transistor element and first to Nth signal source operations Provided corresponding to each of the reject signals, and one of the two terminals is connected to the first terminal of the first to Nth output side transistor elements corresponding to each of the two terminals, and the first to first corresponding to each of the first to Nth output side transistor elements. First to Nth operation switching means for switching connection / disconnection between two terminals according to N signal source operation enable / disable signals, a second current source for generating a threshold current of the light source, and the digital gradation Provided corresponding to each bit of the signal, one end of which is connected to the second common potential line, one end to the Nth dummy load, and provided corresponding to each bit of the digital gradation signal. Depending on the corresponding bit data, the other terminal of the first to Nth operation switching means corresponding to each is connected to the other end of the first to Nth dummy loads, or the second current source. 1st to Nth output changeover switch for switching whether to connect to one end of A current mirror circuit that outputs a drive current having substantially the same current value as the current flowing through one end of the second current source as the drive signal, and the electric current of the first to Nth output side transistor elements is provided. It is desirable that the target characteristic is set so as to generate a current corresponding to the bit data corresponding to each.
When a digital gradation signal with N bits that defines the gradation value of the display target pixel corresponding to the light irradiation position is used as the gradation signal, the drive signal can be easily and inexpensively employed by adopting the above configuration. A generation circuit can be realized.

Further, in the drive signal generation circuit described above, the PWM gradation signal that defines the gradation value of the display target pixel is input, and the first current source that generates a current corresponding to the maximum gradation value and the control terminal are excluded. The first terminal of the two terminals is connected to the first current source, the second terminal is connected to the first common potential line, and the control terminal is connected to the first terminal of itself. An output side transistor in which an input side transistor element and a second terminal of the two terminals excluding the control terminal are connected to the first common potential line, and the control terminal is connected to a control terminal of the input side transistor element An operation switching means for switching the connection / disconnection between the two terminals according to the signal source operation enable / disable signal, wherein the element and one of the two terminals are connected to the first terminal of the output side transistor element; Second to generate a threshold current of the light source A current source, a dummy load having one end connected to the second common potential line, and the other terminal of the operation switching means is connected to the other end of the dummy load according to the PWM gradation signal, or An output changeover switch for switching whether to connect to one end of the second current source, and a current mirror circuit for outputting a drive current having substantially the same current value as the current flowing through one end of the second current source as the drive signal; It is desirable to provide.
When using the PWM gradation signal that defines the gradation value of the display target pixel corresponding to the light irradiation position as the gradation signal, the drive signal generation circuit can be realized easily and inexpensively by adopting the above configuration. Is possible.

Furthermore, the image display apparatus driving method according to the present invention includes a scanning unit that scans light generated from a light source on a projection surface, and a pixel that receives a video signal as an input and corresponds to a light irradiation position on the projection surface. Video signal processing means for generating a gradation signal defining a gradation value of the image signal, a drive signal source for generating a drive signal corresponding to the gradation signal, a dummy load, and an output destination of the drive signal as the gradation signal According to another aspect of the present invention, there is provided a driving method of an image display device including a driving signal generation unit having an output changeover switch for switching to either the dummy load or the light source according to a predetermined number of pixels. While accumulating every minute, the video signal of the display target pixel corresponding to the irradiation position of the current light on the projection surface is output to the video signal processing means, and based on the accumulated video signal, Determines whether it is necessary to operate the driving source after a predetermined number of pixels from the display pixel, it switches the operation / non-operation of the drive signal source based on the determination result, characterized in that.
According to the driving method of the image display apparatus having such characteristics, is it necessary to operate the driving signal source after a predetermined number of pixels from the display target pixel based on the accumulated video signal that is the source of the gradation signal? It is determined whether or not the drive signal source is in operation / non-operation based on the determination result. That is, when the drive signal source needs to be operated after a predetermined number of pixels from the display target pixel in consideration of the time lag until the drive signal is actually generated by switching the drive signal source from the non-operating state to the operating state. Since the drive signal source is operated in advance and the drive signal source is switched to the non-operating state when it is not necessary to operate, it is possible to reduce the power consumption while satisfying the demand for high-speed operation.

Hereinafter, an embodiment of the present invention will be described with reference to the drawings.
[First Embodiment]
FIG. 1 is a functional block diagram of the image display device LSD according to the first embodiment. The image display device LSD will be described by exemplifying a laser scan display that scans a laser beam on a screen (projected surface) 110 to display an image.

 As shown in FIG. 1, the image display device LSD according to the first embodiment includes a red video signal buffer 10R, a green video signal buffer 10G, a blue video signal buffer 10B, a red operation determination circuit 20R, a green operation determination circuit 20G, and a blue color. Operation determination circuit 20B, video signal processing circuit 30, red laser driver 40R, green laser driver 40G, blue laser driver 40B, red laser diode 50R, green laser diode 50G, blue laser diode 50B, optical axis alignment optical system 60, laser A scanning unit 70, a scanning drive unit 80, an irradiation position detection unit 90, and a pixel synchronous clock generation circuit 100 are provided.

 The red video signal buffer (video signal storage means) 10R stores red digital video signals VR input from an external image supply device (not shown) such as a notebook personal computer for a predetermined number of pixels. The digital video signal VR of the pixel (display target pixel) corresponding to the current laser light irradiation position on the screen 110 is output to the video signal processing circuit 30. Here, the digital video signal VR is N-bit serial data. In the present embodiment, for convenience of explanation, the bit number N of the digital video signal VR is set to 4. That is, the image display apparatus LSD can display an image with 16 gradations (4096 colors) from “0” to “15”.

  The red operation determination circuit (operation determination means) 20R is a drive provided in a red laser driver 40R described later after a predetermined number of pixels from the display target pixel based on the digital video signal VR accumulated in the red video signal buffer 10R. It is determined whether or not it is necessary to operate a current source (first output side transistor element To1 to fourth output side transistor element To4) as a signal source, and a current source enable signal (signal source) indicating the determination result Operation enable / disable signal ER is output to the red laser driver 40R.

  Hereinafter, the circuit configurations of the red video signal buffer 10R and the red operation determination circuit 20R will be described in detail with reference to FIG. In the present embodiment, for convenience of explanation, it is assumed that the red video signal buffer 10R stores digital video signals VR for four pixels. Also, the bit data of the first bit which is the LSB of the digital video signal VR is VR1, the bit data of the second bit is VR2, the bit data of the third bit is VR3, and the bit data of the fourth bit which is the MSB is VR4. .

  As shown in FIG. 2, the red video signal buffer 10R is provided corresponding to each bit data VR1 to VR4 of the digital video signal VR. A first shift register 201, a second shift register 202, a third shift register 203, and a fourth shift register 204 having a configuration in which flip-flops are connected in series are provided. The red operation determination circuit 20R includes a first OR circuit 301, a second OR circuit 302, and a third OR circuit provided corresponding to each of the first shift register 201 to the fourth shift register 204. The logical sum circuit 303 and the fourth logical sum circuit 304 are provided.

  More specifically, the first shift register 201 has a configuration in which D-type flip-flops 201a to 201d are connected in series. The bit data VR1 of the digital video signal VR is input to the input terminal of the flip-flop 201a in the input stage. The output terminal of the flip-flop 201d at the final stage is connected to the video signal processing circuit 30. The output terminals of all the flop flops 201a to 201d are connected to the first OR circuit 301, and the clock input terminals of all the flop flops 201a to 201d are output from the pixel synchronous clock generation circuit 100 described later. A pixel synchronization clock signal CL is input. That is, the first shift register 201 sequentially shifts the bit data VR1 of the digital video signal VR by four pixels in synchronization with the pixel synchronization clock signal CL, and the current irradiation position of the laser light on the screen 110. The bit data VR1 of the digital video signal VR corresponding to the display target pixel is output from the final flip-flop 201d to the video signal processing circuit 30.

  The first OR circuit 301 receives the output signals of all the flip-flops 201a to 201d in the first shift register 201, and uses the OR signal of these output signals as the first current source enable signal ER1 for the red laser driver 40R. Output to. That is, the first OR circuit 301 determines that the bit data VR1 corresponding to the four pixels from the display target pixel that is currently displayed to the next three pixels has “1” (1 ”). A first current source enable signal ER1 indicating a high level is output. Although details will be described later, in the present embodiment, the first that indicates “1” when it is necessary to operate the current source (specifically, the first output-side transistor element To1) provided in the red laser driver 40R. Current source enable signal ER1 is output, and when it is not necessary to operate, the first current source enable signal ER1 indicating "0" (low level) is output.

  The second shift register 202 has a configuration in which D-type flip-flops 202a to 202d are connected in series. The bit data VR2 of the digital video signal VR is input to the input terminal of the flip-flop 202a in the input stage. The output terminal of the final flip-flop 202d is connected to the video signal processing circuit 30. The output terminals of all the flop flops 202a to 202d are connected to the second OR circuit 302, and the clock input terminals of all the flop flops 202a to 202d are output from the pixel synchronous clock generation circuit 100 described later. A pixel synchronization clock signal CL is input. That is, the second shift register 202 sequentially shifts the bit data VR2 of the digital video signal VR by four pixels in synchronization with the pixel synchronization clock signal CL, and the current laser light irradiation position on the screen 110. The bit data VR2 of the digital video signal VR corresponding to the display target pixel is output from the final flip-flop 202d to the video signal processing circuit 30.

  The second OR circuit 302 receives the output signals of all the flip-flops 202a to 202d in the second shift register 202, and uses the logical sum signal of these output signals as the second current source enable signal ER2 for the red laser driver 40R. Output to. In other words, the second OR circuit 302 sets “1” if there is at least one “1” in the bit data VR2 corresponding to the four pixels from the currently displayed pixel to be displayed to the next three pixels. The second current source enable signal ER2 shown is output. In the present embodiment, the second current source enable signal ER2 indicating “1” when the current source (specifically, the second output side transistor element To2) provided in the red laser driver 40R needs to be operated. Is output and the second current source enable signal ER2 indicating "0" is output when there is no need to operate.

  The third shift register 203 has a configuration in which D-type flip-flops 203a to 203d are connected in series. The bit data VR3 of the digital video signal VR is input to the input terminal of the flip-flop 203a in the input stage. The output terminal of the final flip-flop 203d is connected to the video signal processing circuit 30. Further, the output terminals of all the flop flops 203a to 203d are connected to the third OR circuit 303, and the clock input terminals of all the flop flops 203a to 203d are output from the pixel synchronous clock generation circuit 100 described later. A pixel synchronization clock signal CL is input. That is, the third shift register 203 sequentially shifts the bit data VR3 of the digital video signal VR by four pixels in synchronization with the pixel synchronization clock signal CL, and the current laser light irradiation position on the screen 110. The bit data VR3 of the digital video signal VR corresponding to the display target pixel is output from the final flip-flop 203d to the video signal processing circuit 30.

  The third OR circuit 303 receives the output signals of all the flip-flops 203a to 203d in the third shift register 203 as input, and uses the OR signal of these output signals as a third current source enable signal ER3 for the red laser driver 40R. Output to. In other words, the third OR circuit 303 sets “1” if there is at least one “1” in the bit data VR3 corresponding to the four pixels from the currently displayed pixel to be displayed to the next three pixels. The third current source enable signal ER3 shown is output. In the present embodiment, the third current source enable signal ER3 indicating “1” when it is necessary to operate the current source (specifically, the third output side transistor element To3) provided in the red laser driver 40R. Is output and the third current source enable signal ER3 indicating "0" is output when there is no need to operate.

  The fourth shift register 204 has a configuration in which D-type flip-flops 204a to 204d are connected in series, and the bit data VR4 of the digital video signal VR is input to the input terminal of the flip-flop 204a in the input stage. The output terminal of the final flip-flop 204d is connected to the video signal processing circuit 30. The output terminals of all the flop flops 204a to 204d are connected to the fourth OR circuit 304, and the clock input terminals of all the flop flops 204a to 204d are output from the pixel synchronous clock generation circuit 100 described later. A pixel synchronization clock signal CL is input. That is, the fourth shift register 204 sequentially shifts the bit data VR4 of the digital video signal VR by four pixels in synchronization with the pixel synchronization clock signal CL, and the current irradiation position of the laser light on the screen 110. The bit data VR4 of the digital video signal VR corresponding to the display target pixel is output to the video signal processing circuit 30 from the flip-flop 204d at the final stage.

The fourth OR circuit 304 receives the output signals of all the flip-flops 204a to 204d in the fourth shift register 204 as inputs, and uses the OR signal of these output signals as a fourth current source enable signal ER4 for the red laser driver 40R. Output to. In other words, the fourth OR circuit 304 sets “1” if there is at least one “1” in the bit data VR4 corresponding to the four pixels from the currently displayed pixel to be displayed to the third pixel after. The fourth current source enable signal ER4 shown is output. In the present embodiment, the fourth current source enable signal ER4 indicating “1” when it is necessary to operate the current source (specifically, the fourth output side transistor element To4) provided in the red laser driver 40R. Is output and the fourth current source enable signal ER4 indicating "0" is output when there is no need to operate.
The above is the description of the red video signal buffer 10R and the red operation determination circuit 20R. Hereinafter, description will be made with reference to FIG.

 A green video signal buffer (video signal storage means) 10G stores a digital video signal VG (4-bit serial data) for a green pixel input from an external image supply device for every four pixels, while on the screen 110. The digital video signal VG of the display target pixel corresponding to the current irradiation position of the laser beam is output to the video signal processing circuit 30. The blue video signal buffer (video signal storage means) 10B stores the digital video signal VB (4-bit serial data) for blue pixels input from the external image supply device for every four pixels, while on the screen 110. The digital video signal VB of the display target pixel corresponding to the current irradiation position of the laser beam is output to the video signal processing circuit 30. The circuit configuration of the green video signal buffer 10G and the blue video signal buffer 10B is the same as that of the red video signal buffer 10R shown in FIG.

  The green operation determination circuit (operation determination means) 20G operates a current source provided in the green laser driver 40G after four pixels from the display target pixel in advance, based on the digital video signal VG stored in the green video signal buffer 10G. The current source enable signal EG (first current source enable signal EG1 to fourth current source enable signal EG4) indicating the determination result is output to the green laser driver 40G. The blue operation determination circuit (operation determination means) 20B operates a current source provided in the blue laser driver 40B after four pixels from the display target pixel in advance, based on the digital video signal VB stored in the blue video signal buffer 10B. The current source enable signal EB (first current source enable signal EB1 to fourth current source enable signal EB4) indicating the determination result is output to the blue laser driver 40B. The circuit configurations of the green operation determination circuit 20G and the blue operation determination circuit 20B are the same as the red operation determination circuit 20R shown in FIG.

  The video signal processing circuit (video signal processing means) 30 is 4-bit red gradation data DR that defines the red gradation value of the display target pixel based on the digital video signal VR input from the red video signal buffer 10R. Is generated based on the digital video signal VG input from the green video signal buffer 10G, and the 4-bit green tone data DG defining the green tone value of the display target pixel is generated, and the blue video signal buffer 10B is generated. 4 bit blue gradation data DB for defining the blue gradation value of the pixel to be displayed is generated based on the digital video signal VB input from the pixel synchronization clock input from the pixel synchronization clock generation circuit 100 In synchronization with the signal CL, the red gradation data DR is output to the red laser driver 40R, and the green gradation data DG is output to the green laser driver 40G. And it outputs the tone data DB blue laser driver 40B.

 The red laser driver (driving signal generation means) 40R includes the red gradation data DR and the current source enable signal ER (first current source enable signal ER1 to fourth current source enable) output from the red operation determination circuit 20R. Signal ER4) as an input, and switching the operation / non-operation of the current source (first output side transistor element To1 to fourth output side transistor element To4) based on the current source enable signal ER, and red gradation data A drive current IR corresponding to DR is generated and output to the red laser diode 50R. Hereinafter, a detailed configuration of the red laser driver 40R will be described.

 FIG. 3 is a circuit configuration diagram of the red laser driver 40R. As shown in FIG. 3, the red laser driver 40R includes a first current source CS1, a second current source CS2, a first input side transistor element Ti1, a second input side transistor element Ti2, and a first output. Side transistor element To1, second output side transistor element To2, third output side transistor element To3, fourth output side transistor element To4, fifth output side transistor element To5, first operation selector switch SW1, 2 operation switch SW2, 3rd operation switch SW3, 4th operation switch SW4, 1st output switch S1, 2nd output switch S2, 3rd output switch S3, 4th The output switch S4, the first dummy load R1, the second dummy load R2, the third dummy load R3, and the fourth dummy load R4 are included. It is.

 The first current source CS1 has an input terminal connected to the power supply line Vcc (second common potential line), an output terminal connected to the drain terminal and the gate terminal of the first input side transistor element Ti1, A current Is having a current value corresponding to the adjustment value (“15” in the present embodiment) is generated.

 The first input side transistor element Ti1 is an n-channel MOS (Positive Metal Oxide Semiconductor) transistor element, the drain terminal (first terminal) is connected to the output terminal of the first current source CS1, and the gate terminal The (control terminal) is connected to the output terminal of the first current source CS1 and the gate terminals of the first output side transistor element To1 to the fourth output side transistor element To4, and the source terminal (second terminal) is the ground line. (First common potential line).

 The first output side transistor element To1 is an n-channel type MOS transistor element, the drain terminal is connected to one terminal of the first operation changeover switch SW1, and the gate terminal is connected to the first input side transistor element Ti1. The second output side transistor element To2 to the fourth output side transistor element To4 are connected to the gate terminals, and the source terminal is connected to the ground line.

 The second output side transistor element To2 is an n-channel MOS transistor element, the drain terminal is connected to one terminal of the second operation changeover switch SW2, and the gate terminal is the first input side transistor element Ti1, The first output side transistor element To1, the third output side transistor element To3, and the fourth output side transistor element To4 are connected to the gate terminals, and the source terminal is connected to the ground line.

 The third output side transistor element To3 is an n-channel type MOS transistor element, the drain terminal is connected to one terminal of the third operation changeover switch SW3, and the gate terminal is the first input side transistor element Ti1, The first output side transistor element To1, the second output side transistor element To2, and the fourth output side transistor element To4 are connected to the gate terminals, and the source terminal is connected to the ground line.

 The fourth output side transistor element To4 is an n-channel type MOS transistor element, the drain terminal is connected to one terminal of the fourth operation changeover switch SW4, and the gate terminal is the first input side transistor element Ti1, The gate terminals of the first output side transistor element To1 to the third output side transistor element To3 are connected, and the source terminal is connected to the ground line.

 That is, the first input side transistor element Ti1 is changed to the input side transistor by the first current source CS1, the first input side transistor element Ti1, and the first output side transistor element To1 to the fourth output side transistor element To4. Thus, a current mirror circuit is configured in which the first output side transistor element To1 to the fourth output side transistor element To4 are output side transistors (that is, current sources). Here, in the present embodiment, the electrical characteristics of the first output-side transistor element To1 to the fourth output-side transistor element To4 are set so as to generate currents corresponding to the corresponding bit data.

 Specifically, the first output side transistor element To1 corresponds to the bit data B1 of the first bit which is LSB among the 4-bit red gradation data DR, and is generated by the first current source CS1. The electrical characteristics are set so that 1/15 of the current Is generated is generated. The second output side transistor element To2 corresponds to the bit data B2 of the second bit out of the 4-bit red gradation data DR so that a current that is 2/15 of the current Is is generated. Electrical characteristics are set. Further, the third output side transistor element To3 corresponds to the bit data B3 of the third bit out of the 4-bit red gradation data DR so that a current of 4/15 of the current Is is generated. Electrical characteristics are set. Further, the fourth output side transistor element To4 corresponds to the bit data B4 of the fourth bit which is the MSB in the 4-bit red gradation data DR, and a current of 8/15 of the current Is is generated. The electrical characteristics are set as follows.

 The first operation changeover switch (operation changeover means) SW1 is provided corresponding to the first signal source operation enable / disable signal ER1, and the connection between the two terminals according to the first signal source operation enable / disable signal ER1. / A switch element that switches between non-connections, one terminal of which is connected to the drain terminal of the first output-side transistor element To1, and the other terminal that is connected to the first terminal S1a and the second terminal of the first output changeover switch S1. Terminal S1b. In the present embodiment, the connection is made when the first signal source operation availability signal ER1 is “1”, and the connection is not made when it is “0”.

 The second operation changeover switch (operation changeover means) SW2 is provided corresponding to the second current source enable signal ER2, and the connection / non-connection between the two terminals according to the second current source enable signal ER2. A switch element for switching the connection, one terminal of which is connected to the drain terminal of the second output side transistor element To2, and the other terminal being the first terminal S2a and the second terminal of the second output changeover switch S2. Connected to S2b. In the present embodiment, the connection is made when the second current source enable signal ER2 is “1”, and the connection is not made when the second current source enable signal ER2 is “0”.

 The third operation changeover switch (operation changeover means) SW3 is provided corresponding to the third current source enable signal ER3, and the connection / non-connection between the two terminals according to the third current source enable signal ER3. A switch element for switching the connection, one terminal of which is connected to the drain terminal of the third output side transistor element To3, and the other terminal being the first terminal S3a and the second terminal of the third output changeover switch S3. Connected to S3b. In the present embodiment, the connection is made when the third current source enable signal ER3 is “1”, and the connection is not made when the third current source enable signal ER3 is “0”.

 The fourth operation changeover switch (operation changeover means) SW4 is provided corresponding to the fourth current source enable signal ER4, and the connection / non-connection between the two terminals according to the fourth current source enable signal ER4. The switch element for switching connection, one terminal of which is connected to the drain terminal of the fourth output side transistor element To4, and the other terminal is the first terminal S4a and the second terminal of the fourth output changeover switch S4. Connected to S4b. In the present embodiment, the connection is made when the fourth current source enable signal ER4 is “1”, and the connection is not made when the fourth current source enable signal ER4 is “0”.

 The first dummy load R1 is a resistance element having a predetermined resistance value, one end is connected to the power supply line Vcc, and the other end is connected to the third terminal S1c of the first output changeover switch S1. The second dummy load R2 is a resistance element having a predetermined resistance value, one end is connected to the power supply line Vcc, and the other end is connected to the third terminal S2c of the second output changeover switch S2. The third dummy load R3 is a resistance element having a predetermined resistance value, one end is connected to the power supply line Vcc, and the other end is connected to the third terminal S3c of the third output changeover switch S3. The fourth dummy load R4 is a resistance element having a predetermined resistance value. One end is connected to the power supply line Vcc, and the other end is connected to the third terminal S4c of the fourth output changeover switch S4.

  The first output changeover switch S1 is provided corresponding to the bit data B1 of the first bit which is LSB in the 4-bit red gradation data DR, and the first output changeover switch S1 corresponds to the value of the bit data B1. 1 is a switching element that switches connection / disconnection between the first terminal S1a and the third terminal S1c and between the second terminal S1b and the fourth terminal S1d, and the first terminal S1a and the second terminal S1b is connected to the drain terminal of the first output-side transistor element To1, the third terminal S1c is connected to the other end of the first dummy load R1, and the fourth terminal S1d is the input of the second current source CS2. Connected to the terminal. In the present embodiment, when the bit data B1 is “1”, the first terminal S1a and the third terminal S1c are not connected, and the second terminal S1b and the fourth terminal S1d are connected. , “0”, the first terminal S1a and the third terminal S1c are connected, and the second terminal S1b and the fourth terminal S1d are not connected.

  The second output changeover switch S2 is provided corresponding to the bit data B2 of the second bit in the red gradation data DR of 4 bits, and the first terminal is changed according to the value of the bit data B2. A switching element that switches connection / disconnection between S2a and the third terminal S2c and between the second terminal S2b and the fourth terminal S2d. The first terminal S2a and the second terminal S2b Connected to the drain terminal of the second output side transistor element To2, the third terminal S2c is connected to the other end of the second dummy load R2, and the fourth terminal S2d is connected to the input terminal of the second current source CS2. Has been. In the present embodiment, when the bit data B2 is “1”, the first terminal S2a and the third terminal S2c are not connected, and the second terminal S2b and the fourth terminal S2d are connected. , “0”, the first terminal S2a and the third terminal S2c are connected, and the second terminal S2b and the fourth terminal S2d are not connected.

  The third output changeover switch S3 is provided corresponding to the bit data B3 of the third bit in the red gradation data DR of 4 bits, and the first terminal is changed according to the value of the bit data B3. A switching element that switches connection / disconnection between S3a and the third terminal S3c and between the second terminal S3b and the fourth terminal S3d. The first terminal S3a and the second terminal S3b 3 is connected to the drain terminal of the output side transistor element To3, the third terminal S3c is connected to the other end of the third dummy load R3, and the fourth terminal S3d is connected to the input terminal of the second current source CS2. Has been. In the present embodiment, when the bit data B3 is “1”, the first terminal S3a and the third terminal S3c are not connected, and the second terminal S3b and the fourth terminal S3d are connected. , “0”, the first terminal S3a and the third terminal S3c are connected, and the second terminal S3b and the fourth terminal S3d are not connected.

  The fourth output changeover switch S4 is provided corresponding to the bit data B4 of the 4th bit, which is the MSB, of the 4-bit red gradation data DR, and the fourth output changeover switch S4 corresponds to the value of the bit data B4. 1 is a switching element that switches connection / disconnection between the first terminal S4a and the third terminal S4c and between the second terminal S4b and the fourth terminal S4d, the first terminal S4a and the second terminal. S4b is connected to the drain terminal of the fourth output-side transistor element To4, the third terminal S4c is connected to the other end of the fourth dummy load R4, and the fourth terminal S4d is the input of the second current source CS2. Connected to the terminal. In the present embodiment, when the bit data B4 is “1”, the first terminal S4a and the third terminal S4c are not connected, and the second terminal S4b and the fourth terminal S4d are connected. , “0”, the first terminal S4a and the third terminal S4c are connected, and the second terminal S4b and the fourth terminal S4d are not connected.

The second current source CS2 has input terminals such as the fourth terminals S1d to S4d in the first output changeover switch S1 to the fourth output changeover switch S4, and the drain terminal and gate terminal of the second input side transistor element Ti2. is connected to the bets, the output terminal is connected to the ground line, to generate the threshold current I _th of the red laser diode 50R. FIG. 4 is a characteristic diagram showing the relationship between the laser light amount of the red laser diode 50R and the drive current IR. As shown in FIG. 4, the threshold current I _th, it refers to the current value necessary for generating the laser beam in the red laser diode 50R. More precisely, does not lead to the occurrence of the laser beam by supplying a threshold current I _th in the red laser diode 50R (0 laser light amount) is, the laser beam is generated by supplying a large drive current than the threshold current I _th To do. That is, laser light amount increases or decreases in proportion to the current value obtained by subtracting the threshold current I _th of the driving current IR is supplied to the red laser diode 50R.

 The second input side transistor element Ti2 is a p-channel type MOS transistor element, the source terminal is connected to the power supply line Vcc, the gate terminal is connected to the drain terminal and the gate terminal of the fifth output side transistor element To5. The drain terminal is connected to the input terminal of the second current source CS2 and the fourth terminals S1d to S4d in the first output changeover switch S1 to the fourth output changeover switch S4. The fifth output side transistor element To5 is a p-channel MOS transistor element, the source terminal is connected to the power supply line Vcc, and the gate terminal is connected to the gate terminal and drain terminal of the second input side transistor element Ti2. The drain terminal is connected to the anode terminal of the red laser diode 50R.

That is, the second input-side transistor element Ti2 and the fifth output-side transistor element To5 are current mirror circuits having the second input-side transistor element Ti2 as the input side and the fifth output-side transistor element To5 as the output side. configured and a threshold current _{I th} of a second current source CS2 is generated, the resultant current of the current flowing through the fourth terminal S1d~S4d of the first output switch S1~ fourth output switching switch S4 , And a current having substantially the same current value as the combined current is output as a drive current IR to the red laser diode 50R.

  As can be seen from the above description, the red laser driver 40R includes the first operation switch SW1 to the fourth operation switch SW4 according to the first current source enable signal ER1 to the fourth current source enable signal ER4. By switching between connection and non-connection, the operation / non-operation of the first output-side transistor element To1 to the fourth output-side transistor element To4 that are current sources is switched. Further, the first output side transistor element To1 to the fourth output side transistor are switched by connecting / disconnecting the first output changeover switch S1 to the fourth output changeover switch S4 according to the red gradation data DR. It is configured to switch whether the current generated by the element To4 is output to the corresponding first dummy load R1 to the fourth dummy load R4 or to the red laser diode 50R that is a light source. .

For example, assuming that all of the first operation changeover switch SW1 to the fourth operation changeover switch SW4 are in the connected state, the red gradation data DR is the gradation value “0”, that is, all the bit data B1 to B4 are “ In the case of “0”, the current generated by the first output-side transistor element To1 to the fourth output-side transistor element To4 flows to the corresponding first dummy load R1 to fourth dummy load R4. , a driving current IR = the threshold current _{I th.} In this case, as shown in FIG. 4, no laser light is generated in the red laser diode 50R (red is displayed in black).

When the red gradation data DR is the gradation value “1”, that is, the bit data B1 is “1” and B2 to B4 are “0”, only the first output side transistor element To1 is the second current source CS2. Since it is connected to the input terminal, drive current IR = threshold current I _th + Is / 15. In this case, laser light of an amount corresponding to the current Is / 15 obtained by subtracting the threshold current I _th of the driving current IR in the red laser diode 50R (an amount corresponding to the grayscale value "1") occurs. When the red gradation data DR is the gradation value “2”, that is, when the bit data B2 is “1” and B1, B3, and B4 are “0”, only the second output side transistor element To2 has the second value. Since it is connected to the input terminal of the current source CS2, the drive current IR is equal to the threshold current I _th + 2 · Is / 15. In this case, laser light of an amount corresponding to the current 2 · Is / 15 obtained by subtracting the threshold current I _th of the driving current IR in the red laser diode 50R (an amount corresponding to the grayscale value "2") occurs.

Thus, every time the gradation value increases by “1”, the drive current IR increases by Is / 15. When the maximum gradation value is “15”, that is, when the bit data B1 to B4 are all “1”. since all of the first output-side transistor device To1~ fourth output-side transistor device To4 it is connected to the input terminal of the second current source CS2, the drive current IR = the threshold current _I th + is. In this case, the laser light of an amount corresponding to the current Is by subtracting the threshold current I _th of the driving current IR in the red laser diode 50R (amount of light corresponding to the maximum tone value) is generated. The above is the description of the red laser driver 40R, and the following description will be given returning to FIG.

  The green laser driver (driving signal generation means) 40G includes green gradation data DG and a current source enable signal EG (first current source enable signal EG1 to fourth current source enable signal) output from the green operation determination circuit 20G. EG4) as an input, and on the basis of the current source enable signal EG, the operation / non-operation of the current source (first output side transistor element To1 to fourth output side transistor element To4) is switched and the green gradation data DG Is generated and output to the green laser diode 50G. The blue laser driver (drive signal generating means) 40B includes the blue gradation data DB and the current source enable signal EB (first current source enable signal EB1 to fourth current source enable signal) output from the blue operation determination circuit 20B. EB4) as an input, and the operation / non-operation of the current source (first output side transistor element To1 to fourth output side transistor element To4) is switched based on the current source enable signal EB, and the blue gradation data DB Is generated and output to the blue laser diode 50B. The circuit configurations of the green laser driver 40G and the blue laser driver 40B are the same as those of the red laser driver 40R shown in FIG.

 The red laser diode (light source) 50R generates a single red laser beam LR in accordance with the drive current IR supplied from the red laser driver 40R, and aligns the laser beam LR on the optical axis LA. Irradiation toward the optical system 60 (specifically, the first dichroic mirror 60a). In this embodiment, as shown in FIG. 1, the direction substantially parallel to the horizontal plane is set as the X axis, the direction orthogonal to the X axis in the horizontal plane is set as the Y axis, and the direction substantially perpendicular to the horizontal plane (XY plane) is set as the Z axis. The optical axis LA is set substantially parallel to the X axis. The outgoing optical axis of the laser beam LR coincides with the optical axis LA.

  The green laser diode (light source) 50G generates a green monochromatic laser beam LG in accordance with the drive current IG supplied from the green laser driver 40G, and the optical system 60 for optical axis alignment (specifically, the first laser beam LG). Irradiate along the Y axis toward one dichroic mirror 60a). The blue laser diode (light source) 50B generates a green monochromatic laser beam LB in accordance with the drive current IB supplied from the blue laser driver 40B, and the optical system 60 for optical axis alignment (specifically, the first laser beam LB). Irradiate along the Y axis toward the second dichroic mirror 60b).

  The optical axis alignment optical system 60 is an optical system for aligning the optical axes of the laser beams LR, LG, and LB, and includes a first dichroic mirror 60a and a second dichroic mirror 60b. The first dichroic mirror 60a is installed on the optical axis LA with an inclination of 45 ° with respect to the optical axis LA, and directs the laser beam LR toward the second dichroic mirror 60b along the optical axis LA. While transmitting, the laser beam LG is reflected toward the second dichroic mirror 60b so as to coincide with the optical axis LA. The second dichroic mirror 60b is installed on the optical axis LA with an inclination of 45 ° with respect to the optical axis LA, and the laser light LR and the laser light LG are transmitted to the laser scanning unit 70 along the optical axis LA. The laser beam LB is reflected toward the laser scanning unit 70 so as to coincide with the optical axis LA. That is, the second dichroic mirror 60 b emits the combined light (hereinafter simply referred to as laser light) of the laser beams LR, LG, and LB toward the laser scanning unit 70.

 A laser scanning unit (scanning unit) 70 is a resonance type MEMS (Micro Electro Mechanical System) scanner, and enters through an optical axis alignment optical system 60 based on a scanning driving signal input from a scanning driving unit 80. The laser beam to be scanned is scanned on the screen 110. Hereinafter, a detailed configuration of the laser scanning unit 70 will be described.

 FIG. 5 is a schematic configuration diagram of a laser scanning unit 70 which is a MEMS scanner. As shown in FIG. 5, the laser scanning unit 70 includes a reflection mirror 70a, a first torsion spring 70b, an inner frame part 70c, a second torsion spring 70d, and an outer frame part 70e. The reflecting mirror 70a, the first torsion spring 70b, the inner frame portion 70c, the second torsion spring 70d, and the outer frame portion 70e are integrally formed by finely processing a semiconductor material such as single crystal silicon. It is.

 The reflection mirror 70a is a plate-like object having a reflection film formed on the reflection surface side so as to reflect the laser beam toward the screen 110. The first axis AX1 along the reflection surface (when the XY plane is a horizontal plane) The first frame is connected to the inner frame portion 50c by a first torsion spring (first rotation support portion) 70b provided along the horizontal plane. That is, the reflection mirror 70a is supported by the first torsion spring 70b so as to be rotatable about the first axis AX1. The shape of the reflection mirror 70a may be a square as shown in FIG. 5, or may be a circle or an ellipse.

 The inner frame portion 70c is a frame-shaped plate-like object, and is connected to the reflection mirror 70a by a first torsion spring 70b, along the reflection surface, and substantially perpendicular to the first axis AX1. 2 is connected to the outer frame portion 70e by a second torsion spring 70d provided along an axis AX2 (when the XY plane is a horizontal plane, substantially parallel to the horizontal plane). That is, the inner frame portion 70c (reflection mirror 70a) is supported by the second torsion spring 70d so as to be rotatable around the second axis AX2. The outer frame part 70e is a frame-shaped plate-like object, and is connected to the inner frame part 70c by a second torsion spring 70d and is connected to a fixed part (not shown). In this embodiment, since the optical axis LA is set to be parallel to the X axis, when the second axis AX2 is set to be parallel to the X axis, the laser beam is shielded by the outer frame portion 70e, The light does not enter the reflection mirror 70a. In order to prevent this, in this embodiment, as shown in FIG. 5, the laser scanning unit 70 is arranged so that the second axis AX2 has an inclination φ with respect to the optical axis LA (X axis).

 The laser scanning unit 70 configured as described above scans the laser beam in the X-axis direction on the screen 110 (that is, scans in the horizontal direction) and rotates the reflection mirror 70a around the first axis AX1. By rotating the mirror 70a (inner frame portion 70c) about the second axis AX2, the laser beam is scanned in the Z-axis direction on the screen 110 (that is, scanned in the vertical direction). The driving method for rotating the reflecting mirror 70a is generated by applying a voltage signal as a scanning drive signal to an electrode arranged at a predetermined position as described in Japanese Patent Application Laid-Open No. 2007-47354. A method using an electrostatic force may be adopted, or in addition, a permanent magnet is provided to form a magnetic field, and a current signal is supplied as a scanning drive signal to a coil provided in the reflection mirror 70a or the inner frame portion 70c. You may employ | adopt the system using the Lorentz force to do. Since the driving method of the reflection mirror 70a in such a MEMS scanner is a known technique, a detailed description thereof will be omitted.

 Returning to FIG. 1, the description will be continued. The scanning drive unit 80 rotates the reflection mirror 70a of the laser scanning unit 70 based on a synchronization signal input together with the digital video signals VR, VG, and VB from an external image supply device. A scanning drive signal for driving is generated and output to the laser scanning unit 70.

 The irradiation position detection unit (irradiation position detection means) 90 detects the irradiation position of the laser light on the screen 110, and includes a horizontal angle sensor 90a, a vertical angle sensor 90b, and a timing signal generation circuit 90c. The horizontal angle sensor 90a detects the rotation angle θ1 around the first axis AX1 of the reflection mirror 70a, and outputs a horizontal angle detection signal indicating the rotation angle θ1 to the timing signal generation circuit 90c. The vertical angle sensor 90b detects the rotation angle θ2 around the second axis AX2 of the reflection mirror 70a, and outputs a vertical angle detection signal indicating the rotation angle θ2 to the timing signal generation circuit 90c. The horizontal angle sensor 90a and the vertical angle sensor 90b detect the angle by irradiating the back surface of the reflection mirror 70a (the surface opposite to the laser light reflection surface) and receiving the light reflected by the back surface. An optical angle sensor is used.

As shown in FIG. 6, the rotation angle θ1 detected by the horizontal angle sensor 90a is an angle of the reflection mirror 70a with respect to the Y axis in the XY plane. Further, as shown in FIG. 6, assuming that a position separated from the center point C0 of the screen 110 having the width W by a distance X in the X-axis direction is a laser beam irradiation position P, the coordinate Px of the irradiation position P in the horizontal scanning direction Can be expressed as a function of the rotation angle θ1 if the distance D between the reflection mirror 70a and the screen 110 is known. On the other hand, the rotation angle θ2 detected by the vertical angle sensor 90b is the angle of the reflection mirror 90a with respect to the Y axis in the YZ plane, and the coordinate Py in the vertical scanning direction of the irradiation position P is expressed as a function of the rotation angle θ2.
That is, the irradiation position P (Px, Py) can be uniquely determined by detecting the rotation angle θ1 and the rotation angle θ2 of the reflection mirror 70a.

 Referring back to FIG. 1, the timing signal generation circuit 90c generates a pulsed scanning timing signal St defining the start and end of one horizontal scanning period based on the horizontal angle detection signal indicating the rotation angle θ1. To the video signal processing circuit 30 and the pixel synchronous clock generation circuit 100. The timing signal generation circuit 90c generates a pulse-like frame timing signal Ft that defines the start of one frame based on the vertical angle detection signal indicating the rotation angle θ2 and outputs the frame timing signal Ft to the video signal processing circuit 30. To do.

 Specifically, the timing signal generation circuit 90c includes a start position and an end position of one horizontal scanning period based on the unique relationship between the rotation angle θ1 and rotation angle θ2 of the reflection mirror 70a and the irradiation position P described above. And a rotation angle θ2 corresponding to the irradiation position P corresponding to the start position of one frame is set in advance, and the timing signal generation circuit 90c generates a horizontal angle detection signal. Is output when the rotation angle θ1 indicated by is coincident with the preset rotation angle θ1, and when the rotation angle θ2 indicated by the vertical angle detection signal coincides with the preset rotation angle θ2. A frame timing signal Ft is output.

 The pixel synchronization clock generation circuit 100 receives the scanning timing signal St, and based on the scanning timing signal St, a pulsed pixel synchronization clock signal that defines the irradiation timing of the laser light corresponding to each pixel in one horizontal scanning period. CL is generated and output to the red video signal buffer 10R, the green video signal buffer 10G, the blue video signal buffer 10B, and the video signal processing circuit 30.

 The screen 110 is a transmissive screen that transmits the laser light scanned by the laser scanning unit 70. That is, the image display apparatus LSD is a rear projection type projector, and the user views the display image from the surface of the screen 110 opposite to the laser light irradiation surface. Although not shown in FIG. 1, the image display apparatus LSD exposes only the viewing side surface of the screen 110, and other components are housed inside the housing, and are influenced by external light. It is the structure which excludes.

  Next, the operation of the image display device LSD in the first embodiment having the above-described configuration will be described with reference to FIGS.

  FIG. 7 is a timing chart showing the temporal change of the rotation angle θ1 with respect to the horizontal scanning direction of the reflection mirror 70a, and the scanning timing signal St and the pixel synchronization clock signal CL generated along with the temporal change of the rotation angle θ1. As shown in FIG. 7, since the laser scanning unit 70 is a resonance type MEMS scanner, the rotation angle θ1 of the reflection mirror 70a shows a sinusoidal change. That is, as shown in this figure, the rotation angle θ1, that is, the irradiation position Px, reciprocates in the horizontal scanning direction (width W) of the screen 110 in a sinusoidal manner with the center point C0 of the screen 110 as the center as time elapses. Accordingly, the laser beam is reciprocally scanned in the horizontal scanning direction. In the figure, “1H” indicates one horizontal scanning period. Further, since the laser beam is irradiated outside the screen 110 near the top of the sine waveform, both ends of the screen 110 are set within the range of the rotation angle θ1 excluding the vicinity of the top of the sine waveform. Yes.

  The reflection mirror 70a of the laser scanning unit 70 starts rotating by the scanning drive signal output from the scanning driving unit 80 in response to the input of the synchronization signal from the external image supply device, and the rotation angle θ2 of the reflection mirror 70a with respect to the vertical scanning direction. Coincides with the angle corresponding to the start position of one frame on the screen 110, and at time T1, the rotation angle θ1 of the reflection mirror 70a with respect to the horizontal scanning direction corresponds to the start position of one horizontal scanning period on the screen 110. It is assumed that it coincides with the angle to be performed. That is, the scanning timing signal St that defines the start of one horizontal scanning period is output from the timing signal generation circuit 90c at time T1. Further, it is assumed that the rotation angle θ1 of the reflection mirror 70a with respect to the horizontal scanning direction coincides with the angle corresponding to the end position of one horizontal scanning period on the screen 110 at time T2. That is, the scanning timing signal St that defines the end of one horizontal scanning period is output from the timing signal generation circuit 90c at time T2.

 At time T1, the pixel synchronous clock generation circuit 100 receives a scanning timing signal St that defines the start of one horizontal scanning period, and a pixel that defines the irradiation timing of laser light corresponding to each pixel in one horizontal scanning period. A synchronous clock signal CL is generated and output to the red video signal buffer 10R, the green video signal buffer 10G, the blue video signal buffer 10B, and the video signal processing circuit 30. Since the rotation angle θ1 in one horizontal scanning period, that is, the irradiation position Px is uniquely related to the time elapsed from the start of one horizontal scanning period, naturally, the irradiation position Px corresponding to each pixel in one horizontal scanning period There is a unique relationship with time. Therefore, in the present embodiment, the pixel synchronous clock generation circuit 100 performs scanning that defines the start of one horizontal scanning period based on a unique relationship between the irradiation position Px and time corresponding to each pixel in one horizontal scanning period. After the timing signal St is input, the pixel synchronization clock signal CL corresponding to each pixel is generated according to the elapsed time. Here, as can be seen from FIG. 7, the pulse interval of the pixel synchronization clock signal CL changes according to the irradiation position Px, that is, the elapsed time. For example, the pulse interval is short near the center of the screen 110 and the pulse interval is long near both ends of the screen 110. This is because the changing speed (scanning speed) of the rotation angle θ1 of the reflection mirror 70a changes according to the elapsed time due to the characteristics of the laser scanning unit 70 which is a MEMS scanner.

  On the other hand, the digital video signal VR for red supplied from the external image supply device is input to the red video signal buffer 10R, and the bit data VR1 to VR4 of the digital video signal VR correspond to the first shift register 201 corresponding to each. To the fourth shift register 204. Since the pixel synchronization clock signal CL is input to the first shift register 201 to the fourth shift register 204 at the timing as shown in FIG. 7, the bit data VR1 to VR4 of the digital video signal VR are pixel synchronized. The data is sequentially shifted in synchronization with the clock signal CL, and the bit data VR1 to VR4 of the display target pixels corresponding to the current irradiation position Px of the laser beam are output from the flip-flops 201d to 204d in the final stage.

  FIG. 8 shows the pixel synchronization clock signal CL, the output signal P4 of the flip-flop 201d of the first shift register 201 in the red video signal buffer 10R, and the output signal of the flip-flop 201c within the period of time T1 to T2 shown in FIG. 11 is a timing chart showing P3, the output signal P2 of the flip-flop 201b, the output signal P1 of the flip-flop 201a, and the first current source enable signal ER1 output from the first OR circuit 301 of the red operation determination circuit 20R. . Note that FIG. 8 is described using the first shift register 201 and the first OR circuit 301 as representatives, but the other second shift register 202 to the fourth shift register 204, The same applies to the operations of the OR circuit 302 to the fourth OR circuit 304.

  First, at time t1, the pixel synchronization clock signal CL is generated, and the output signal P4 of the flip-flop 201d (that is, the bit data VR1 of the digital video signal VR corresponding to the display target pixel at time t1) is set to “1”. The output signal P3 of the flip-flop 201c is “0” which is the bit data VR1 corresponding to the pixel one pixel after the display target pixel, and the output signal P2 of the flip-flop 201b is the pixel two pixels after the display target pixel. Corresponding to “1”, the output signal P1 of the flip-flop 201a is set to “1” corresponding to the pixel three pixels after the display target pixel. At this time, the first OR circuit 301 outputs the first current source enable signal ER1 set to “1”, and the video signal processing circuit 30 outputs the bit data of the first bit of the red gradation data DR. B1 is set to “1” and output to the red laser driver 40R.

  That is, at the time t1, the first operation changeover switch SW1 in the red laser driver 40R is in the connected state, so that the first output side transistor element To1 is in the operating state. In addition, since the first output changeover switch S1 is connected to the second terminal S1b and the fourth terminal S1d, the current Is / 15 generated by the first output-side transistor element To1 becomes the drive current IR. It is included and output to the red laser diode 50R.

  Subsequently, at time t2, when the pixel synchronization clock signal CL is generated and the output signal P4 of the flip-flop 201d is set to “0” (bit data VR1 corresponding to the display target pixel at time t2), the flip-flop 201c. The output signal P3 of the flip-flop 201b is “1” corresponding to the pixel one pixel after the display target pixel, and the output signal P2 of the flip-flop 201b is “1” corresponding to the pixel two pixels after the display target pixel. In addition, the output signal P1 of the flip-flop 201a is set to “1” corresponding to the pixel three pixels after the display target pixel. At this time, the first OR circuit 301 outputs the first current source enable signal ER1 set to “1”, and the video signal processing circuit 30 outputs the bit data of the first bit of the red gradation data DR. B1 is set to “0” and output to the red laser driver 40R.

  That is, at time t2, the first operation selector switch SW1 in the red laser driver 40R maintains the connection state, so the first output-side transistor element To1 maintains the operation state. In addition, since the first output selector switch S1 is connected to the first terminal S1a and the third terminal S1c, the current Is / 15 generated by the first output-side transistor element To1 is the first dummy. It flows through the load R1 and is not included in the drive current IR.

  The same operation as described above is repeated until time t8. At time t9, the pixel synchronization clock signal CL is generated, and the output signal P4 of the flip-flop 201d (bit data VR1 corresponding to the display target pixel at time t9) is “0”. When the output signal P3 of the flip-flop 201c is set to "0" which is the bit data VR1 corresponding to the pixel immediately after the display target pixel, two output signals P2 of the flip-flop 201b are output from the display target pixel. The output signal P1 of the flip-flop 201a is set to “0” corresponding to the pixel that is three pixels after the display target pixel. At this time, the first OR circuit 301 outputs the first current source enable signal ER1 set to “0”, and the video signal processing circuit 30 outputs the bit data of the first bit of the red gradation data DR. B1 is set to “0” and output to the red laser driver 40R.

  That is, at time t9, the first operation changeover switch SW1 in the red laser driver 40R is in the non-connected state, and thus the first output side transistor element To1 is in the non-operating state. In addition, the first output changeover switch S1 is connected to the first terminal S1a and the third terminal S1c. However, since the first output side transistor element To1 is inactive, the current Is / 15 is generated. No current flows through the first dummy load R1 (power consumption does not occur).

  From time t10 to t12, the same operation as at time t9 is repeated. At time t13, the pixel synchronization clock signal CL is generated, and the output signal P4 of the flip-flop 201d (bit data VR1 corresponding to the display target pixel at time t13). Is set to “0”, the output signal P3 of the flip-flop 201c is set to “0” which is the bit data VR1 corresponding to the pixel one pixel after the display target pixel, and the output signal P2 of the flip-flop 201b is the display target The output signal P1 of the flip-flop 201a is set to “0” corresponding to the pixel two pixels after the pixel, and “1” corresponding to the pixel three pixels after the display target pixel. At this time, the first OR circuit 301 outputs the first current source enable signal ER1 set to “1”, and the video signal processing circuit 30 outputs the bit data of the first bit of the red gradation data DR. B1 is set to “0” and output to the red laser driver 40R.

  That is, at time t13, the first operation changeover switch SW1 in the red laser driver 40R is in the connected state, and thus the first output-side transistor element To1 is in the operating state. The first output changeover switch S1 is connected to the first terminal S1a and the third terminal S1c, but at this time, no current flows through the first dummy load R1. This is because the first output-side transistor element To1 which is a current source cannot be switched between the operating state and the non-operating state at high speed, and the first current source enable signal ER1 is set to “1” to perform the first operation. This is because there is a time lag from when the changeover switch SW1 is connected to when the current Is / 15 actually flows. Therefore, it is necessary to operate the first output-side transistor element To1 that is a current source after a predetermined number of pixels from the currently displayed display target pixel in consideration of the time lag until switching from the non-operating state to the operating state. It is necessary to determine whether or not there is.

  In the present embodiment, it is assumed that it is determined whether or not the first output-side transistor element To1 needs to be operated three pixels after the currently displayed display target pixel. That is, during the period from time t13 to time t15, even if the first current source enable signal ER1 is set to “1”, the current Is / 15 does not flow to the first output side transistor element To1, but at time t16. Current Is / 15 flows. In such a period t13 to t15 in which the current Is / 15 does not flow through the first output side transistor element To1, the bit data B1 of the red gradation data DR corresponding to the display target pixel is “0”, so the current Is / 15 is There is no problem on the display even if it does not flow. At time t16, the bit data B1 of the red gradation data DR corresponding to the display target pixel becomes “1”. At this time, the current Is / 15 flows through the first output-side transistor element To1, so that driving is performed. The current Is / 15 is included in the current IR, and the drive current IR corresponding to the red gradation data DR corresponding to the display target pixel can be output to the red laser diode 50R.

  Thus, in the present embodiment, it is assumed that it is determined whether or not the first output-side transistor element To1 needs to be operated three pixels after the currently displayed display target pixel. It is necessary to refer to the digital video signal for pixels, and therefore, it is necessary to use the first shift register 201 composed of four flip-flops 201a to 201d. For example, if the operating frequency of the first output-side transistor element To1 that is a current source is about 1 (MHz), it is necessary to determine whether or not it is necessary to operate 1 μs before the highest pixel. If the synchronous clock frequency is 50 (MHz), it is necessary to refer to the digital video signal for 50 pixels. In this case, the first shift register 201 may be configured by 50 flip-flops, and the output signals of all the flip-flops may be input to the first OR circuit 301. The same applies to the other second shift registers 202 to 204.

  In the above description of the operation, focusing on the bit data VR1 of the digital video signal VR, the red video signal buffer 10R, the red operation determination circuit 20R, and the red laser driver 40R have been representatively described, but the green video signal buffer 10G, The same applies to the operations of the blue video signal buffer 10B, the green operation determination circuit 20G, the blue operation determination circuit 20B, the green laser driver 50G, and the blue laser driver 50B.

 As described above, according to the image display device LSD according to the first embodiment, the digital video signal that is the source of the digital gradation data is buffered, and the current source is operated after a predetermined number of pixels from the display target pixel in advance. It is determined whether or not it is necessary, and the operation / non-operation of the current source is switched based on the operation enable signal indicating the determination result. In other words, in consideration of the time lag from when the current source is switched from the non-operating state to the operating state and when the drive current is actually generated, the current source must be operated after a predetermined number of pixels from the display target pixel. Is operated in advance and the current source is switched to the non-operating state when it is not necessary to operate it, so that it is possible to reduce the power consumption while satisfying the demand for high-speed operation.

[Second Embodiment]
Next, a second embodiment of the present invention will be described. FIG. 9 is a functional block diagram of an image display device LSD ′ according to the second embodiment. In FIG. 9, the same components as those in FIG.

 The image display device LSD ′ according to the second embodiment is different from the image display device LSD according to the first embodiment in that the video signal processing circuit 30 ′ defines a PWM (Pulse Width) that defines the gradation value of the display target pixel. Modulation) is to output a gradation signal. Here, the PWM gradation signal is a pulse signal having a pulse width corresponding to the gradation value. Specifically, the video signal processing circuit 30 ′ generates a red PWM gradation signal PR based on the digital video signal VR corresponding to the display target pixel input from the red video signal buffer 10R and generates a red laser driver 40R ′. And a green PWM gradation signal PG is generated based on the digital video signal VG corresponding to the display target pixel input from the green video signal buffer 10G and output to the green laser driver 40G ′. Based on the digital video signal VB corresponding to the display target pixel input from the blue video signal buffer 10B, a blue PWM gradation signal PB is generated and output to the blue laser driver 40B ′.

 The red laser driver 40R ′ has the red PWM gradation signal PR and the current source enable signal ER output from the red operation determination circuit 20R ′ as inputs, and a current source (first output) based on the current source enable signal ER. The operation / non-operation of the output side transistor element Tr2) is switched, and a drive current IR corresponding to the red PWM gradation signal PR is generated and output to the red laser diode 50R. Hereinafter, a detailed configuration of the red laser driver 40R 'in the second embodiment will be described.

 FIG. 10 is a circuit configuration diagram of the red laser driver 40R ′ in the second embodiment. As shown in FIG. 10, the red laser driver 40R ′ includes a first current source CS1, a second current source CS2, a first input side transistor element Tr1, a first output side transistor element Tr2, and a second current source CS2. The input side transistor element Tr3, the second output side transistor element Tr4, an operation changeover switch SW, an output changeover switch S, and a dummy load R are included.

 Since the first current source CS1 and the second current source CS2 are the same as those in the first embodiment, description thereof is omitted. The first input side transistor element Tr1 is an n-channel MOS transistor element, the drain terminal is connected to the output terminal of the first current source CS1, and the gate terminal is connected to the output terminal of the first current source CS1. One output side transistor element Tr2 is connected to the gate terminal, and the source terminal is connected to the ground line. The first output side transistor element Tr2 is an n-channel MOS transistor element, the drain terminal is connected to one terminal of the operation changeover switch SW, and the gate terminal is connected to the gate terminal of the first input side transistor element Tr1. The source terminal is connected to the ground line.

 That is, the first input-side transistor element Tr1 is set as an input-side transistor by the first current source CS1, the first input-side transistor element Tr1, and the first output-side transistor element Tr2, and the first output-side transistor element. A current mirror circuit using Tr2 as an output-side transistor (current source) is configured. Here, in the second embodiment, the electrical characteristics of the first input-side transistor element Tr1 and the first output-side transistor element Tr2 are matched. That is, the current flowing through the first output-side transistor element Tr2 is substantially the same as the current Is generated by the first current source CS1.

 The operation selector switch SW is a switch element that receives the current source enable signal ER and switches connection / disconnection between the two terminals according to the current source enable signal ER, and one terminal of the switch is a first output side transistor. The other terminal is connected to the first terminal Sa and the second terminal Sb of the output changeover switch S. The other terminal is connected to the drain terminal of the element Tr2. In the present embodiment, connection is made when the current source enable signal ER is “1”, and connection is not made when the current source enable signal ER is “0”.

 The dummy load R is a resistance element having a predetermined resistance value, and one end is connected to the power supply line Vcc and the other end is connected to the third terminal Sc of the output changeover switch S. The output changeover switch S receives the red PWM gradation signal PR, and according to the red PWM gradation signal PR, between the first terminal Sa and the third terminal Sc and between the second terminal Sb and the fourth terminal Sb. Is a switch element that switches connection / disconnection between the first terminal Sa and the second terminal Sb. The first terminal Sa and the second terminal Sb are connected to the drain terminal of the first output-side transistor element Tr2, and the third terminal Sc. Is connected to the other end of the dummy load R, and the fourth terminal Sd is connected to the input terminal of the second current source CS2. In the present embodiment, when the red PWM gradation signal PR is “1” (high level), the first terminal Sa and the third terminal Sc are not connected, and the second terminal Sb and the fourth terminal are connected. The connection between the first terminal Sa and the third terminal Sc in the case of “0” (low level), and the connection between the second terminal Sb and the fourth terminal Sd. Not connected.

 The second input side transistor element Tr3 is a p-channel type MOS transistor element, the source terminal is connected to the power supply line Vcc, the gate terminal is connected to the drain terminal and the gate terminal of the second output side transistor element Tr4. The drain terminal is connected to the input terminal of the second current source CS2 and the fourth terminal Sd of the output changeover switch S. The second output side transistor element Tr4 is a p-channel type MOS transistor element, the source terminal is connected to the power supply line Vcc, and the gate terminal is connected to the gate terminal and drain terminal of the second input side transistor element Tr3. The drain terminal is connected to the anode terminal of the red laser diode 50R.

That is, the second input side transistor element Tr3 and the second output side transistor element Tr4 are current mirror circuits having the second input side transistor element Tr3 as the input side and the second output side transistor element Tr4 as the output side. configured and, the combined current of the current flowing through the fourth terminal Sd threshold current I _th and the output switch S to the second current source CS2 is generated (i.e. is) as input, substantially the same as the combined current Is output to the red laser diode 50R as a drive current IR.

For example, assuming that the current source enable signal ER is “1”, that is, a case where the operation changeover switch SW is in a connected state, when the red PWM gradation signal PR is at a low level, the first terminal Sa of the output changeover switch S. And the third terminal Sc are connected, and the second terminal Sb and the fourth terminal Sd are not connected. Therefore, the current Is generated by the first output-side transistor element Tr2 is It flows into the dummy load R, current input to the second input-side transistor device Tr3 is only the threshold current _{I th,} the drive current IR = the threshold current _{I th.} In this case, laser light is not generated in the red laser diode 50R (that is, red is displayed in black). On the other hand, when the red PWM gradation signal PR is at a high level, the output changeover switch S is not connected between the first terminal Sa and the third terminal Sc, and the second terminal Sb and the fourth terminal Sd Is connected to each other, the current input to the second input side transistor element Tr3 is the threshold current I _th + Is, and the drive current IR is _{equal to the} threshold current I _th + Is. That is, the second terminal Sb and the fourth terminal Sd of the output selector switch S are connected only during the period when the red PWM gradation signal PR is at a high level (a period corresponding to the pulse width), and the drive current IR The laser light LR having a light amount corresponding to the current Is obtained by subtracting the threshold current I _th from the red laser diode 50R is generated for a period corresponding to the pulse width.

 Since the pulse width of the red PWM gradation signal PR defines the gradation value, when the gradation value becomes high, the pulse width also increases, and the irradiation time of the laser beam to the irradiation position corresponding to the display target pixel. Longer (display brightness becomes brighter). As described above, in the red laser driver 40R ′ in the second embodiment, the display luminance corresponding to the gradation value of the display target pixel is adjusted by adjusting the irradiation time of the laser light (pulse width of the red PWM gradation signal PR). The structure which realizes is adopted. The circuit configurations of the green laser driver 40G 'and the blue laser driver 40B' are the same as those of the red laser driver 40R 'shown in FIG.

 FIG. 11 is a circuit configuration diagram of the red operation determination circuit 20R ′ in the second embodiment. As shown in this figure, in the red operation determination circuit 20R ′ in the second embodiment, the output signals of the first OR circuit 301 to the fourth OR circuit 304 are input and the OR signal of these output signals is input. Is newly provided as a current source enable signal ER. That is, the red operation determination circuit 20R ′ outputs the logical sum signal of the output signals of all the flip-flops of the first shift register 201 to the fourth shift register 204 in the red video signal buffer 10R as the current source enable signal ER. The circuit configurations of the green operation determination circuit 20G 'and the blue operation determination circuit 20B' are the same as the red operation determination circuit 20R 'shown in FIG.

  Next, the operation of the image display device LSD ′ in the second embodiment having the above-described configuration will be described. In the following, description of operations similar to those in the first embodiment will be omitted, and characteristic operations in the second embodiment will be described.

  FIG. 12 shows the pixel synchronization clock signal CL, the output signal ER1 of the first OR circuit 301 of the red operation determination circuit 20R ′, and the second OR circuit 302 within the period of time T1 to T2 shown in FIG. 4 is a timing chart showing an output signal ER2, an output signal ER3 of a third OR circuit 303, an output signal ER4 of a fourth OR circuit 304, and a current source enable signal ER of the OR circuit 300.

  First, at time t1, the output signal ER1 of the first OR circuit 301 is “1”, the output signal ER2 of the second OR circuit 302 is “1”, and the output signal ER3 of the third OR circuit 303 is Assuming that the output signal ER4 of the fourth OR circuit 304 is set to “0”, the current source enable signal ER of the OR circuit 300 is set to “1”. That is, the current source enable signal ER is set to “1” if at least one “1” exists in the digital video signal VR from the display target pixel at the time t1 to the third pixel after.

  At this time, the video signal processing circuit 30 ′ generates a red PWM gradation signal PR that defines the gradation value of the display target pixel based on the digital video signal VR of the display target pixel input from the red video signal buffer 10R. And output to the red laser driver 40R ′. The red PWM gradation signal PR generated here is a pulse signal having a pulse width corresponding to the gradation value if the gradation value of the display target pixel is “1” or more. If the gradation value is “0”, the level is low. On the other hand, since the operation changeover switch SW in the red laser driver 40R 'is in the connected state, the first output side transistor element Tr2 is in the operating state. The output changeover switch S is generated by the first output-side transistor element Tr1 because the second terminal Sb and the fourth terminal Sd are connected if the red PWM gradation signal PR is a pulse signal. The current Is is included in the drive current IR for a period corresponding to the pulse width of the red PWM gradation signal PR and is output to the red laser diode 50R. The output changeover switch S is generated by the first output side transistor element Tr1 because the first terminal Sa and the third terminal Sc are connected if the red PWM gradation signal PR is at a low level. Current Is flowing through the dummy load R and not included in the drive current IR.

  The same operation as described above is repeated until time t8. At time t9, the output signal ER1 of the first OR circuit 301 is “0”, the output signal ER2 of the second OR circuit 302 is “0”, the third Assuming that the output signal ER3 of the OR circuit 303 is “0” and the output signal ER4 of the fourth OR circuit 304 is set to “0”, the current source enable signal ER of the OR circuit 300 is “0”. Set to That is, the current source enable signal ER is set to “0” when all the digital video signals VR from the display target pixel at the time t9 to the pixel after the third become “0”.

 At this time, the video signal processing circuit 30 ′ generates a red PWM gradation signal PR that defines the gradation value of the display target pixel based on the digital video signal VR of the display target pixel input from the red video signal buffer 10R. And output to the red laser driver 40R ′. On the other hand, since the operation changeover switch SW in the red laser driver 40R 'is in a non-connected state, the first output side transistor element Tr2 is in a non-operating state. Further, since the current source enable signal ER becomes “0” means that the gradation value of the display target pixel is “0”, the low-level red PWM gradation signal PR is output and output. In the changeover switch S, the first terminal Sa and the third terminal Sc are connected. However, since the first output side transistor element Tr2 is in a non-operating state, the current Is is not generated and the current is supplied to the dummy load R. Does not flow (no power consumption).

 From time t10 to t12, the same operation as at time t9 is repeated. At time t13, the output signal ER1 of the first OR circuit 301 is “1” and the output signal ER2 of the second OR circuit 302 is “0”. Assuming that the output signal ER3 of the third OR circuit 303 is set to “0” and the output signal ER4 of the fourth OR circuit 304 is set to “0”, the current source enable signal ER of the OR circuit 300 is assumed. Is set to “1”.

  In the present embodiment, it is assumed that it is determined whether or not the first output-side transistor element Tr2 needs to be operated three pixels after the currently displayed display target pixel. That is, during the period from time t13 to t15, even if the current source enable signal ER is set to “1”, the current Is does not flow to the first output side transistor element Tr2, but the current Is flows at time t16. become. In such a period t13 to t15 in which the current Is does not flow through the first output side transistor element Tr2, the gradation value of the display target pixel is “0”, so there is no problem in display even if the current Is does not flow. . At time t16, the gradation value of the display target pixel is at least “1” or more. At this time, the current Is flows through the first output-side transistor element Tr2, and thus the current Is is included in the drive current IR. Thus, the drive current IR corresponding to the pulse width of the red PWM gradation signal PR corresponding to the display target pixel can be output to the red laser diode 50R.

  In the above description of the operation, focusing on the bit data VR1 of the digital video signal VR, the red operation determination circuit 20R ′ and the red laser driver 40R ′ are representatively described, but the green operation determination circuit 20G ′ and the blue operation determination are performed. The same applies to the operations of the circuit 20B ′, the green laser driver 50G ′, and the blue laser driver 50B ′.

 As described above, according to the image display device LSD ′ according to the second embodiment, even when the PWM gradation signal is used instead of the digital gradation data, the high-speed operation is performed as in the first embodiment. It is possible to reduce power consumption while satisfying the requirements.

 In the first embodiment and the second embodiment, the laser scan display that scans the laser beam on the screen 110 to display an image has been described as an example. However, the present invention is not limited to this, and an LED (Light Emitting Diode) is used. ) And other light sources, the present invention can also be applied to an image display device that displays an image by scanning light. In the first and second embodiments, the laser scan display using one scanner for the three-color laser diodes has been described as an example. However, the present invention is not limited to this, and a scanner is provided for each color. Any configuration may be used.

 Further, the red video signal buffer 10R (green video signal buffer 10G, blue video signal buffer 10B), red operation determination circuit 20R (green operation determination circuit 20G, blue operation determination circuit 20B), red laser driver 40R in the first embodiment. The circuit configuration of (green laser driver 40R, blue laser driver 40B) may be changed as appropriate according to the maximum number of gradations. For example, when the maximum number of gradations is set to “256 (8 bits)”, eight shift registers, OR circuits, output side transistor elements that are current sources, operation selector switches, and output selector switches are provided. It ’s fine.

 In this case, the electrical characteristics of the output side transistor element corresponding to the bit data of the first bit are set so that a current of 1/255 of the current Is is generated, and the output side corresponding to the bit data of the second bit is set. The electrical characteristic of the transistor element is set so that a current of 2/255 of the current Is is generated, and the electrical characteristic of the output side transistor element corresponding to the bit data of the third bit is 4/255 of the current Is. Current characteristic of the output side transistor element corresponding to the bit data of the 4th bit is set so that 8/255 current of the current Is is generated, and the 5th bit. The electrical characteristics of the output-side transistor element corresponding to the bit data are set so that a current of 16/255 of the current Is is generated, and corresponds to the bit data of the sixth bit. The electrical characteristics of the force-side transistor element are set so that a current of 32/255 of the current Is is generated, and the electrical characteristic of the output-side transistor element corresponding to the bit data of the seventh bit is 64 of the current Is. The current characteristic of the output side transistor element corresponding to the bit data of the 8th bit may be set so that a current of 128/255 of the current Is is generated. .

1 is a functional block diagram of an image display device LSD according to a first embodiment of the present invention. FIG. 3 is a circuit configuration diagram of a red video signal buffer 10R and a red operation determination circuit 20R in the image display device LSD according to the first embodiment of the present invention. FIG. 3 is a circuit configuration diagram of a red laser driver 40R in the image display device LSD according to the first embodiment of the present invention. It is a laser light quantity-drive current characteristic view of red laser diode 50R in image display device LSD concerning a 1st embodiment of the present invention. FIG. 3 is a schematic configuration diagram of a laser scanning unit in the image display device LSD according to the first embodiment of the present invention. It is explanatory drawing regarding rotation angle (theta) 1 of the reflective mirror 70a which the horizontal angle sensor 90a detects in the image display apparatus LSD which concerns on 1st Embodiment of this invention. It is a 1st timing chart which shows operation | movement of the image display apparatus LSD which concerns on 1st Embodiment of this invention. It is a 2nd timing chart which shows operation | movement of the image display apparatus LSD which concerns on 1st Embodiment of this invention. FIG. 6 is a functional block diagram of an image display device LSD ′ according to a second embodiment of the present invention. FIG. 6 is a circuit configuration diagram of a red laser driver 40R ′ in an image display device LSD ′ according to a second embodiment of the present invention. FIG. 6 is a circuit configuration diagram of a red video signal buffer 10R and a red operation determination circuit 20R ′ in an image display device LSD ′ according to a second embodiment of the present invention. 12 is a timing chart showing an operation of the image display device LSD ′ according to the second embodiment of the present invention.

Explanation of symbols

  LSD, LSD ′: image display device, 10R: red video signal buffer, 10G: green video signal buffer, 10B: blue video signal buffer, 20R, 20R ′: red operation determination circuit, 20G, 20G ′: green operation determination circuit, 20B, 20B '... blue operation determination circuit, 30, 30' ... video signal processing circuit, 40R, 40R '... red laser driver, 40G, 40G' ... green laser driver, 40B, 40B '... blue laser driver, 50R ... red Laser diode, 50G ... Green laser diode, 50B ... Blue laser diode, 60 ... Optical axis alignment optical system, 70 ... Laser scanning unit, 80 ... Scanning drive unit, 90 ... Irradiation position detection unit, 100 ... Pixel synchronous clock generation circuit 110 ... screen, CS1 ... first current source, CS2 ... second current source, Ti1, Tr1 ... 1 input side transistor element, Ti2, Tr3 ... second input side transistor element, To1, Tr2 ... first output side transistor element, To2, Tr4 ... second output side transistor element, To3 ... third output side Transistor element, To4 ... fourth output side transistor element, To5 ... fifth output side transistor element, SW1 ... first operation selector switch, SW2 ... second operation selector switch, SW3 ... third operation selector switch, SW4: fourth operation changeover switch, S1: first output changeover switch, S2: second output changeover switch, S3: third output changeover switch, S4: fourth output changeover switch, R1: first output changeover switch Dummy load, R2 ... Second dummy load, R3 ... Third dummy load, R4 ... Fourth dummy load, SW ... Operation selector switch, S ... Output selector switch H, R ... dummy load, 60a ... first dichroic mirror, 60b ... second dichroic mirror, 70a ... reflection mirror, 70b ... first torsion spring, 70c ... inner frame, 70d ... second torsion spring, 70e ... Outer frame part, 90a ... Horizontal angle sensor, 90b ... Vertical angle sensor, 90c ... Timing signal generation circuit

Claims (7)

Generating a scanning means for scanning the light generated from the light source to the projection morphism surface, a tone signal for defining the tone values of pixels corresponding to the irradiation position of the light definitive video signal to the input pre Kito morphism surface The video signal processing means, a drive signal source for generating a drive signal corresponding to the gradation signal, a dummy load, and an output destination of the drive signal are switched to either the dummy load or the light source according to the gradation signal. Drive signal generating means having an output changeover switch for the image display device,
The video signal input from the outside accumulating a predetermined number of pixels, and the image for outputting video signals to be displayed pixels corresponding to the irradiation position of the light having the predetermined timekeeping before Kito morphism surface to said video signal processing means Signal storage means;
Based on the video signal stored in said video signal storage means, to determine the whether Luke not a drive signal source to operate during a period from the display pixel of said predetermined time to display target pixel after a predetermined number of pixels Operation determining means for outputting a signal source operation enable / disable signal indicating the determination result;
With
The drive signal generation means includes operation switching means for switching operation / non-operation of the drive signal source based on the signal source operation availability signal.
An image display device characterized by that. The video signal is a digital video signal having a bit number N,
The video signal storage means includes
The first to Nth shift registers are provided corresponding to each bit data of the digital video signal, each bit data corresponding to the input is input, and a plurality of flip-flops are connected in series.
The operation determination means includes
Provided corresponding to each of the first to Nth shift registers, and outputs a logical sum signal of the output signals of all flip-flops in the corresponding shift register as the first to Nth signal source operation enable / disable signals. Having first to Nth OR circuits;
The video signal processing means includes
The number of bits that defines the output signal of the flip-flop at the last stage in the first to Nth shift registers as the digital video signal of the display target pixel and defines the gradation value of the display target pixel based on the digital video signal N digital gradation signals are generated,
The drive signal generation means includes
A first current source for generating a current corresponding to the maximum gradation value;
The first terminal of the two terminals excluding the control terminal is connected to the first current source, the second terminal is connected to the first common potential line, and the control terminal is the first terminal of itself. An input-side transistor element connected to
Provided corresponding to each bit of the digital gradation signal, a second terminal of the two terminals excluding the control terminal is connected to the first common potential line, and the control terminal is connected to the input side transistor element. First to Nth output side transistor elements connected to the control terminal;
Provided corresponding to each of the first to Nth signal source operation enable / disable signals, and one of the two terminals is connected to the first terminal of the corresponding first to Nth output side transistor elements. First to Nth operation switching means for switching connection / disconnection between the two terminals according to the first to Nth signal source operation enable / disable signals corresponding to each of them,
A second current source for generating a threshold current of the light source;
A first to Nth dummy load provided corresponding to each bit of the digital gradation signal and having one end connected to a second common potential line;
The other terminals of the first to Nth operation switching means corresponding to each bit data provided corresponding to each bit of the digital gradation signal are connected to the first to Nth operation switching means corresponding to each bit data. First to Nth output changeover switches for switching between connecting to the other end of the dummy load or connecting to one end of the second current source;
A current mirror circuit that outputs, as the drive signal, a drive current having substantially the same current value as a current flowing through one end of the second current source;
The electrical characteristics of the first to Nth output side transistor elements are set so as to generate a current corresponding to the bit data corresponding to each of the first to Nth output side transistor elements.
The image display device according to claim 1. The video signal is a digital video signal having a bit number N,
The video signal storage means includes
The first to Nth shift registers are provided corresponding to each bit data of the digital video signal, each bit data corresponding to the input is input, and a plurality of flip-flops are connected in series.
The operation determination means includes
A logical sum circuit that outputs a logical sum signal of output signals of all flip-flops in the first to Nth shift registers as the signal source operation enable / disable signal;
The video signal processing means includes
The PWM (which defines the gradation value of the display target pixel based on the digital video signal by inputting the output signal of the flip-flop at the last stage in the first to Nth shift registers as the digital video signal of the display target pixel. (Pulse Width Modulation)
The drive signal generation means includes
A first current source for generating a current corresponding to the maximum gradation value;
The first terminal of the two terminals excluding the control terminal is connected to the first current source, the second terminal is connected to the first common potential line, and the control terminal is the first terminal of itself. An input-side transistor element connected to
A second terminal of the two terminals excluding the control terminal is connected to the first common potential line, and the output side transistor element is connected to the control terminal of the input side transistor element;
One of the two terminals is connected to the first terminal of the output side transistor element, and an operation switching means for switching connection / disconnection between the two terminals according to the signal source operation enable / disable signal;
A second current source for generating a threshold current of the light source;
A dummy load having one end connected to the second common potential line;
An output changeover switch for switching whether to connect the other terminal of the operation switching means to the other end of the dummy load or to one end of the second current source according to the PWM gradation signal;
A current mirror circuit that outputs, as the drive signal, a drive current having substantially the same current value as a current flowing through one end of the second current source;
The image display device according to claim 1. The scanning unit includes a reflection mirror that reflects the light, and a first rotation support unit that rotates the reflection mirror about a first axis along a reflection surface of the reflection mirror. Mechanical System) scanner,
An irradiation position detecting means for detecting the rotation angle of the first axis of the reflecting mirror as the light irradiation position of the definitive before Kito morphism surface,
Pixel synchronization clock generation means for generating a pixel synchronization clock signal that defines the output timing of the gradation signal to the drive signal generation means according to the light irradiation position detected by the irradiation position detection means;
With
Using the pixel synchronization clock signal as a clock signal of the flip-flop in the video signal storage means,
The video signal processing means outputs a gradation signal of a display target pixel to the drive signal generation means in synchronization with the image synchronization clock signal;
The image display device according to claim 2, wherein the image display device is an image display device. A light source;
Scanning means for scanning the projection surface with light generated from the light source;
Video signal storage means for storing the input video signal and outputting a video signal of a pixel corresponding to the irradiation position of the light at the first time T1 on the projection plane;
Video signal processing means for receiving the video signal output from the video signal storage means and generating a gradation signal defining a gradation value of a pixel corresponding to the irradiation position at the first time T1,
Drive signal generating means comprising a drive signal source for generating a drive signal in accordance with the gradation signal generated by the video signal processing means;
An operation determining unit that determines whether the drive signal source is operable with reference to the video signal stored in the video signal storage unit, and that outputs a signal source operation enable / disable signal indicating the determination result;
The drive signal generation means includes
An operation switching means for switching the drive signal source to an operating or stopped state in response to the signal source operation enable / disable signal output from the operation determining means;
Dummy load,
An output changeover switch that switches the output destination of the drive signal to either the dummy load or the light source,
The operation determination means includes
When there is a pixel irradiated with the light among pixels corresponding to a position irradiated between the first time T1 and a second time T2 later than the first time T1, Outputting the signal source operation enable / disable signal for operating the drive signal source;
When there is no pixel irradiated with the light among the pixels corresponding to the position irradiated between the first time T1 and the second time T2, the driving signal source is stopped. Output signal source operation enable / disable signal,
An image display device characterized by that. Scanning means for scanning the projection surface with light generated from the light source; and video signal processing means for inputting a video signal and generating a gradation signal for defining a gradation value of a pixel corresponding to the light irradiation position on the projection surface; An output changeover switch for switching a drive signal source for generating a drive signal according to the gradation signal, a dummy load, and an output destination of the drive signal to either the dummy load or the light source according to the gradation signal A drive signal generation means comprising: a driving method for an image display device comprising:
The video signal input from the outside is accumulated for a predetermined number of pixels, and a video signal of a display target pixel corresponding to a light irradiation position at a predetermined time on the projection plane is output to the video signal processing means,
Based on the accumulated video signal, it is determined whether to operate the drive signal source between the display target pixel at the predetermined time and the display target pixel after a predetermined number of pixels, and based on the determination result Switching the operation / non-operation of the drive signal source,
An image display device driving method characterized by the above. A drive device for an image display device that displays an image by scanning light generated from a light source on the projection surface based on a video signal,
Video signal storage means for storing the input video signal and outputting a video signal of a pixel corresponding to the irradiation position of the light at the first time T1 on the projection plane;
Video signal processing means for receiving the video signal output from the video signal storage means and generating a gradation signal defining a gradation value of a pixel corresponding to the irradiation position at the first time T1,
Drive signal generating means comprising a drive signal source for generating a drive signal in accordance with the gradation signal generated by the video signal processing means;
An operation determining unit that determines whether the drive signal source is operable with reference to the video signal stored in the video signal storage unit, and that outputs a signal source operation enable / disable signal indicating the determination result;
The drive signal generation means includes
An operation switching means for switching the drive signal source to an operating or stopped state in response to the signal source operation enable / disable signal output from the operation determining means;
A dummy load,
An output changeover switch that switches the output destination of the drive signal to either the dummy load or the light source,
The operation determination means includes
When there is a pixel irradiated with the light among pixels corresponding to a position irradiated between the first time T1 and a second time T2 later than the first time T1, Outputting the signal source operation enable / disable signal for operating the drive signal source;
When there is no pixel irradiated with the light among the pixels corresponding to the position irradiated between the first time T1 and the second time T2, the driving signal source is stopped. A drive device for an image display device, characterized in that a signal source operation enable / disable signal is output .

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