JP5016071B2 - Semiconductor flash memory - Google Patents

Description

  The present invention relates to a semiconductor flash memory.

  In a semiconductor flash memory, in general, when erasing / writing is repeated many times, application of a high voltage during writing / erasing causes stress, so that the transconductance characteristic gm of the memory cell is physically As a result, it is known that the on-current of the memory cell decreases and the off-current increases. If the phenomenon that the transconductance gm decreases is referred to as “gm deterioration”, the adverse effects of gm deterioration include “decrease in reading speed due to decrease in on-current of memory cell” and “increase in off-leakage current of unselected memory cell. Decrease in read margin associated with “.

  The former is that sensing is performed by inputting the on-current of the memory cell to the sense amplifier at the time of reading, so that when the on-current decreases, the reading speed decreases. The latter also means that the difference between the on-current and the off-leakage current is reduced by the increase in the off-leakage current of the non-selected memory cell, and it becomes difficult to determine “0” or “1” of the read data, so that the read margin is reduced. .

  For example, Patent Document 1 discloses a technique for writing true data to two or more memory cells and obtaining true data by logical sum or majority decision at the time of reading in order to cope with the above-described gm degradation. Further, Patent Document 2 discloses a technique for writing the same data to two or more memory cells and simultaneously reading the data. However, it is considered that the adjustment of the verify threshold is collectively performed for two or more memory cells. Therefore, there is a possibility that a threshold value is generated between simultaneously written memory cells.

JP 2001-43691 A

  However, conventionally, when reading from a semiconductor flash memory, 1-bit data is read by sensing the on-current of one memory cell. Therefore, when the above-described gm deterioration occurs, the reading speed decreases. It was. On the other hand, a large number of rewrite guarantees has been requested from the user side due to factors such as complexity of applications.

  In this case, if the data that is frequently requested to be rewritten has a relatively small capacity, the data area is a highly reliable block of “multiple cells / 1-bit configuration”, and other data areas that have a relatively small number of rewrites. The normal reliability block of “one cell / one bit configuration” is effective in reducing the cost in applications where high reliability is required for the semiconductor flash memory.

  However, in order to realize this, it is necessary to solve the following problems. In other words, in a plurality of erase blocks existing in a semiconductor flash memory, when a high reliability block and a normal reliability block are mixed, a plurality of block layouts must be newly formed by different word line decoding methods. This situation should be avoided as much as possible because it impairs the reusability of the layout. In addition, it should be avoided that the circuit area is remarkably increased and the layout area is increased due to the difference in decoding method.

  It should also be noted that selecting a plurality of word lines can lead to a loss of high-speed access. When a plurality of word lines are selected at the same time, the load to be finally driven is a multiple of that when a single word line is selected. Configure the circuit so that the fanout of the drive circuit does not become extremely large compared to the block that selects a single word line in a block that selects multiple word lines at the same time without impairing circuit reusability It is required to do. Otherwise, since it becomes necessary to change the timing for reading depending on the block to be accessed, the semiconductor flash memory becomes difficult to use when viewed from the user side.

  The present invention has been made in view of the above, and provides a semiconductor flash memory capable of maintaining high-speed accessibility and realizing good circuit layout reusability between a high-reliability block and a normal-reliability block. The purpose is to obtain.

In order to achieve the above-described object, a semiconductor flash memory according to the present invention includes a plurality of memory cells arranged in a matrix, a plurality of word lines arranged corresponding to the rows of the plurality of memory cells, Each of the plurality of word line drivers provided corresponding to the plurality of word lines and driving the corresponding word line, and a first predecode signal obtained by decoding an address signal serving as an input signal of the plurality of word line drivers and a first predecoder circuit for generating a word line when reading data is selected only one, first that holds one bit of information in a single memory cell to be driven by the selected word line and block, the arranged near the first block, the second pre-decoding the address signals applied to the power supply side terminal of each word line driver of the first block A second predecode circuit for generating a code signal; a plurality of memory cells arranged in a matrix; a plurality of word lines arranged corresponding to rows of the plurality of memory cells; A plurality of word line drivers provided corresponding to the word lines and driving a corresponding word line, and a third predecode signal generated by decoding an address signal serving as an input signal of the plurality of word line drivers. A predecode circuit, and at the time of normal data reading, a plurality of word lines are simultaneously selected , and 1-bit information is obtained by adding the cell currents of a plurality of memory cells driven by the selected plurality of word lines. It holds, at the time of operation other than the normal data reading one or more word lines fewer than during the normal data read is selected, than the first block A plurality of second blocks small amounts, is arranged in the vicinity of the plurality of second blocks, the fourth pre-decoded by decoding the address signal applied to the power supply terminals of each wordline driver of the second block A fourth predecode circuit that generates a signal in common to the plurality of second blocks, and the layout of the first block and the second predecode circuit includes the plurality of second blocks, This is shared with the layout of the fourth predecode circuit .

According to the present invention, the second block to ensure high reliability by holding one bit of data in multiple cells (reliability block), 1 cheap not high reliability per bit bit / 1 in the case of providing a mix of the first block of cells (usually reliable block), maintaining the high-speed access properties, and reusability of good circuit layout between the highly reliable block the normal reliability block There is an effect that can be realized.

FIG. 1 is a block diagram showing a basic configuration of a word line decoding circuit of a semiconductor flash memory according to Embodiment 1 of the present invention. FIG. 2 is a circuit diagram showing a configuration of the high reliability block shown in FIG. FIG. 3 is a circuit diagram showing a configuration of the normal reliability block shown in FIG. FIG. 4 is a block diagram showing a basic configuration of the word line decoding circuit of the semiconductor flash memory according to the second embodiment of the present invention. FIG. 5 is a circuit diagram showing a configuration of the high reliability block shown in FIG. FIG. 6 is a circuit diagram showing a configuration of the normal reliability block shown in FIG.

  Embodiments of a semiconductor flash memory according to the present invention will be described below in detail with reference to the drawings. Note that the present invention is not limited to the embodiments.

Embodiment 1 FIG.
FIG. 1 is a block diagram showing a basic configuration of a word line decoding circuit of a semiconductor flash memory according to Embodiment 1 of the present invention. FIG. 2 is a circuit diagram showing a configuration of the high reliability block shown in FIG. FIG. 3 is a circuit diagram showing a configuration of the normal reliability block shown in FIG.

In Figure 1, pre-decode circuit 110 includes a predecode signal _ZA 0 _{~ZA 3} of the lower address _A 0 to A ₁ and predecoding of the address _A 0 _{to A n-1,} the address _A 2 _{to A n-1} The other predecode signal 111 and the block selection signal 112 obtained by predecoding the signal are output. Here, the predecode signals ZA _{0 to} ZA ₃ are used as block addresses, and the inverted signal is expressed by adding “/” to ZA ₀ = / A ₀ · / A ₁ and ZA ₁ = / A ₀ · A ₁ , ZA ₂ = A ₀ · / A ₁ , and ZA ₃ = A ₀ · A ₁ .

i (i ≧ 2) high reliability blocks (# 1) 130 to high reliability blocks (#i) 131 and j (j ≧ 1) normal reliability blocks (# 1) 145 to normal reliability blocks (#J) 155 is physically arranged adjacent to each other even if they are mixed in the physical address space. The high-reliability block (# 1) 130 to the high-reliability block (#i) 131 are configured as shown in FIG. 2, respectively, and the normal reliability block (# 1) 145 to the normal reliability block (#J) 155 is configured as shown in FIG. In the Figure 1 and later, each block, although not shown only four word lines from the convenience of description, in fact, is the presence of a larger number of word lines.

A common predecode circuit PDW is provided for i high reliability blocks (# 1) 130 to high reliability blocks (#i) 131. The predecode circuit PDW is composed of two AND circuits 120 and 121 in the first embodiment. The high reliability block # 1 selection signal to the high reliability block #i selection signal in the block selection signal 112 are ORed by the OR circuit 115 and applied to one input terminal of the AND circuits 120 and 121. The The address / _{A 0} obtained by inverting the least significant address _{A 0} by the inverter 11 3 is applied to the other input terminal of the AND circuit 120. On the other hand, to the other input terminal of the AND circuit 121 addresses _{A 0} obtained by inverting the output by the inverter 114 of the inverter 11 3 is applied. Predecode signals ZAW ₀ and ZAW ₁ that are the outputs of the AND circuits 120 and 121 are commonly supplied to i high reliability blocks (# 1) 130 to high reliability blocks (#i) 131.

Further, the block selection signal 112 and the predecode signal 111 are input to the i high reliability blocks (# 1) 130 to the high reliability block (#i) 131. FIG. 2 shows the configuration of the high reliability block (# 1) 130 as a representative example. As shown in FIG. 2, the high reliability block (# 1) 130 has four word line drivers WLDE ₀ and WLDO _0. , WLDE ₁ and WLDO _1, and a predecode circuit PDGW ₀ .

The power supply side input terminals of the word line drivers WLDE ₀ and WLDO ₀ are commonly connected to the output terminal of the AND circuit 120, and the power supply side input terminals of the word line drivers WLDE ₁ and WLDO ₁ are commonly connected to the output terminal of the AND circuit 121. It is connected to the. The gate side input terminals of the four word line drivers WLDE ₀ , WLDO ₀ , WLDE ₁ and WLDO ₁ are connected in parallel to the output terminal of the predecode circuit PDGW ₀ .

The highly reliable block # 1 select signal 112 and the pre-decode signal 111 is input to the predecoder circuit PDGW _0. The predecode circuit PDGW ₀ calculates the logical product of the high reliability block # 1 selection signal 112 and the predecode signal 111 and uses the gate side input terminals of the four word line drivers WLDE ₀ , WLDO ₀ , WLDE ₁ and WLDO _1. Activate or deactivate all at once.

The power supply input terminal of the word line driver WLDE _0, WLDO ₀ predecode signals ZAW ₀ is commonly applied to the power supply input terminal of the word line driver WLDE _1, WLDO ₁ is the pre-decode signal ZAW ₁ common Therefore, the word lines WLE ₁₀ and WLO ₁₀ are selected as a pair, and the word lines WLE ₁₁ and WLO ₁₁ are selected as a pair.

  As described above, since two word lines can be selected at the same time, two memory cells in which the same data has been written in advance can be simultaneously selected and connected to the same bit line. As a result, the memory cell current for two memory cells drives the bit line, so that the conductance gm of the memory cell can be apparently doubled.

On the other hand, in the normal reliability block (# 1) 145 to the normal reliability block (#j) 155, one word line is selected independently by the predecode signals ZA _{0 to} ZA ₃ respectively. Yes. That is, in the normal reliability block (# 1) 145, the normal reliability block # 1 selection signal in the block selection signal 112 and the corresponding predecode signal in the other predecode signal 111 are input, and four AND circuits are provided. 140-143 four predecode signal obtained by ANDing the predecode signals _ZA 0 _{~ZA 3} and normal reliability block # 1 selection signal is input at the four word lines _{WL 10, WL 11, WL 12} , WL ₁₃ , only one of the power supply side terminals of the word line driver that drives WL ₁₃ is selected.

In the normal reliability block (#j) 155, the normal reliability block #j selection signal in the block selection signal 112 and the corresponding predecode signal in the other predecode signal 111 are input, and four AND circuits 150-153 four predecode signal obtained by ANDing the predecode signals _ZA 0 _{~ZA 3} and normal reliability block #j selection signal is input at the four word lines _{WL j0, WL j1, WL j2} one only in the power supply side terminal of the word line driver for driving the WL _j3 is selected.

FIG. 3 shows the configuration of the normal reliability block (# 1) 145 as a representative example. As shown in FIG. 3, the normal reliability block (# 1) 145 includes four word line drivers WLD ₀ and WLD _1. , WLD ₂ and WLD ₃ and a predecode circuit PDG ₀ .

The power supply side input terminal of the word line driver WLD ₀ is connected to the output terminal of the AND circuit 140, the power supply side input terminal of the word line driver WLD ₁ is connected to the output terminal of the AND circuit 141, and the power supply side of the word line driver WLDE ₂ The input terminal is connected to the output terminal of the AND circuit 142, and the power supply side input terminal of the word line driver WLD ₃ is connected to the output terminal of the AND circuit 143. The gate side input terminals of the four word line drivers WLD ₀ , WLD ₁ , WLD ₂ and WLD ₃ are connected in parallel to the output terminal of the predecode circuit PDG ₀ .

The normally reliable block # 1 selection signal signal 112 and the pre-decode signal 111 is input to the predecoder circuit PDG _0. The predecode circuit PDG ₀ takes the logical product of the normal reliability block # 1 selection signal signal 112 and the predecode signal 111 and inputs the gate side input terminals of the four word line drivers WLD ₀ , WLD ₁ , WLD ₂ and WLD _3. Are activated or deactivated collectively.

Predecode signals _ZA 0 _{~ZA 3} is a power supply-side input of the word line driver _WLD 0 _{~WLD 3,} since only one is activated, only the word line just one is selected according to the address A0, A1 Is done.

As described above, according to the first embodiment, in two or more high-reliability blocks, the predecode circuit PDW can be shared by sharing the predecode signals ZAW ₀ and ZAW ₁ , so that the layout area can be reduced. Become. Further, since the high reliability blocks sharing the predecode signals ZAW ₀ and ZAW ₁ are arranged adjacent to each other, when the predecode signal is shared by two or more high reliability blocks, wiring of the predecode signal is performed. The length can be shortened. Therefore, the time from the address change to the rise of the word line can be shortened, and the access speed can be increased.

Embodiment 2. FIG.
FIG. 4 is a block diagram showing a basic configuration of a word line decoding circuit of a semiconductor flash memory according to the second embodiment of the present invention. FIG. 5 is a circuit diagram showing a configuration of the high reliability block shown in FIG. FIG. 6 is a circuit diagram showing a configuration of the normal reliability block shown in FIG.

In the first embodiment (FIG. 1), two adjacent word line drivers share predecode signals ZAW ₀ and ZAW ₁ respectively, so that two word lines can be selected simultaneously in the high reliability block. However, it cannot be selected one by one. However, even in the high reliability block, it may be desirable to select a plurality of memory cells in which the same data is written one by one, such as during a write verify operation or when a program voltage is applied. Hereinafter, a write operation will be described as an example.

  The write operation is performed by performing write verify after applying the write voltage and determining whether or not the threshold value of the memory cell has risen above a desired value. When the threshold value of the memory cell rises above a desired value, the application of the write voltage is stopped and the write operation is terminated. When the threshold level of the memory cell is lower than a desired value, a write voltage is further applied to continue the write operation. The operation of determining whether or not the threshold value of the memory cell has risen to a desired value is called a write verify operation, and is performed by selecting a memory cell to be written and performing reading.

  In this write verify operation, if the write verify is performed using the same voltage condition as that of the normal read operation, the margin at the time of reading is eliminated, and for example, a voltage higher than that at the time of normal reading is applied to the word line, that is, the memory as the write verify voltage. It is applied to the gate electrode of the cell and it is checked whether or not the obtained memory cell current is smaller than a desired current value.

  If the threshold value varies among a plurality of memory cells selected at the same time during a write verify operation performed in the middle of the write operation, only one of the plurality of memory cells does not sufficiently increase the threshold value. In other memory cells, the threshold can be raised sufficiently. In this case, when only one memory cell having a low threshold value passes a current exceeding the write verify determination current value, it is determined by verify read that all the memory cells selected simultaneously are insufficiently written. Things happen. As a result, the program voltage is applied collectively to other memory cells except for one memory cell having a low threshold value among a plurality of memory cells selected at the same time, although they are sufficiently written. Thus, there are memory cells to which an excessive program voltage is applied. The application of such an excessive program voltage is a problem in reliability because the deterioration of the memory cell is accelerated.

Therefore, even in a high-reliability block that simultaneously selects a plurality of memory cells at the time of reading, it is preferable to select a plurality of memory cells that hold the same data one by one at the time of write verification and program voltage application. This is desirable in reducing cell degradation. FIG. 4 is a circuit example configured from such a viewpoint. In FIG. 4, are denoted by the same reference numerals in the configuration is identical to the like and the elements shown in FIG. Here, the description will be focused on the portion related to the second embodiment.

That is, as shown in FIG. 4, the predecode circuit PDW provided in common for the i high reliability blocks (# 1) 17 1 to the high reliability blocks (#i) 17 2 includes four AND circuits. 161-164. A predecode circuit 160 for supplying predecode signals ZAW _{0 to} ZAW ₃ is provided at one input terminal of each of the four AND circuits 161 to 164 of the predecode circuit PDW. The outputs of the OR circuit 115 are commonly input to the other input terminals of the four AND circuits 161 to 164.

Predecode circuit 160, a combination circuit of two inverters and four OR circuits and four AND circuits, in addition to the lowest address _{A 0,} the address AW and READ signal. The lowest address _A0 is one input of two AND circuits among the four AND circuits. The lowest address _A0 is inverted by one inverter and is one input of the remaining two AND circuits.

  The address AW is a binary level signal for identifying which one of the word lines is selected in two pairs as described in the first embodiment when reading the highly reliable block. The address signal AW is one input of two OR circuits among the four OR circuits. The address signal AW is inverted by the remaining inverters and is one input of the remaining two OR circuits. As the address AW, an address not related to address decoding of the normal reliability block is used.

The READ signal is a binary level signal that is at the H level when reading the highly reliable block and is at the L level when not reading. This READ signal is the other input of each of the four OR circuits. The outputs of these four OR circuits are the other inputs corresponding to the four AND circuits. Thus, predecode signals ZAW _{0 to} ZAW ₃ are output from the four AND circuits.

Here, the predecode signals ZAW _{0 to} ZAW ₃ are as follows. That is, ZAW ₀ = / A ₀ · (READ · / AW). ZAW ₁ = / A ₀ · (READ · AW). ZAW ₂ = A ₀ · (READ · / AW). ZAW ₃ = A ₀ · (READ · AW).

FIG. 5 shows the configuration of the high reliability block (# 1) 171 as a representative example. As shown in FIG. 5, the high reliability block (# 1) 171 has four word line drivers WLDE ₀ and WLDO _0. , WLDE ₁ and WLDO ₁ and a predecode circuit PDG W ₀ . Although the gate side input terminals of the four word line drivers WLDE ₀ , WLDO ₀ , WLDE ₁ and WLDO ₁ are connected in parallel to the output terminal of the predecode circuit PDGW ₀ , they are the same as in the first embodiment. The connection relations of the power supply side input terminals of the four word line drivers WLDE ₀ , WLDO ₀ , WLDE ₁ and WLDO ₁ are different.

That is, the power supply side input terminal of the word line driver WLDE ₀ is connected to the output terminal of the AND circuit 161. The power supply side input terminal of the word line driver WLDO ₀ is connected to the output terminal of the AND circuit 162. The power supply side input terminal of the word line driver WLDE ₁ is connected to the output terminal of the AND circuit 163. The power supply side input terminal of the word line driver WLDO ₁ is connected to the output terminal of the AND circuit 164.

Here, the conditions for selecting the word lines WLE ₁₀ , WLO ₁₀ , WLE ₁₁ , WLO ₁₁ are as follows. That is, WLE ₁₀ = / A _n−1 ... / A ₀ · / AW. WLO ₁₀ = / A _n−1 ... / A ₀ · AW. WLE ₁₁ = / _n-1 ... A ₀ · / AW. WLO ₁₁ = / A _n−1 ... A ₀ · AW.

In the above configuration, during an operation other than normal reading in which the READ signal is at L level, pre-decode signals ZAW _{0 to} ZAW ₃ are pre-decoded when address AW and addresses A _{0 to An 1} are all at L level. Only the decode signal ZAW ₀ becomes H level, and the gate side input terminals of the word line drivers WLDE ₀ , WLDO ₀ , WLDE ₁ , WLDO ₁ become H level. Therefore, only the word line WLE ₁₀ is at H level. That is, only a single word line is selected.

When only the address AW is at the H level and the addresses A _{0 to An 1} are all at the L level, the gate side input terminals of the word line drivers WLDE ₀ , WLDO ₀ , WLDE ₁ , WLDO ₁ are at the H level, Of the predecode signals ZAW _{0 to} ZAW ₃ , only the predecode signal ZAW ₁ is at the H level, so that only the word line WLO ₁₀ is selected.

On the other hand, during the normal read operation in which the READ signal is at the H level, regardless of whether the address AW is at the H level or the L level, the word lines WLE ₁₀ and WLO ₁₀ and the word lines WLE ₁₁ and WLO ₁₁ are Each is selected in pairs. Therefore, for example, when the addresses A _{0 to An n−1} are all at the L level, the word lines WLE ₁₀ and WLO ₁₀ are selected in pairs, and two memory cells are simultaneously selected. Moreover, only the address _{A 0} is H level, the word line _WLE 11, _{WLO 11} are selected in pairs when the address _{A 1 ~A n-1} are all L level, also the two memory cells are simultaneously selected .

Here, in the configuration in which two word lines are simultaneously selected during the normal read operation, it is necessary to pay attention to the difference from the first embodiment. That is, in the first embodiment, the power supply side terminals of the word line drivers that drive two word lines that are selected simultaneously are connected to the same predecode signal. For example, the power supply side terminals of word line drivers WLDE ₀ and WLDO ₀ for driving simultaneously selected word lines WLE ₁₀ and WLO ₁₀ are connected to the same predecode signal ZAW ₀ . In this case, the driving circuit of the predecode signals ZAW ₀ (the AND circuit 120) will be necessary to drive the parasitic load of the two word lines via the word line drivers. Therefore, in order to achieve the same word line rising speed in the normal reliability block and the high reliability block, it is necessary to carefully determine the driving force of the predecode signal driver in consideration of an increase in load.

On the other hand, in the second embodiment, the power supply side terminals of the word line drivers that drive two word lines that are simultaneously selected during the normal read operation are connected to different predecode signals. That is, in the high reliability block, the parasitic loads on the word lines driven by the drive circuits (AND circuits 161 to 164) of the predecode signals ZAW _{0 to} ZAW ₃ used for decoding are pre-used in the normal reliability block. One line is the same as the decode signal driver.

Therefore, in the second embodiment, if the load of the predecode signal itself is approximately the same as the predecode signal used in the normal reliability block, the predecode signal ZAW ₀ to ZAW ₀ used for decoding in the high reliability block will be described. driving circuit (aND circuit 161 to 164) of ZAW ₃ would be the same as the drive circuit of the predecode signals _ZA 0 _{~ZA 3} used in a normal reliable block (aND circuit 180-183).

On the other hand, regarding the decoding of the gate side input terminal of the word line driver, in the high reliability block, it is necessary to decode the addresses A _{0 to} A _n−1 , whereas in the normal reliability block, the addresses A ₂ to An _n-1 may be decoded, and the reliability block usually has fewer addresses to be predecoded by 1 bit. That is, the number of inputs of the NAND circuit, which is a circuit for predecoding the gate side input terminal of the word line driver, is one more in the high reliability block.

Therefore, if the normal reliability block is configured as shown in FIG. 6, the layout can be shared between the high reliability block and the normal reliability block. However, in this case, the memory capacity of the high reliability block is half that of the normal reliability block. That is, as shown in FIG. 6, if one input terminal of the predecode circuit PDG ₀ is connected to the power source 200 and fixed to the H level, the layout can be completely shared.

  As described above, according to the second embodiment, it is also possible to select a plurality of word lines simultaneously by sharing a predecode signal in two or more highly reliable blocks. However, it is possible to select a number smaller than the plurality. At that time, the high reliability block and the normal reliability block share the layout, and their word line rise times can be made equal.

  As described above, the semiconductor flash memory according to the present invention includes a highly reliable block that secures high reliability by holding 1-bit data in a plurality of cells, and 1 bit that is not highly reliable but has a low bit unit price. / Semiconductor capable of maintaining high-speed accessibility and realizing good circuit layout reusability between the high-reliability block and the normal-reliability block when a single-cell normal-reliability block is provided in a mixed manner It is useful as a flash memory, and is particularly suitable for cost reduction in applications where high reliability is required for a semiconductor flash memory.

110, PDW, PDGW ₀ , PDG ₀ , 160 Predecode circuit 115 OR circuit 130 to 131 High reliability block 145 to 155 Normal reliability block WLDE ₀ , WLDO ₀ , WLDE ₁ , WLDO ₁ Word line drivers WLD _{0 to} WLD ₃ Word line driver 120, 121, 161-164 AND circuit

Claims (4)

A plurality of memory cells arranged in a matrix, a plurality of word lines arranged corresponding to the rows of the plurality of memory cells, and a corresponding word line provided corresponding to the plurality of word lines And a first predecode circuit that generates a first predecode signal obtained by decoding an address signal that is an input signal of the plurality of wordline drivers, and the word line is only one is selected, a first block that holds one bit of information in a single memory cell to be driven by the selected word line,
A second predecode circuit that is disposed in the vicinity of the first block and generates a second predecode signal obtained by decoding an address signal applied to a power supply side terminal of each word line driver of the first block;
A plurality of memory cells arranged in a matrix, a plurality of word lines arranged corresponding to rows of the plurality of memory cells, and corresponding word lines provided corresponding to the plurality of word lines And a third predecode circuit that generates a third predecode signal obtained by decoding an address signal that is an input signal of the plurality of wordline drivers, and at the time of normal data reading, A plurality of lines are selected simultaneously , and 1-bit information is held by adding the cell currents of a plurality of memory cells driven by the selected plurality of word lines, and during operation other than normal data reading the normal one or more word lines is less than the time of data reading is selected, and a plurality of second blocks smaller capacity than the first block,
Disposed in the vicinity of the plurality of second blocks, common to the fourth of the second block of predecode signals of said plurality of decoding the address signals applied to the power supply side terminal of each word line driver in the second block A fourth predecode circuit generated in
The semiconductor flash memory characterized in that a layout of the first block and the second predecode circuit is shared with a layout of the plurality of second blocks and the fourth predecode circuit . Normal data reading and a first control signal identifying the operation of the non-normal data read, the normal operation other than the normal data read in the plurality of word lines to be selected when reading data based on a second control signal specifying a word line to be selected at the fifth pre-generating a fifth pre-decode signals of mutually different applied to the power supply side terminal of each word line drivers in each of the second blocks The semiconductor flash memory according to claim 1, further comprising a decoding circuit. It said second control signal, claims, characterized in that the normal address signals for designating individually a plurality of word lines for selecting the normal data read out as word lines for selecting the operation other than the data reading 2. The semiconductor flash memory according to 2. Wherein the address signal, a semiconductor flash memory according to claim 3, characterized in that the address signals that are not used in the first block is used.

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