JP5012285B2 - Hadamard transform circuit - Google Patents

Description

  The present invention relates to a Hadamard transform circuit, and more particularly to a Hadamard transform circuit that restores spread data that has been spread and multiplexed with a plurality of channelization codes by Hadamard transform.

  In recent years, a service called HSDPA (High Speed Downlink Packet Access) is being provided as a high-speed communication service for wireless terminals. The maximum communication speed provided by the HSDPA is defined by the service category, and varies according to the communication environment (best effort type).

  The terminal receives data through HS-PDSCH (High-Speed Physical Downlink Shared Channel), but the communication speed increases or decreases depending on the number of HS-PDSCH multicodes. That is, the number of HS-PDSCH multicodes varies depending on the service category and communication environment.

  As a despreading process for the multicode, an FHT circuit using FHT (Fast Hadamard Transform) is often used (for example, see Patent Document 1). In the FHT circuit, it is possible to obtain a despread output for a multicode at the same time, which is advantageous in the despread processing for the multicode.

However, in HS-PDSCH, the number of multicodes increases and decreases as described above. For this reason, when the number of multicodes is small, there is a portion where the FHT circuit does not need to perform an arithmetic operation. That is, when the number of multicodes is large, the FHT circuit functions effectively, but when the number of multicodes is small, the number of parts that operate wastefully increases.
JP 2003-198504 A

As described above, when the number of multi-codes is variable, there is a problem in that a part that operates unnecessarily occurs in the circuit, and the efficiency of calculation amount and power consumption of the circuit is low.
The present invention has been made in view of these points, and an object thereof is to provide a Hadamard transform circuit capable of reducing the amount of Hadamard transform computation and the power consumption of the circuit.

  In the present invention, in order to solve the above problem, a plurality of Hadamard transform circuits for performing Hadamard transform in a Hadamard transform circuit that restores spread data that has been spread and multiplexed by a plurality of channelization codes as shown in FIG. A buffer 1 that holds calculation results at each stage of the butterfly calculation, and an adder 2 that performs a plurality of butterfly calculations at the next stage using the calculation results held in the buffer 1 and holds the calculation results in the buffer 1; And adder operation determination means 3 for determining whether or not the addition processing is necessary in each of the addition processing in the plurality of butterfly operations of the adder 2 based on the identification number for identifying the channelization code. A Hadamard transform circuit is provided.

  According to such a Hadamard transform circuit, the adder operation determination means 3 determines whether or not the addition process is necessary in each addition process in the butterfly calculation of the adder 2. Thereby, unnecessary addition processing of the adder 2 can be omitted.

  In the Hadamard transform circuit of the present invention, it is determined whether or not the addition processing is necessary in each addition processing in the adder butterfly calculation. As a result, unnecessary addition processing of an adder can be omitted, and the amount of Hadamard transform computation and the power consumption of the circuit can be reduced.

Hereinafter, the principle of the present invention will be described in detail with reference to the drawings.
FIG. 1 is a diagram showing an outline of a Hadamard transform circuit. As shown in the figure, the Hadamard transform circuit includes a buffer 1, an adder 2, an adder operation determination unit 3, and a multiplier 4. The Hadamard transform circuit shown in the figure is capable of simultaneously restoring a plurality of spread data spread and multiplexed by a plurality of channelization codes by Hadamard transform.

  The buffer 1 receives diffusion data and holds calculation results at each stage of a plurality of butterfly calculations. For example, when the spread data is 16 chips, 16 × 4 stages of butterfly calculations are performed, and the buffer 1 holds the results of butterfly calculations performed in each of the stages 1 to 4.

The adder 2 performs the next butterfly operation using the diffusion data stored in the buffer 1 or the operation result of the butterfly operation, and stores the operation result in the buffer 1.
The adder operation determination means 3 receives the identification number of the channelization code used for spreading the spread data. Based on the input identification number, the adder operation determination means 3 determines whether or not the addition process is necessary in the individual addition processes in the plurality of butterfly computations of the adder 2. The adder operation determination means 3 prevents data from being output from the buffer 1 to the adder 2 in the unnecessary addition processing of the determined adder 2, and omits the addition processing.

  For example, it is assumed that the identification numbers of channelization codes in which data is spread are 1 to 5. In this case, the adder operation determination unit 3 determines which addition process in the butterfly calculation of the adder 2 is unnecessary based on the identification numbers 1 to 5. In the unnecessary addition process of the adder 2 determined, data for the addition process is not output from the buffer 1 to the adder 2 and data necessary for the next addition process is output. That is, the adder operation determination unit 3 omits unnecessary addition processing of the adder 2.

  FIG. 2 is a diagram illustrating a determination unit that does not require addition processing in the Hadamard transform circuit. 2A and 2B show examples of butterfly computation. The dotted circles shown in FIGS. 2A and 2B correspond to the addition process of the adder 2 shown in FIG. As shown in FIGS. 2A and 2B, the butterfly operation is an addition operation of the in1 and in2 data (spread data held in the buffer 1 or the result of the previous butterfly operation) as indicated by the arrows. Then, the butterfly calculation result of the next stage of out1 and out2 is obtained.

  Adder operation determination means 3 determines whether or not the addition processing is necessary in each addition processing in a plurality of butterfly calculations. Therefore, the adder operation determination means 3 does not stop the operation in the butterfly calculation unit shown in FIG. 2A, but as shown by the dotted arrows in FIG. Stops operation in increment processing units. That is, the adder operation determination unit 3 stops the processing in units of adders.

  Returning to the description of FIG. The multiplier 4 multiplies the data output from the buffer 1 by 1 or -1. In the butterfly operation, addition / subtraction processing is performed, and the multiplier 4 multiplies the data by -1 when subtraction processing of the butterfly operation is necessary. Thereby, the adder 2 performs the data addition process, but can also perform the substantial subtraction process.

  As described above, the Hadamard transform circuit determines whether or not the addition processing is necessary in each addition processing in the adder butterfly calculation. As a result, unnecessary addition processing of an adder can be omitted, and the amount of Hadamard transform computation and the power consumption of the circuit can be reduced.

Next, a first embodiment of the present invention will be described in detail with reference to the drawings.
FIG. 3 is a diagram illustrating a system configuration example of a terminal to which the FHT circuit according to the first embodiment is applied. In the figure, terminals 11 and 12 and a base station 13 are shown.

  The terminals 11 and 12 receive data from the base station 13 using the HS-PDSCH. The base station 13 varies the number of multicodes assigned to the terminals 11 and 12 according to the service category and communication environment supported by the terminals 11 and 12. Terminals 11 and 12 are equipped with an FHT circuit and can simultaneously obtain a despread output for a multicode.

  The spreading factor of HS-PDSCH is SF (Spreading Factor) = 16. In the case of SF = 16, the base station 13 can create 16 channelization codes Cc (SF, k) for identifying users (terminals). k is an identification number for identifying the channelization code. When SF = 16, k = 0 to 15. Specifically, the base station 13 can create 16 channelization codes such as Cc (16, 0), Cc (16, 1),..., Cc (16, 15). The base station 13 can identify communication with 16 terminals by assigning one channelization code to one terminal.

  The multi-code is a method in which the base station 13 assigns a plurality of channelization codes as one set to the terminals 11 and 12 and performs wireless communication. If the base station 13 assigns many channelization codes to one terminal, a plurality of data can be spread with a plurality of channelization codes and multiplexed and transmitted by radio, so that the amount of data that can be wirelessly increased is increased. Speed can be improved.

  FIG. 4 is a diagram illustrating an example of FHT butterfly computation. The terminal 11 shown in FIG. 3 can simultaneously obtain the despread output for the multicode by performing the butterfly operation shown in FIG. 4 using the FHT circuit. The same applies to the terminal 12.

  In the in shown in FIG. 4, the spread data (chip) received from the base station 13 is input. FIG. 4 shows an example of SF = 16 of HS-PDSCH, and 16-chip data is input to in.

  The symbol “+” shown in FIG. 4 indicates an addition operation (adder). The adder adds the data of the starting point of the arrow. For example, the top left adder of the 16 × 4 stage adder shown in FIG. 4 adds chip 0 and chip 8 received from the base station 13. The adder on the right side adds the addition result of the adder at the top left and the addition result of the adder four lower than the adder. When SF = 16, the number of FHT butterfly calculation adders necessary for despreading is 64 in 16 chips × 4 stages.

  The dotted line arrows shown in FIG. 4 indicate that the data is multiplied by −1 and output to the next adder. For example, the adder eight lower than the upper left in FIG. 4 adds chip 0 and chip 8 multiplied by -1. In other words, this adder is performing an addition operation, but is the same as subtracting as a result.

Note that the data can be multiplied by −1, for example, by providing a multiplier that performs multiplication of −1 in the preceding stage of the adder.
The FHT circuit can obtain a despread output from out shown in FIG. 4 by performing the butterfly operation shown in FIG. For example, a despread output for a channelization code of k = 0 can be obtained from out0 in the figure, and a despread output for a channelization code of k = 8 can be obtained from out1. 4 indicates the identification number of the despread output channelization code obtained from out.

  In the conventional FHT circuit, all adders of 16 × 4 stages are used regardless of the number of multicodes. For example, even when only five channelization codes of k = 1 to 5 are used, the butterfly calculation is performed by operating all adders of 16 × 4 stages.

  On the other hand, in the FHT circuit mounted on the terminal 11, the operation of an adder that does not need to operate is stopped. Also, the operation is stopped in units of adders, not in units of butterfly computation.

  For example, it is assumed that the base station 13 assigns an identification number of a channelization code of k = 1 to 5 to the terminal 11, spreads the data, and wirelessly transmits. In this case, the FHT circuit of the terminal 11 stops the operation of the adder indicated by hatching in FIG. That is, the FHT circuit stops the adder operation unnecessary for the butterfly calculation of k = 1 to 5.

  The adder that does not require operation is the adder that outputs the result of despreading the identification number of the unused channelization code, the last stage (the leftmost adder row in FIG. 4 is the first row, the right adder row) Can be understood by tracing from the adder of the second stage to the input (in) side.

  For example, in the case of the example of FIG. 4, it can be understood that the fourth-stage adder corresponding to the unused identification numbers k = 0, 6 to 15 is the adder whose operation should be stopped. It should be noted that the adder with the diagonal line in the fourth row in FIG. 4 is the adder whose operation should be stopped.

  Next, in the third-stage adder, the adder that outputs the addition result only to the adder that stops the fourth-stage operation is known as the adder whose operation should be stopped. In the example of FIG. 4, the first, second, seventh, eighth, fifteenth, and sixteenth adders from the top of the third stage output the addition result only to the adder that stops the fourth stage operation. Can be seen as an adder that should stop operating. Note that the adder with the hatched line in the third row in FIG. 4 is the adder whose operation should be stopped.

  Next, in the second-stage adder, the adder that outputs the addition result only to the adder that stops the third-stage operation is known as the adder whose operation should be stopped. In the example of FIG. 4, in the second-stage adder, there is no adder that outputs the addition result only to the adder that stops the third-stage operation.

  That is, even if the operation of the adder with hatching is stopped to obtain the despread output of k = 1 to 5, there is no effect on the butterfly calculation result. Thereby, the power consumption of the FHT circuit can be reduced. Note that the alternate long and short dash line in the figure indicates that the addition result is not output from the adder (indicating that the operation of the adder has been stopped).

  FIG. 5 is a diagram showing another example of butterfly computation of the FHT circuit. The butterfly calculation in FIG. 5 is the same as the butterfly calculation in FIG. 4 except for the order. That is, the butterfly calculation of FIG. 5 is only the reverse of the calculation direction of the butterfly calculation of FIG. The symbols and the like in FIG. 5 are the same as those in FIG.

  Also in the case of FIG. 5, the adder for stopping the operation can be understood by the same idea as in FIG. 4. For example, assume that channelization codes of k = 1 to 5 are assigned to the terminal 11 as in FIG. In this case, if the adder that outputs the despreading result of the identification numbers k = 0, 6 to 15 of the unused channelization codes is traced from the final stage adder to the input side, an adder that does not require operation is obtained. I understand.

  In the case of the example in FIG. 5, it can be seen that the fourth-stage adder corresponding to the unused identification numbers k = 0, 6 to 15 is the adder whose operation should be stopped. Note that the adder with the diagonal line in the fourth row in FIG. 5 is the adder whose operation should be stopped.

  Next, in the third-stage adder, the adder that outputs the addition result only to the adder that stops the fourth-stage operation is known as the adder whose operation should be stopped. In the example of FIG. 5, the second, fourth, sixth to eighth, tenth, twelfth, fourteenth to sixteenth adders from the top of the third stage output the addition result only to the adder that stops the operation of the fourth stage. These adders are known as adders that should stop operating. The adder with the hatched line in the third row in FIG. 5 is the adder whose operation should be stopped.

  Next, in the second-stage adder, the adder that outputs the addition result only to the adder that stops the third-stage operation is known as the adder whose operation should be stopped. In the example of FIG. 5, the second, fourth, sixth, eighth, tenth, twelfth, fourteenth and sixteenth adders from the top of the second stage output the addition result only to the adder that stops the third stage operation. These adders are known as adders that should stop operating. Note that the adder with the hatched line in FIG. 5 is the adder whose operation should be stopped.

  Finally, in the first-stage adder, the adder that outputs the addition result only to the adder that stops the second-stage operation is recognized as the adder whose operation should be stopped. In the example of FIG. 5, the second, fourth, sixth, eighth, tenth, twelfth, fourteenth and sixteenth adders from the top of the first stage output the addition result only to the adder that stops the second stage operation. These adders are known as adders that should stop operating. Note that the adder with the hatched line in FIG. 5 is the adder whose operation should be stopped.

In this way, the amount of computation and power consumption of the FHT circuit can be reduced even by different butterfly computations.
FIG. 6 is a block diagram of the FHT circuit. As shown in FIG. 6, the FHT circuit includes a buffer 21, control units 22 and 24, a selector 23, a multiplier 25, and an adder 26. The FHT circuit shown in FIG. 6 performs the butterfly operation described in FIG. 4 or FIG.

  An input signal for FHT is input to the buffer 21. The input signal corresponds to the chip described in FIG. That is, the input signal in FIG. 6 corresponds to in shown in FIGS.

The buffer 21 temporarily holds an input signal. In addition, the addition result of the adders at the respective stages described in FIGS. 4 and 5 is temporarily held.
As described with reference to FIGS. 4 and 5, the chip held in the buffer 21 is input to the first-stage adder and is subjected to addition calculation (butterfly calculation). As will be described in detail below, the selector 23, the control unit 24, the multiplier 25, and the adder 26 in FIG. 6 perform the addition operation in the first stage of the arrows shown in FIGS.

  The first stage addition operation result (adder result) is held in the buffer 21 again. That is, the first stage adder results shown in FIGS. 4 and 5 are temporarily held in the buffer 21. Note that the result of the addition operation is stored in an area different from the area where the chip of the buffer 21 is stored.

  Similarly, the first-stage adder result stored in the buffer 21 is obtained by the second stage indicated by the arrows shown in FIGS. 4 and 5 by the selector 23, the control unit 24, the multiplier 25, and the adder 26 shown in FIG. Are added.

  The second-stage adder result is held in the buffer 21 again. That is, the second stage adder results shown in FIGS. 4 and 5 are temporarily held in the buffer 21. The adder result of the second stage may be overwritten in the area where the chip of the buffer 21 is stored, or may be stored in another area.

  Similarly, the FHT circuit performs adder processing in the third and fourth stages. Thereby, the buffer 21 finally holds the despreading result in each channelization code. And if it outputs as an output signal from the buffer 21, a de-spreading result will be obtained.

  The control unit 22 performs data input / output control of the buffer 21. For example, the chip temporarily held in the buffer 21 is output to the multiplier 25 and the adder 26. Further, the control unit 22 outputs the adder result at each stage to the multiplier 25 and the adder 26. The control unit 22 outputs the chip or adder result to the multiplier 25 and the adder 26 so that the addition processing of the arrows shown in FIGS. 4 and 5 is performed.

  For example, the upper left adder shown in FIG. 4 performs addition processing of chip 0 and chip 8. Therefore, in this case, the control unit 22 performs control so that the chip 0 and the chip 8 are output from the buffer 21. Also, the adder (adder A) adjacent to the right of the adder at the top left shown in FIG. 4 adds the top adder result at the first stage and the adder result at the fifth from the top. Therefore, when the adder 26 performs the adder A addition process, the control unit 22 outputs the corresponding first-stage adder result temporarily stored in the buffer 21 to the multiplier 25 and the adder 26. To.

  The terminal 11 is notified of the identification number (k) of the channelization code assigned from the base station 13. The identification number of the channelization code notified from the base station 13 is input to the control unit 22. The control unit 22 determines an adder that does not require addition processing based on the input identification number of the channelization code.

  For example, it is assumed that the identification number of the channelization code of k = 1 to 5 is notified from the base station 13. In this case, as described with reference to FIG. 4, the adder addition operation indicated by hatching in FIG. 4 is not necessary. When performing addition processing corresponding to the hatched adders in FIG. 4 based on the identification number of the channelization code of k = 1 to 5 notified from the base station 13, the control unit 22 receives data from the buffer 21. Is not output. As a result, the control unit 22 can omit unnecessary addition processing of the adder 26.

1 and −1 are input to the selector 23. The selector 23 outputs one of 1 and −1 to the multiplier 25 according to an instruction from the control unit 24.
The control unit 24 controls the selector 23 to output −1 when a subtraction process is required in the butterfly calculation. For example, when data corresponding to the dotted arrow shown in FIGS. 4 and 5 is output from the buffer 21, the selector 23 is controlled to output −1.

  The multiplier 25 multiplies 1 and −1 output from the selector 23 and the data output from the buffer 21. When -1 is output from the selector 23, the data output from the buffer 21 is set to a negative value, so that the adder 26 performs a subtraction process. When 1 is output from the selector 23, the adder 26 performs addition processing.

  The adder 26 adds the data output from the buffer 21. The adder 26 corresponds to the adder calculation shown in FIGS. Since the data of the starting point of the arrow shown in FIGS. 4 and 5 is output to the adder 26 under the control of the control unit 22, the adder 26 adds the data of the arrow shown in FIGS. 4 and 5. Become.

  For example, it is assumed that the data of the chip 0 and the chip 8 temporarily stored in the buffer 21 is output from the buffer 21 under the control of the control unit 22. In this case, the adder 26 performs addition processing of the chip 0 and the chip 8. This result is held in the buffer 21 again. This addition process corresponds to the adder process at the top left in FIG.

  FIG. 7 is another block diagram of the FHT circuit. As shown in FIG. 7, the FHT circuit includes a buffer 31, control units 32 and 33, and adders 34 and 35. The FHT circuit of FIG. 7 performs the butterfly operation described in FIG. 4 or FIG. 5 in the same manner as the FHT circuit of FIG.

The buffer 31 and the control unit 32 have the same functions as the buffer 21 and the control unit 22 described with reference to FIG.
Data output from the buffer 31 is output to the adders 34 and 35. The adder 35 performs an addition operation with one data set to be negative (for example, 2's complement). That is, the adder 35 has the same function as the subtracter.

  The control unit 33 outputs the enable signal En and selects the adders 34 and 35 to be operated. For example, as shown by the solid line arrows in FIGS. 4 and 5, when adding data output from the buffer 31, the control unit 33 selects the adder 34. As shown by the dotted arrows in FIGS. 4 and 5, when subtracting data output from the buffer 31, the control unit 33 selects the adder 35.

  In the FHT circuit of FIG. 6, the data input by the multiplier 25 is multiplied by −1 in order to perform subtraction processing with one adder 26. In the FHT circuit of FIG. 7, the adder 35 directly performs the subtraction process without using the multiplier 25.

  That is, the control unit 33 and the adders 34 and 35 in FIG. 7 perform the same functions as the selector 23, the control unit 24, the multiplier 25, and the adder 26 in FIG. 6, and the adders in the respective stages in FIGS. Processing is performed and the adder result is temporarily stored in the buffer 31.

FIG. 8 is a flowchart for explaining the operation of the FHT circuit of FIG. The FHT circuit of FIG. 6 performs the butterfly operation described in FIG. 4 according to the following steps.
In step S1, the control unit 22 of the FHT circuit substitutes 1 for a variable N. The value of the variable N corresponds to the adder shown in FIG. For example, it corresponds to 1, 2,..., 16 in order from the topmost adder in the first row in FIG. 4 and corresponds to 17, 18,. Similarly, from the topmost adder of the 4th stage, they correspond to 49, 50,.

  In step S <b> 2, the control unit 22 determines whether or not an adder N addition operation is necessary based on the identification number of the channelization code notified from the base station 13. For example, when the identification number of the channelization code is k = 1 to 5, as described with reference to FIG. 4, the addition operation of the shaded adders is unnecessary. Therefore, when N = 33, 34, 39, 40, 47 to 50, 52, 54 to 56, 58, 60, 62 to 64, the control unit 22 proceeds to Step S4. If N is any other value, an addition operation is necessary, and the process proceeds to step S3.

  In step S <b> 3, the control unit 22 outputs predetermined data from the buffer 21 in order to calculate the adder N. For example, when calculating the second stage adder N = 20, the control unit 22 multiplies the previous stage (first stage) adder N = 4,8 adder result temporarily stored in the buffer 21. Control to output to the device 25 and the adder 26. Further, when performing the calculation of adder N = 21, the control unit 22 outputs the adder result of the previous stage adder N = 1, 5 temporarily stored in the buffer 21 to the multiplier 25 and the adder 26. To control. In addition, as shown in FIG. 4, the addition operation of N = 21 has to add the adder result of N = 1 by multiplying the adder result of N = 5 by −1. Therefore, in this case, the control unit 24 controls the selector 23 to output -1.

In step S4, the control unit 22 adds 1 to the variable N.
In step S5, the control unit 22 determines whether the calculation for all adders has been completed. That is, it is determined whether the value of the variable N has reached 65. If the variable N is smaller than 65, the process proceeds to step S2. If the variable N is 65, the process is terminated.

  In the above description, the butterfly calculation of FIG. 4 has been described using the flowchart. However, the butterfly calculation of FIG. 5 also operates according to the flowchart of FIG. In the case of the butterfly calculation of FIG. 5, only the control for outputting data from the buffer 21 of the control unit 22 is different.

  In the above description, the operation of the FHT circuit of FIG. 6 has been described with reference to the flowchart. However, the FHT circuit of FIG. 7 also operates according to the flowchart of FIG. In the case of the FHT circuit in FIG. 7, the only difference is that the control unit 33 and the adder 35 perform addition processing and subtraction processing on the multiplier 25 in FIG. 6.

  As described above, the FHT circuit determines whether or not the addition process is necessary in each addition process in the adder butterfly calculation. As a result, unnecessary addition processing of an adder can be omitted, and the amount of Hadamard transform computation and the power consumption of the circuit can be reduced.

  Next, a second embodiment of the present invention will be described in detail with reference to the drawings. In the first embodiment, the control units 22 and 32 perform predetermined processing based on the identification number of the channelization code and determine whether or not the adder N is calculated. In the second embodiment, the control units 22 and 32 determine whether or not the adder N is calculated based on a table stored in the storage device.

  FIG. 9 is a block diagram of the FHT circuit according to the second embodiment. FIG. 9 shows the buffer 21 described in FIG. In addition, a storage device 41 and a control unit 42 including a RAM (Random Access Memory) and the like are shown. 9, illustration of the selector 23, the control unit 24, the multiplier 25, and the adder 26 shown in FIG. 6 is omitted.

  The storage device 41 stores an identification number of the channelization code and adder information indicating which adder is stopped for the identification number of the channelization code.

  For example, the storage device 41 has channelization code identification numbers k = 1 to 5 and adder information to be stopped when the channelization code identification numbers k = 1 to 5 (the hatched lines shown in FIG. 4 are attached). Adders, that is, N = 33, 34, 39, 40, 47 to 50, 52, 54 to 56, 58, 60, 62 to 64) are stored correspondingly.

  Similarly to the control unit 22 described in FIG. 6, the control unit 42 receives the channelization code identification number k. The control unit 42 refers to the storage device 41 and obtains adder information whose operation should be stopped corresponding to the identification number of the input channelization code. When the acquired adder information is added, data is not output from the buffer 21.

  For example, it is assumed that an identification number of a channelization code with k = 1 to 5 is input to the control unit 42. In this case, the control unit 42 refers to the storage device 41 and adds information N = 33, 34, 39, 40, 47 to 50, 52, 54 to 56, 58, 60, 62 corresponding to k = 1 to 5. ~ 64 will be acquired. The control unit 42 does not output data from the buffer 21 so that addition processing is not performed for this N value adder.

Needless to say, the above storage device can be applied to the FHT circuit in FIG.
FIG. 10 is a diagram showing an example of a table configured in the storage device of FIG. As shown in FIG. 10, the table 43 is provided with a column for an identification number and a column for adder information.

  In the identification number column, an identification number of a channelization code assigned to the terminal 11 is stored. The adder information column stores information on the adder whose operation should be stopped.

  For example, when a channelization code having an identification number of k = 1 is assigned to the terminal 11, the control unit 42 refers to the adder information of the identification number 1 in the table 43 in FIG. It is possible to obtain information about whether it is good. The controller 42 controls the output of data in the buffer 21 based on the acquired adder information to be stopped.

  Thus, by creating the table 43 in which the identification number of the channelization code assigned to the terminal 11 is associated with the adder information to be stopped, the control unit 42 creates the table 43 without performing a predetermined calculation. An adder that does not need to be operated at high speed can be recognized only by referring to it.

(Supplementary Note 1) In a Hadamard transform circuit that restores spread data that has been spread and multiplexed by a plurality of channelization codes by Hadamard transform,
A buffer for holding calculation results at each stage of a plurality of butterfly calculations for performing the Hadamard transform;
An adder that performs a plurality of butterfly computations of the next stage using the computation results held in the buffer, and holds the computation results in the buffer;
Based on an identification number for identifying the channelization code, adder operation determination means for determining whether or not the addition processing is necessary in each of the addition processing in the plurality of butterfly operations of the adder;
And a Hadamard transform circuit.

  (Supplementary Note 2) The Hadamard transform circuit according to Supplementary note 1, further comprising a storage device that stores the identification number and information indicating which addition process of the adder is necessary in association with each other.

  (Supplementary note 3) The Hadamard transform circuit according to Supplementary note 2, wherein the adder operation determination means determines whether or not each of the addition processes of the adder is necessary with reference to the storage device.

  (Additional remark 4) When the said adder operation | movement judgment means judges that the addition process of the said adder is unnecessary, it does not output the said calculation result required for the addition process of the said adder from the said buffer, It is characterized by the above-mentioned. The Hadamard transform circuit according to appendix 1.

(Additional remark 5) The Hadamard transformation circuit of Additional remark 1 characterized by providing the multiplier which makes the said operation result input into the said adder a negative value in the front | former stage of the said adder.
(Additional remark 6) The said adder has the 1st adder which carries out the addition process of the said operation result, and the 2nd adder which carries out the addition process by making one of the said operation results into a negative value, Additional remark 1 characterized by the above-mentioned. Hadamard transform circuit.

It is the figure which showed the outline | summary of the Hadamard transformation circuit. It is a figure explaining the determination unit which does not require the addition process of a Hadamard transformation circuit. It is a figure which shows the system configuration example of the terminal to which the FHT circuit which concerns on 1st Embodiment is applied. It is the figure which showed the butterfly calculation example of FHT. It is the figure which showed another butterfly calculation example of the FHT circuit. It is a block block diagram of a FHT circuit. It is another block block diagram of a FHT circuit. It is a flowchart explaining operation | movement of the FHT circuit of FIG. It is a block block diagram of the FHT circuit which concerns on 2nd Embodiment. FIG. 10 is a diagram illustrating an example of a table configured in the storage device of FIG. 9.

Explanation of symbols

1 buffer 2 adder 3 adder operation judging means 4 multiplier

Claims (5)

In a Hadamard transform circuit that restores spread data that has been spread and multiplexed with a plurality of channelization codes by Hadamard transform,
A buffer for holding calculation results at each stage of a plurality of butterfly calculations for performing the Hadamard transform;
An adder that performs a plurality of butterfly computations of the next stage using the computation results held in the buffer, and holds the computation results in the buffer;
Based on an identification number for identifying the channelization code, adder operation determination means for determining whether or not the addition processing is necessary in each of the addition processing in the plurality of butterfly operations of the adder;
And a Hadamard transform circuit.   The Hadamard transform circuit according to claim 1, further comprising: a storage device that stores the identification number and information indicating which addition process of the adder is necessary.   The Hadamard transform circuit according to claim 2, wherein the adder operation determination unit determines whether or not each of the addition processes of the adder is necessary with reference to the storage device.   2. The adder operation determination unit, when determining that the adder addition process is unnecessary, does not output the calculation result necessary for the adder addition process from the buffer. Hadamard transform circuit.   The Hadamard transform circuit according to claim 1, wherein a multiplier that sets the operation result input to the adder to a negative value is provided before the adder.

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