JP5006668B2 - Network processor, network device equipped with network processor, and frame transfer method - Google Patents

Description

  The present invention relates to a technique for speeding up data transfer in a network processor in which a plurality of systems are connected on a data transmission path.

  With the speeding up of broadband communication, demand for home network devices that transfer Ethernet (registered trademark) frames is rapidly increasing. Along with this, there is a demand for speeding up data communication of a network processor mounted on a network device that transmits and receives Ethernet frames.

  Here, in a network device that receives an Ethernet frame from an external network device and forwards the frame to another external network device, the received header information indicating the destination and source of the received Ethernet frame is sent to the destination of the Ethernet frame to be transmitted. And transmission header information indicating the transmission source. When a closed network such as an in-house network is connected to the Internet, it is necessary to convert a private address used in the in-house network into a global address used on the Internet by using an address conversion function. Such conversion of header information and conversion from a private address to a global address are processed by a network processor installed in the network device.

  Such a conventional technique is described in Non-Patent Document 1. FIG. 9 is a functional block diagram in which the configuration of the conventional network processor described in Non-Patent Document 1 is partially simplified. The network processor includes a MAC block unit 91, a lookup block unit 92, a switch block unit 93, and a host interface block unit 96. The host interface block unit 96 incorporates a FEF NAT / IP forwarding table 94 and a transmission / reception buffer 95.

  The MAC block unit 91 is configured to transmit and receive an Ethernet frame via the interface 99. The switch block unit 93 is configured to input information from the lookup block unit 92 via the system bus 97 and transfer a corresponding interface Ethernet frame based on this information. The lookup block unit 92 is configured to transfer the reception header information extracted from the Ethernet frame in the MAC block unit 91 to the switch block unit 93 via the system bus 97. The lookup block unit 92 is configured to convert the reception header information into transmission header information with reference to an FEF NAT / IP forwarding table 94 which is an internal table described later.

  The host interface block unit 96 is configured to perform packet forwarding processing and temporarily store Ethernet frames. The host interface block unit 96 is configured to exchange Ethernet frames with the external memory unit 98.

  The FEF NAT / IP forwarding table 94 is an internal table in which reception header information included in a reception Ethernet frame and transmission header information of a transmission Ethernet frame are registered in association with each other. The transmission / reception buffer 95 is configured to temporarily store an Ethernet frame transmitted / received via the MAC block unit 91. The external memory 98 is configured to store an Ethernet frame.

  In the network processor configured as described above, when a received Ethernet frame is input from the interface 99, received header information is extracted by the MAC block unit 91. The received Ethernet frame is temporarily stored in the transmission / reception buffer 95 via the system bus 97. The lookup block unit 92 compares the received header information extracted by the MAC block unit 91 with the FEF NAT / IP forwarding table 94 that is an internal table. When the reception header information and the internal table match, the lookup block unit 92 transfers the transmission header information of the transfer destination specified in the internal table to the MAC block unit 91 and indicates that it matches the internal table. The coincidence information is transmitted to the switch block unit 93. Upon receiving this match information, the switch block unit 93 receives the Ethernet frame temporarily stored in the transmission / reception buffer 95, rewrites the reception header information with the transmission header information, and generates a transmission Ethernet frame.

Such a network processor is also disclosed in Patent Documents 1 to 3.
JP 2002-208945 A JP 2003-152882 A JP-A-11-187045 Fujitsu Limited, “Fujitsu Semiconductor Device DATA SHEET: DS04-22114-1 IP Forwarding Engine MB86977”, [online], [searched on February 20, 2007], Internet <URL: http://edevice.fujitsu.com /jp/datasheet/j-ds/j422114.pdf>

  However, in the conventional network processor as described above, when the capacity of the transmission / reception buffer 95 is small or when a large amount of transmission / reception of Ethernet frames occurs, the received reception header information and the FEF NAT / IP forwarding table 94 Even if they match, the number of Ethernet frames transferred to the external memory 98 via the system bus 97 increases in order to prevent overflow of the transmission / reception buffer 95. As a result, a read / write process with the external memory 98 via the system bus 97 as a transmission path occurs, and the Ethernet frame transfer rate is lowered.

  The network processor according to the present invention includes transmission header information indicating a destination and a transmission source of a transmission frame transmitted to another external network device, and reception header information indicating a destination and a transmission source included in the reception frame received from the external network device. A network processor that generates the transmission frame by converting the data into a transmission path in which data in the network processor is transferred, address data having a smaller data amount than the reception header information, and the reception header information A frame receiving unit that refers to the comparison table generated, replaces the received header information with the corresponding address data, generates reconstructed frame data that is transferred on the transmission path, and transfers the reconstructed frame data to the transmission path; Connected to the transmission path, and stores the reconstructed frame data. The transmission frame is generated by referring to a conversion table in which the address data and the transmission header information are associated with each other and replacing the address data of the reconstructed frame data with the corresponding transmission header information. A frame transmission unit configured to transmit the transmission frame to the other external network device;

  As described above, the frame receiving unit generates the reconstructed frame data by replacing the address data having a smaller data amount than the received header information with the received header information, and the frame transmitting unit transmits corresponding to the address data of the reconstructed frame data. By generating a transmission frame by replacing the header information, the amount of data transferred on the transmission path of the network processor can be reduced and the frame transfer rate can be increased.

  According to the network processor of the present invention, it is possible to improve the efficiency of frame transfer by reducing the amount of data on the transmission path.

Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.
[First Embodiment]
FIG. 1 is a block diagram showing a network device 102 according to the first embodiment of the present invention. The network device 102 is connected to the external network device 101 and the external network device 103. The external network devices 101 and 102 are, for example, terminals such as router devices or personal computers. The network device 102 is configured to receive the reception Ethernet frame A from the external network device 101 and transmit the transmission Ethernet frame B to the external network device 103.

  The network device 102 and the external network devices 101 and 103 are assigned MAC addresses and IP addresses for identifying the network devices 101 to 103, respectively. Here, the network device 102 has the MAC address = B, the IP address = 192.168.50.1, the external network device 101 has the MAC address = A, the IP address = 192.168.50.2, and the external network device 103. Assume that MAC address = C and IP address = 192.168.50.3 are assigned.

  The reception Ethernet frame A has reception header information INF1 indicating the destination and transmission destination of the reception Ethernet frame A. The reception header information INF1 includes a destination MAC address that is the MAC address of the destination network device of the reception Ethernet frame A and a transmission source MAC address that is the MAC address of the transmission source network device of the reception Ethernet frame B. . Since the received Ethernet frame A is transferred from the external network device 101 to the network device 102, the destination MAC address = B and the source MAC address = A.

  On the other hand, the transmission Ethernet frame B has transmission header information INF2 indicating the destination and transmission destination of the transmission Ethernet frame B. The transmission header information INF2 has a destination MAC address and a transmission source MAC address, similarly to the reception header information INF1. Since the transmission Ethernet frame B is transferred from the network apparatus 102 to the network apparatus 103, the destination MAC address = C and the transmission source MAC address = B.

  The network device 102 is configured to convert the reception header information INF1 included in the received reception Ethernet frame A into transmission header information INF2 and transmit the transmission Ethernet frame B. Such conversion from the reception Ethernet frame A to the transmission Ethernet frame B is processed by a network processor 20 (described later) included in the network device 102.

  FIG. 2 is a diagram showing a more detailed configuration of the reception Ethernet frame A and the transmission Ethernet frame B. The received Ethernet frame A and the transmitted Ethernet frame B are a destination MAC address 1, a source MAC address 2, a type field 3, an IP header 4, a destination IP address 5, a source IP address 6, a destination port 7, a source port 8, And data 9.

  As described above, the destination MAC address 1 and the source MAC address 2 are the MAC addresses of the destination and source network devices. It is assumed that the destination MAC address 1 and the source MAC address are MAC addresses 10. Type field 3 indicates what protocol the network layer is using. The destination IP address 5 and the source IP address 6 are the IP addresses of the destination and source network devices. It is assumed that the destination IP address 5 and the source IP address 6 are IP addresses 11. The destination port 7 and the source port 8 are physical ports included in the destination and source switching HUBs. Note that the destination port 7 and the source port 8 are port numbers 12.

  The MAC address 10, the IP address 11, and the destination port number 12 included in the reception Ethernet frame A constitute reception header information INF1 indicating the destination and transmission source of the reception Ethernet frame A described above. The transmission Ethernet frame B has the same components as the reception Ethernet frame A. Similarly, the MAC address 10, IP address 11, and port number 12 included in the transmission Ethernet frame B constitute transmission header information INF2 indicating the destination and transmission source of the transmission Ethernet frame B.

  FIG. 3 is a functional block diagram showing the configuration of the network processor 20. The network device 102 has a network processor 20. The network processor 20 includes an Ethernet frame receiving unit 21, an Ethernet frame transmitting unit 22, a CPU unit 23, and an external memory unit 24.

  The Ethernet frame receiving unit 21, the Ethernet frame transmitting unit 22, and the CPU unit 23 are connected to the same system bus 25, and each is configured to operate as a bus master. The Ethernet frame receiving unit 21 is configured to control the operation of writing the input received Ethernet frame A into the external memory unit 24. The Ethernet frame transmission unit 22 is configured to control the operation of reading data from the external memory unit 24. The CPU unit 23 is configured to refer to data stored in the external memory unit 24 and to perform overall control of the network processor 20 in writing operation and reading operation.

  The Ethernet frame receiving unit 21 includes a header extraction circuit 27, an entry comparison table circuit 28, a comparison circuit 29, a header deletion circuit 30, and a reconstructed data frame generation circuit 31.

  The header extraction circuit 27 is configured to receive the received Ethernet frame A from the network device 101 and extract the received header information INF1 included in the received Ethernet frame A. The entry comparison table circuit 28 includes an entry comparison table. As shown in FIG. 4, in the entry comparison table, a plurality of reception header information INF is registered in association with each address data AD. As the entry comparison table, an arbitrary number of tables can be set by expanding and contracting the data length of the address data AD.

  The comparison circuit 29 inputs and compares the header part information INF1 output from the header extraction circuit 27 and the received header information INF1 registered in the entry comparison table, and matches / mismatch information indicating whether or not they match. It is configured to output to the deletion circuit 30 and the reconstructed frame data generation circuit 31.

  The header deletion circuit 30 receives the received Ethernet frame A from the network communication apparatus 101, and deletes the received header information INF1 from the received Ethernet frame A when the match / mismatch information input from the comparison circuit 29 is match information. It is configured to

  The reconstructed data frame generation circuit 31 is configured to input match / mismatch information from the comparison circuit 29, reconstruct the received Ethernet frame A, and generate a reconstructed data frame MD. The generated reconstructed data frame MD is transferred via the system bus 25 and stored in the external memory unit 24.

  When the reconstructed data frame generation circuit 31 receives the coincidence information from the comparison circuit 29, as shown in FIG. 2, the reconstructed data frame generation circuit 31 converts the received header information INF1 from the received Ethernet frame A to the data deleted by the header deletion circuit 30. The reconstructed frame data MD is generated by adding the coincidence information 13 and the coincidence table 14. The coincidence table is composed of address data AD.

  On the other hand, when the mismatch data is input from the comparison circuit 29, the reconstructed data frame generation circuit 31 generates the reconstructed frame data MD by adding the mismatch information 16 to the received Ethernet frame A as shown in FIG. It is configured to When mismatch information is input from the comparison circuit 29, the received header information INF1 is not deleted.

  The Ethernet frame transmission unit 22 includes an entry conversion table circuit 33 and a transmission frame generation circuit 34.

  The entry conversion table circuit 33 has an entry conversion table as shown in FIG. In the entry conversion table, transmission header information INF2 is registered in association with address data AD. Note that the address data AD of the entry conversion table corresponds to the address data AD of the entry comparison table. When the match information 13 is included in the reconstructed frame data MD, the entry conversion table circuit 33 refers to the address data AD (match table 14) included in the reconstructed frame data MD. The corresponding transmission header information INF2 is output to the data bus 26.

  The transmission frame generation circuit 34 receives the transmission header part information INF2 from the entry conversion table circuit 33, and replaces the matching information 13 and the matching table 14 of the reconstructed data frame MD with the transmission header information INF2, thereby transmitting the transmission Ethernet frame B. Is configured to build. Further, when the reconstructed frame data MD includes the mismatch information 16, the mismatch information 16 is deleted and the transmission Ethernet frame B is constructed.

  The CPU unit 23 is connected to the system bus 25 and is configured to manage the operation of the entire network processor 20. The external memory unit 24 is connected to the system bus 25 and configured to store the reconstructed frame MD. In FIG. 3, the external memory unit 24 is included in the network processor 20, but the external memory unit 24 may be installed anywhere as long as it is installed on the same system as the CPU unit 23.

  Next, the operation of the network apparatus 102 configured as described above will be described. The network device 102 operates to receive the reception network frame A from the external network device 101 and output the transmission network frame B to the external network device 103. FIG. 6 is a flowchart showing the operation of the network device 102 when receiving the received Ethernet frame A.

  First, the received Ethernet frame A is received from the external network device 101 (S11). This received Ethernet frame A is taken into the header extraction circuit 27 and the header deletion circuit 30. The header extraction circuit 27 extracts reception header information INF1 including the MAC address 10, the IP address 11, and the port number 12 from the received reception Ethernet frame A (S12). The reception header information INF1 is output to the comparison circuit 29.

  The comparison circuit 29 compares the received reception header information INF1 with the entry comparison table (FIG. 4) of the entry comparison table circuit 28 (S13), and determines whether or not the reception header information INF1 matches the entry comparison table. (S14). The match / mismatch information that is the determination result is output to the reconstructed data frame generation circuit 31.

  When the received header information INF1 matches the entry comparison table, the header deleting circuit 30 deletes the received header information INF1 of the received Ethernet frame A (S15). Next, the reconstructed data frame generation circuit 31 generates the reconstructed frame data MD by adding the match information 13 and the match table 14 information to the data in which the received header information part INF1 is deleted from the received Ethernet frame A. (S16). The generated reconstructed frame data MD is stored in the external memory unit 24 via the system bus 25. When the storage is completed, the CPU unit 23 issues a transmission request to the Ethernet frame transmission unit 22.

  On the other hand, if the received header information INF1 does not match the entry comparison table in step S4, the mismatch information 16 is added to the received Ethernet frame A to generate reconstructed frame data MD (S17). The reconstructed frame data MD generated in this way is stored in the external memory unit 24 via the system bus 25. Thereafter, the CPU unit 23 reads out the header information INF1 of the reconstructed frame data MD, converts the received header information INF1 into transmission header information INF2 by an arithmetic process, overwrites the reconstructed frame data MD, and re-writes the external memory unit 24. Save to. When the storage is completed, the CPU unit 23 issues a transmission request to the Ethernet frame transmission unit 22. Thereby, the network processor 20 performs the operation | movement at the time of the transmission Ethernet frame B shown next.

  FIG. 7 is a flowchart showing the operation of the network device 102 when transmitting the transmission Ethernet frame B. First, the Ethernet frame transmission unit 22 receives the reconstructed frame data MD from the memory unit 24 via the system bus 25 (S21). The reconstructed frame data MD is output to the entry conversion table circuit 33 and the transmission frame generation circuit 34 via the data bus 26. Next, the transmission frame generation circuit 34 extracts the comparison result information 15 included in the reconstructed frame data MD (S22), and determines whether or not the match information 13 is included in the comparison result information 15 (S23). ).

  If the comparison result information 15 includes the match information 13, the address data AD that is the match table 14 is extracted from the reconstructed frame data MD, and then the comparison result information 15 is deleted (S24). The transmission frame generation circuit 34 extracts the transmission header information INF2 corresponding to the address data AD from the entry conversion table circuit 33, and adds this transmission header information INF2 to the reconstructed frame data MD from which the comparison result information 15 has been deleted. An Ethernet frame B is generated (S25). Thereafter, the transmission frame generation circuit 34 transmits the transmission Ethernet frame B to the external network device 103 (S26).

  On the other hand, when the mismatch information 16 is included in the comparison result information 15 in step (S23), the transmission Ethernet frame B is generated by deleting the mismatch information 16 from the reconstructed frame data MD (S27). The transmission Ethernet frame B is transmitted to the external network device 103.

  In this way, the entry comparison table and the entry conversion table associated with each other by the address data AD are divided and provided on the reception side and the transmission side, and the received header information INF1 is replaced with the comparison result information 15 and compressed. By transferring the frame data MD onto the system bus 25, the amount of data transferred between the system bus 25 and the memory unit 24 can be reduced, and the data processing time can be reduced. Thereby, the efficiency of data transfer in the network device 102 can be improved.

Here, the Ethernet frames A and B transferred to the external network devices 101 and 103 are, as shown in FIG. 3, a 6-byte destination MAC address, a 6-byte transmission source MAC address, a 16-byte destination IP address, 16 It has 48-byte reception header information INF1 including a byte transmission source IP address, a 2-byte destination port, and a 2-byte transmission source port. On the other hand, in the reconstructed frame data MD when INF1 matches the entry comparison table, 48-byte reception header information INF1 matches 1 bit indicating whether or not the reception header information INF1 matches the entry comparison table. It is possible to replace the information 13 with a match table 14 that is 7-bit address data AD (when the entry comparison table has 2 ⁷ = 128 tables). As a result, the 48-byte received header information INF1 is compressed into 1-byte comparison result information 15.

Here, the number of bytes required for the shortest frame defined by the Ethernet protocol is 64 bytes. The data reduction rate (%) on the system bus 25 is
(Expression 1) 100− (transfer data amount after reduction / transfer data amount before reduction) × 100
Can be represented by Therefore, the data reduction rate when communicating with the shortest frame length is
(Formula 2) 100 − ((64−48 + 1) × 100/64) = 73 (%)
Thus, the amount of data on the system bus 25 can be reduced to about 1/4.

On the other hand, the number of bytes required for the longest frame defined by the Ethernet protocol is 1518 bytes. Therefore, the data reduction rate when communicating with the longest frame length is
(Formula 3) 100 − ((1518−48 + 1) × 100/1518) = 3 (%)
Thus, the amount of data on the system bus 25 can be reduced by 3%.

  Thus, by reducing the amount of data on the system bus 25, even when a plurality of bus masters request access to the system bus 25, the access waiting state of each bus master is reduced, and Ethernet frame transfer processing is performed. A decrease in efficiency can be prevented. In addition, it is possible to reduce the probability of discarding data transferred on the system bus 25 when a plurality of bus masters request access. Further, by providing the external memory unit 24 outside the network processor 20, it is not necessary to increase the memory capacity built in the network processor 20.

Note that the number of entry tables is not limited to 128. When the number of entry tables is ²ⁿ (n is a natural number), the data amount of the comparison result information 15 when the entry table and the received header information INF1 match is (1 bit of match / mismatch information) + (address data) n bits) = (n + 1) bits. Therefore, when the (n + 1) bits are smaller than the data amount of the 48-byte received header information INF1, it is possible to achieve the effect of reducing the data amount of the present invention.

[Second Embodiment]
FIG. 8 is a block diagram showing the configuration of the network device 202 according to the second embodiment of the present invention. The network device 202 has a network processor 40. The feature of the second embodiment is that the Ethernet frame receiver 21 is connected to the system bus 25 via a switch block (hereinafter referred to as S / W block) 35, and the Ethernet frame transmitter 22 is connected to the S / W block 36. It is connected to the system bus 25 via A built-in memory 37 is connected between the S / W block 35 and the S / W block 36. Since other configurations are substantially the same as those in the first embodiment, the same elements are denoted by the same reference numerals, and the description thereof is omitted.

  The built-in memory 37 compares the received header information INF1 and the entry comparison table, and if the received header information INF1 and the entry comparison table match, the reconstructed data frame MD generated by the reconstructed data frame generation circuit 31. Is configured to temporarily save.

  The S / W block 35 switches between storing the reconstructed data frame MD in the built-in memory 37 or the external memory unit 24 according to the free space of the built-in memory 37, and the CPU unit uses the stored information as saved information. 23 to transmit to. The S / W block 36 is configured to take out the data stored in the internal memory 37 or the external memory unit 24 based on the storage information transmitted to the CPU unit 23 and output the data to the Ethernet frame transmission unit 22. The system is configured to be selectable as a system so that the reconstructed data frame MD is preferentially stored in either the internal memory 37 or the external memory unit 24.

  Thus, by providing the S / W blocks 35 and 36 and the built-in memory 37, the built-in memory 37 has a free space when the received header information INF1 matches the entry comparison table (FIG. 4). In some cases, the reconstructed data frame MD can be transferred from the Ethernet frame receiver 21 to the Ethernet frame transmitter 22 without going through the system bus 25. Thereby, the data occupation rate of the system bus 25 can be reduced. In the reconstructed data frame MD, when the received header information INF1 matches the entry comparison table, the 48-byte received header information INF1 is compressed into the 1-byte comparison result information 15 (the number of entry tables is 128). The number of frames that can be stored in the internal memory 37 can be increased. If there is no free space in the internal memory 37, the reconstructed data frame MD is transferred from the Ethernet frame receiving unit 21 to the Ethernet frame transmitting unit 22 via the system bus 25, as in the first embodiment. The data reduction rate at this time is the same as that in the first embodiment.

It is a block diagram which shows the function of the network apparatus 102 which concerns on the 1st Embodiment of this invention. 2 is a functional block diagram showing a configuration of a network processor 20. FIG. 2 is a diagram illustrating a configuration of an Ethernet frame transmitted and received in a network processor 20. FIG. 6 is a diagram showing an entry comparison table of an entry comparison table circuit 28. FIG. 6 is a diagram showing an entry conversion table of an entry conversion table circuit 33. FIG. 10 is a flowchart showing an operation of the network device 102 when receiving a received Ethernet frame A. 4 is a flowchart showing an operation at the time of transmission of a transmission Ethernet frame B of the network apparatus 102. It is a block diagram which shows the structure of the network apparatus 202 which concerns on the 2nd Embodiment of this invention. It is the functional block diagram which simplified the structure of the conventional network processor described in the nonpatent literature 1 partially.

Explanation of symbols

1 ... Destination MAC address 2 ... Source MAC address 3 ... Type field 4 ... IP header 20 ... Network processor 21 ... Ethernet frame receiver 22 ... Ethernet frame transmitter 23 ... CPU 24 ... External memory 25 ... System bus

Claims (11)

The reception frame information indicating the destination and the transmission source included in the reception frame received from the external network device is converted into the transmission header information indicating the destination and the transmission source of the transmission frame transmitted to another external network device, and the transmission frame is converted into the transmission header information. A network processor to generate,
A transmission path through which data in the network processor is transferred;
Match / mismatch information indicating whether or not the received header information matches the comparison table with reference to a comparison table in which the received header information is associated with address data having a smaller data amount than the received header information. A frame receiving unit that generates and reconstructs frame data by replacing the received header information with the corresponding address data when the match / mismatch information indicates a match ;
An arithmetic processing unit that converts the reception header information of the reception frame into the transmission header information and transfers the transmission header information to the transmission path when the match / mismatch information indicates mismatch;
A memory connected to the transmission line and storing the reconstructed frame data;
When the match / mismatch information indicates a match, the address data of the reconstructed frame data is replaced with the corresponding transmission header information by referring to the conversion table in which the address data and the transmission header information are associated with each other. A frame transmission unit that generates the transmission frame and transmits the transmission frame to the other external network device;
A network processor comprising: When the match / mismatch information indicates mismatch,
The frame receiving unit generates the reconstructed frame data by adding the match / mismatch information indicating that the received header information does not match the comparison table to the received frame ,
The frame transmission unit generates the transmission frame by deleting the match / mismatch information indicating mismatch from the reconstructed frame data having the match / mismatch information and the transmission header information transferred from the memory. The network processor according to claim 1.   The transmission path is connected to the frame reception unit, the frame transmission unit, and the memory, and transfers data between the frame reception unit and the memory, and data transfer between the frame transmission unit and the memory. 3. The network processor according to claim 1, further comprising a first transmission line that is used in common. The transmission path includes a first transmission path and a second transmission path that are connected to the frame reception unit and the frame transmission unit via a switching unit, respectively.
The memory is connected to the first transmission path and stores only the reconstructed frame data having the address data, and the reconstructed frame data is connected to the second transmission path and has the mismatch information. The network processor according to claim 1, further comprising a second memory in which is stored. A transmission path through which data is transferred;
A header extraction circuit that extracts reception header information indicating a destination and a transmission source from a reception frame received from an external network device, and a comparison in which address data having a data amount smaller than the reception header information is associated with the reception header information A comparison table circuit having a table, a comparison circuit for determining whether or not the received header information matches the comparison table, and deleting the received header information from the received frame when it is determined by the comparison circuit to match And a match / mismatch information indicating whether or not the received header information matches the comparison table. When the match / mismatch information indicates a match, the delete circuit sets the received header information The address data corresponding to the received header information is added to the deleted data to add the address data. A reconstructed frame generation circuit to be transferred to the transmission path to generate a reconstructed frame data is data to be transferred to the sending passage, the frame receiving section having a,
An arithmetic processing unit that converts the reception header information of the reception frame into the transmission header information and transfers the transmission header information to the transmission path when the match / mismatch information indicates mismatch;
A memory connected to the transmission line and storing the reconstructed frame data;
The conversion table in which the address data included in the comparison table is associated with the transmission header information, the reconstructed frame data is input from the memory via the transmission path, and the conversion table is referred to . A transmission frame generation circuit that generates a transmission frame to be transmitted to another external network device by replacing the transmission header information corresponding to the address data with the address information when the information indicates a match. A transmission unit;
A network processor comprising: If the received header information does not correspond to the comparison table, the frame generation circuit adds mismatch information indicating that the received header information does not match the comparison table to the received frame and reconstructs the frame. Generate frame data,
The arithmetic processing unit converts the reception header information of the reconstructed frame data having the mismatch information transferred to the memory into the transmission header information by arithmetic processing and stores the transmission header information in the memory.
The frame transmission unit generates the transmission frame by deleting the mismatch information from the reconstructed frame data having the mismatch information and the transmission header information transferred from the memory. The described network processor.   The network processor according to claim 5 or 6, wherein the transmission path is a first transmission path connected to the frame reception unit, the frame transmission unit, and a memory. The transmission path is connected to the frame receiving section via a switching section and connected to the frame receiving section via the switching section and a first transmission path connected to the frame transmitting section via another switching section. And a second transmission line connected to the frame transmission unit via the other switching unit,
The network processor according to claim 5, wherein the memory includes a first memory connected to the first transmission path and a second memory connected to the second transmission path.   A network device comprising the network processor according to claim 1. Receive frames from external network devices,
Extracting the received header information indicating the destination and source of the received frame;
A determination is made as to whether or not the received header part information matches the comparison table in which the received header information is associated with address data having a smaller data amount than the received header information;
When the comparison table and the received header part information match, the match / mismatch information indicating whether the received header information matches the comparison table is generated, and the match / mismatch information indicates match And generating the reconstructed frame data transferred on the system bus by replacing the received header part information with the address data and storing it in the memory,
When the match / mismatch information indicates a mismatch, the received header information of the received frame is converted into the transmitted header information, the reconstructed frame data is generated and stored in a memory,
Receiving the reconstructed frame data stored in the memory;
When the match / mismatch information indicates a match, the address data is referred to by referring to a conversion table in which transmission address information indicating a destination and a transmission source of a transmission frame to be transmitted to another external network device is associated. Extracting the transmission header information corresponding to the data;
A frame transfer method comprising: generating the transmission frame by replacing the address data included in the reconstructed frame data with the transmission header part information. If the comparison table and the received header part information do not match, the reconstructed frame data is generated by adding mismatch information indicating that the comparison table and the received header part information do not match to the received frame. Save it in memory,
Converting the received header information of the reconstructed frame data having the match / mismatch information indicating mismatch to the transmission header information and storing it in the memory;
The transmission frame is generated by deleting the match / mismatch information indicating mismatch from the reconstructed frame data having the match / mismatch information indicating mismatch and the transmission header information stored in the memory. The frame transfer method according to claim 10.

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