JP5006390B2 - 算術および初等関数ユニットを有する図形プロセッサ - Google Patents
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Description
本開示は一般に回路に関し、そしてより詳しくは図形プロセッサに関する。
図形プロセッサはビデオゲーム、図形、計算機利用設計(CAD)、シミュレーションおよび可視化ツール、イメージング、等のような、いろいろなアプリケーションのための2次元(2−D)および3次元(3−D)画像を表現するために広く使用される。3−D画像は表面でモデル化され、そして各表面は多角形(典型的に三角形)で近似されることができる。3−D画像を表すために使用された三角形の数は画像の望ましい解像度と同様に表面の複雑性に左右され、そして非常に大きくなり、例えば、数百万であるかもしれない。各三角形は3つの頂点によって定義され、そして各頂点は空間配位、カラーバリュー、およびテクスチャ配位のようないろいろな属性と関連する。各属性は4コンポーネントまで持つことができる。
算術演算(arithmetic operation)を効率的に実行しそして初等関数(elementary function)を計算できる図形プロセッサがこの中に記述される。述語“演算”および“機能”は時には互換的に使用される。図形プロセッサはシェーダコアおよび多分他のユニットを具備する。シェーダコアは算術演算を実行できる少なくとも1つのALUおよび初等関数を計算できる少なくとも1つの初等関数ユニットを有する。ある実施形態では、ALUおよび初等関数ユニットはそれらが処理能力を改善するために同じまたは異なるスレッド(thread)に関する命令上で同時に動作できるように調整および相互接続される。例えば、ALUは1つのスレッドに関する1つの命令を実行でき、そして初等関数ユニットはもう1つのスレッドに関するもう1つの命令を同時に実行できる。これらのスレッドは同じまたは異なる図形アプリケーションのためのものであってもよい。
この発明のいろいろな局面および実施形態がさらに詳細に下記される。
付記
[1] 装置であって、算術演算を実行するように動作する少なくとも1つの算術論理ユニット(ALU)と、そして 初等関数を計算するように動作する少なくとも1つの初等関数ユニットとを含み、該少なくとも1つの初等関数ユニットおよび該少なくとも1つのALUが複数スレッド上で同時に動作可能である装置。
[2] 4つの算術論理ユニットを含む[1]記載の装置。
[3] 該4つの算術論理ユニットが1画素について1属性の4コンポーネントまでの上で算術演算を実行するように動作可能である、[2]記載の装置。
[4] 該4つの算術論理ユニットが4画素までについて1属性の1コンポーネントの上で算術演算を実行するように動作可能である、[2]記載の装置。
[5] 算術論理ユニットよりも少数の初等関数ユニットを含む[1]記載の装置。
[6] 単一の初等関数ユニットを含む[1]記載の装置。
[7] 該少なくとも1つの初等関数ユニットに関する命令が負荷命令として同期と共にコンパイルされる、[1]記載の装置。
[8] 制御ビットが該少なくとも1つの初等関数ユニットに関する該命令による他の命令と共に該少なくとも1つの初等関数ユニットに関する命令の同期のために使用される、[1]記載の装置。
[9] 該少なくとも1つの算術論理ユニットが第1のスレッドに関する第1の命令を実行するように動作可能であり、そして該少なくとも1つの初等関数ユニットが第2のスレッドに関する第2の命令を該少なくとも1つの算術論理ユニットと同時に実行するように動作可能である、[1]記載の装置。
[10] 該少なくとも1つの算術論理ユニットおよび該少なくとも1つの初等関数ユニットが異なる待ち時間を有する、[1]記載の装置。
[11] さらに、該少なくとも1つの算術論理ユニットとメモリシステムとの間および該少なくとも1つの初等関数ユニットと該メモリシステムとの間のデータの交換を容易とするように動作する負荷制御ユニットを含む、[1]記載の装置。
[12] 該少なくとも1つの初等関数ユニットが該負荷制御ユニットに連結される、[11]記載の装置。
[13] 該少なくとも1つの初等関数ユニットが該負荷制御ユニットと同時に動作可能である、[11]記載の装置。
[14] 該少なくとも1つの初等関数ユニットに関する要求および該負荷制御ユニットに関する負荷要求がバスを共有し、そして該少なくとも1つの初等関数ユニットおよび該負荷制御ユニットが異なるスレッドを同時に実行するように動作可能である、[12]記載の装置。
[15] さらに少なくとも1つの図形アプリケーションからスレッドを受信するようにおよび該少なくとも1つの算術論理ユニットおよび該少なくとも1つの初等関数ユニットによって該スレッドの実行を予定するように動作するスケジューラを含む、[1]記載の装置。
[16] 該少なくとも1つの初等関数ユニットが該スケジューラに連結される、[15]記載の装置。
[17] さらに、該少なくとも1つの算術論理ユニットおよび該少なくとも1つの初等関数ユニットと連結されたおよび該少なくとも1つのALUおよび該少なくとも1つの初等関数ユニットからの結果を蓄積するように動作する出力バッファを含む、[1]記載の装置。
[18] 集積回路であって、算術演算を実行するように動作する少なくとも1つの算術論理ユニット(ALU)と、そして初等関数を計算するように動作する少なくとも1つの初等関数ユニットとを含み、該少なくとも1つの初等関数ユニットおよび該少なくとも1つのALUが複数スレッド上で同時に動作可能である集積回路。
[19] および、4つの算術論理ユニットおよび4よりも少数の初等関数ユニットを含む[18]記載の集積回路。
[20] 無線装置であって、算術演算を実行するように動作する少なくとも1つの算術論理ユニット(ALU)および初等関数を計算するように動作する少なくとも1つの初等関数ユニットを含む図形プロセッサと、なお該少なくとも1つの初等関数ユニットおよび該少なくとも1つの算術論理ユニットが複数スレッド上で同時に動作可能であり、そして該図形プロセッサに関するデータを蓄積するように動作するメモリシステムと、を含む無線装置。
[21] 該図形プロセッサが4つの算術論理ユニットおよび4よりも少数の初等関数ユニットを含む、[20]記載の無線装置。
[22] 装置であって、算術演算を実行するように動作する少なくとも1つの算術論理ユニット(ALU)と、そして初等関数を計算するように動作する少なくとも1つの初等関数ユニットとを含み、該少なくとも1つの初等関数ユニットの数が該少なくとも1つの算術論理ユニットの該数よりも少数である装置。
[23] 該少なくとも1つの算術論理ユニットが該少なくとも1つの初等関数ユニットと同時に動作可能である、[22]記載の装置。
[24] さらに、該少なくとも1つの算術論理ユニットとメモリシステムとの間および該少なくとも1つの初等関数ユニットと該メモリシステムとの間のデータの交換を容易とするように動作する負荷制御ユニットを含む[22]記載の装置。
[25] 該少なくとも1つの初等関数ユニットが該負荷制御ユニットに連結される、[24]記載の装置。
Claims (17)
- 出力バッファと、
加算、減算、乗算、積和、絶対、否定、比較、飽和を含む算術演算を算術論理ユニット(ALU)命令に基づいて実行するように動作する少なくとも1つの算術論理ユニット(ALU)と、
正弦、余弦、逆数、対数、指数、平方根、および逆平方根を含む初等関数を初等関数ユニット命令に基づいて計算するように動作する少なくとも1つの初等関数ユニットと、
を含み、前記少なくとも1つの初等関数ユニットおよび前記少なくとも1つの算術論理ユニットが前記出力バッファに独立して接続され、異なる命令で同時に動作するように構成され、前記ALU命令は同期ビットを含み、前記同期ビットは前記初等関数ユニット命令に従属している前記ALU命令が、前記ALU命令が従属している前記初等関数ユニット命令に従うことを保証する、装置。 - 4つの算術論理ユニットを含む、請求項1記載の装置。
- 前記4つの算術論理ユニットが1画素について1属性の最大4つのコンポーネントに算術演算を実行するように動作可能である、請求項2記載の装置。
- 前記4つの算術論理ユニットが4画素までについて1属性の1つのコンポーネントに算術演算を実行するように動作可能である、請求項2記載の装置。
- 前記4つの算術論理ユニットよりも少数の初等関数ユニットを含む、請求項1記載の装置。
- 単一の初等関数ユニットを含む、請求項1記載の装置。
- 前記少なくとも1つの算術論理ユニットおよび前記少なくとも1つの初等関数ユニットが異なる待ち時間を有する、請求項1記載の装置。
- 前記少なくとも1つの算術論理ユニットとメモリシステムとの間および前記少なくとも1つの初等関数ユニットと前記メモリシステムとの間のデータの交換を容易とするように動作する負荷制御ユニットを更に含む、請求項1記載の装置。
- 前記少なくとも1つの初等関数ユニットが前記負荷制御ユニットに接続される、請求項8記載の装置。
- 前記少なくとも1つの初等関数ユニットが前記負荷制御ユニットと同時に動作可能である、請求項9記載の装置。
- 前記少なくとも1つの初等関数ユニットに関する要求および前記負荷制御ユニットに関する負荷要求がバスを共有し、前記少なくとも1つの初等関数ユニットおよび前記負荷制御ユニットが異なるスレッドを同時に実行するように動作可能である、請求項9記載の装置。
- 少なくとも1つの図形アプリケーションからスレッドを受信するようにおよび前記少なくとも1つの算術論理ユニットおよび前記少なくとも1つの初等関数ユニットによって前記スレッドの実行をスケジュールするように動作するスケジューラを更に含む、請求項1記載の装置。
- 前記少なくとも1つの初等関数ユニットが前記スケジューラに接続される、請求項12記載の装置。
- 出力バッファと、
ALU命令に基づいて加算、減算、乗算、積和、絶対、否定、比較、飽和を含む算術演算を実行するように動作する少なくとも1つの算術論理ユニット(ALU)と、
正弦、余弦、逆数、対数、指数、平方根、および逆平方根を含む初等関数を計算するように動作する少なくとも1つの初等関数ユニットと、
を含み、前記少なくとも1つの初等関数ユニットおよび前記少なくとも1つの算術論理ユニットは前記出力バッファに独立して接続され、異なる命令で同時に動作するように構成され、前記ALU命令は同期ビットを含み、前記同期ビットは前記初等関数ユニット命令に従属している前記ALU命令が、前記ALU命令が従属している前記初等関数ユニット命令に従うことを保証する、集積回路。 - 4つの算術論理ユニットおよび4つ未満の初等関数ユニットを含む、請求項14記載の集積回路。
- 出力バッファと、ALU命令に基づいて加算、減算、乗算、積和、絶対、否定、比較、飽和を含む算術演算を実行するように動作する少なくとも1つの算術論理ユニット(ALU)および初等関数ユニット命令に基づいて正弦、余弦、逆数、対数、指数、平方根、および逆平方根を含む初等関数を計算するように動作する少なくとも1つの初等関数ユニットを含む図形プロセッサと、前記図形プロセッサのためのデータを記憶するように動作するメモリシステムと、を具備し、前記少なくとも1つの初等関数ユニットと前記少なくとも1つの算術論理ユニットは前記出力バッファに独立して接続され、異なる命令で同時に動作するように構成され、前記ALU命令は同期ビットを含み、前記同期ビットは前記初等関数ユニット命令に従属している前記ALU命令が前記ALU命令が従属している前記初等関数ユニット命令に従うことを保証する、無線装置。
- 前記図形プロセッサが4つの算術論理ユニットおよび4よりも少数の初等関数ユニットを含む、請求項16記載の無線装置。
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2006
- 2006-05-25 US US11/441,696 patent/US8884972B2/en active Active
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- 2007-05-25 CN CN2007800187302A patent/CN101449239B/zh active Active
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JP2009538486A (ja) | 2009-11-05 |
WO2007140338A3 (en) | 2008-03-06 |
CN101449239B (zh) | 2012-07-18 |
KR101012625B1 (ko) | 2011-02-09 |
CN101449239A (zh) | 2009-06-03 |
WO2007140338A2 (en) | 2007-12-06 |
US20070273698A1 (en) | 2007-11-29 |
EP2024819B1 (en) | 2012-06-06 |
EP2024819A2 (en) | 2009-02-18 |
IN266871B (ja) | 2015-06-10 |
CA2650539A1 (en) | 2007-12-06 |
KR20090021286A (ko) | 2009-03-02 |
US8884972B2 (en) | 2014-11-11 |
US20150022534A1 (en) | 2015-01-22 |
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