JP4999921B2 - Combination of distortion estimation and error correction coding for memory devices. - Google Patents

Description

(Refer to related applications)
This application is filed on May 12, 2006, US provisional patent application No. 60/747106, filed on October 30, 2006, US provisional patent application No. 60/863480, filed on November 1, 2006. U.S. Provisional Patent Application No. 60/863810, U.S. Provisional Patent Application No. 60/867399 filed on November 28, 2006, U.S. Provisional Patent Application No. 60/887524 filed on January 16, 2007, 2007. US Provisional Patent Application No. 60/886102 filed on January 23, 2007, US Provisional Patent Application No. 60/886277 filed on February 11, 2007, US Provisional Patent Application filed on March 4, 2007 No. 60/892869, US Provisional Patent Application No. 60/894290 filed on March 12, 2007, US Provisional Patent Application No. 60/894456 filed on March 13, 2007, April 2007 Of submission to the 6th US Provisional Patent Application No. 60/912056, and is related to US Provisional Patent Application No. 60/913281, filed on April 22, 2007.

  The present invention relates generally to memory devices, and more particularly to a method and apparatus for improving memory device performance using error correction coding and distortion estimation.

  Some types of memory devices, such as flash memory and dynamic random access memory (DRAM), use an array of analog memory cells to store data. A flash memory device is described in Non-Patent Document 1, for example, which is incorporated herein by reference.

  In such a memory device, each analog memory cell typically includes a transistor that holds a certain amount of charge representing the information stored in the cell. The charge written to a particular cell affects the “threshold voltage” of the cell, ie, the voltage that must be applied to the cell so that the cell conducts current.

  Some memory devices, commonly referred to as single level cell (SLC) devices, store a single bit of information in each memory cell. Usually, the range of possible threshold voltages of a cell is divided into two regions. A voltage value falling in one of the regions represents a “0” bit value, and a voltage belonging to the second region represents a “1” bit value. High density devices, often referred to as multilevel cell (MLC) devices, store more than one bit per memory cell. In a multi-level cell, the threshold voltage range is divided into two or more regions, each region representing two or more bits.

  Multilevel flash cells and devices are described, for example, in Non-Patent Document 2, which is incorporated herein by reference. This paper compares several types of multi-level flash cells, such as common ground, DINOR, AND, NOR, and NAND cells.

  Other typical types of analog memory cells include nitride read only memory (NROM) cells, ferroelectric RAM (FRAM) cells, magnetic RAM (MRAM) cells, and phase change RAM (PRAM). Cell) (also called PCM). NROM cells are described, for example, in Non-Patent Document 3, which is incorporated herein by reference.

  FRAM, MRAM, and PRAM are described in Non-Patent Document 4, for example, which is incorporated herein by reference.

  In some applications, data stored in the memory device is encoded using error correction symbols (ECC). For example, Rodney and Sayano described many on-chip coding techniques for the protection of random access memory (RAM) devices using multilevel storage cells in [5]. Which is incorporated herein by reference. As another example, Patent Document 1 describes a method of storing data in an analog memory device using a coded modulation technique, the disclosure of which is incorporated herein by reference. Other ECC schemes for multi-level memory elements are described in US Pat.

  The threshold voltage value read from the analog memory cell is sometimes distorted. Distortion is due to various reasons, such as electric field coupling from adjacent memory cells, back pattern dependency (BPD) due to other cells along the same column of the array, disturbance noise due to operation of other cells in the array , And threshold voltage drift caused by element aging. Several common strain mechanisms are described in the article by Bez et al. Interference in memory cells is also described in Non-Patent Document 6, which is incorporated herein by reference.

US Pat. No. 6,057,049 describes a method of compensating for electric field coupling between floating gates of a high density flash electrically erasable / writable read only memory (EEPROM) cell array, the disclosure of which is incorporated herein by reference. It is. In accordance with the disclosed method, cell reading is compensated by first reading the state of all cells that are field coupled with the cell being read. The number associated with the floating gate voltage or the state of each coupled cell is then multiplied by the coupling ratio between the cells. The breakpoint level between states for each of the cells is adjusted by an amount that compensates for the voltage coupled from adjacent cells.
US Pat. No. 6,212,654 US Pat. No. 6,469,931 US Pat. No. 7,023,735 US Pat. No. 5,867,429 “Introduction to Flash Memory” by Bez et al., Proceedings of the IEEE, (91: 4), April 2003, p. 489-502 Eitan et al., “Multilevel Flash Cells and the Trade Trade-Offs” Proceedings of the 1996 IEEE International Electron Devices Meeting (IEDM), New York, New York, New York. 169-172 Mayan et al., "A 512 Mb NROM Flash Data Storage Memory with 8 MB / s Data Rate, 2 CIS, 2 Fr. p. 100-101 Kim and Koh, “Future Memory Technology Inclusion Emerging New Memories”, Proceedings of the 24th International Conference on Microelectronics (MEL), 19th month, 4th International Conference on Microelectronics. 377-384 “On-Chip ECC for Multi-Level Random Access Memories” Proceedings of the 1989 IEEE / CAM International Theory Workshop, Ithaca, New York, May 29, 1989. Lee et al., “Effects of Floating Gate Interference on NAND Flash Memory Cell Operation” IEEE Electron Device Letters, (23: 5), May 2002, p. 264-266 “Closest Point Search in Lattices” by Agrell et al., IEEE Transaction on Information Theory, volume 48, August 2002, p. 2201-2214 Jung et al., "A 117mm2 3.3V Only 128Mb Multilevel NAND Flash Memory for Mass Storage Applications" IEEE Journal of Solid State Circuits, 11:11. 1575-1583 Takeuchi et al., “A Multipage Cell Architecture for High-Speed Programming Multilevel NAND Flash Memories” IEEE Journal of Solid State Circuit, March, 8: 1998. 1228-1238

Embodiments of the present invention provide a method of operating a memory device, the method comprising:
Encoding the data using an error correction symbol (ECC) and storing the encoded data as a first analog value in an associated analog memory cell of the memory element;
After storing the encoded data, reading the associated second analog value from the memory cell of the memory element in which the encoded data is stored, wherein at least some of the associated second analog values are different from the associated first analog value. Stages,
Estimating distortion contained in the second analog value;
Calculating error correction metrics for the second analog value so as to be responsive to the estimated distortion;
Processing the second analog value using error correction metrics in an ECC decoding process to recover the data;
including.

In some embodiments, calculating error correction metrics includes evaluating, for each memory cell, one or more cell parameters indicative of distortion, and calculating error correction metrics to be responsive to the cell parameters. Stages. The cell parameters are: analog values read from other memory cells, estimated mutual coupling coefficients of other memory cells, statistical distribution parameters of second analog values read, programming and erase cycles previously received by the memory cells , Elapsed time after previous programming and erasing cycles, error previously detected in memory cell, identification of word line to which memory cell is connected, identification of bit line to which memory cell is connected, memory cell At least one parameter selected from the group of parameters consisting of an estimated parameter of the sense amplifier coupled to the bit line to which the is connected and an environmental parameter.

  In another embodiment, processing the second analog value includes dividing a range of possible values of the second analog value into a plurality of determination intervals and determining an associated determination interval in which the second analog value falls. And calculating error correction metrics includes defining a function to change the second analog value relative to the decision interval to improve the performance of the ECC decoding process.

  In yet another embodiment, processing the second analog value includes receiving feedback regarding the performance of the ECC decoding process and modifying the ECC decoding process to be responsive to the feedback. In yet another embodiment, processing the second analog value includes comparing the second analog value to a decision threshold, and changing the ECC decoding process includes changing the decision threshold. Changing the decision threshold includes rereading the second analog value from the memory cell using the changed decision threshold. In some embodiments, comparing the second analog value to the decision threshold includes reading the second analog value of the memory element using the decision threshold, and changing the decision threshold sends a command to the memory element. Requesting to change the threshold.

  In the disclosed embodiment, processing the second analog value comprises performing a plurality of related iterations of the ECC decoding process using various sets of decision thresholds to store the data stored in each memory cell. Generating a plurality of estimates, and restoring the data so as to be responsive to the plurality of estimates of the data. The step of restoring data may include the step of selecting one of a plurality of estimated values independently for each memory cell.

  In some embodiments, processing the second analog value includes applying a first ECC decoding process having a first error performance, and receiving the feedback is decoding on data decoded using the first process. Receiving an indication of error and altering the ECC decoding process includes processing the second analog value using a second ECC decoding process having a second error performance that is better than the first error performance. In another embodiment, changing the ECC decoding process includes changing the sampling resolution used to read the second analog value.

  In some embodiments, reading the second analog value includes reading multiple instances of the second analog value using various sets of associated decision thresholds, and calculating the error correction metric comprises: Combining multiple instances independently for a memory cell and calculating error correction metrics based on the combined multiple instances. Reading and combining multiple instances of the second analog value includes repeatedly obtaining additional instances of the second analog value and updating error correction metrics with the additional instances until the ECC is successfully decoded. It is good to include.

  In some embodiments, for each memory cell, estimating the distortion is from a potentially disturbing subset of memory cells that potentially contributes to distortion of the second analog value read from the memory cell. Reading the second analog value and calculating the error correction metric includes evaluating distortion due to potentially disturbing memory cells. In some embodiments, evaluating the distortion imparted to the memory cell by the potentially disturbing memory cell includes the second analog value read from the potentially disturbing memory cell and the second analog value read from the memory cell. Approximating the distortion provided by each potentially disturbing memory cell based on both analog values. In another embodiment, processing the second analog value includes processing the second analog value of the memory cell at the first quantization level and second analog value read from the potentially disturbing memory cell. Processing at a second quantization level coarser than the first quantization level. Processing the second analog value includes reading the second analog value at the first and second quantization levels by iteratively changing a threshold of a circuit used to read the second analog value; Good.

  In the disclosed embodiment, storing the encoded data includes writing a first analog value to the memory cell using a program and verify (P & V) process, and estimating the distortion potentially interferes. The memory cell comprises a memory cell that is fully programmed earlier than the memory cell, a memory cell that is fully programmed later than the memory cell, and a memory cell that is fully programmed simultaneously with the memory cell by a P & V process. Classifying into at least two classes selected from a group of classes and calculating total distortion separately within each of the classes.

  In some embodiments, the memory cells are flash memory cells, dynamic random access memory (DRAM) cells, phase change memory (PCM) cells, nitride read only memory (NROM) cells, magnetic RAM (MRAM). ) Cell, or ferroelectric RAM (FRAM) cell.

  In the disclosed embodiment, the ECC includes a block code. The block code may include one of a BCH code and a Reed-Solomon (RS) code. In some embodiments, the block code may include one of a low density odd-even test (LDPC) code, a turbo code, and a turbo product code (ТPC). The ECC decoding process may include an iterative decoding process. Additionally or alternatively, the ECC decoding process may use feedback generated by reading the second analog value. The ECC decoding process may include a maximum likelihood sequence estimation (MLSE) process. The ECC may include one of a conventional code, a trellis coded modulation (TCM) code, a bit interleaved coded modulation (BICM) code, and a concatenated code. The error correction metrics may include a likelihood ratio (LR) or a log likelihood ratio (LLR).

  In some embodiments, estimating the distortion includes predicting distortion included in one of the memory cells based on distortion included in another memory cell.

  In some embodiments, the memory cells are arranged in separate groups of potentially disturbing memory cells, and the step of estimating the distortion of each group is a mutual coupling matrix that represents mutual interference between pairs of memory cells in the group. Calculating the error correction metric is applied to the first analog value and is applied to the inverse of the mutual coupling matrix summed at the average distortion level of the associated memory cells in the group and to the second analog value. Calculating the distance between the inverse of the applied interconnection matrix. In another embodiment, the separate groups include associated nitride read only memory (NROM) cells, and potentially disturbing memory cells within each group include first and second charge storage regions of the associated NROM cells. In yet another embodiment, the memory cells are arranged in separate groups of potentially disturbing memory cells, and estimating the distortion of each group includes a vector of the average distortion level of the associated memory cells in the group and the group. Evaluating a mutual coupling matrix representing mutual interference between pairs of memory cells and calculating an error correction metric include a second vector of analog values read from the memory cells in the group, Calculating a metric to be responsive to the difference between the product of the coupling matrix and the vector of average distortion levels. In another embodiment, the separate groups include associated nitride read only memory (NROM) cells, and potentially disturbing memory cells within each group include first and second charge storage regions of the associated NROM cells.

  In yet another embodiment, storing the encoded data includes scrambling the encoded data and storing the scrambled data, and processing the second analog value is read from the memory cell. Descrambling the generated second analog value. In yet another embodiment, storing the data includes maintaining at least some of the memory cells at an erase level, reading the second analog value, estimating the distortion, and calculating error correction metrics. And processing the second analog value includes compensating for distortion of the second analog value read from the memory cell that was maintained at the erase level.

In accordance with an embodiment of the present invention, a method for operating a memory device is also provided, the method comprising:
Storing data as a first analog value in an associated analog memory cell of the memory element;
After storing data, reading a plurality of instances of a second analog value from an associated memory cell, each of the instances being read by comparing the second analog value to an associated decision threshold;
Estimating distortion contained in the second analog value;
Processing multiple instances of the second analog value to be responsive to the estimated distortion to recover the data;
including.

In some embodiments, reading and processing the plurality of instances includes iteratively obtaining additional instances of the second analog value.

According to an embodiment of the present invention, there is additionally provided an apparatus for retrieving data encoded using an error correction symbol (ECC) and stored as a first analog value in an associated analog memory cell of a memory element. The device
A reading unit configured to read an associated second analog value from an analog memory cell of a memory element in which encoded data is stored, wherein at least some of the associated second analog values are related to the associated first analog value and With different reading units,
A signal processing unit configured to estimate distortion contained in the second analog value and calculate error correction metrics for the second analog value to be responsive to the estimated distortion;
A decoder configured to process the second analog value using error correction metrics to decode the ECC and recover the data;
Is provided.

  In some embodiments, the reading unit is in a first integrated circuit (IC) and the signal processing unit and the decoder are in a second IC that is different from the first IC. In an alternative embodiment, the reading unit, signal processing unit, and decoder are integrated in a single element.

In accordance with an embodiment of the present invention, there is further provided an apparatus for retrieving data stored in an associated analog memory cell of a memory element as a first analog value, the apparatus comprising:
A read unit configured to read a plurality of instances of a second analog value from an associated memory cell, each of the instances being read by comparing the second analog value to an associated decision threshold;
A signal processing unit configured to estimate distortion contained in the second analog value and to process multiple instances of the second analog value to be responsive to the estimated distortion to recover the data;
Is provided.

  The invention will be more fully understood from the following detailed description of the embodiments thereof, taken together with the drawings.

(Brief description of the drawings)
FIG. 1 is a block diagram that schematically illustrates an apparatus for memory signal processing, in accordance with an embodiment of the present invention.
FIG. 2 is a diagram schematically illustrating a memory cell array in accordance with an embodiment of the present invention.
FIG. 3 is a graph illustrating the voltage distribution of a memory cell array according to an embodiment of the present invention.
FIG. 4 is a functional block diagram that schematically illustrates a process for retrieving data from a memory cell array, in accordance with an embodiment of the present invention.
FIG. 5 is a flow diagram that schematically illustrates a method for retrieving data from a memory cell array, in accordance with an embodiment of the present invention.
FIG. 6 is a flow diagram that schematically illustrates a method for estimating memory cell array distortion, in accordance with an embodiment of the present invention.

Overview Embodiments of the present invention provide improved methods and schemes for retrieving information stored in memory elements. In the embodiments described below, data is stored as the level of charge written to the array of memory cell arrays. The charge level determines the respective threshold voltage of the cell. In order to reduce the effects of various distortion mechanisms, the data is encoded using error correction symbols (ECC) prior to storing it in the memory cells.

  Data is recovered by reading the threshold voltage of the memory cell and decoding the ECC using an ECC decoder. The ECC decoder operates with ECC metrics, eg, a log likelihood ratio (LLR) defined over the read voltage.

The signal processing unit estimates distortion contained in the read voltage. Distortion may be due to effects such as other cells in the array, operations performed on such cells, and / or aging. Depending on the strain mechanism, the actual level of charge stored in the cell and / or the sensed and sampled voltage may be affected. The signal processing unit calculates ECC metrics based on the estimated distortion and provides the ECC metrics to the ECC decoder. The ECC decoder decodes the ECC using metrics in order to restore the data stored in the target memory cell. The ECC metrics may also consider some additional cell parameters that indicate the expected distortion level. In some embodiments, feedback depending on the success, failure, or quality of the ECC decoding process is used to change the operation of the decoding process.

  By using ECC metrics based on the estimated distortion, the performance of the ECC decoding process is significantly improved. The improved performance of the ECC decoding process can be used to achieve higher information storage density in several ways. For example, the number of voltage levels (and hence the number of information bits) stored in each memory cell can be increased. In other embodiments, a smaller, higher density memory cell array, which may have increased mutual coupling between cells and higher aging rates, provides better performance for improved ECC performance. Can be used in conjunction. Additionally or alternatively, the code rate can be reduced for a given error rate requirement, resulting in smaller coding overhead. In an alternative embodiment, performance errors for a given memory array and ECC can be improved. Improved performance can also be used to reduce the range of threshold voltages used by a memory device, thus reducing the power consumption of the device and improving its reliability and durability.

  The methods and apparatus described herein may be used with a wide variety of memory devices and cell types, such as various flash memory cells, DRAM cells, NROM cells, MRAM cells, and PCM cells. The principles of the present invention may also be used in data storage and retrieval on various storage media and devices, such as hard disk drives (HDDs).

  Any suitable estimation method can be used to estimate the distortion of the voltage read from the memory cell array. Several exemplary methods are now described.

System Description FIG. 1 is a block diagram that schematically illustrates an apparatus 20 for memory signal processing, in accordance with an embodiment of the present invention. Device 20 includes a memory element 24 that stores data in a memory cell array 28. The memory array includes a plurality of analog memory cells 32. In the context of this patent application and in the claims, the term “analog memory cell” refers to any memory that stores information by holding a continuous analog value of a physical parameter, such as a voltage or charge. Used to represent a cell. Array 28 may comprise any type of analog memory cell, such as NAND and NOR flash cells, PCM, NROM, FRAM, MRAM, DRAM cells, and the like.

  Data to be stored in the memory device 24 is provided to the device and stored in the data buffer 36. The data is then converted to an analog voltage and written to the memory cell 32 using a read / write (R / W) unit 40, the function of which is described in further detail below. When reading data from the array 28, the unit 40 converts the charge, and thus the analog voltage of the memory cell 32, into a digital sample. Each digital sample is represented using one or more bits. Samples are stored in buffer 36. Samples generated by unit 40 are also referred to as soft samples. The operation and timing of the memory element 24 is managed by the control logic 48.

  Storage of data into and retrieval from the memory element 24 is performed by a memory signal processor (MSP) 52. The MSP 52 is interposed between the memory element 24 and a host or application that stores and retrieves data. As described in detail below, MSP 52 uses a new method that combines error correction coding and distortion estimation to improve data reliability and storage density.

  The MSP 52 includes an encoder / decoder 64 that encodes data to be written to the element 24 using ECC and decodes the ECC as data is read from the element 24. The signal processing unit 60 processes the data written to and retrieved from the element 24. Specifically, unit 60 estimates the distortion that affects the voltage read from element 24. Estimated distortion is used to improve ECC performance, as described in more detail below.

  The MSP 52 includes a data buffer 72 that is used by the unit 60 to store data and to interface with the memory element 24. The MSP 52 also includes an input / output (I / O) buffer 56 that forms an interface between the MSP and the host. The controller 76 manages the operation and timing of the MSP 52. In addition to performing the functions described below, the controller 76 may perform additional memory management functions, such as wear leveling and bad block management. The signal processing unit 60 and the controller 76 may be incorporated in hardware. Alternatively, unit 60 and / or controller 76 may comprise a microprocessor executing appropriate software or a combination of hardware and software elements.

  The configuration of FIG. 1 is an exemplary device configuration, which is shown for clarity of concept only. Other suitable configurations can also be used. Elements that are not necessary to understand the principles of the present invention, such as various interfaces, addressing circuitry, timing and sequencing circuitry, data scrambling circuitry, and debugging circuitry, have been omitted from the figures for clarity.

  In the exemplary device shown in FIG. 1, memory element 24 and MSP 52 are incorporated as two separate integrated circuits (ICs). In alternative embodiments, however, the memory elements and MSPs may be integrated on a single IC or system on chip (SoC). In some embodiments, a single MSP 52 may be connected to multiple memory elements 24. Additional architectural aspects of some embodiments of apparatus 20 implementation are described in further detail in the above-mentioned US Provisional Patent Application No. 60/867399.

  In a typical write operation, data to be written to the memory element 24 is received from the host and stored in the I / O buffer 56. The encoder / decoder 64 encodes the data, and the encoded data is transferred to the memory element 24 via the data buffer 72. In the element 24, data is temporarily stored in the buffer 36. The R / W unit 40 converts the data to an analog voltage and writes the data to the appropriate cell 32 of the array 28.

  In a typical read operation, the R / W unit 40 reads an analog voltage value from the appropriate memory cell 32 and converts the voltage to a digital sample. Samples are stored in buffer 36 and transferred to buffer 72 of MSP 52. The signal processing unit 60 estimates the distortion contained in the data samples using the method described below.

  The block of data is transferred from the buffer 72 to the unit 60, and the encoder / decoder 64 decodes the ECC of this block. Encoder / decoder 64 uses the distortion estimation provided by unit 60 to improve the performance of the ECC decoding process. The decoded data is transferred to the host via the I / O buffer 56.

  In some embodiments, the MSP 52 scrambles the data before it is written to the memory cell and descrambles the data read from the memory cell to improve distortion estimation performance.

Memory Array Configuration and Distortion Mechanism FIG. 2 is a diagram that schematically illustrates memory cell array 28, in accordance with an embodiment of the present invention. Although FIG. 2 refers to flash memory cells connected in a particular array configuration, the principles of the present invention are equally applicable to other types of memory cells and other array configurations. Some exemplary cell types and array configurations are described in the references cited in the background section above.

  Memory cells 32 of array 28 are arranged in a grid having a plurality of rows and columns. Each cell 32 comprises a floating gate metal oxide semiconductor (MOS) transistor. A certain amount of charge (electrons or holes) can be stored in a particular cell by applying appropriate voltage levels to the gate, source, and drain of the transistor. The value stored in the cell can be read by measuring the threshold voltage of the cell, which is defined as the minimum voltage that must be applied to the gate of the transistor to make the transistor conductive. The read threshold voltage is proportional to the charge stored in the cell.

  In the exemplary configuration of FIG. 2, the gates of the transistors in each row are connected by a word line 80. The sources of the transistors in each column are connected by a bit line 84. In some embodiments, for example, in some NOR cell devices, the source is connected directly to the bit line. In an alternative embodiment, for example in some NAND cell devices, the bit line is connected to a string of floating gate cells.

  Typically, the R / W unit 40 applies varying voltage levels to the gate of a particular cell 32 (ie, to the word line to which the cell is connected) and whether the cell drain current exceeds a certain threshold. The threshold voltage of a particular cell 32 is read by examining (ie, whether the transistor is conducting). Unit 40 typically applies a series of different voltage values to the word line to which the cell is connected to determine the lowest gate voltage value at which the drain current exceeds the threshold. Typically, unit 40 reads the entire row of cells, also called a page, simultaneously.

  In some embodiments, unit 40 measures the drain current by precharging the cell's bit line to a voltage level. When the gate voltage is set to a desired value, the drain current discharges the bit line voltage through the cell. After the gate voltage is applied, for a few microseconds, unit 40 measures the bit line voltage and compares the bit line voltage to a threshold value. In some embodiments, each bit line 84 is connected to an associated sense amplifier that amplifies the bit line current and converts it to a voltage. The amplified voltage is compared with a threshold using a comparator.

  Some of the methods described below include adjusting the threshold against which the read voltage level is compared. Such threshold adjustment may be performed at high speed prior to each reading operation in some cases. In some embodiments, the memory element 24, specifically the R / W unit 40, is designed to allow fast, effective and flexible threshold adjustment. For example, the interface between the MSP 52 and the memory device 24 includes commands that allow the R / W unit 40 to perform fast, effective and flexible threshold adjustment. Such a command may define the requested adjustment for each individual threshold or request the same adjustment for the entire threshold set. Exemplary command interfaces that can be used for this are described in the above-mentioned US Provisional Patent Application Nos. 60 / 888,277, 60 / 91,056, and 60 / 913,281.

  The voltage reading method described above is an exemplary method. Alternatively, the R / W unit 40 may use another suitable method for reading the threshold voltage of the cell 32. For example, unit 40 includes one or more analog-to-digital converters (ADCs) that convert bit line voltages into digital samples. Additionally or alternatively, the methods and apparatus described herein may be used with any suitable method or means for writing analog values to and reading from analog memory cells.

  In some embodiments, all pages (rows) are written and read in parallel. Cell erasing is usually performed on blocks containing multiple pages. A typical memory device may contain hundreds of thousands of pages, each containing thousands of cells (eg, 16K or 32K cells). A typical erase block is about 128 pages, although other block sizes may be used.

  The voltage digitized by the R / W unit 40 can include various types of distortion, which is due to various distortion mechanisms of the array 28. Some distortion mechanisms affect the actual charge stored in the cell, while others distort the sensed voltage. For example, electrical coupling between adjacent cells in the array can change the threshold voltage of a particular cell. This effect is called disturbing noise. As another example, charge can leak from the cell over time. As a result of this aging effect, the cell threshold voltage may drift over time from the originally written value.

  Another type of distortion, commonly referred to as disturbing noise, results from reading, writing, or erasing in one cell of the array, which causes unintentional programming or erasing of other cells. As yet another example, the source-drain current of a particular cell can be affected by changes in adjacent cells, eg, other cells in the same NAND cell string, due to an effect called back pattern dependency.

  FIG. 3 is a graph illustrating the voltage distribution of memory cell array 28 in accordance with an embodiment of the present invention. FIG. 3 is used to illustrate the effect of distortion on the accuracy of reading values from the memory cell array. In the example of FIG. 3, each cell 32 stores 2 bits of information using four nominal voltage levels. Graph 92A. . . 92D shows the voltage distribution across the entire array as each cell is programmed. Graph 92A shows the voltage distribution in the cell storing the “11” bit value. Graphs 92B, 92C, and 92D show the voltage distributions in the cells storing “01”, “00”, and “10” bit values, respectively.

  In this example, the threshold voltage of the cell 32 is read using 3-bit conversion. Accordingly, the threshold voltage range is divided into eight decision zones 96A. . . Divided into 96H. The data content of each cell is determined based on the determination zone where the threshold level read from the cell falls. For example, a voltage level 98 read from a particular cell that falls within decision zone 96F indicates that the data content of the cell is “00”. It should be noted that voltage levels falling within decision zone 96E are also interpreted as indicating a data content of “11”. Although four decision zones are usually sufficient to decode the four possible bit combinations, using eight decision zones gives better resolution and improves distortion estimation and decoding performance.

  As a result of various distortion mechanisms, the threshold voltage distribution can change. For example, the threshold voltage can drift over time due to aging. Graph 100A. . . 100D shows the distribution of cells having data contents of “11”, “01”, “00”, and “10”, respectively, after the voltage is shifted with time.

  Specifically, voltage level 98 changed to level 104 shifted due to distortion. As can be seen, voltage level 104 falls within zone 96E, rather than decision zone 96F, as originally intended. In this example, the bias does not necessarily cause a decision error due to the improved resolution provided by the eight decision zones. However, in general, distortion can cause reading errors in the cell data contents.

ECC encoding assisted by distortion estimation The device 20 encodes the data stored in the cell using ECC, thereby reducing the possibility of making erroneous decisions about the data content of the cell 32. In this example, the encoder / decoder 64 encodes each page of data separately. In alternative embodiments, the data may be encoded with blocks having other suitable sizes. For example, each page can be divided into several sectors, and the encoder / decoder 64 encodes the data for each sector separately. Alternatively, the data can be encoded across multiple pages.

  Various types of error correction symbols known in the art can be used to encode the data. The ECC may include, for example, a block code that separately encodes a fixed-size block of data. Exemplary block codes may include a Bose, Chowdry, Hochkengem (BCH) code or a Reed-Solomon (RS) code. A special class of block codes is a class of codes that are suitable for the iterative decoding process. Codes that are normally decoded using an iterative process include, for example, low density odd-even (LDPC) codes, turbo-codes, and turbo product codes (TPC). Other types of codes may include superposition codes and trellis coded modulation (TCM) codes. As a further alternative, the code may include a known bit interleaved coded modulation (BICM) code, which typically includes a conventional code, a bit interleaver, and a gray mapper.

  The ECC process may alternatively include a feedback encoding programming process, such as the process described in the above-mentioned US Provisional Patent Application No. 60 / 863,810. In some cases, the two codes can be used sequentially as inner and outer codes to form a concatenated code.

  The ECC used by the encoder / decoder 64 operates on metrics defined over the read data. If a voltage level is read, the ECC metrics provide information about the statistical likelihood that a particular information bit (or symbol, as in the case of Reed-Solomon code and trellis code) is encoded. Good. ECC metrics are based on voltage distribution 92A. . . It may be based on parameters such as 92D center and variance.

  Typically, the MSP 52 estimates voltage distribution parameters and uses the estimated parameters to calculate bit or symbol likelihood. In addition, the MSP stores or receives information about the state of the cell and uses this information to evaluate the characteristics of the voltage distribution of the cell and change the ECC metrics accordingly. For example, the MSP may keep track of the number of program and erase cycles received by the cell and how long they were programmed. These parameters indicate the level of leakage noise that it has suffered since the cell was programmed.

  In some embodiments, the ECC metrics may include a likelihood ratio (LR) or a log likelihood ratio (LLR), which are defined as follows:

ここで、Ｘ_ｉは特定のメモリセルに格納された１つ以上のビットの特定のデータビットを示し、ｒはセルから読取られた電圧レベルを示す。あるいは、ＥＣＣメトリクスは、メモリセルから読み取られる電圧レベルにわたって規定されたその他のメトリックを含むとよく、これはＥＣＣ復号プロセスを支援する。

Here, X _i indicates a specific data bit of one or more bits stored in a specific memory cell, and r indicates a voltage level read from the cell. Alternatively, the ECC metrics may include other metrics defined over the voltage level read from the memory cell, which aids the ECC decoding process.

  Other types of ECC metrics may include the square error LLR commonly used in additive white Gaussian noise scenarios and the mean square error estimate often used in Viterbi decoders, TCM codes, and BICM codes.

  In some embodiments, the ECC metric may indicate the relative reliability of the decoded bits. For example, a bit may be classified as “suspected false”, “normal”, or “safe” based on the distance from the center of the reading threshold level distribution. If the read voltage is close to the edge of the decision zone, the associated bit is classified as “suspected false”. An associated bit is classified as “safe” if the voltage is well within the decision zone. Otherwise, the bit is classified as “normal”. Such ECC metrics can be used, for example, by a block code soft decoder.

  The signal processing unit 60 estimates distortion included in the voltage read from the memory cell 32 and calculates ECC metrics based on the estimated distortion. By using ECC metrics based on the estimated distortion, the performance of the ECC decoding process performed by the encoder / decoder 64 is significantly improved and vice versa because it places more importance on values with smaller distortions. The same.

Referring to the example of FIG. 3 and assuming that p (X _i = 0) = p (X _i = 1) = 0.5, equation [2] becomes:

ここで、Ｓは決定ゾーン９６Ａ．．．９６Ｈを示し、Ｓ｜Ｘ_ｉ＝０は、ビットＸ_ｉが「０」に等しいセルにプログラムされる値のサブセットを示し、そしてＳ｜Ｘ_ｉ＝１は、ビットＸ_ｉが「１」に等しいプログラムされた値のサブセットを示す。

Here, S is a decision zone 96A. . . 96, where S | X _i = 0 indicates a subset of values programmed into the cell where bit X _i is equal to “0”, and S | X _i = 1 indicates that bit X _i is equal to “1” Indicates a subset of programmed values.

Let T ₀ denote the value for X _i = 0 closest to the read voltage r, and T ₁ denote the value for X _i = 1 closest to the read voltage r. In most practical cases, the sum of equation [3] can be approximated by the maximum term of each sum, and the maximum term is usually the term containing T ₀ and T ₁ . Also, assuming that the voltage distribution of r is a Gaussian distribution with variance σ ² , Equation [3] can be approximated by:

ｒは特定の決定ゾーン内の値を表わし、符号［Ｖ_ａ、Ｖ_ｂ］で示されるので、式［４］は次式のようにより正確に書くことができる。

Since r represents a value within a specific decision zone and is denoted by the sign [V _a , V _b ], equation [4] can be written more accurately as:

ここで、Ｑ（）はガウス相補累積分布関数（ＣＤＦ）を示す。本例では、ユニット６０はＶ_ａ、Ｖ_ｂ、Ｔ_０、Ｔ_１およびσに基づいてＬＬＲを計算する。

Here, Q () represents a Gaussian complementary cumulative distribution function (CDF). In this example, unit 60 calculates LLR based on V _a , V _b , T ₀ , T ₁ and σ.

In some embodiments, the ECC metrics evaluated by the MSP may take into account additional cell parameters available to the MSP to improve the accuracy and performance of the ECC metrics. Such additional information may be any parameter indicating the expected distortion level of the cell, such as the value written to the neighboring cell, the estimated mutual coupling coefficient of the neighboring cell, the number of program and erase cycles received by the cell, the previous program and erase cycle Subsequent periods, previous decoding errors detected in the cell, identification of the word line and / or bit line to which the cell is connected, environmental parameters such as supply voltage (V _CC ) and temperature, and / or other Appropriate parameters should be included. For example, the conditional probability in equation [3] can be replaced with a conditional probability that takes into account additional cell parameters.

  In some practical cases, the level of mutual coupling interference from neighboring cells depends not only on the voltage (or charge) stored in the neighboring cell, but also on the voltage level (or charge level) of the disturbed cell. Thus, in some embodiments, the MSP calculates ECC metrics by evaluating the function defined over the disturbing cell and the voltage (or charge) level of the disturbed cell.

  Several aspects of estimating the value of the mutual coupling coefficient are described in a PCT application filed on May 10, 2007 entitled “Distortion Estimation and Cancellation in Memory Elements”, the disclosure of which is hereby incorporated by reference And incorporated herein.

  In some cases, it is possible to divide the memory cell array into groups of cells, so that mutual coupling interference is limited to each group, and the various groups are isolated from each other. An extreme example occurs with NROM devices, where each cell stores two values in two charge regions of the cell. If cell-to-cell separation is high enough, it can be assumed that mutual coupling only occurs between the two values of each cell.

  In such a case, the mutual coupling coefficient between cells in a specific cell group can be composed of a mutual coupling matrix, and ECC metrics can be calculated using the mutual coupling matrix.

Let x = [x ₁ x ₂ ... X _k ] denote _k values written in a group of k interfering cells. Let y = [y ₁ y ₂ ... Y _k ] denote _k values read from the cell. In some cases, for example, if a cell is written using a program and verify (P & V) process that is applied to all cells in the group simultaneously, x = y when the cell is programmed. The vector y changes over time due to various distortion mechanisms, such as aging. The value of vector y at a later time can be written as:

ここで、ｍはエージングに因るｋ個の電圧の関連電圧変化のベクトルを示し、はランダム・エージング・ノイズ構成要素のベクトルを示す。ｋ個のランダム構成要素は分散σ^２を有するガウス分布を有すると仮定される。Ｈは次式のように規定される相互結合行列である。

Here, m represents a vector of related voltage changes of k voltages due to aging, and represents a vector of random aging noise components. The k random components are assumed to have a Gaussian distribution with variance σ ² . H is an interconnection matrix defined by the following equation.

ここで、α_ｉｊはグループ内のセルｊからセルｉまでの相互結合係数を示す。ｋ＝２の場合、例えばＮＲＯＭの場合、

Here, α _ij represents a mutual coupling coefficient from cell j to cell i in the group. When k = 2, for example, in the case of NROM,

そのｋ個の構成要素は相関性があるので、上式［６］の項Ｈｎはホワイトではない。上式［６］の両辺にＨの逆数を乗じて次式を得る。

Since the k components are correlated, the term H n in the above equation [6] is not white. The following equation is obtained by multiplying both sides of the above equation [6] by the reciprocal of H.

ここで、項（Ｈ^−１ ｘ＋ｍ）は決定性であり（そして、書き込まれたレベルは既知であると仮定すれば、既知であり）、ｎはランダムかつホワイトである。
ＭＳＰ５２は係数α_ｉｊを推定することによってＨ^−１を計算する。次にＭＳＰは次式を最小にするｘの値を決定することによってデータを復号することができる。

Here, the term (H ⁻¹ x + m ) is deterministic (and is known, assuming the level written is known), and n is random and white.
The MSP 52 calculates H ⁻¹ by estimating the coefficient α _ij . The MSP can then decode the data by determining the value of x that minimizes

ここで、‖‖はユークリッドノルムを示す。

Here, ‖‖ indicates the Euclidean norm.

For example, when using a hard-decision ECC decoder, the MSP can scan or search through various possible data value combinations of x to determine the set of values that minimizes [9] above. . Any suitable search process can be used for this purpose. For example, MSP can use a sphere decoding method such as the method described in Non-Patent Document 7 (which is incorporated herein by reference). Alternatively, V-BLAST approximate decoding methods can also be used as is well known in the art.

When using a soft-decision ECC decoder, for example when using BICM, the MSP typically calculates the LLR for each data bit during the search process. For example, the MSP calculates the minimum value of equation [9] for all x values for which the data bit in question is set to “1”, and from this, all values for which the data bit in question is set to “0” are calculated. The minimum value of equation [9] can be subtracted from the x value. The resulting LLR can then be used as a metric by the soft ECC decoder. Alternatively, m can be approximated by using the nominal average value of change based on a hard decision in y . The equation y −H · m can then be used as an input to the LLR calculation in equation [4] or [5] above.

  In general, equation [9] can be used as an ECC metric by an ECC decoder. For example, when the ECC includes a TCM scheme and the ECC decoder includes a Viterbi decoder, the decoder uses the above equation [9] as a metric for a group of values corresponding to k cells in the group. Can do.

  FIG. 4 is a functional block diagram that schematically illustrates a process for retrieving data from memory cell array 28, in accordance with an embodiment of the present invention. When reading data from the memory element 24, the R / W unit 40 generates digitized samples based on the voltage level read from the memory cells 32 of the array 28. Samples are stored in the data buffer 72.

  Within the context of this patent application, and in the claims, terms such as “read data”, “sampling voltage”, and “read voltage” explicitly refer to analog voltages stored in memory cells as digital samples. Or to receive such samples through the interface. For example, when using a two-chip configuration as shown in FIG. 1 above, these terms can refer to receiving samples generated by an external comparator or A / D converter by the MSP.

  The target sample (ie, the sample of the memory cell whose data is requested by the host) is provided to the metric calculation module 108 of the signal processing unit 60. The metric calculation module calculates the ECC metrics for the target sample.

  The target samples as well as samples from other cells that could potentially distort the target cell are provided to the distortion estimation module 112 of the signal processing unit 60. Module 112 estimates the distortion due to the target cell based on samples of the target cell and potentially disturbing cells. Module 112 may perform various methods to estimate the distortion. An exemplary estimation method is further described below.

  Module 112 may consider various numbers and types of potentially disturbing cells based on the type of distortion mechanism in question and the estimation method used. For example, in some embodiments, module 112 estimates the mutual coupling interference from each cell in the array to its eight neighboring cells. In these embodiments, the normal module 112 processes both the page (row) to be decoded and the previous and subsequent pages. The data buffer in this case can be several pages in size.

  In an alternative embodiment, module 112 may consider distortions that originate only from the left and right neighbors of a cell. In these embodiments, the data buffer is smaller and may be about a single page.

  In some embodiments, module 112 estimates distortion due to cells in a page away from the target cell. For example, back pattern noise can be attributed to cells in the same column as target cells other than remote pages. In these embodiments, the contents of such remote cells, or other information about this cell, may be provided to module 112.

  In some cases, samples read from potentially disturbing cells can be stored and processed with a coarser quantization, i.e., with a smaller number of bits compared to the quantization of the samples in the target cell. Reduced quantization can reduce the size of the data buffer and the complexity of the module 112.

  The distortion estimation module 112 provides the estimated distortion to the metric calculation module 108. The metric calculation module calculates ECC metrics based on the estimated distortion and provides the metrics to the encoder / decoder 64. The ECC encoder / decoder decodes the ECC using metrics to restore the data stored in the target memory cell.

  In some embodiments, the metric calculation module 108 defines functionality for sample values read from the target cell and for decision thresholds. This function changes the sample value with respect to the decision threshold to reduce the error probability of the ECC decoding process, assuming that distortion estimation is provided by module 112. For example, referring to FIG. 3, the function evaluated by module 108 is the curve 100A. . . 100D with curve 92A. . . It almost wraps around the voltage axis so that it maps to 92D respectively. If the function operates on a subsequent target sample, the bit decision is made with the shifted distribution 100A. . . Performed based on 100D.

  In some cases, feedback from the ECC decoding process (eg, decoding success or failure) can be used to further improve the distortion estimation and metric calculation process. A data retrieval method using such feedback will be described below with reference to FIG.

  The ECC decoder may consider the sequence of cells and make a joint decision. For example, the decoder may apply various maximum likelihood sequence estimation (MLSE) techniques for this purpose, which are well known in the art.

Iterative Distortion Estimation Using ECC Encoded Feedback FIG. 5 is a flow diagram that schematically illustrates a method for retrieving data from memory cell array 28, in accordance with another embodiment of the present invention. Method steps 128-140 represent a process similar to that of FIG. Subsequent stages 144-156 perform an iterative adaptation of the decoding process based on feedback from the ECC decoding process.

  The method begins at read stage 128 with an R / W unit 40 that reads the voltage of the desired target cell of array 28 and the voltage from potentially disturbing cells. In the distortion estimation stage 132, the signal processing unit 60 estimates the distortion included in the read voltage. In the metric calculation stage 136, the unit 60 calculates ECC metrics. Unit 60 may use any ECC metric and any distortion estimation method, such as the method described herein. At the decoding stage 140, the ECC encoder / decoder 64 decodes the ECC and restores the stored data.

  The ECC encoder / decoder 64 informs the unit 60 (or controller 76) whether the page has been successfully decoded, ie whether the decoded page contains errors. When checked in the success check stage 144, if the decryption is successful, the method ends successfully as a successful end stage 148. Unit 60 may use various methods to determine if the decoded page contains errors. For example, unit 60 may check whether the decoder output is a valid codeword. Alternatively, one or more checksum bits, such as cyclic redundancy check (CRC), may be stored with the data. Unit 60 may calculate a CRC for the decoded data and compare it to the stored CRC value. As a further alternative, unit 60 may calculate a reliability metric for the decoded data and compare it to a predetermined threshold.

  In this example, only a certain maximum number of feedback iterations are allowed to avoid endless loops, clogging conditions. Thus, if feedback from the ECC decoder indicates that the decoded page contains errors, at iteration check stage 152, unit 60 (or controller 76) checks whether the maximum number of iterations has already been performed. If the maximum number of iterations has already been exhausted, at error termination stage 160, the method ends without successfully decoding the data.

  Otherwise, in the feedback adaptation stage 156, the ECC decoder adapts the decoding process. For example, the ECC decoder can mark the LLR value that produced the minimum error probability. Unit 60 then uses this information to mark the target sample with the lowest error probability. Alternatively, the decoder may mark the bits with a low confidence level as “erase points” and update the erasure mark with the result of the decoding process. As a further alternative, other techniques that use ECC decoder feedback to adjust or update the decoding process can also be used. The method then loops back to the upper distortion estimation stage 132, where unit 60 re-estimates the distortion based on the provided feedback.

  The MSP 52 uses a certain set of voltage thresholds when decoding data in the decoding stage 140 above. In some embodiments, if an error is detected in the success check stage 144 above, unit 60 changes the decoding process by adjusting the threshold to improve decoding performance. Unit 60 may use any suitable method of adjusting the threshold. For example, unit 60 may perform a gradient search, where the threshold is increased or decreased depending on whether error performance improves or decreases. Alternatively, the threshold can be adjusted to minimize the number of required read operations. Additional threshold adaptation methods that can be used to adjust the decision threshold are described in the above-mentioned US Provisional Patent Application No. 60/894290.

  It should be noted that in some cases adjusting the decision threshold includes rereading the cell voltage. For example, if the cell threshold voltage is read by applying various voltages to the word line as described above, the cell is reread using the changed decision threshold. If the cell is read using a high resolution ADC, cell re-reading is usually not necessary.

  In some embodiments, unit 60 may select a threshold for each cell to match the distortion characteristics of each individual cell. Possible thresholds can be predetermined or adjusted in an adaptive manner. For example, a group of cells may have the code TH1. . . Assume that it is read in three decoding iterations using three predetermined sets of thresholds denoted TH3. In this example, the following table tabulates the bit sequence that results from the three decoding iterations.

シーケンス中の各ビットについて、３つの閾値セットの１つは最も低い歪みレベルを生じた。各ビットの最良閾値セットは次の表によって与えられる。

For each bit in the sequence, one of the three threshold sets yielded the lowest distortion level. The best threshold set for each bit is given by the following table.

ユニット６０は、シーケンス中の各ビットについて、最良閾値セットを用いた復号結果を選択する。このようにして、決定結果は次の表によって与えられる。

Unit 60 selects a decoding result using the best threshold set for each bit in the sequence. In this way, the decision result is given by the following table.

代替実施形態では、ユニット６０はＥＣＣ復号前に閾値をセルごとに選択する。これらの実施形態では、セルはＥＣＣ復号に先立って複数の所定セットの閾値を用いて読み取られる。次に、各セルについて、閾値の最良セットがこのセルの推定歪みに従って使用される。最良閾値セットはＥＣＣ復号器への入力を生成するために各セルに対して適用される。

In an alternative embodiment, unit 60 selects a threshold for each cell before ECC decoding. In these embodiments, the cells are read using a plurality of predetermined sets of thresholds prior to ECC decoding. Next, for each cell, the best set of thresholds is used according to the estimated distortion of this cell. The best threshold set is applied to each cell to generate an input to the ECC decoder.

  Alternatively, in order to select a value decoded using the best threshold, unit 60 may combine data values read at different iterations using different thresholds. For example, unit 60 may perform a majority vote on bit values decoded in various iterations.

  As a further alternative, unit 60 can read the voltage from the cell using different thresholds and combine the readings from different iterations before decoding the ECC. In other words, for each cell, unit 60 can read the cell voltage using various thresholds and generate ECC decoding metrics (eg, LLR) based on the multiple read voltages. The ECC is then decoded using the metrics. In some embodiments, the cells are iteratively read using various thresholds until ECC decoding is successful. At each iteration, the cell is read using various thresholds. Decoding metrics are calculated or updated based on the voltage read from the cell at various iterations. The process continues until the ECC is successfully decoded.

  Although the above description refers to rereading cells cell by cell at various thresholds, a single set of thresholds can be used for the entire page.

  In some embodiments, the MSP 52 comprises two or more different decoders with increased performance. Higher performance decoders typically have higher complexity, use more power, and generate greater processing delay than simpler decoders. Initially, the MSP decodes the page using the least complex decoder and returns to a higher performance decoder only when a decoding error is detected. Using this method, high performance and complex decoders are activated only when needed, thus reducing average power consumption and processing delay.

  For example, the MSP first attempts to decode the data without any ECC decoding and returns to using the ECC decoder when an error is detected. This technique may be used, for example, if the ECC scheme used by the MSP comprises a systematic code, ie a code that adds separate redundant bits without changing unencoded information bits. As another example, a simpler decoder may comprise a hardware-implemented hard decision Reed-Solomon (RS) decoder, this input comprising a cell-by-cell decision without memory. A higher performance decoder may include a soft decision RS decoder, which is implemented in software and uses high resolution sampling of the cell voltage.

  Another possibility to change the decoding process based on the feedback provided by the ECC decoder is to change the resolution at which the voltage level is read. The resolution can be changed, for example, by iteratively changing the threshold voltage used to digitize the voltage read from the memory cell until successful decoding is achieved. As noted above, in some embodiments, potentially disturbing cell voltages and disturbed cell voltages are read at various resolutions. In such cases, the reading resolution of potentially disturbing cells, disturbed cells, or both can be adapted.

Suitable Distortion Approximation Method The signal processing unit 60 of the MSP 52 can use any suitable method for estimating the distortion contained in the voltage read from the memory cell 32. Several exemplary methods are described in the above-mentioned US Provisional Patent Applications 60/747106 and 60/885024. Alternatively, other suitable distortion estimation methods can be used.

  FIG. 6 is a flow diagram that schematically illustrates a method for estimating distortion of memory cell array 28, in accordance with an embodiment of the present invention. The methods described below may be used by the distortion estimation module 112, for example, in the distortion estimation stage 132 of the method of FIG. This method uses the fact that the distortion due to cells programmed prior to the target cell may differ from the distortion due to cells programmed after the target cell.

  Another assumption is that the array was programmed using a program and test (P & V) process, as is well known in the art. The P & V process is described, for example, in Non-Patent Document 8 and Non-Patent Document 9, both of which are incorporated herein by reference.

  In some known P & V processes, each cell of a page has the code 0. . . Programmed to one of the M voltage levels denoted M-1, where level 0 is the erase level. The P & V process programs a page with M phases. In phase i, a series of voltage pulses are applied to the cell and this programmed level must be greater than or equal to i. After each pulse, the process reads the voltage of the various cells and stops applying the pulse to the cell that has reached the desired level.

  The method begins at a voltage reading stage 170 with an MSP 52 that accepts the sampled voltage read from the cells 28 of the array 32. The voltage includes both the voltage of the target cell and the voltage of the cell that potentially causes interference to the target cell. In this example, the pages of array 28 are read in order, ie row by row, although other read settings may be used.

  For a given target cell, at the classification stage 174, potentially disturbing cells are classified by the time of programming. The subset of cells 32, indicated by D1, includes potentially disturbing cells that were not yet fully programmed by the P & V process when the target cell was programmed. The class D1 cell was at the erase level when the target cell was programmed, but may have been programmed since then.

  In some programming schemes, the cell is programmed in several stages. For example, in some 4-level cell programming methods, the least significant bit (LSB) and the most significant bit (MSB) are written in two separate stages. Exemplary methods are described in the literature by Takeuchi et al. In such a method, the cell may be programmed to an intermediate level at some point, and future programming steps bring the cell to its final programmed value. When such a programming method is used, class D1 is the cell that was at the erase level or the intermediate programming level when the target cell was programmed, but has since been programmed to its final value. Enlarged to include.

  Another subset of cells 32, denoted by D2, includes potentially disturbing cells that were already programmed when the target cell was programmed. Since there was already a disturbance from this cell to the target cell when the target cell was programmed, the P & V process has already corrected this disturbance at least partially. However, the P & V algorithm was not applied to this case except when the target cell was erased. A third class of cells, indicated by the symbol D3, includes potentially disturbing cells that are programmed at the same time as the target cell, eg, cells on the same page as the target cell.

The signal processing unit 60 estimates the distortion for the target cell due to various classes of potentially disturbing cells in a class-based distortion estimation stage 178. Let n and m denote the number of rows and columns of target cells in the array 28, respectively. x _{n, m} indicates the voltage of the target cell after the target cell has been written using the P & V process. x _{i, j} indicates the voltage of the cell located in row i and column j when the target cell is programmed. y _{n, m} represents the cell voltage value read from the target cell, which differs from x _{n, m} due to distortion. Similarly, y _{i, j} represents the cell voltage value read from the target cell, which differs from x _{i, j} due to distortion.
The set distortion included in yn _{, m} can be estimated as follows:

ここで、ｈ_{ｎ，ｍ，ｉ，ｊ}は行ｉおよび列ｊの妨害するセルから行ｎおよび列ｍの目標セルへの相互結合妨害係数を示す。ｂは一定のバイアス項を示す。

Here, h _{n, m, i, j} represents the mutual coupling interference coefficient from the disturbing cell in row i and column j to the target cell in row n and column m. b represents a constant bias term.

  Class D1 cells include cells that are programmed after the target cell is programmed. Therefore, the disturbance due to this cell was not present at that time and the P & V process may not have compensated for this distortion.

The class D2 cell was already programmed when the target cell was programmed, and the distortion due to this cell was already present when the P & V process programmed the target cell. Thus, when the target cell was programmed, the P & V process had already (at least partially) compensated for this distortion. Note that class D2 is empty when the target cell is erased because in this case it is not processed by the P & V algorithm and the distortion from the previously programmed cell was not compensated. is there. Nevertheless, this compensation was correct when the target cell was programmed and does not take into account aging or other effects that occurred between the time the target cell was read. The second term x _i , _{j in} equation [10] is an estimate of the voltage, which was present in the disturbing cell when the target cell was programmed.

  It should be noted that the first and second terms of Equation [10] are different from each other due to disturbing cell voltage changes between programming and reading, and class D1 cells for voltage changes are added. While due to programming, class D2 cells for change are due to distortion.

In some embodiments, (Equation) can be estimated by applying ECC decoding to the output of these cells. ECC can help to correct serious errors, eg, errors due to severe leakage, by restoring a set of bits written to a cell. Alternatively, y _{i, j} −x _{i, j} in the second term of equation [10] is a function without memory of y _{i, j} , for example _, α · which estimates a leakage error for a cell whose voltage level is y _{i, j.} It can be estimated using y _{i, j} . Alternatively, y _{i, j} −x _{i, j} can be approximated by the average expected leakage from the cell.

  The third term of the above equation [10], which refers to a class D3 cell, assumes the use of a P & V process, and the P & V process inherently suffers from distortion due to a D3 cell being programmed to a level equal to or less than the target cell. Compensate. If a potentially disturbing cell on the same page as the target cell is programmed to a higher level, this programming is performed in a later pass after the P & V process after the target cell has already been fully programmed. Thus, a significant portion of the distortion due to the D3 cell having a higher level than the target cell does not exist when the target cell is programmed, and the P & V process cannot compensate for this portion of distortion.

In some cases, the number of P & V pulses used to program a cell can vary depending on the per cell tolerance of the P & V process and various read and write errors. As a result, some cells may be faster to write from others, even at the same voltage level. If the target cell is faster to program than a disturbing cell, the interference from this cell is not correctly compensated by the P & V process.
In some embodiments, equation [10] above can be modified to compensate for this difference. The third term of equation [10] can be written as:

ここで、

here,

式［１２］で、ｘ_ｎ，_ｍは、例えば、上述のＥＣＣ復号プロセスを用いることによるｘ_ｎ，_ｍの抽出値を示す。Δは目標セルが妨害するセルよりもプログラムするのが速かった事実を補償する因子を示す。

In Expression [12], x _n , _m represents an extracted value of x _n , _m by using the above ECC decoding process, for example. Δ represents a factor that compensates for the fact that the target cell was faster to program than the disturbing cell.

  Equation [10] assumes that distortion depends only on the disturbing cell voltage change and not on the disturbing cell voltage. Equation [10] also assumes that the distortion is linear, i.e., can be modeled as a constant multiplied by the disturbing cell voltage change. In some practical scenarios, however, these two assumptions may not apply. Specifically, in some cases, interference from a disturbing cell to a disturbed cell depends on both the disturbing cell voltage and the disturbed cell voltage. In some cases, equation [10] can be generally rewritten as:

ここで、ｆ（ｔ_ｉ，ｔ_ｆ，ｒ）は電圧が、ｔ_ｉからｔ_ｆへ変化する妨害するセルに起因する、電圧レベルがｒである妨害されるセルに対する歪みを示す。

Here, f (t _i , t _f , r) represents the distortion for the disturbed cell whose voltage level is r due to the disturbing cell whose voltage changes from t _i to t _f .

  In some cases, for example, when the cell voltage is affected by back pattern dependency (BPD), the disturbing cell is located along the same cell string or bit line as the disturbed cell, and the distortion to a cell Depends on the voltage of the cell located above it along the bit line.

In some cases, unit 60 may predict the distortion of a particular cell from known or previously estimated distortion values of other cells. For example, cells that are located close to each other in the array may have similar or correlated distortion levels. As another example, cells sharing the same power supply (V _CC ) circuit may have similar distortions if some of the distortion is due to or propagates through the supply voltage.

In some embodiments, unit 60 corrects the ECC metrics to be responsive to distortion due to gain and bias errors in the sense amplifier. When a memory cell is read, the sense amplifier converts the current flowing through the cell into a voltage. Therefore, the voltage at the sense amplifier output must satisfy v = k _SA i, where v indicates the output voltage, i indicates the cell current, and k _SA indicates the gain of the amplifier, which is Is assumed to be constant. In many practical cases, however, the gain of the amplifier is not constant. Amplifiers can also cause bias errors. Thus, the output voltage of the sense amplifier can be expressed as v = (k _SA + Δ _SA ) i + B _SA , where k _SA is constant, Δ _SA indicates a gain error, and B _SA indicates a bias error. Show. Δ _SA and B _SA can vary from one sense amplifier to another (ie, from one bit line to another).

In some embodiments, unit 60 estimates the values of Δ _SA and B _SA and changes the ECC metrics based on the estimated sense amplifier parameters. For example, the LLR calculation of the above equations [4] and [5] can be performed by changing and scaling the read voltage r of equation [4] or the interval boundaries V _a and V _b of equation [5]. _SA and B may be changed to account for _SA values.

For example, the read voltage r in equation [4] can be replaced with r ₀ , which is defined as r ₀ = (r−B _SA ) · k _SA / (k _SA + Δ _SA ).

  Although the exemplary method of FIG. 6 refers to a particular P & V process implementation, this method may be used with other suitable P & V processes, with changes where it should be changed. Adaptation of the method for use in other types of P & V processes based on the disclosed embodiments will be apparent to those skilled in the art.

  In many known devices, one of the nominal voltage levels is defined as the “erase” level. In some known data storage methods and devices, cells at the erase level do not participate in the P & V process. Therefore, these cells can suffer from mutual coupling interference from neighboring cells that are not corrected by the P & V process. This disturbance expands the erase level voltage distribution toward the level immediately above and increases the required margin. In many NAND flash cells, the erase level has a negative voltage while the other levels have a positive voltage. With such known devices, it is often impossible to read a negative voltage, and therefore it is impossible to read the exact voltage of the erased cell to correct the disturbance. In some embodiments, if the MSP 52 detects that a memory cell has a slightly positive voltage level and measures that the distortion level of the cell is high, the MSP is an erase cell. Yes, the voltage is judged to be positive by mistake due to distortion. The MSP can compensate for such cell distortions to reduce the required margin.

  In an NROM flash cell, the erase cell voltage level is usually positive and can therefore be read. Although the mutual coupling between the two sides of the NROM cell is usually compensated by the P & V process, the distortion is not compensated when one or both sides of the cell are erased. In such a case, the MSP 52 can compensate for the distortion and reduce the required margin even if one or both sides of the cell are erased.

  Although the embodiments described herein primarily address the stage of retrieving data from a multi-level cell (MLC), the principles of the present invention can also be used in a single-level cell (SLC). Although the embodiments described herein primarily address the stage of retrieving data from a solid state memory device, the principles of the present invention provide data for hard disk drives (HDDs) and other storage media and devices. It can also be used to store and retrieve.

  Accordingly, it will be appreciated that the embodiments described above are referred to by way of example, and that the invention is not limited to what has been particularly shown and described above. Rather, the scope of the present invention is not limited to the various features described above, and combinations and sub-combinations of modifications and variations that will occur to those skilled in the art upon reading the previous description and are not disclosed in the prior art. Includes both combinations.

FIG. 2 is a block diagram schematically illustrating an apparatus for memory signal processing according to an embodiment of the present invention. FIG. 3 schematically illustrates a memory cell array in accordance with an embodiment of the present invention. 3 is a graph illustrating a voltage distribution of a memory cell array according to an embodiment of the present invention. FIG. 4 is a functional block diagram that schematically illustrates a process for retrieving data from a memory cell array, in accordance with an embodiment of the present invention. 3 is a flow diagram that schematically illustrates a method for retrieving data from a memory cell array, in accordance with an embodiment of the present invention. 4 is a flow chart that schematically illustrates a method for estimating memory cell array distortion, in accordance with an embodiment of the present invention.

Explanation of symbols

20 device 24 memory element 28 memory cell array 32 analog memory cell 36 data buffer 40 read / write unit 48 control logic 52 memory signal processor 56 input / output buffer 60 signal processing unit 64 encoder / decoder 72 data Buffer 76 controller

Claims (42)

A method of operating one memory device, comprising:
A step of encoding, and stored in each of the analog memory cells in the memory device the encoded data as the first analog value using one error correction symbol (ECC) data,
After storing the encoded data, a step of reading the second analog value from each of the memory cells of the memory device in which the encoded data is stored,
At least some of said second analog value in this case, unlike the each of the first analog value,
Estimating a single distortion contained in said second analog value,
Calculating an error correction value with respect to said second analog value in response to the estimated distortion,
To reconstruct the data, processing the second analog value using the error correction value in one ECC decoding process,
A method characterized by comprising : Calculating the error correction value,
For each of the memory cells, and evaluating the one or more cells parameter indicating the distortion,
Calculating the error correction value in response to said cell parameter,
The method of claim 1, which comprises a. The cell parameter is, the analog value read from other memory cells, the other estimated cross-coupling coefficient of the memory cell, one of the statistical distribution of the parameters of the second analog value the read, the memory cell There number of programming and erase cycles undergone prior slave, the elapsed time from after the slave prior to programming and erase cycles, the detected memory cells was the previous error, the one in which memory cells are connected to word lines one identifier of said one identifier of one bit line of the memory cells are connected, one estimated parameter of one sense amplifier coupled to the bit line in which the memory cells are connected, and is selected from a group of parameters consisting of one environment parameter, claims, characterized in that it comprises at least one parameter The method according to. Processing the second analog value,
Dividing one range of possible values of the second analog value into a plurality of decision interval,
Anda determining each of the determined intervals the second analog value falls,
Calculating the error correction value,
To improve the performance of the ECC decoding process, comprising the step of defining a single function to be chosen for the second analog value to the decision interval,
The method according to claim 1. Processing the second analog value,
Receiving a feedback on one of the performance of the ECC decoding process,
A step of changing the ECC decoding process in response to said feedback,
The method of claim 1, which comprises a. Wherein the step of processing the second analog value, comprising the step of comparing the determining threshold value the second analog value, the step of changing the ECC decoding process, comprising the step of changing the determination threshold value the method according to any one of claims 1 to 5. The step of changing the determination threshold value A method according to claim 6 with a decision threshold that the changed, characterized in that it comprises a re-reading step the second analog value from the memory cell. Comparing said second analog value and the decision threshold comprises a step of reading the second analog value of the memory element using the determined threshold value, change the step of changing the decision threshold is the threshold the method of claim 6 including a one step that sent to the memory device a command, it is characterized in that. Processing the second analog value,
Using different sets of said decision thresholds, by repeating several times the ECC decoding process, respectively, and generating an estimate of a multiple of the data stored in each memory cell,
A step of reconstructing the data in response to the estimated value of the multiple of the data,
The method according to claim 6, characterized in that it comprises a. The method of claim 9 the step of reconstructing the data, characterized in that it comprises the step of selecting independently one of the estimates of the multi against each of the memory cells. Processing the second analog value, comprising the step of applying one of the first ECC decoding process with one first error performance,
Receiving the feedback comprises the step of receiving one display of decoding error in the data decoded using the first ECC decoding process,
Altering the ECC decoding process, processing the second analog value with a single second ECC decoding process with the first one second error performance performance is better than error performance the method of claim 5 including the step, characterized by. It said step of changing the ECC decoding process, method according to claim 5, characterized in that it comprises a step of changing one of the sampling resolution used to read the second analog value. The step of reading the second analog value,
Includes a step of reading multiple instances of the second analog value with a respective different sets of said decision threshold,
Calculating the error correction value,
And combining the instances of each of said multi against the memory cell independently,
A step of based on said combination has been multiplexed instance, calculating the error correction value,
The method according to claim 1, comprising: Reading the plurality of instances of the second analog value, combining step,
A step that can be repeated an additional instance of the second analog value,
And updating the error correction value by using the up successfully ECC decoding, the additional instances,
The method of claim 13, which comprises a. For each of the memory cell, the step of estimating the distortion,
The read from the memory cell might contribute to the strain in the second analog value, from the memory cell having one sub-set of potential interference includes the step of reading the second analog value,
Calculating the error correction value comprises the step of evaluating the distortion contributed by the memory cell having the possibility of interference,
A method according to any one of claims 1 to 5 , characterized in that The step of evaluating the distortion applied to the memory cell due to the contribution of the memory cell having the possibility of interference is read from said second analog value and the memory cell read from the memory cell having the possibility of interference the method of claim 15, wherein the second based on both analog value, characterized in that due to the contribution of each of the memory cells comprises a step of approximating the distortion having a potential interference was. Processing the second analog value,
Processing the second analog value of the memory cell in one of a first quantization level,
A step of the second analog value read from the memory cell, is treated with the first one of the second quantization level coarser than the quantizing level having the possibility of interference,
The method according to claim 15, comprising: Processing the second analog value,
By changing iteratively the one threshold value of one circuit that are used to read the second analog value, the step of reading the second analog value at the first and second quantization levels Including,
The method according to claim 17, wherein: Storing the encoded data,
Comprising the step of writing the first analog value to the memory cell using a single program and verify (P & V) process,
The step of estimating the distortion,
The P & V process is fully programmed earlier than the one memory cell, fully programmed memory cell later than the one memory cell, and completely programmed simultaneously with the one memory cell. at least two categories selected from the class of a group consisting of memory cells, comprising the steps of classifying the memory cells having a plurality of said interference potential,
Calculating separately sum of distortion within each of said classes,
The method according to claim 1, comprising: The method according to any one of claims 1 to 5, characterized in that said memory cell is formed of a flash memory cell. The method according to any one of claims 1 to 5, wherein the memory cell is characterized in that it consists of dynamic random access memory (DRAM) cell. The method according to any one of claims 1 to 5, wherein the memory cell is characterized by comprising the phase change memory (PCM) cell. The method according to any one of claims 1 to 5, characterized in that said memory cell is a nitride read only memory (NROM) cell. 6. The method according to claim 1, wherein the memory cell comprises a magnetic RAM (MRAM) cell. 6. The method according to claim 1, wherein the memory cell comprises a ferroelectric RAM (FRAM) cell. The method according to claim 1, wherein the ECC comprises one block code. The method of claim 26, wherein the block code is characterized by comprising a single BCH code or one Reed-Solomon (RS) code. The method according to claim 26, characterized in that from one of said block codes are one low-density parity check (LDPC) codes, one turbo codes, and one turbo product code (TPC) . The method of claim 28, wherein the ECC decoding process is characterized in that it consists of one iterative decoding process. The ECC decoding process, the method according to any one of claims 1-5, characterized by using feedback generated by reading the second analog value. The method according to claim 1, wherein the ECC decoding process comprises a maximum likelihood sequence estimation (MLSE) process. The ECC is one conventional code, one trellis coded modulation (TCM) codes, and characterized in that from one of the one-bit Interleaved Coded Modulation (BICM) code, and one of the connecting cord the method according to any one of claims 1 to 5. The method according to claim 1, wherein the error correction value comprises a likelihood ratio (LR). The method according to claim 1, wherein the error correction value comprises a log likelihood ratio (LLR). Estimating the distortion of the preceding claims, characterized in that it comprises a step of predicting, based on the distortion contained the distortion contained in one of the memory cells to another of the plurality of memory cells The method according to any one of the above. The memory cell is disposed in a memory cell having a plurality of isolated group interference possibilities ;
Estimating the distortion of each group comprises the step of evaluating one of the inverse matrix of the one cross-coupling matrix representing the mutual interference between pairs of said memory cells in said group,
Calculating the error correction value, the applied to the first analog value, and the inverse matrix of the cross-coupling matrix which is the sum respective average distortion level of said memory cells in said group, said second in comprising the step of calculating one of the distance between the inverse of the applied the cross-coupling matrix into an analog value,
A method according to any one of claims 1 to 5 , characterized in that The plurality of isolated groups are each composed of a nitride read only memory (NROM) cell , and the memory cells having the possibility of interference in each group are composed of first and second charge storage regions of the respective NROM cell. the method of claim 36, characterized in that. The memory cell is disposed in a memory cell having a plurality of isolated group interference possibilities ;
Estimating the distortion of each group is, one cross cup representing the mutual interference between each of the one vector of average distortion level of memory cells, and said memory cells in said group pairs within the groups comprising the step of evaluating the ring matrix,
Calculating the error correction value, and one vector of the said second analog value read from the memory cells in said group, said one of the cross-coupling matrix and the vector of the average level of distortion in response to one of the difference component of the product comprises the step of calculating said value,
A method according to any one of claims 1 to 5 , characterized in that A plurality of group receiving the isolated, respectively consist nitride read only memory (NROM) cell,
The method of claim 38, the memory cell having the possibility of interference in each group, respectively comprising first and second charge storage regions of the NROM cell, and wherein the. Storing the encoded data,
A step of scrambling the encoded data,
Comprises the steps of storing the scrambled data,
Processing the second analog value,
Comprising the step of descrambling the second analog value read from the memory cell,
A method according to any one of claims 1 to 5 , characterized in that Storing the data,
Wherein the step of maintaining at least some of the memory cells to one erased level,
The step of reading the second analog value, the step of estimating the distortion, the step of calculating the error correction value, and processing the second analog value,
Read from the memory cell which has been maintained in the erased level, comprising the step of compensating for the distortion of the second analog value,
A method according to any one of claims 1 to 5 , characterized in that Coded using one error correction symbols (ECC), a device for acquiring the data stored in each of the analog memory cells of a memory device as the first analog value,
From the analog memory cell of said memory device, wherein the encoded data is stored, and one reading unit configured to read the second analog value, respectively,
At least some of said second analog value wherein the Unlike each of the first analog value,
And one signal processing unit configured to calculate an error correction value with respect to said second estimate one distortion contained in the analog value, the response to the estimated distortion second analog value,
Decoding the ECC, to reconstruct the data, and one decoder configured to process the second analog value using the error correction value,
A device characterized by comprising .

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