JP4998347B2 - How to create a mask pattern - Google Patents

Description

  The present invention relates to a mask pattern creating method, and more particularly to a mask pattern creating method used when semiconductor devices such as transistors are regularly formed in large quantities on a wafer.

In recent years, a technique for predicting the completion of a semiconductor device by exposure simulation and pointing out and correcting defects at the design stage has become widespread.
This technology evaluates for each semiconductor device whether the size of the semiconductor device on the semiconductor substrate (wafer) is within a certain range when compared to the mask pattern design data (design mask pattern). Was.

  Note that a method using a simulation-based OPC (Optical Proximity Correction) (see, for example, Patent Document 1), and comparing the calculation results of the Fourier transform of the pattern formed on the mask and the design mask pattern, respectively, can be used. A technique for inspecting defects (for example, see Patent Document 2) is known.

  By the way, in an SRAM (Static Random Access Memory) or the like, a large number of transistors and via holes are regularly arranged on an LSI (Large Scale Integrated circuit) chip (hereinafter simply referred to as a chip). When such a device pattern of a semiconductor device is transferred in large quantities on the wafer at an equal pitch in the exposure process, the shape of the device pattern on the peripheral side (device shape) is affected by the optical influence of another device pattern, and is centered. There is a problem that manufacturing variation occurs due to a difference from the side device shape.

FIG. 11 is a diagram illustrating an example of manufacturing variation in device shape.
Here, a case where a device pattern of a MOSFET (Metal-Oxide Semiconductor Field Effect Transistor) is formed is shown.

When the transferred device patterns 51a and 51b are compared with the design mask pattern 50 that defines the gate shape, the device pattern 51b has a thicker gate and a smaller protrusion to the diffusion layers 52a and 52b than the device pattern 51a. As the gate becomes thicker, the resistance increases and the switching voltage of the MOSFET increases. In addition, when the gate protrusion is small, the channel region is insufficient and a leakage current is generated. When such manufacturing variations occur, a large operating voltage may be required.
JP-A-9-34095 International Publication No. 2004/088417 Pamphlet

In the prior art, evaluation of individual semiconductor devices has been performed, but it has not been possible to predict how much manufacturing variation will occur in the device shape on the wafer.
In view of the above points, the present inventor aims to provide a mask pattern creation method capable of predicting the degree of manufacturing variation at the design stage and correcting the design mask pattern.

  In order to achieve the above object, a mask pattern forming method including the following steps is provided. This mask pattern creating method includes extracting a design mask pattern for forming a device pattern to be repeatedly arranged on a semiconductor substrate from mask layout data of a semiconductor device to be manufactured, A plurality of provisional arrangements up to a range that affects the shape of the central design mask pattern due to interference, a step of performing a first exposure simulation using the provisionally arranged design mask pattern, and the design mask pattern, A step of obtaining a first difference from a first exposure simulation result of the central design mask pattern, a step of performing a second exposure simulation using the design mask pattern after chip layout, and the design mask pattern Second of the design mask pattern after the chip layout A step of obtaining a second difference from an exposure simulation result, a step of comparing the first difference and the second difference, and correcting the design mask pattern based on predicted manufacturing variation. Have.

  It is possible to predict manufacturing variations of semiconductor devices in the entire wafer. If the manufacturing variation is excessive, the design can be changed to suppress the manufacturing variation.

Hereinafter, the present embodiment will be described in detail with reference to the drawings.
FIG. 1 is a flowchart showing an outline of a mask pattern creation method according to the present embodiment.
FIG. 2 is a diagram showing a specific hard wafer configuration for realizing the mask pattern creating method of the present embodiment.

  The mask pattern creation method of the present embodiment is realized by a computer 1 as shown in FIG. 2, for example. A computer 1 includes a central processing unit (CPU) 2, a read only memory (ROM) 3, a random access memory (RAM) 4, a hard disk drive (HDD) 5, a graphic processing unit 6, an input I / F (Interface) 7, The communication I / F 8 and the like are connected to each other via a bus 9.

Here, the CPU 2 controls each unit in accordance with the program stored in the ROM 3 and the HDD 5 and various data, and performs each process of the mask pattern creation method described below.
The ROM 3 stores basic programs and data executed by the CPU 2.

The RAM 4 stores programs being executed by the CPU 2 and data being calculated.
The HDD 5 stores an OS (Operation System) executed by the CPU 2, a program for performing mask pattern creation processing, various application programs, and various data.

  For example, a display 6a is connected to the graphic processing unit 6 as a display device, and mask layout data, an exposure simulation result, a manufacturing variation evaluation result, etc., which will be described later, are displayed on the display 6a in accordance with a drawing command from the CPU 2. indicate.

  An input device such as a mouse 7 a and a keyboard 7 b is connected to the input I / F 7, receives information input by the mask pattern designer, and transmits it to the CPU 2 via the bus 9.

  The communication I / F 8 is connected to a network 8a such as a LAN (Local Area Network), a WAN (Wide Area Network), or the Internet in a company, and transmits and receives various data.

Hereinafter, a mask pattern creation method using such hardware will be described with reference to FIG.
First, for example, in response to a user input, the CPU 2 creates mask layout data corresponding to the LSI to be manufactured (step S1). Next, the CPU 2 extracts design mask patterns to be repeatedly arranged from the mask layout data (step S2).

FIG. 3 is a diagram illustrating an example of a design mask pattern repeatedly arranged and a cell arrangement example.
Here, a design mask pattern 10 used when forming a MOSFET is shown. For example, when manufacturing an SRAM, the design mask pattern 10 is transferred onto a wafer using a mask in which the design mask pattern 10 is repeatedly arranged at a constant pitch, and a cell arrangement as shown in the figure is obtained. At the time of transfer, the device pattern 11 formed on the wafer has a shape different from that of the design mask pattern 10 due to the influence of light interference during transfer of the adjacent design mask pattern 10 and other cells. .

  Next, the CPU 2 repeats the same design mask pattern 10 to be repeatedly arranged at the same pitch up to a range (for example, a range of about several μm) that affects the central design mask pattern 10 due to light interference during exposure. A plurality of temporary arrangements are made (step S3). An exposure simulation program is executed to perform exposure simulation (step S4).

FIG. 4 is a diagram showing an exposure simulation result after provisional arrangement.
As shown in the figure, a plurality of device patterns 11a are obtained as an exposure simulation result. Next, the CPU 2 calculates a difference between the central one of the device patterns 11a as a result of the exposure simulation and the design mask pattern 10 as a reference difference (step S5).

FIG. 5 is a diagram illustrating how the reference difference is obtained.
By obtaining the difference between the design mask pattern 10 and the central device pattern 11a of the exposure simulation result after the temporary arrangement as shown in FIG. 4, a difference graphic 12 as shown in the figure is obtained. Such a deviation from the design mask pattern 10 caused by the influence of light when only the device pattern 11a having the same shape is arranged is set as a reference difference.

Next, the CPU 2 performs chip layout according to the layout data (step S6), and again performs exposure simulation (step S7).
FIG. 6 is a diagram illustrating an example of an exposure simulation result after chip layout.

  As shown in the figure, other cells 22, 23, 24, 25 are arranged adjacent to the cells 20, 21 where the device pattern 11b is arranged repeatedly. In the other cells 22 to 25, for example, a wiring pattern or the like is formed.

Thereafter, the CPU 2 obtains a difference between the device pattern 11b as a result of the exposure simulation after the chip layout and the design mask pattern 10 (step S8).
The device pattern 11b obtained by the exposure simulation after the chip layout is affected by light interference when transferring the patterns of other peripheral cells 22 to 25 as shown in FIG. A shift different from the case where only a plurality of device patterns 11a are arranged occurs. This leads to manufacturing variations. A similar shift occurs when there are no cells in the periphery.

  Therefore, the CPU 2 evaluates the manufacturing variation predicted by comparing the reference difference obtained in step S5 with the difference after chip layout (step S9). Then, the CPU 2 determines whether the predicted manufacturing variation is within the allowable range (step S10), and if it is within the allowable range, the creation of the design mask pattern 10 is terminated. If the allowable range is exceeded, the design mask pattern 10 is corrected in accordance with the predicted manufacturing variation (step S11), and the processes from step S2 are repeated.

  According to the process as described above, it is possible to predict the manufacturing variation of the semiconductor device in the whole wafer, not the evaluation of each semiconductor device. Further, if the predicted manufacturing variation is excessive, the design can be changed to suppress the manufacturing variation.

Details of the manufacturing variation evaluation will be described below.
FIG. 7 is a flowchart showing a flow of manufacturing variation evaluation.
An evaluation area is set in the design mask pattern 10 in order to compare the difference between the device pattern 11b after the chip layout and the design mask pattern 10 and the reference difference.

  First, the CPU 2 determines the evaluation area size (step S20). The evaluation region size is, for example, 45 to 90 nm square depending on the transistor dimensions. For example, in the case of 65 nm technology, a square having a size of 65 nm square is set as the evaluation region, and in the case of 45 nm technology, a square having a size of 45 nm square is set as the evaluation region. A square having a size smaller than that may be used as the evaluation area.

  Next, the CPU 2 sets the evaluation area having the size set in the process of step S20 at the vertex portion of the design mask pattern 10 (step S21), and then sets the evaluation area on the side (non-vertex portion). (Step S22). Note that the size of the evaluation area on the side may be the same as the evaluation area of the vertex portion, but may be made larger.

FIG. 8 is a diagram illustrating an example of an evaluation area set in a device pattern.
Here, an evaluation region 30 set for the design mask pattern 10 and a difference graphic 31 between the device pattern 11b and the design mask pattern 10 based on the exposure simulation result after chip layout are shown.

Next, the CPU 2 sets an allowable range of the area difference between the actual difference (difference graphic 31 in FIG. 8) and the reference difference (difference graphic 12 in FIG. 4) in each evaluation region 30 (step S23).
For example, 2% in the evaluation area 30 of the apex portion and 1% or less on the side may be separately input by the user in the simulation computer 1 as shown in FIG. Similarly, the processing in steps S20 to S22 may be external input by the user.

  Next, the CPU 2 compares the areas of the actual difference and the reference difference in the same evaluation region 30 (step S24), and determines whether or not the tolerance is set in the process of step S23 (step S25). ). If it is within the permissible range, the process is terminated. If the permissible range is exceeded, the evaluation region 30 that is equal to or greater than the permissible range is extracted (step S26).

FIG. 9 is a diagram showing the extracted evaluation areas.
The state where the evaluation region 30 having an area difference exceeding the allowable range is extracted is shown.
By making a comparison based on the area difference, it is possible to evaluate manufacturing variations that are easily predicted.

  For example, the CPU 2 displays the extracted evaluation area 30 on the display 6a, and the user refers to the extracted evaluation area 30 and corrects the design mask pattern 10 (step S27).

FIG. 10 is a diagram illustrating a modification example of the design mask pattern.
Based on the evaluation region 30 extracted in the process of step S26, for example, as shown in FIG. 10A, the distance between the design mask patterns 10a and 10b is increased, or as shown in FIG. 10B. The shape of the mask pattern 10b is corrected.

  Thereafter, by repeating the process from step S2 in FIG. 1 using the mask layout data updated by correcting the design mask pattern, a device pattern 11b with less manufacturing variation when formed on the wafer is formed. Such mask layout data can be created.

  In the above description, a MOSFET is taken as an example of a device pattern to be repeatedly arranged. However, the present invention is not limited to this, and for example, a device pattern of a via hole connecting each layer in a multilayer wiring board may be used.

It is a flowchart which shows the outline of the mask pattern production method of this Embodiment. It is a figure which shows the concrete hard wafer structure which implement | achieves the mask pattern production method of this Embodiment. It is a figure which shows the example of the design mask pattern arrange | positioned repeatedly, and the example of cell arrangement | positioning. It is a figure which shows the exposure simulation result after temporary arrangement | positioning. It is a figure which shows a mode that a reference | standard difference is calculated | required. It is a figure which shows an example of the exposure simulation result after chip | tip layout. It is a flowchart which shows the flow of manufacture dispersion | variation evaluation. It is a figure which shows the example of the evaluation area | region set to the device pattern. It is a figure which shows the extracted evaluation area | region. It is a figure which shows the example of correction of a design mask pattern. It is a figure which shows the example of the manufacture dispersion | variation in a device shape.

Explanation of symbols

10, 10a, 10b Design mask pattern 11, 11a, 11b Device pattern 12, 31 Difference graphic 20, 21 Cell 22, 23, 24, 25 Other cell 30 Evaluation area

Claims (5)

A step of extracting a design mask pattern for forming a device pattern to be repeatedly arranged on a semiconductor substrate from mask layout data of a semiconductor device to be manufactured;
A step of temporarily arranging a plurality of the extracted design mask patterns up to a range in which the shape of the design mask pattern at the center is affected by light interference;
Performing a first exposure simulation using the temporarily placed design mask pattern;
Obtaining a first difference between the design mask pattern and a first exposure simulation result of the central design mask pattern;
A step of performing a second exposure simulation using the design mask pattern after the chip layout;
Obtaining a second difference between the design mask pattern and a second exposure simulation result of the design mask pattern after chip layout;
Comparing the first difference with the second difference and correcting the design mask pattern based on predicted manufacturing variation;
A mask pattern creating method characterized by comprising:   The evaluation area is provided in the vertex part and the non-vertex part of the design mask pattern, and the area comparison between the first difference and the second difference is performed for each evaluation area. Mask pattern creation method.   3. The method of creating a mask pattern according to claim 2, wherein the size of the evaluation region is a size according to a transistor size.   4. The mask pattern creation method according to claim 2, wherein in the evaluation area, an evaluation criterion is set separately for the vertex portion and the non-vertex portion. 5.   The mask pattern creation method according to claim 4, wherein when the manufacturing variation exceeds the evaluation standard, a change in a distance between the design mask patterns or a shape of the design mask pattern is corrected.

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