JP4996094B2 - Semiconductor memory device and refresh method thereof - Google Patents

Description

  The present invention relates to a semiconductor memory device and a refresh method thereof, and more particularly to an improvement in a DRAM (Dynamic Random Accesses Memory) capable of inserting a refresh operation during a normal access operation and a refresh method thereof.

  Recently, replacement of SRAM (Static Random Accesses Memory) to DRAM has become popular for low power consumption applications. This is because the storage capacity per unit area is much larger in DRAM than in SRAM. However, DRAM requires refreshing that is unnecessary for SRAM. Therefore, it is desired that refresh is automatically performed by an internal circuit of the DRAM instead of an external circuit such as a refresh controller so that the DRAM can be used in exactly the same manner as the SRAM.

  In the following Patent Document 1, a normal read or write operation (hereinafter referred to as “normal access operation” or simply “access operation”) and a refresh operation are performed within one cycle time (hereinafter referred to as “external cycle time”). A DRAM employing an insertion method is disclosed. According to this method, since access time and refresh time are secured within one external cycle time, refresh can be performed at any time without waiting for normal access. Since the access time and the refresh time are substantially the same, these are hereinafter collectively referred to as “internal cycle time”.

  For this DRAM, the external cycle time is the actual cycle time and determines the operating speed. Therefore, in order to increase the speed of this DRAM, the external cycle time must be shortened. However, in order to do so, the internal cycle time must be less than half of the external cycle time, and it is not easy to shorten the external cycle time. In the first place, this DRAM has an internal cycle time for refreshing within each external cycle time so that it can be refreshed at any time. It is difficult.

JP 2002-298574 A

  A main object of the present invention is to provide a semiconductor memory device capable of inserting a refresh during normal access and capable of speeding up, and a refresh method thereof.

  A semiconductor memory device according to the present invention includes a memory cell array, refresh means, address selection means, word line selection means, and selection stop means. The memory cell array includes a plurality of word lines. The refresh means requests refresh and sequentially generates refresh addresses. The address selecting means selects an access address when access is requested, and selects a refresh address when refresh is requested. The word line selection means selects the word line in response to the address selected by the address selection means. The selection stop unit stops address selection by the address selection unit while access or refresh is being performed in the memory cell array.

  A refresh method according to the present invention comprises a step of requesting refresh and generating a refresh address sequentially, an address selection step of selecting an access address when access is requested, and selecting a refresh address when refresh is requested, A word line selecting step for selecting a word line in response to the address, and a selection stopping step for stopping the selection of the access address and the refresh address while the memory cell array is being accessed or refreshed.

  According to the present invention, an access address is selected when access is requested, a refresh address is selected when refresh is requested, and a word line is selected in response to the selected address. Therefore, refresh is inserted during normal access. In addition, the address selection is stopped while the memory cell array is accessed or refreshed. Therefore, when a refresh is requested before an access, the refresh is prioritized, and the later requested access is waited until the previous refresh is completed. Conversely, if access is requested before refresh, the access is given priority, and the later requested refresh waits until the previous access is completed. As a result, the internal cycle time can be made longer than the external cycle time, thereby shortening the external cycle time and increasing the operation speed.

  Preferably, the memory cell array is divided into a plurality of blocks. The semiconductor memory device further includes block selection means for selecting a block in response to the address selected by the address selection means. The selection stop unit stops address selection by the address selection unit while access or refresh is being performed in the block selected by the block selection unit. Meanwhile, the refresh method further includes a step of selecting a block in response to the selected address. The selection stop step stops the selection of the access address and the refresh address while access or refresh is being performed in the selected block.

  More preferably, in the semiconductor memory device, the word line selection means continuously selects all the word lines for each block in response to the refresh address. On the other hand, in the refresh method, the word line selection step continuously selects all the word lines for each block in response to the refresh address.

  In this case, since so-called burst refresh is performed in units of blocks, even if the refresh is delayed, the delay is eliminated during the operation of the block and is not carried over until the operation of another block.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals and description thereof will not be repeated.

  Referring to FIG. 1, a DRAM 10 according to an embodiment of the present invention includes 64M (= 64 × 10 <SUP> 20 </ SUP>) memory cells MC and 4K (= 4 × 2 <SUP> 10 </ SUP>) word line WL. Memory cell array 12 is divided into 16 access array blocks (hereinafter simply referred to as “blocks”) BK. Each block BK includes 256 word lines WL, 16K (= 16 × 2 <SUP> 10 </ SUP>) bit line pairs BL intersecting these word lines WL, and bit line pairs BL. And a 16K sense amplifier (not shown) connected thereto. Each memory cell MC is connected to a corresponding word line WL and bit line pair BL.

  The DRAM 10 further includes a row decoder 14 and a row decoder control circuit 16 that controls the row decoder 14. Row decoder 14 selects word line WL in response to a row address signal. Similar to the memory cell array 12, the row decoder 14 is also divided into 16 decoder blocks DB.

  FIG. 2 shows details of the row decoder control circuit 16 and one decoder block DB. Referring to FIG. 2, DRAM 10 further includes a refresh circuit 17 and an address selector 18. Refresh circuit 17 generates refresh enable signal / RE and sequentially generates refresh row address signal RRA. The address selector 18 selects the access row address signal ERA or the refresh row address signal RRA given from the outside, and gives it to the row decoder control circuit 16 as the row address signal RA. The row decoder control circuit 16 decodes the applied row address signal RA to generate row address decode signals ADU and ADL, and supplies them to the row decoder 14.

FIG. 3 shows details of the address selector 18 and the refresh circuit 17. Referring to FIG. 3, refresh circuit 17 includes a refresh timer 30, an address counter 32, and a refresh enable circuit 34. The refresh timer 30 generates a refresh timer signal / RT at a predetermined cycle. Address counter 32 counts up the refresh row address in response to refresh timer signal / RT and generates refresh row address signal RRA. The refresh enable circuit 34 generates a refresh enable signal / RE in response to the chip enable signal / CE and the refresh timer signal / RT.
Referring to FIG. 4, chip enable signal / CE is activated to L (logic low) level every external cycle time Tec. Activating the chip enable signal / CE corresponds to issuing an access command. When the chip enable signal / CE is activated, the access row address signal ERA given from the outside is taken into the address selector 18 and data is read from the memory cell MC accordingly.

  If the internal cycle time Tic required for the read or refresh operation is made half of the external cycle time Tec, the refresh operation can be surely inserted even during the read operation. If the retention time of the memory cells MC is 64 ms, in order to refresh all the memory cells MC during this period, the 4K word lines WL must be sequentially selected every 16 μs (= 64 ms ÷ 4K). Such refresh in which all the word lines WL are sequentially selected uniformly at a constant cycle is called “distributed refresh”.

  In the case of distributed refresh, refresh timer signal / RT is activated to L level at a period of 16 μs irrespective of chip enable signal / CE. When chip enable signal / CE is activated after activation of refresh timer signal / RT, refresh enable signal / RE is activated to L level. Activating the refresh enable signal / RE corresponds to issuing a refresh command. When a predetermined period elapses after activation of the refresh enable signal / RE, the refresh timer 30 is reset and the refresh timer signal / RT returns to the H (logic high) level. When the refresh enable signal / RE is activated, the refresh row address signal RRA generated by the address counter 32 is taken into the address selector 18 and the memory cell MC is refreshed accordingly.

  In this way, if the internal cycle time Tic is made half of the external cycle time Tec, the refresh command will not conflict with the access command (here, the read command), so that the refresh can be performed at any time. In this embodiment, the internal cycle time Tic is longer than half of the external cycle time Tec. As a result, even if the refresh command conflicts with the access command, the refresh operation is performed during the normal access operation by arbitrating them. It can be inserted.

  Referring back to FIG. 2, each decoder block DB includes a block enable circuit 20, a row decoder circuit 22, a word line driver 24, and a block control circuit 26. The upper bit row address decode signal ADU is applied to the block enable circuit 20, and the lower bit row address decode signal ADL is applied to the row decoder circuit 22. Each block enable circuit 20 generates a block enable signal BE in response to a row address decode signal ADU, and selects a corresponding decoder block DB. Each row decoder circuit 22 selects one of the corresponding 256 word lines WL in response to a row address decode signal ADL. The word line driver 24 drives the selected word line WL. In this example, a 12-bit row address signal RA is provided, of which 4 bits are used for selecting the block BK, and the remaining 8 bits are used for selecting the word line WL.

  The block control circuit 26 is activated in response to the block enable signal BE, receives the timing monitor signal TM from the corresponding block BK, and applies the array control signal AC to the corresponding block BK. The timing monitor signal TM is generated in the corresponding block BK. The array control signal AC is a signal for controlling the corresponding block BK, such as activation of the sense amplifier and bit line precharge after restoration. That is, each block control circuit 26 controls the corresponding block BK so that a series of operations are completed.

  As a feature of this embodiment, the DARM 12 further includes one busy signal line 28 for generating the busy signal BUSY. The busy signal line 28 is provided in common to the 16 blocks BK and runs in the row decoder 14 in parallel with the bit line pair BL.

  FIG. 5 shows a circuit for generating the busy signal / BUSY. Referring to FIG. 5, each block control circuit 26 includes an array access timing control circuit 36, a delay circuit 38, and an N channel MOS transistor 40. The array access timing control circuit 36 applies various array control signals AC to the corresponding block BK in addition to the bit line equalize signal BLEQ. The delay circuit 38 delays the bit line equalize signal BLEQ by a predetermined time. The transistor 40 is turned on in response to the delayed bit line equalize signal BLEQ, and pulls down the voltage of the busy signal line 28 to the ground voltage GND.

  Row decoder control circuit 16 includes a P-channel MOS transistor 42 and an inverter 44. The transistor 42 is turned on in response to the array enable signal / AE, and pulls up the voltage of the busy signal line 28 to the power supply voltage VDD. The array enable signal / AE is a pulse signal that is temporarily generated in response to the chip enable signal / CE or the refresh enable signal / RE.

  When the normal access operation or the refresh operation is started in any block BK, a pulse of the array enable signal / AE is given to the gate of the transistor 42. As a result, the busy signal line 28 is pulled up, and the busy signal BUSY is precharged to H level. Accordingly, the busy signal / BUSY becomes L level by the inverter 44, indicating that any block BK is in operation, thereby prohibiting the start of the next normal access operation or refresh operation.

  When the selected block BK finishes a series of operations, the transistor 40 is turned on after a predetermined time has elapsed since the bit line equalize signal BLEQ is output. As a result, the busy signal line 28 is pulled down, and the busy signal BUSY returns to the L level. Therefore, the busy signal / BUSY is returned to the H level by the inverter 44, indicating that the block BK has completed the operation, thereby unblocking the start of the next operation.

  As described above, the busy signal / BUSY is maintained at the H level while no block BK is selected, but is set to the L level when any block BK is selected, and the selected block BK is selected. It is maintained at the L level until a series of operations in is completed. The busy signal / BUSY is supplied from the row decoder control circuit 16 to the address selector 18. That is, the transistor 42 charges the busy signal line 28 in response to the access command or the refresh command, and the transistor 40 discharges the busy signal line 28 when the access operation or the refresh operation is completed in the corresponding block BK. The busy signal line 28, the transistor 42, and the 16 transistors 40 provided corresponding to the 16 blocks BK activate the busy signal / BUSY in response to an access command or a refresh command, and a block enable circuit This is means for inactivating the busy signal / BUSY when the normal access operation or the refresh operation is completed in the block BK selected by 20.

  When the busy signal BUSY is at L level, no block BK is selected, so that the row decoder control circuit 16 is activated and supplies the row address decode signals ADU and ADL to the row decoder 14. Once any block BK is selected, the busy signal BUSY is activated to H level, but the row address decode signals ADU and ADL are maintained as they are, and even if the row address signal RA changes, the previous block It does not change until the operation of BK ends and the busy signal BUSY returns to the L level.

  FIG. 6 shows the configuration of the address selector 18. Referring to FIG. 6, address selector 18 includes NAND circuits 46 to 49, inverters 50 and 51, NOR circuit 52, and D-type latch circuit 54. N NAND circuits 46 to 48 and N type latch circuits 54 are provided. In this example, since the row address signals ERA, RRA and RA are 12 bits, N = 12. The twelve NAND circuits 46 receive a 12-bit access row address signal ERA when the chip enable signal / CE is at L level. The 12 NAND circuits 47 receive a 12-bit refresh row address signal RRA when the refresh enable signal / RE is at L level. The twelve NAND circuits 48 output the input 12-bit access row address signal ERA or refresh row address signal RRA.

  When the busy signal / BUSY is at the H level, the NAND circuit 49 functions as an inverter. Therefore, when the chip enable signal / CE or the refresh enable signal / RE becomes L level, the latch signal LT supplied from the NAND circuit 49 to the 12 latch circuits 54 becomes H level. When the latch signal LT becomes H level, the twelve latch circuits 54 take in and latch the 12-bit access row address signal ERA or the refresh row address signal RRA output from the 12 NAND circuits 48, and latch the 12-bit row. Output as address signal RA. In short, when the busy signal / BUSY is at the H level, the address selector 18 selects the access row address signal ERA when the chip enable signal / CE is at the L level, and the refresh row address when the refresh enable signal / RE is at the L level. The signal RRA is selected.

  On the other hand, when busy signal / BUSY is at L level, latch signal LT is fixed at H level. Therefore, even if the chip enable signal / CE or the refresh enable signal / RE becomes L level during this time and the next new access row address signal ERA or refresh row address signal RRA is input, the latch circuit 54 does not change the previous old access. The row address signal ERA or the refresh row address signal RRA is continuously latched, and the next new access row address signal ERA or the refresh row address signal RRA is not captured. In short, when the busy signal / BUSY is at the L level, the address selector 18 may provide the next access row address signal ERA or refresh row address to be applied even if the chip enable signal / CE or the refresh enable signal / RE is at the L level. The signal RRA is ignored without being selected, and the previously selected access row address signal ERA or refresh row address signal RRA is continuously output.

  Referring to FIG. 7, when chip enable signal CE is activated, an access operation starts in selected block BK, and busy signal / BUSY is activated to L level. When the access operation is finished, the busy signal / BUSY returns to the H level. On the other hand, when the refresh enable signal RE is activated, the refresh operation starts in the selected block BK, and the busy signal / BUSY is activated to the L level. When the refresh operation is finished, the busy signal / BUSY returns to the H level.

  As described above, when the busy signal / BUSY returns to the H level, the DRAM 10 determines the next operation to be started in accordance with the earlier command of the access command and the refresh command. As a result, the access row address signal ERA given from the outside and the internally generated refresh row address signal RRA are not distinguished from each other, and the operation according to the new row address signal RA until the operation of the previous block BK is completed. Will wait. That is, the DRAM 10 gives priority to the command that comes first, and the subsequent operation is made to wait until the previous operation is completed.

  Therefore, when distributed refresh is performed with the internal cycle time Tic longer than half of the external cycle time Tec, the refresh command contends with the access command, and the refresh tends to wait. Therefore, this embodiment preferably performs block-based burst refresh. This is a burst refresh of all 256 word lines WL for each block BK in a short time and continuously.

  In order to refresh each memory cell MC every 64 ms, a burst refresh start signal is given to each of the 16 blocks BK every 4 ms (= 64 ms ÷ 16), and 256 blocks in each block BK are correspondingly changed. The word line WL is continuously burst refreshed. Accordingly, each block BK performs 256 refreshes within a period of 4 ms. Even if the time required for one refresh is actually 50 ns, the time required for burst refresh is 12.8 μs (= 256 × 50 ns), which is much shorter than 4 ms. Therefore, the burst refresh ends in the first short time in the 4 ms period. When a normal access command is received during burst refresh, the refresh is waited. According to block-based burst refresh, the refresh delay is eliminated during the operation of the block BK and is not carried over to another block BK. This will be described in detail below.

  FIG. 8 shows a burst refresh operation when the access commands A1 and A2 come continuously every minimum external cycle time Tec. (A) is a case where the internal cycle time Tic is half of the external cycle time Tec as in the prior art, and (B) is a case where the internal cycle time Tic is longer than half of the external cycle time Tec. Here, since the refresh command R1 enters immediately before the access command A1 and the refresh operation R1 (using the same sign as the corresponding command) has started, the cycle time and the access time are worst for the normal access operation A1. Suppose.

  Referring to FIG. 8A, when refresh command R1 comes immediately before access command A1, refresh operation R1 starts first. The refresh operation R1 ends after the internal cycle time Tic has elapsed. Since the burst refresh is performed here, a refresh command is issued every time the previous normal access operation or refresh operation is completed. Accordingly, when the refresh operation R1 is completed, the refresh command R2 comes again. At this time, the access command A1 comes at the previous time T0, so that the normal access operation A1 starts in response to the access command A1. The normal access operation A1 is also terminated after the internal cycle time Tic has elapsed. This operation is repeated, and as a result, the individual refresh operations R1, R2 and the normal access operations A1, A2 in the burst refresh are alternately performed. This operation will be specifically described as follows.

  The address selector 18 latches the refresh row address signal RRA in response to the L level refresh enable signal / RE and supplies it to the row decoder control circuit 16. Row decoder control circuit 16 activates busy signal / BUSY to L level, and provides row address decode signals ADU and ADL to row decoder 14 in response to refresh row address signal RRA. One block BK is selected in response to the row address decode signal ADU, and one word line WL is activated in response to the row address decode signal ADL in the block BK, and is connected to the word line WL. All the memory cells MC are refreshed.

  During this refresh operation R1, the chip enable signal / CE is activated to L level and the access row address signal ERA is applied to the address selector 18, but the busy signal / BUSY is activated, so that address selection is performed. The unit 18 does not latch the access row address signal ERA, but continues to latch the refresh row address signal RRA latched one time before.

  When the refresh operation R1 is completed in the selected block BK, the busy signal / BUSY is inactivated to the H level. Therefore, the address selector 18 latches the already provided access row address signal ERA and supplies it to the row decoder control circuit 16. As a result, the normal access operation A1 is performed in the selected block BK.

  In the case of (A), since the internal cycle time Tic is half of the external cycle time Tec, each normal access operation is completed within the external cycle time Tec. The arrow in the figure indicates the end of the normal access operation from the input of the access command. The access time indicated by this arrow is also within the external cycle time Tec as in the SRAM.

  On the other hand, in the case of (B), the internal cycle time Tic is the same as in the case of (A), but the external cycle time Tec is shorter than the case of (A). Referring to FIG. 8B, when refresh command R1 comes just before access command A1, refresh operation R1 starts first. Because the refresh operation is burst refresh, the next refresh command R2 comes immediately after the refresh operation R1 ends. At this time, the access command A1 comes at the previous time T0. Begins. When the normal access operation A1 is completed, the refresh command R3 comes again. At this time, the access command A2 is received at the previous time T1, so the normal access operation A2 starts in response to the access command A2. When the normal access operation A2 ends, the refresh command R4 comes again. At this time, however, no access command has come before that, so the refresh operation R4 starts in response to the refresh command R4.

  In the case of (B), the refresh command may be skipped, but the memory cell MC is accessed every external cycle time Tec while being refreshed.

  First, how far the internal cycle time Tic can be increased when the internal cycle time Tic is set to be longer than half of the external cycle time Tec will be described with reference to FIG.

As the internal cycle time Tic is longer than half of the external cycle time Tec, the frequency of the refresh operation is reduced. Therefore, a condition is required for the refresh operation to be performed at least once after several normal access operations. N normal access operations are performed after the internal cycle time (1 × Tic) by the first refresh operation, and the time required for the N normal access operations (N × Tic) is N external cycle times (N × Tec). ), The refresh command comes before the N + 1th normal access command and the refresh operation is started. Accordingly, the condition for entering the refresh operation is given by the following equation (1).
Tic + N × Tic &lt; N × Tec (1)

When equation (1) is transformed, the following equation (2) is obtained.
Tic &lt; N / (N + 1) × Tec (2)

  Expression (2) indicates that if the internal cycle time Tic is within N / (N + 1) times the external cycle time Tec, the refresh operation is performed for the (N + 1) th time. For example, as shown in FIG. 9A, when N = 1, if the internal cycle time Tic is shorter than half of the external cycle time Tec, a refresh operation is performed every other time.

  As is clear from equation (2), when N increases, the internal cycle time Tic approaches the external cycle time Tec. That is, the internal cycle time Tic may be much closer to the external cycle time Tec if there is no problem even if the frequency of the refresh operation is considerably reduced.

  As shown in FIGS. 9A to 9E, when N is finite times, the refresh command is skipped N times. On the other hand, as shown in FIG. 9F, when N becomes infinite, the internal cycle time Tic is the same as the external cycle time Tec, but the refresh command is skipped infinitely and the refresh operation is not performed at all. Even if a refresh command comes in immediately before the first access command arrives and a refresh operation is started, the access command is always received one cycle before the end of the previous access operation, so no refresh operation is entered. If N is not infinite and the internal cycle time Tic is slightly shorter than the external cycle time Tec, the refresh operation is always performed.

Therefore, next, an upper limit value of N for which the refresh operation is surely entered is obtained. If the number of word lines per block BK is Nwlb, the value obtained by multiplying this by N × Tec should be shorter than the value obtained by dividing the retention time Tr by the number of blocks Nb. Therefore, the following equation (3) is obtained.
N × Tec × Nwlb &lt; Tr / Nb (3)

Since Nwlb × Nb is the total number of word lines Ntwl, when equation (3) is transformed using this, the following equation (4) is obtained.
N &lt; Tr / (Tec × Ntwl) (4)

  Assuming that the retention time Tr is 64 ms typical, the total number of word lines Ntwl is 4K as in this embodiment, and the external cycle time is 50 ns, the upper limit value of N is a very large number of about 312.

  If N = 312 is substituted into equation (2), the internal cycle time Tic is 0.997 times the external cycle time Tec (= 312/313), that is, 99.7% 49.85 μs. The refresh operation is performed once, and the normal access operation is continuously performed every external cycle time Tec without missing the refresh of all the word lines.

  However, even if N is not so large, the internal cycle time Tic is much closer to the external cycle time Tec. For example, as shown in FIG. 9D, when N = 4, that is, when a refresh operation is performed at a rate of once every four normal access operations, the internal cycle time Tic is 4/5 (= 80) of the external cycle time Tec. %). From the viewpoint of the frequency of the refresh operation, even if the external cycle time is 50 ns, the time required for 256 burst refreshes is 64 μs (= 5 × 50 ns × 256). In this case, the 256th word line refresh is most delayed, but the delay is only 51.2 μs (= 64 μs− (50 ns × 256)). This is only 0.08% of the retention time of 64 ms and can be completely ignored.

  In addition, since it is block-based burst refresh, the refresh delay is eliminated during the operation of the block BK, and it is carried over to another block BK and is not accumulated. Therefore, 51.2 μs is the maximum delay among all the word lines. Therefore, according to the present embodiment, there is almost no problem due to the refresh delay, and the internal cycle time Tic can be extended to near the external cycle time Tec. In other words, the speed can be increased to near the true capability of the DRAM 10 that can operate with the internal cycle time Tic. Therefore, it is possible to provide an SRAM compatible DRAM in which refresh is performed internally, and an external cycle time Tec close to half of the conventional one can be realized.

  Thus, even if the internal cycle time Tic is longer than half of the external cycle time Tec, from the viewpoint of “cycle time”, if N is finite, the normal access operation and the refresh operation are performed within the external cycle time Tec. There is no problem, but the problem remains from the viewpoint of “access time” required for normal access operation. That is, since the cycle time and the access time are generally the same in the SRAM, it is desirable that the read data is valid within the external cycle time Tec in the DRAM 10 as well. However, as shown in FIG. 8B, the first read data (the tip of the arrow indicating the access time) is not valid within the external cycle time Tec, and the access time Tac satisfies the general specifications of the SRAM. Absent. As can be seen from the figure, in order for the access time Tac to satisfy the specification, the sum of the internal cycle time Tic and the access time Tac for the refresh operation must be within the external cycle time Tec. In the above embodiment, the internal cycle time Tic for the refresh operation and the internal cycle time Tic for the normal access operation are the same. However, in the normal access operation, the access time of the first data is not changed depending on the DRAM. Since the precharge cannot be started immediately for some reason such as page or burst reading, the cycle time may be long. In such a case, even if the internal cycle time Tic for the normal access operation is long, it is not necessary to extend the external cycle time Tec and the access time.

  Further, as shown in FIG. 8B, the access time Tac differs between immediately after the refresh operation and after the normal access operation continues, so it is difficult for the user to use it as it is. Therefore, as shown in FIG. 10, the access latency is intentionally set so that the sum of the internal cycle time Tic for the refresh operation and the internal cycle time Tic for the normal access operation becomes the apparent access time from the outside. Tlt is provided in the specification, and the time when the data becomes valid may be delayed even during continuous normal access operation. Of course, the access time Tac becomes longer, but the cycle time can be shortened. This operation is similar to the pipeline burst SRAM disclosed in Digest of Technical Papers, ISSC91, p.50, Feb. 1991 (Pipeline Burst SRAM).

  FIG. 10 shows the operation when N = 5. FIG. 10A shows the operation when only the normal access command is received. The access time Tac is intentionally described longer in the specification and is longer than the external cycle time Tec. (B) shows the operation when burst refresh starts when a normal access command comes every external cycle time Tec. (C) shows the operation when only the refresh command is received. In both cases (A) and (B), unlike the case of the same N = 5 shown in FIG. 9 (E), the same access time Tac is always obtained from the input of the access command. Even if the access time Tac is longer than the external cycle time Tec, the data is continuously valid in the same cycle as the external cycle time Tec. When data is continuously accessed in this way, the bandwidth can be increased.

  While the embodiments of the present invention have been described above, the above-described embodiments are merely examples for carrying out the present invention. Therefore, the present invention is not limited to the above-described embodiment, and can be implemented by appropriately modifying the above-described embodiment without departing from the spirit thereof.

  The semiconductor memory device according to the present invention can be used for a DRAM used in place of the SRAM particularly for low power consumption.

1 is a functional block diagram showing an overall configuration of a DRAM according to an embodiment of the present invention. FIG. 2 is a functional block diagram showing a configuration of a decoder block and a row decoder control circuit shown in FIG. 1. FIG. 3 is a functional block diagram showing configurations of an address selector and a refresh circuit in FIG. 2. FIG. 4 is a timing chart showing read and refresh operations by the DRAM shown in FIGS. 1 to 3. FIG. 3 is a functional block diagram showing a configuration of a block control circuit in FIG. 2. FIG. 4 is a functional block diagram showing a configuration of an address selector in FIGS. 2 and 3. FIG. 7 is a timing chart showing an operation of the address selector shown in FIG. 6. FIG. 4 is a timing chart showing a burst refresh operation by the DRAM shown in FIGS. 1 to 3. FIG. 9 is a timing diagram showing operations at various values of N when the burst refresh operation is shown in the same manner as in FIG. 8, and the number of normal access operations after the refresh operation is N. FIG. 9E is a timing chart showing an operation when N = 5 shown in FIG. 9E, where FIG. 9A shows only an access operation, FIG. 9B shows a mixed operation of refresh and access, and FIG. 9C shows only a refresh operation. .

Explanation of symbols

12 memory cell array 14 row decoder 16 row decoder control circuit 17 refresh circuit 18 address selector 20 block enable circuit 22 row decoder circuit 24 word line driver 26 block control circuit 28 busy signal line 30 refresh timer 32 address counter 34 refresh enable circuit 40, 42 Transistors 46 to 49 NANAD circuit 54 Latch circuit / AE Array enable signal BUSY, / BUSY Busy signal CE, / CE Chip enable signal RE, / RE Refresh enable signal / RT Refresh timer signal A1, A2 Access command (normal access operation)
BE block enable signal BK access array block BL bit line pair BLEQ bit line equalize signal DB decoder block ERA access row address signal LT latch signal MC memory cells R1, R2, R3, R4 refresh command (refresh operation)
RRA Refresh row address signal Tac Access time Tec External cycle time Tic Internal cycle time WL Word line

Claims (4)

A memory cell array including a plurality of word lines and divided into a plurality of blocks;
Refresh means for requesting refresh and sequentially generating refresh addresses;
Address selecting means for selecting an access address when access is requested and selecting a refresh address when the refresh is requested, wherein the access address is input when the access is requested, and the refresh is requested Address selection means including input means for inputting the refresh address at a time and latch means for taking in and latching the input address when a busy signal is inactivated;
Word line selection means for selecting the word line in response to an address selected by the address selection means;
Block selecting means for selecting the block in response to the address selected by the address selecting means;
Selection stop means for stopping address selection by the address selection means while the access or refresh is being performed in the block selected by the block selection means, when the access or refresh is requested A selection stop means including a busy signal generation means for activating a busy signal and inactivating the busy signal when the access or the refresh is completed in the block selected by the block selection means;
The busy signal generating means includes:
A busy signal line provided in common to the plurality of blocks;
Charging means for charging the busy signal line when the access or the refresh is requested;
A semiconductor memory device comprising: a plurality of discharge means provided corresponding to the plurality of blocks, each discharging the busy signal line when the access or the refresh is completed in the corresponding block. A refresh method for a semiconductor memory device including a memory cell array including a plurality of word lines and divided into a plurality of blocks, and a busy signal line provided in common to the plurality of blocks,
Requesting refresh and sequentially generating refresh addresses;
An address selection step of selecting an access address when access is requested and selecting a refresh address when the refresh is requested;
A word line selection step of selecting the word line in response to the selected address;
Selecting the block in response to the selected address;
A selection stop step for stopping selection of the access address and the refresh address while the access or the refresh is being performed in the selected block,
The selection stop step includes a busy signal generation step of activating a busy signal when the access or the refresh is requested, and inactivating the busy signal when the access or the refresh is completed in the selected block. Including
The address selection step includes:
Entering the access address when the access is requested;
Inputting the refresh address when the refresh is requested;
Capturing and latching the input address when the busy signal is deactivated, and
The busy signal generation step includes:
Charging the busy signal line when the access or the refresh is requested;
And a step of discharging the busy signal line when the access or the refresh is completed in the selected block. A memory cell array including a plurality of word lines and divided into a plurality of blocks;
Refresh means for requesting refresh and sequentially generating refresh addresses;
Address selecting means for selecting an access address when access is requested and selecting a refresh address when the refresh is requested, wherein the access address is input when the access is requested, and the refresh is requested Address selection means including input means for inputting the refresh address at a time and latch means for taking in and latching the input address when a busy signal is inactivated;
All the word lines in the block selected in response to the refresh address selected by the address selecting means are selected in response to the access address selected by the address selecting means. Word line selection means for continuously selecting
Block selecting means for selecting the block in response to the address selected by the address selecting means;
Selection stop means for stopping address selection by the address selection means while the access or refresh is being performed in the block selected by the block selection means, when the access or refresh is requested A selection stop means including a busy signal generation means for activating a busy signal and inactivating the busy signal when the access or the refresh is completed in the block selected by the block selection means;
The busy signal generating means includes:
A busy signal line provided in common to the plurality of blocks;
Charging means for charging the busy signal line when the access or the refresh is requested;
A semiconductor memory device comprising: a plurality of discharge means provided corresponding to the plurality of blocks, each discharging the busy signal line when the access or the refresh is completed in the corresponding block. A refresh method for a semiconductor memory device including a memory cell array including a plurality of word lines and divided into a plurality of blocks, and a busy signal line provided in common to the plurality of blocks,
Requesting refresh and sequentially generating refresh addresses;
An address selection step of selecting an access address when access is requested and selecting a refresh address when the refresh is requested;
Selecting the block in response to the selected address;
A word line selection step of selecting a word line in the selected block in response to the selected access address;
Successively selecting all word lines in the selected block in response to the selected refresh address;
A selection stop step for stopping selection of the access address and the refresh address while the access or the refresh is being performed in the selected block,
The selection stop step includes a busy signal generation step of activating a busy signal when the access or the refresh is requested, and inactivating the busy signal when the access or the refresh is completed in the selected block. Including
The address selection step includes:
Entering the access address when the access is requested;
Inputting the refresh address when the refresh is requested;
Capturing and latching the input address when the busy signal is deactivated, and
The busy signal generation step includes:
Charging the busy signal line when the access or the refresh is requested;
And a step of discharging the busy signal line when the access or the refresh is completed in the selected block.

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