JP4991263B2 - High frequency power amplifier and portable radio terminal using the same - Google Patents

Description

  The present invention relates to a high frequency power amplifier and a portable radio terminal using the same.

  Conventionally, a high frequency power amplifier using a compound semiconductor as a final amplification stage is often used in an output circuit of a portable wireless terminal. However, with the progress of miniaturization of the CMOS process, efforts are being made to realize not only digital circuits in the baseband part but also high-frequency analog circuits in the front end part with CMOS, and some of them have already been commercialized. ing. This is because a standard CMOS integrated circuit process originally used for a logic circuit is relatively inexpensive per unit area as compared with a compound semiconductor process or a Si-Ge process.

On the other hand, high-frequency power amplifiers are required to have high power efficiency in order to realize long-time driving with a battery of a portable wireless terminal device. The power consumption of high-frequency power amplifiers accounts for a large proportion of the power consumption of the entire portable wireless terminal equipment. If you want to use the power stored in the battery as much as possible, increase the efficiency of the high-frequency power amplifier. Is essential. High efficiency of a high frequency power amplifier used in a transmission circuit of a portable wireless terminal device is known (for example, see Patent Document 1).
JP 2005-86673 A

  When an attempt is made to construct a high-frequency power amplifier with an inexpensive MOS field effect transistor, a new problem arises that the compound semiconductor does not cause much problems. This occurs because the resistance of the Si substrate is relatively low compared to a compound semiconductor. If the resistance of the substrate is low, the current flowing through the substrate increases in the high frequency band, thereby increasing the power loss of the power amplifier and decreasing the power efficiency.

In general, a high-frequency power amplifier includes an amplifying MOS transistor, a DC power supply, a choke coil, an input side impedance matching circuit, and an output side impedance matching circuit. 12 shows an example of the relationship between the input power _{P in} and the power gain of the high frequency power amplifier in a 2 GHz. In FIG. 12, the power gain is defined by the following equation.

As shown in FIG. 12, the high-frequency power amplifier, the Yuku increase the input power P _in, gradually power gain decreases. This is because the transistor output power is saturated with respect to a large amplitude input.

On the other hand, as shown in FIG. 13, as the input power is increased, the power added efficiency (PAE) gradually increases. The power added efficiency is defined by the following equation.

Power added efficiency As apparent from this equation, the additional power obtained by subtracting the input power P _in from the output power P _out, which is the ratio of the power P _DC supplied from the voltage source. That is, the power added efficiency is an index indicating how effectively the power supplied from the voltage source (battery) is used for power amplification. In particular, wireless portable terminals are strongly required to have high power added efficiency.

  12 and 13 show simulation results when only the BSIM3 model, which is a typical CMOS simulation model, is used, and when a model obtained by extending the BSIM3 model for high frequency is used. In the extended model for high frequency, the influence of the gate resistance of the CMOS transistor, the parasitic capacitance between the gate and the source, the drain, the junction capacitance between the source and the drain and the substrate, the substrate resistance and the like is taken into consideration. FIG. 12 and FIG. 13 show that the presence of these parasitic components reduces both power gain and power added efficiency at high frequencies (2 GHz).

  As described above, when a high-frequency power amplifier is configured by CMOS, there is a problem that power efficiency at a high frequency is greatly deteriorated due to the influence of power loss caused by low substrate resistance.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a high-frequency power amplifier with high power efficiency and a portable wireless terminal using the same while suppressing a decrease in power added efficiency.

  A high frequency power amplifier according to a first aspect of the present invention includes a first conductivity type first well formed in a first conductivity type semiconductor substrate, and a first conductivity type second well formed in the first well. A source region and a drain region of a second conductivity type formed separately from the second well, a channel region formed on the second well between the source region and the drain region, and the channel region A MOS type transistor having a gate insulating film formed thereon and a gate electrode formed on the gate insulating film; and in a direction adjacent to one of the source region and the drain region and extending the gate electrode A first contact region provided along the first contact region for making contact with the first well, a first contact provided in the first contact region, and the gate electrode A second contact region provided in a direction orthogonal to the extending direction for making contact with the second well; and a second contact provided in the second contact region. It is characterized by that.

  A portable radio terminal according to the second aspect of the present invention is characterized in that the power amplifier described is provided in a transmission circuit.

  According to the present invention, it is possible to provide a high-frequency power amplifier with high power efficiency and a portable wireless terminal using the same while suppressing a decrease in power added efficiency.

(First embodiment)
Next, a high frequency power amplifier according to a first embodiment of the present invention will be described with reference to FIGS. A circuit diagram of the high-frequency power amplifier of this embodiment is shown in FIG. The high-frequency power amplifier according to the present embodiment includes an amplification MOS transistor 1, DC power supplies 42a and 42b, choke coils 43a and 43b, an input side impedance matching circuit 44 including a capacitor and an inductor, and an output including a capacitor and an inductor. The side impedance matching circuit 45 is provided. The power input to the high frequency power amplifier of this embodiment is sent to the amplification MOS transistor 1 via the input side impedance matching circuit 44 and amplified, and this amplified power is passed through the output side impedance matching circuit 45. Output to the outside.

  FIG. 1 shows a plan view of an amplifying MOS transistor 1 according to the high-frequency power amplifier of this embodiment, FIG. 2 shows a cross section taken along the cutting line AA shown in FIG. 1, and FIG. FIG. 3 shows a cross section cut at −B. The amplifying MOS transistor 1 is an N-channel MOS transistor, and is formed in an N-type well 4 (also referred to as a deep well 4) formed in a P-type substrate (silicon substrate) 2 and in the N-type well 4. P-type well 8 that is isolated by element isolation insulating film 6, N-type drain region 10 and source region 12 that are formed apart from P-type well 8, and between drain region 10 and source region 12. A gate insulating film 16 formed on the P-type well 8 serving as the channel 14 and a gate electrode 18 formed on the gate insulating film 16. In this embodiment, two gate electrodes 18 are provided, and they are commonly connected at one end. The source region 12 is provided between the two gate electrodes 18, and the drain region 10 is provided on the opposite side of the two gate electrodes 18 from the source region 12. That is, in FIG. 1, two MOS transistors share the source region 12 and the gate electrode 18 is connected in common.

A contact region 20 for making contact with the N-type well 4 is provided on the N-type well 4 along the direction in which the two gate electrodes 18 extend adjacent to the drain region 10 (FIG. 1, FIG. 2). That is, two contact regions 20 are provided in FIG. 1, and each contact region 20 is provided along the direction in which the gate electrode 18 extends adjacent to the corresponding drain region 10. For this reason, the shortest distance L _dw between the contact region 20 and the corresponding drain region 10 is substantially constant from any point of the drain region 10. The contact region 20 is rectangular in shape, and its longitudinal direction is parallel to the direction in which the gate electrode 18 extends. The contact region 20 is connected to the metal wiring 26 through a plurality of contacts 24 provided in the interlayer insulating film 22 (see FIG. 2). The metal wiring 26 is connected to a constant potential source (not shown) provided outside.

Further, a contact region 21 for making contact with the P-type well 8 extends in a direction substantially perpendicular to the direction in which the contact region 20 extends (the short axis direction of the contact region 20) and is on the P-type well 8. (FIGS. 1 and 3). In this embodiment, two contact regions 21 are provided, and the distance L _p between each contact region 21 and the drain region 10 is configured to be substantially constant from any point of the drain region 10. Yes. The contact region 21 is connected to the metal wiring 28 via a plurality of contacts 25 provided in the interlayer insulating films 22 and 23 (see FIG. 3). The metal wiring 28 is connected to a constant potential source (not shown) provided outside.

In the present embodiment, the drain region 10 is disposed outside the gate electrode 18. This is because when the drain potential changes at a high frequency and with a large amplitude, the drain region 10 can be quickly charged and discharged to the junction capacitance formed between the drain region 10 and the P-type well 8. This is because it is preferable to make the distance L _dw between the contact region 20 to the N-type well 4 as short as possible in order to prevent power loss due to the current flowing through the substrate.

  Further, contrary to the case shown in FIG. 1, the drain region 10 can be disposed between the two gate electrodes 18. In this case, since the drain region 10 is shared between the two transistors, the distance between the drain region 10 and the contact region 20 is slightly longer than in the case of FIG. However, the low-resistance N-type well 4 extends just below the drain region 10 so that power loss can be suppressed as much as possible.

In this embodiment, when the width of the channel 14 of the MOS transistor 1 is W, as a result, the width of the source region 12 or the drain region 10 is also equal to the channel width W of the MOS transistor 1. The length Wc of the contact region 20 with respect to the type well 4 is longer than the channel width W of the MOS type transistor 1. That is, the relationship of W <Wc is established. With such an arrangement, as described above, the shortest distance L _dw between the position of the drain region 10 having the largest potential fluctuation and the contact region 20 arranged adjacent to each drain region 10 is _equal to the drain region 10. Since it can be assumed that the arbitrary position is almost constant, variation in parasitic resistance can be reduced.

Further, by arranging the distance L _dw from the drain region 10 to the contact region 20 to the N-type well 4 shorter than the distance L _p from the drain region 10 to the contact region 21, the N-type well 4 having a lower resistance is arranged. It is possible to shorten the route of the via, and the parasitic resistance component can be reduced.

  A plurality of contacts to the N-type well 4 are arranged adjacent to at least one of the source region 12 and the drain region 10 formed on both sides of the gate electrode 18 and parallel to the adjacent region, and N The contact to the mold well 4 is electrically connected to the ground potential. The resistivity of the N-type well is generally lower than that of the P-type well. Therefore, it is more power loss due to the substrate current to arrange the contact region 20 to the N-type well 4 adjacent to the MOS type transistor than to arrange the contact region 21 to the P-type well adjacent to the MOS type transistor. Can be reduced.

(Comparative example)
As a comparative example of the MOS transistor of the high-frequency power amplifier according to the present embodiment, a well-known high-frequency power amplifier MOS transistor having the layout shown in FIG. 5 was created. FIG. 6 shows a cross-sectional view of the MOS transistor of this comparative example taken along the cutting line CC shown in FIG.

  The MOS transistor of this comparative example is formed in the element region of the P-type substrate 71 that is element-isolated by the element isolation insulating film 72. Then, a plurality of N-type source regions 73 and N-type drain regions 74 formed alternately in this element region, and an element region that becomes a channel region 75 between the adjacent source region 73 and drain region 74. A plurality of gate electrodes 77 formed with a gate insulating film 76 interposed therebetween. That is, in FIGS. 5 and 6, six MOS transistors share the source region 73 or the drain region 74, and the six gate electrodes 77 are commonly connected at one end (the upper end in the figure). It becomes the composition.

  In the MOS transistor of this comparative example, a contact region 79 for the P-type substrate 71 is disposed around the element region where the gate, source, and drain are formed so as to surround the MOS transistor. A plurality of contacts 80 are provided in the contact region 79. The contact region 79 is connected to a metal wiring 81 through a plurality of contacts 80, and the metal wiring 81 is connected to a constant potential source provided outside. Further, between the region where the transistor is formed and the contact region 79, one or two dummy gate electrodes 79 are provided on one side (in FIGS. 5 and 6) for the purpose of suppressing the influence of characteristic variations caused by the process. 2) each.

Comparing this embodiment and the comparative example, the distance L _dw between the drain region of the MOS transistor and the contact region to the substrate (N-type well in this embodiment) is substantially constant in the case of this embodiment. On the other hand, in the case of the comparative example, there are near points and far points, which are not constant, have large variations, and it is understood that the average distance is also long compared to this embodiment. .

  Therefore, when the drain potential is driven at a high frequency and a large amplitude, the substrate current flowing to charge / discharge the junction capacitance between the drain region and the well or substrate located thereunder is relatively small in this embodiment. In contrast to the uniform resistance, in the comparative example, the resistance is greatly varied.

  When the drain potential is driven at a high frequency and with a large amplitude, charging / discharging to the junction capacitance formed between the drain region and the P-type well is performed through the substrate (N-type well in this embodiment). Is called. Here, assuming that the drain junction capacitance per unit channel width is the same in this embodiment and the comparative example, the amount of charge that must be supplied through the substrate resistance is also equal. It is possible to reduce the power loss caused by.

However, since a silicon substrate is used in the CMOS process and the resistivity of the substrate is already determined, it is necessary to shorten the distance between the drain region and the contact in order to reduce the substrate resistance. In the present embodiment, the distance L _p between the drain region 10 and the P-type well contact region 21 is as short as possible, and the shortest distance L _dw between the drain region 10 and the N-type contact region 20 is almost equal. It is constant. Thereby, the power loss resulting from the substrate current can be suppressed to the minimum, and the power efficiency of the power amplifier can be improved.

  In this embodiment, the N-type well 4 is used as a main substrate current path. Since the mobility of the N-type well is higher than that of the P-type substrate used in the comparative example, the substrate resistance can be further reduced.

  Next, an equivalent circuit of a MOS transistor used in the high frequency power amplifier according to the present embodiment is shown in FIG. 7, and an equivalent circuit of a MOS transistor used in the high frequency power amplifier according to the comparative example is shown in FIG. 7 and 8 are high-frequency expansion model equivalent circuits.

  In the equivalent circuit model of the comparative example, as shown in FIGS. 5 and 6 of the comparative example, a plurality of sources and drains are alternately arranged. Further, a substrate contact is disposed so as to surround the outside of the transistor region. For this reason, the distance between the source-substrate contact and the distance between the drain-substrate contact differ for each individual transistor, but the average values thereof are substantially equal. As a result, the resistance R6 between the drain-substrate contact and the resistance R7 between the source-substrate contact have substantially the same value (for example, about 71Ω) in the equivalent circuit (see FIG. 8). In FIG. 8, R1 is a gate resistor, R2 and R3 are substrate resistors, C1 is a gate-drain parasitic capacitance, C2 is a gate-source parasitic capacitance, and D1 is a junction diode formed by the drain and the substrate. D2 is a parasitic variable capacitance due to the junction diode formed by the source and the substrate.

  On the other hand, in the MOS transistor of the present embodiment, the substrate contact 20 is disposed close to the drain 10, so that it can be represented by only the resistor R4 between the drain 10 and the substrate contact on the equivalent circuit. The resistance value (for example, 0.36Ω) is lower than that of the comparative example. In FIG. 7, R3 indicates a resistance (0.36Ω) between the P well 8 and the contact 21, and D3 indicates a parasitic capacitance (0.67 pF) due to a junction diode between the P well 8 and the N well 4. , R5 represents substrate resistance.

  Next, FIG. 9 shows the frequency dependence of the power gain of the power amplifier configured using the MOS transistor of this embodiment and the power amplifier configured using the MOS transistor of the comparative example. The power gain of the power amplifier configured using the MOS transistor of the comparative example is calculated using the RF extension model and the BSIM3 model. As can be seen from FIG. 9, in almost all frequency regions, the use of the MOS transistor shown in the comparative example can provide a larger power gain than in the case of using this embodiment. The reason for this is considered to be that the junction capacity of the drain region is smaller in the comparative example because the adjacent transistors share the drain region, and when compared in unit channel length (drain length). Since the drain capacity is relatively small, the ratio of the drain current flowing through the transistor used for charging and discharging the drain capacity is small and the ratio supplied to the load is large, so that the power gain is considered large.

  Next, FIG. 10 shows the frequency dependence of the power added efficiency of the power amplifier configured using the MOS transistor of the present embodiment and the power amplifier configured using the MOS transistor of the comparative example. The power added efficiency of the power amplifier configured using the MOS transistor of the comparative example is calculated using the RF extension model. As can be seen from FIG. 10, the power added efficiency is higher in the comparative example at a low frequency of 1 GHz or less. However, when the frequency is 1 GHz or more, this relationship is reversed, and higher power added efficiency can be obtained in the present embodiment. The reason for this is that, in the low frequency region, the drain capacity of the comparative example is relatively small, so that the substrate current that flows to charge and discharge it is small. Compared with the same frequency, the comparative example has more power. There is little loss. On the other hand, in the high frequency region, since the number of times of charging / discharging per unit time increases, the power loss due to the substrate resistance becomes dominant rather than the size of the drain capacitance. Therefore, at a high frequency of 1 GHz or higher, the present embodiment can provide higher power efficiency than the comparative example.

  As described above, according to the present embodiment, it is possible to reduce the power loss caused by the substrate current that occurs when the MOS transistor configured on the Si substrate is operated with a large amplitude at an extremely high frequency. Thus, a high frequency power amplifier with high power added efficiency can be provided. In addition, by using a standard CMOS process, there is an advantage that the cost at the time of mass production can be reduced and that it can be mixed with other logic circuits.

  In this embodiment, the MOS transistor is an N-type channel, but may be a P-type channel. Since an N-type channel has higher mobility, it is more preferable that the MOS-type transistor used in the high-frequency power amplifier is an N-type channel. That is, the conductivity of the channel is N-type, the conductivity of the source and drain regions is N-type, the conductivity of the well 8 is P-type, the conductivity of the deep well 4 is N-type, and the conductivity of the substrate 2 is P-type. A configuration that is a mold is preferred.

  In the MOS transistor of this embodiment, the source region is disposed on one side and the drain region is disposed on the opposite side across the gate electrode, but at least one of the source region and the drain region is adjacent to this region. In parallel, a plurality of contact regions for the deep well 4 are preferably arranged.

  The substrate contact with respect to the deep well 4 is electrically connected to a constant potential. In the case of an N-channel MOS transistor, this potential is the ground potential of the high-frequency power amplifier circuit, the P-channel MOS transistor. In some cases, it is preferable to be connected to a power supply voltage.

Also, it is preferable that a substrate contact is made to the well 8 having conductivity opposite to that of the deep well 4 and connected to a constant potential. In the present embodiment, since the contact position with respect to the deep well is arranged close to the drain region, the distance L _p from the drain to the contact with respect to the well 8 is necessarily the distance from the drain to the contact with respect to the deep well. It is farther than L _dw (L _p > L _dw ). Here, L _p is the shortest distance from the drain to the closest well contact 21.

  Further, in the present embodiment, two MOS transistors can be arranged adjacent to each other, and either the source region or the drain region can be shared by the two transistors. In this case, (1) an arrangement in which a source, a drain, and a source are arranged in this order across two gate electrodes, and a deep well contact is provided adjacent to the outside of the source region on both sides, and (2) two Two arrangements are conceivable, in which the drain, source, and drain are arranged in this order across the gate electrode, and a deep well contact is provided adjacent to the outside of the drain regions on both sides. In this embodiment, since the main purpose is to reduce the power consumption due to the substrate current caused by a large fluctuation in the drain potential, both the former and the latter have the merit of reducing the substrate resistance, and the optimum configuration is appropriately selected. can do.

  Further, two MOS transistors are arranged adjacent to each other, and either one of the source region or the drain region is shared by the two transistors, and further outside the source region or the drain region. When the arranged deep well contacts are used as one unit and a plurality of the units are arranged in parallel, the adjacent units can share the deep well contacts.

(Second Embodiment)
Next, FIG. 11 shows a block diagram of the transmission circuit of the wireless portable terminal according to the second embodiment of the present invention. The wireless portable terminal of this embodiment includes the power amplifier of the first embodiment. In this transmission circuit, orthogonal digital signals I and Q are received from a baseband circuit (not shown), and modulated by a high-frequency signal so that the phases differ by 90 degrees in the mixers MIX1 and MIX2 of the local oscillator LO. The modulated signal is added by the adder AD, and then passes through the band pass filter BPF. The signal that has passed through the bandpass filter BPF is amplified by the power amplifier PA and radiated as an electromagnetic wave from the antenna ANT. By using the MOS transistor according to the first embodiment for the power amplifier, the power efficiency in the transmission circuit can be greatly improved.

  As described above, by using the high-frequency power amplifier described in the first embodiment, the power can be effectively used, and in the case of a portable wireless terminal driven by a battery, the terminal can be used by one charge. The time can be lengthened.

The top view which shows the MOS type transistor of the high frequency power amplifier by 1st Embodiment of this invention. Sectional drawing of the MOS type transistor by 1st Embodiment cut | disconnected by the cutting line AA shown in FIG. Sectional drawing of the MOS type transistor by 1st Embodiment cut | disconnected by the cutting line BB shown in FIG. The circuit diagram of a high frequency power amplifier. The top view of the MOS type transistor for the high frequency power amplifier by a comparative example. Sectional drawing of the MOS type transistor for high frequency power amplifiers by the comparative example cut | disconnected by the cutting line CC shown in FIG. The extended equivalent circuit for high frequency of the MOS transistor by 1st Embodiment. A high-frequency extended equivalent circuit of a MOS transistor according to a comparative example. The figure which shows the frequency dependence of the power gain of the power amplifier comprised using the MOS type transistor of 1st Embodiment, and the power amplifier comprised using the MOS type transistor of a comparative example. The figure which shows the frequency dependence of the power added efficiency of the power amplifier comprised using the MOS type transistor of 1st Embodiment, and the power amplifier comprised using the MOS type transistor of a comparative example. The block diagram of the transmission circuit of the portable radio | wireless terminal by 2nd Embodiment of this invention. The figure which shows the relationship between input power and a power gain. The figure which shows the relationship between input electric power and electric power addition efficiency.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 MOS type transistor 2 P type substrate 4 N type well 6 Element isolation insulating film 8 P type well 10 Drain region 12 Source region 14 Channel region 16 Gate insulating film 18 Gate electrode 20 Contact region 21 to N type well 21 To P type well Contact region 22 Interlayer insulating film 24 Contact 25 Contact 26 Metal wiring 27 Contact 28 Metal wiring 42a, 42b DC power supply 43a, 43b RF choke 44 Input side matching circuit 45 Output side matching circuit

Claims (5)

A first well of a second conductivity type formed on a semiconductor substrate of the first conductivity type;
A second well of the first conductivity type formed in the first well;
A source region and a drain region of a second conductivity type formed apart from the second well; a channel region formed on the second well between the source region and the drain region; and on the channel region A MOS transistor having a formed gate insulating film and a gate electrode formed on the gate insulating film;
A first contact region for making contact with the first well provided adjacent to one of the source region and the drain region and extending in a direction in which the gate electrode extends;
A first contact provided in the first contact region;
A second contact region provided along a direction orthogonal to a direction in which the gate electrode extends, for making contact with the second well;
A second contact provided in the second contact region;
A high frequency power amplifier comprising:   The first contact region is provided adjacent to the drain region, and a shortest distance between the first contact region and the drain region is shorter than a shortest distance between the second contact region and the drain region. The high frequency power amplifier according to claim 1.   The length of the source region and the drain region in the extending direction of the gate electrode is the same as the width of the channel region, and the length of the first contact region in the extending direction of the gate electrode is the channel length. 3. The high frequency power amplifier according to claim 1, wherein the high frequency power amplifier is larger than a width of the region. The source region and the drain region are arranged in the order of the drain region, the source region, and the drain region with two gate electrodes in between, or the source region, the drain region, with two gate electrodes in between The high-frequency power amplifier according to claim 1, wherein the high-frequency power amplifier is arranged in the order of the source regions . A portable radio terminal comprising the high-frequency power amplifier according to claim 1 in a transmission circuit.

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