JP4985035B2 - Oscillator circuit - Google Patents

Description

  The present invention relates to an oscillation circuit, and more particularly, to an oscillation circuit with improved oscillation frequency accuracy.

  Conventionally, an integrated circuit such as an MCU (microcontroller) that incorporates a CR oscillation circuit (or ring oscillator or the like) on a chip and supplies a clock signal from the built-in oscillation circuit is known.

  The CR oscillation circuit has an advantage that the startup time is shorter than that of an oscillation circuit using a crystal resonator or a ceramic resonator. In addition, when the oscillation circuit is frequently stopped and started, it is desirable to reduce the waiting time when starting the oscillation circuit and the power consumption during this period from the viewpoint of improving overall system performance. There is.

For such a background and purpose, various CR oscillation circuits have been proposed (see, for example, Patent Documents 1 to 7).
FIG. 12 is a diagram showing a configuration of a conventional CR oscillation circuit.

The CR oscillation circuit 80 illustrated in FIG. 12 includes inverters INV81, INV82, INV83, a capacitor CT81, and a resistor RT81.
FIG. 13 is a diagram showing waveforms at various parts during operation of the circuit shown in FIG.

  As shown in FIG. 13, the waveforms at the nodes N81, N82, and N83 are a general output waveform of a CMOS circuit and a rectangular wave. The waveform of the node N84 is such that the potential of the node N84 changes in the same direction as the node N82 due to capacitive coupling at the time of the potential change of the node N82 due to capacitive coupling with the node N82, and then is gradually charged and discharged by the potential of the node N83. Waveform.

According to the CR oscillation circuit 80, the use of the capacitor CT81 and the resistor RT81 has succeeded in realizing an oscillation frequency that does not depend on the power supply voltage.
However, it has also been pointed out that there is room for improvement in the accuracy of the oscillation frequency. Specifically, when the resistor RT81 depends on temperature, there is a drawback that it is difficult to suppress oscillation frequency fluctuations. For example, when the resistor RT81 is integrated in the chip, it is practically difficult to reduce the temperature dependence of the resistor RT81.

In order to improve this problem, the following circuits have been proposed.
FIG. 14 is a diagram showing another configuration of a conventional CR oscillation circuit.
The operation of the circuit of FIG. 14 will be briefly described.

  The CR oscillation circuit 90 includes inverters INV91, INV92, INV93, a capacitor C91, a capacitor C92, NMOS transistors MN91, MN92, PMOS transistors MP91, MP92, a bias generation circuit 91, and a constant voltage circuit that supplies a constant voltage. 92. In FIG. 14, IP91 and IN91 are current sources, N91, N92 and N93 are nodes in the CR oscillation circuit 90, VCC is a positive power source (for example, 3V), GND is a GND potential (0V), and CIP91. Denotes an IP91 control signal, CIP92 denotes an IN91 control signal, VREG denotes an output voltage of the constant voltage circuit 92, and OSCO denotes an output of the CR oscillation circuit 90.

  The CR oscillation circuit 90 drives one end of the capacitor C92 by inverters (NMOS transistors MP92 and MN92) using a constant voltage as a power source, and controls the signal amplitude of the node N91 to be constant regardless of the temperature. In order to design the frequency so as not to depend on the temperature, the circuit is configured so that the currents of the current sources IP91 and IN91 are constant regardless of the temperature.

In the CR oscillation circuit 90, all of the bias generation circuits are integrated on the chip, and a circuit configuration as described below is adopted in order to generate a temperature-independent current.
In order to generate a constant current, a potential generated by passing a current through a resistor is matched with a reference voltage by feedback control. Considering the temperature dependence of on-chip resistance, make the reference voltage temperature dependent. If the resistance value increases as temperature rises, the reference voltage also has a positive temperature dependency that increases with temperature, and the temperature dependency of the resistance is offset by the temperature dependency of the reference voltage. Is designed to be temperature independent.

Such a circuit has provided an oscillation circuit in which the oscillation frequency is constant with respect to temperature and power supply voltage.
JP-A-53-103793 JP-A-57-133715 JP-A-63-182909 JP-A-9-275320 JP-A-11-135725 JP 2000-13193 A JP 2005-217762 A

However, the conventional techniques have the following problems.
The CR oscillation circuit 90 is configured to cancel the temperature dependence of the resistance with the temperature dependence of the built-in reference voltage designed in advance. However, when the built-in resistor has complicated temperature dependence, for example, when the temperature characteristic is approximated by a linear expression, the error becomes large. For this reason, when it is necessary to approximate the temperature characteristics of the resistance with a quadratic equation, or when the temperature characteristics vary greatly from sample to sample, the temperature dependence of the built-in resistance is offset by the temperature dependence of the built-in reference voltage. There is a problem that it is difficult to do.

  The present invention has been made in view of these points, and an object of the present invention is to provide an oscillation circuit with high oscillation frequency accuracy even when there is a large difference in temperature characteristics between samples.

  In the present invention, in order to solve the above problem, in an oscillation circuit mounted on a microcontroller, a reference resistor that generates a reference current, and an operational amplifier circuit that is provided separately from the reference resistor and supplies current to the reference resistor; An integrated circuit having a reference voltage generating circuit for determining a reference voltage to be applied to the reference resistor, and a constant voltage circuit for generating a constant voltage, and determining an oscillation frequency based on the reference current and the constant voltage; There is provided an oscillation circuit comprising a register for setting the temperature dependence of the reference voltage output from the reference voltage generation circuit so as to have the same temperature dependence as the temperature dependence of the reference resistance. The

  According to such an oscillation circuit, the reference current is generated by the reference resistor provided outside the integrated circuit. A reference voltage is applied to the reference resistor by the reference voltage generation circuit. The temperature dependency of the output reference voltage of the reference voltage generation circuit is set by the register so that the temperature dependency is the same as the temperature dependency of the reference resistor. The oscillation frequency is determined based on a reference current and a constant voltage that do not depend on temperature.

  According to the present invention, by providing the reference resistor outside the integrated circuit, it is possible to use a resistance element having a small temperature dependency compared to the case where the reference resistor is provided inside the integrated circuit. In addition, a resistance element whose temperature dependency can be approximated by a linear expression can be selected.

  Further, by providing a register for setting the temperature dependence of the reference voltage, a constant current independent of temperature can be generated. In addition, by setting a value for each reference resistor in the register that sets the temperature dependency of the reference voltage, even if the temperature dependency of the reference resistance varies from sample to sample, the temperature dependency of the reference voltage is set accordingly. As a result, the reference current can be stably generated even when the temperature characteristic of the resistance element varies greatly from sample to sample.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
FIG. 1 is a circuit diagram illustrating the oscillation circuit according to the first embodiment.
The oscillation circuit 1 is configured by SIP (System In Package), and has an integrated circuit 2, a reference resistor RE1, and a setting register 25 therein.

  The integrated circuit 2 includes capacitors (capacitors) C1 and C2, inverters INV1, INV2, and INV3, a constant voltage circuit 21, a constant current source 22, a bias generation circuit 23, a PMOS transistor MP2, an NMOS transistor MN2, and an NMOS. The transistor MN4, the operational amplifier AMP1, and the reference voltage generation circuit 24 are included.

The reference resistor RE1 is provided outside the integrated circuit 2, and is electrically connected to the integrated circuit 2 via the pad PAD1.
In the integrated circuit 2, the input node of the inverter INV1 is the node N1, the output node of the inverter INV1 is the node N2, the output node of the inverter INV3 is the node N3, and the drain nodes of the PMOS transistor MP2 and the NMOS transistor MN2 are the node N4. To do.

The input of the inverter INV1 is connected to one end side of the capacitor C2. The inverter INV1 outputs a GND voltage when the voltage at one end of the capacitor C2 is equal to or higher than the threshold voltage Vth.
The inverter INV1 outputs the supplied power supply voltage VCC when the voltage at one end of the capacitor C2 is smaller than the threshold voltage Vth.

  The input of the inverter INV2 is connected to the output of the inverter INV1. The inverter INV2 inverts the rectangular wave oscillation signal output from the inverter INV1 and outputs the inverted signal as the output OSCO of the oscillation circuit 1.

  The gates of the PMOS transistor MP2 and the NMOS transistor MN2 are connected to the output of the inverter INV1, respectively. The back gate and the source of the PMOS transistor MP 2 are connected and connected to the constant voltage circuit 21. The drain of the PMOS transistor MP2 is connected to the drain of the NMOS transistor MN2, and is connected to the other end of the capacitor C2. The source of the NMOS transistor MN2 is connected to GND.

  The PMOS transistor MP2 and NMOS transistor MN2 constitute an inverter, and the other end side of the capacitor C2 is connected to one of the constant voltage circuit 21 or GND in accordance with the voltage output from the inverter INV1. When the voltage output from the inverter INV1 is the voltage GND (L state), the PMOS transistor MP2 is turned on, and the other end side of the capacitor C2 is connected to the constant voltage circuit 21. When the voltage output from the inverter INV1 is the voltage VDD (H state), the NMOS transistor MN2 is turned on, and the other end side of the capacitor C2 is connected to GND.

  The constant voltage circuit 21 outputs a constant constant voltage VREG without being affected by fluctuations in the supplied power supply voltage and temperature. Thus, when the other end side of the capacitor C2 is connected to the constant voltage circuit 21, the constant voltage VREG that is not affected by the power supply voltage and the temperature is supplied to the other end side of the capacitor C2.

  The input of the inverter INV3 is connected to the output of the inverter INV1. The output of the inverter INV3 is connected to the constant current source 22. The inverter INV3 inverts the output of the inverter INV1 and outputs it to the constant current source 22.

  The constant current source 22 flows a constant current that is not affected by fluctuations in the supplied power supply voltage and temperature into one end of the capacitor C2 according to the voltage output from the inverter INV1 via the inverter INV3. Or from one end of the capacitor C2. The constant current source 22 flows a constant current into the capacitor C2 when the voltage output from the inverter INV1 is the voltage VDD. When the voltage output from the inverter INV1 is the voltage GND, a constant current flows out from the capacitor C2.

  The constant current source 22 includes a PMOS transistor MP1, an NMOS transistor MN1, and a PMOS transistor MP3 and an NMOS transistor MN3 that constitute a current source for supplying current to them. The gates of the PMOS transistor MP1 and the NMOS transistor MN1 are connected to the output of the inverter INV3, respectively. The drain of the PMOS transistor MP1 is connected to the drain of the NMOS transistor MN1, and is connected to one end of the capacitor C1.

  The PMOS transistor MP3 is connected between the power supply voltage VCC and the source of the PMOS transistor MP1. The PMOS transistor MP3 flows a constant current Ip, which is not affected by fluctuations in the power supply voltage and temperature, to one end side of the capacitor C2 through the PMOS transistor MP1 by bias control of the bias generation circuit 23. The NMOS transistor MN3 is connected between GND and the source of the NMOS transistor MN1. The NMOS transistor MN3 causes the constant current In, which is not affected by fluctuations in the power supply voltage and temperature, to flow out from one end side of the capacitor C2 via the NMOS transistor MN1 by the bias control of the bias generation circuit 23.

  When the power supply voltage VCC is output from the inverter INV1, the voltage GND (L state) is output from the inverter INV3. As a result, the PMOS transistor MP1 of the constant current source 22 is turned on, and a constant current Ip flows into one end of the capacitor C2. When the L state is output from the inverter INV1, the H state is output from the inverter INV3. As a result, the NMOS transistor MN1 of the constant current source 22 is turned on, and a constant current In flows out from one end side of the capacitor C2.

Note that the current Ip also flows into the capacitor C1 generated between the nodes N1 and GND. Further, the current In flows out from the capacitor C1.
The bias generation circuit 23 controls the bias of the PMOS transistor MP3 and the NMOS transistor MN3 so that the PMOS transistor MP3 and the NMOS transistor MN3 output a constant current without being affected by the power supply voltage and temperature.

  By generating a constant voltage by the constant voltage circuit 21 and supplying it to the PMOS transistor MP2 and NMOS transistor MN2 constituting the inverter, the amplitude of the portion connected to the inverter output of the capacitor C2 becomes constant regardless of the temperature. . When the currents flowing through the PMOS transistor MP1 and the NMOS transistor MN1 are controlled to be constant without depending on the temperature by the bias potentials PB1 and NB1, the oscillation frequency depends on the temperature because the amplitude of the node N1 is constant. It becomes constant.

On the other hand, an NMOS transistor MN4 that is turned on according to the potential of the output NG4 of the operational amplifier AMP1 is provided on the left side of the bias generation circuit 23 in FIG.
The operational amplifier AMP1 performs feedback control so that the potential of the node NVR connected to the reference resistor RE1 matches the reference voltage VREF generated by the reference voltage generation circuit 24. When the potential of the node NVR becomes higher than the reference voltage VREF, the potential of the output NG4 of the operational amplifier AMP1 becomes lower. As a result, the potential of the node NVR is lowered. Conversely, when the potential of the node NVR becomes lower than the potential of the reference voltage VREF, the potential of the output NG4 of the operational amplifier AMP1 increases. Thereby, the potential of the node NVR is increased. As a result, the potential of the node NVR and the potential of the reference voltage VREF are almost equal.

  When the reference voltage VREF is applied to the reference resistor RE1, a current (reference current) at that time flows to the NMOS transistor MN4. By supplying this reference current to the bias generation circuit 23, the bias generation circuit 23 generates bias potentials PB1 and NB1 based on the reference current. Thereby, the current flowing through the PMOS transistor MP1 and the NMOS transistor MN1 is controlled to be constant regardless of the temperature.

  The setting register 25 is provided for setting the temperature dependence of the reference voltage VREF of the reference voltage generation circuit 24 after the component selection of the reference resistor RE1 is finished or after the component mounting of the reference resistor RE1 is finished. Yes. A value to be set in the setting register 25 is stored in advance in, for example, a non-volatile memory, and the value is set in the setting register 25 by initialization processing after power-on.

2 and 3 are diagrams showing the relationship between the temperature dependence of the reference resistance and the temperature dependence setting of the reference voltage.
When the temperature dependency of the reference resistor RE1 is positive (the resistance value increases with temperature), the temperature dependency of the reference voltage VREF is also positive as shown in FIG. When the temperature dependency of the reference resistor RE1 is negative (the resistance value decreases with temperature), the temperature dependency of the reference voltage VREF is also negative as shown in FIG.

  Since the reference current is a value obtained by dividing the reference voltage VREF by the resistance value of the reference resistor RE1, by appropriately setting the temperature dependency of the reference voltage VREF in accordance with the temperature dependency of the resistance of the reference resistor RE1, The temperature change of the reference current can be almost “0”. Even if the temperature dependency differs for each component of the reference resistor RE1, by setting the value in the setting register 25 accordingly, the stability of the reference current with respect to the temperature can be improved with respect to the conventional circuit.

Next, the configuration of the bias generation circuit 23 will be described.
FIG. 4 is a circuit diagram showing the configuration of the bias generation circuit.
The bias generation circuit 23 includes PMOS transistors MP4 to MP11 and NMOS transistors MN5 and MN6.

  Since the reference current flows to the NMOS transistor MN4 and the PMOS transistor MP4 is diode-connected, the potential of the node N4 connected to the bias generation circuit 23 is lower than VCC by the amount that allows the reference current to flow. Since the potential of the node N4 is the gate potential of each of the PMOS transistor MP5, the PMOS transistor MP7, and the PMOS transistor MP9, these PMOS transistors constitute a current mirror circuit with the PMOS transistor MP4.

  The control signals CMR1, CMR2, and CMR3 for adjusting the absolute value of the current function as signals for changing the mirror ratio (ratio of the current flowing in the PMOS transistor MP4 and the current flowing in the NMOS transistor MN5) to the current mirror circuit, respectively. .

  Next, the operation of the bias generation circuit 23 when the control signals CMR1, CMR2, and CMR3 are all “L” (Low level) will be described, and then the mirror ratio is changed using the control signals CMR1, CMR2, and CMR3. The effect of this will be explained.

  When the control signals CMR1, CMR2, and CMR3 are all “L”, the PMOS transistor MP6, the PMOS transistor MP8, and the PMOS transistor MP10 are turned on, so that the currents that flow through the PMOS transistor MP5, the PMOS transistor MP7, and the PMOS transistor MP9 are NMOS transistors. It flows to MN5. Since the NMOS transistor MN5 is diode-connected, the gate potential at this time is supplied as the bias potential NB1 of the NMOS transistor NM3 of the constant current source 22.

  Since the same current as the NMOS transistor MN5 flows to the NMOS transistor MN6, the same current as the NMOS transistor MN5 flows to the PMOS transistor MP11, and the gate potential at this time is supplied as the bias potential PB1 of the PMOS transistor MP3 of the constant current source 22. The Since the reference current flowing through the NMOS transistor MN4 does not depend on temperature, the current flowing through the MOS transistor having the bias potentials PB1 and NB1 applied to the gate is also constant regardless of the temperature.

  Up to this point, the explanation has been made focusing on the temperature dependence of the reference current. By the way, the oscillation frequency of the integrated circuit 2 depends on the value of current and the value of capacitance. Since the capacitors C1 and C2 are manufactured in the chip through an LSI manufacturing process, the absolute values of the capacitors may vary greatly. By controlling the reference current to be constant with respect to temperature, the oscillation frequency can be controlled to be constant regardless of temperature, but the absolute value of the frequency depends on the absolute value of the capacitance. Therefore, another mechanism is required to control the absolute value of the oscillation frequency to a desired value.

  Control signals CMR1, CMR2, and CMR3 are used to adjust the absolute value of this frequency to a desired value. The absolute value of the oscillation frequency is adjusted by increasing the current value when the absolute value of the capacity increases during the manufacturing process, and by decreasing the current value when the absolute value of the capacity decreases. can do. By setting some of the control signals CMR1, CMR2, and CMR3 to, for example, “H” (High level), the current supplied to the NMOS transistor MN5 can be changed according to the ratio of the gate width W thereof. In FIG. 4, only the control signals CMR1, CMR2, and CMR3 and their associated MOS transistors are shown for the sake of simplicity, but a circuit for changing the necessary mirror ratio can be easily configured based on the same concept. be able to.

Next, the circuit configuration of the reference voltage generation circuit 24 will be described.
FIG. 5 is a circuit diagram showing a configuration of the reference voltage generating circuit.
The reference voltage generation circuit 24 includes PMOS transistors MP12 to 30, operational amplifiers AMP2 and AMP3, PNP transistors Q1 and Q2, and resistors RI1, RI2, and RI3. Control signals CTC2 to CTC9 indicate signals for controlling the temperature dependence of the reference voltage VREF, respectively.

The operation of the reference voltage generation circuit 24 will be described.
In the bandgap circuit, the forward-biased pn junction potential is added to the voltage proportional to the absolute temperature (T) (hereinafter referred to as “PTAT (Proportional To Absolute Temperature) voltage”), so that it does not depend on temperature. A reference voltage VREF is obtained. It is known that the forward-biased pn junction potential is CTAT (Complementary To Absolute Temperature) if the pn junction potential is approximated by a linear expression or within a range that can be approximated by a linear expression. It is known that a reference voltage almost independent of temperature can be obtained by adding (appropriate) PTAT voltage to the potential of the forward-biased pn junction.

  Based on the same principle, a reference voltage having a desired temperature dependency can be generated. First, it will be described that the current flowing through the PMOS transistors MP12 and MP13 of the reference voltage generation circuit 24 becomes a current proportional to the absolute temperature.

  It is known that the relationship between the base temperature of the PNP transistor, the emitter-to-emitter voltage, or the forward voltage of the pn junction (hereinafter referred to as “voltage Vbe”) and the absolute temperature T is generally expressed by equation (1).

Vbe = Veg−aT (1)
Here, Veg: band gap voltage of silicon, about 1.2 V, a: temperature dependence of voltage Vbe, about 2 mV / ° C., T: absolute temperature, the value of temperature dependence a varies depending on the bias current, It is known that it is about 2 mV / ° C. in the practical range.

Further, it is known that the relationship between the emitter current IE of the PNP transistor and the voltage Vbe is generally expressed by the equation (2).
IE = I0exp (qVbe / kT) (2)
Here, IE: emitter current of PNP transistor or diode current, I0: constant (proportional to area), q: electron charge, k: Boltzmann constant.

  When the voltage gain of the operational amplifier AMP2 is sufficiently large due to the negative feedback by the operational amplifier AMP2, the potential of the node IM connected to the non-inverting input terminal of the operational amplifier AMP2 and the potential of the node IP connected to the inverting input terminal are Become (almost) equal and the circuit becomes stable.

  For example, if the gate width W of the PMOS transistor MP12 and the gate width W of the PMOS transistor MP13 are designed to be equal, the ratio of the magnitudes of the currents flowing through the PNP transistor Q1 and the PNP transistor Q2 is 1: 1.

  The emitter area of the PNP transistor Q2 is 10 times the emitter area of the PNP transistor Q1 (“× 1” and “× 10” attached to the PNP transistors Q1 and Q2 in FIG. 5 indicate the relative relationship of the emitter areas. .), The base and emitter voltage Vbe1 of the PNP transistor Q1, and the base and emitter voltage Vbe2 of the PNP transistor Q2 have the relationship shown in the equations (3) and (4) from the equation (2).

I = I0exp (qVbe1 / kT) (3)
I = 10 × I0exp (qVbe2 / kT) (4)
When dividing both sides and expressing as Vbe1−Vbe2 = ΔVbe, Expressions (5) and (6) are obtained.

10 = exp (qVbe1 / kT−qVbe2 / kT) (5)
ΔVbe = (kT / q) ln (10) (6)
That is, the difference between the base and emitter voltages of PNP transistor Q1 and PNP transistor Q2, ΔVbe is the logarithm (ln (10)) of the current density ratio 10 between PNP transistor Q1 and PNP transistor Q2, and the thermal voltage (kT / q). It is represented by Since ΔVbe is equal to the potential difference between both ends of the resistor RI1, a current of ΔVbe / RI1 flows through the resistor RI1 (the resistance value of the resistor RI1 is also represented by RI1).

Therefore, the current IMP12 flowing through the PMOS transistor MP12 (and the PMOS transistor MP13) is expressed by Expression (7).
IMP12 = ΔVbe / RI1 = (kT / q) ln (10) (1 / RI1) (7)
As is clear from the equation (7) and FIG. 5, the currents flowing through the PMOS transistors MP12 and MP13 are proportional to the absolute temperature.

Next, it will be described that the current flowing through the PMOS transistor MP22 of FIG. 5 becomes a current that decreases in proportion to the absolute temperature.
Due to the negative feedback of the operational amplifier AMP3, the potential of the node IP connected to the inverting input terminal of the operational amplifier AMP3 and the potential of the node NR2 connected to the non-inverting input terminal are substantially equal, and the circuit is stabilized. . Since the potential of the node NR2 becomes the potential of the node IP, the base-emitter voltage Vbe1 of the PNP transistor Q1 is applied to the resistor RI2. Since the current flowing through the resistor RI2 also flows through the PMOS transistor MP22, the current IMP22 flowing through the PMOS transistor MP22 is expressed by Expression (8) (the resistance value of the resistor RI2 is also expressed by RI2).

IMP22 = Vbe1 / RI2 (8)
Since the voltage Vbe decreases from the equation (1) in proportion to the absolute temperature, the equation (8) shows that the current flowing through the PMOS transistor MP22 decreases in proportion to the absolute temperature.

  Since the gate potential of the PMOS transistor MP12 is common to the gate potentials of the PMOS transistors MP14 to MP17, a current that increases in proportion to the absolute temperature tends to flow through the PMOS transistors MP14 to MP17.

  Since the gate potential of the PMOS transistor MP22 is the same as that of the PMOS transistors MP23 to MP26, a current that decreases in proportion to the absolute temperature tends to flow through the PMOS transistors MP23 to MP26.

  The PMOS transistors MP18 to MP21 and the PMOS transistors MP27 to MP30 to which the control signals CTC2 to CTC9 are respectively applied to the gates turn on the currents of the PMOSs (PMOS transistors MP14 to MP17 and PMOS transistors MP23 to MP26) that function as current sources. Works as a switch to turn off / on.

  Since the drains of the PMOS transistors MP18 to MP21 and the PMOS transistors MP27 to MP30 are all connected to the reference voltage VREF, the currents of the PMOS transistors MP14 to MP17 and the PMOS transistors MP23 to MP26 all flow to the reference voltage VREF, and the resistor RI3 Is converted into a voltage.

  That is, by controlling the control signals CTC2 to CTC9, the current that increases in proportion to the absolute temperature (PTAT current) and the current that decreases in proportion to the absolute temperature (CTAT current) are added, and the ratio of the addition is calculated. Can be changed.

  Therefore, when the current that increases in proportion to the absolute temperature is large, the temperature dependence of the reference voltage VREF is positive. When the current increasing in proportion to the absolute temperature is small, the temperature dependency of the reference voltage VREF is negative. By setting the control signals CTC <b> 2 to CTC <b> 9 to “L”, it is possible to control the current to flow into the reference voltage VREF.

  Based on such an operation principle, a reference voltage VREF having an arbitrary temperature dependency can be generated. FIG. 5 shows four cases in which the control signal and the PMOS transistor increase in proportion to the absolute temperature, and the current decreases in proportion to the absolute temperature. The configuration of the circuit in FIG. 5 may be expanded or changed so that a proper adjustment accuracy and range can be obtained.

Further, the control signals CTC2 to CTC9 may be generated based on the value of the setting register 25, for example.
<Modification>
Next, a modification of the bias generation circuit 23 will be described.

FIG. 6 is a diagram showing a modification of the bias generation circuit shown in FIG.
In the bias generation circuit 23, only a circuit portion for explaining a basic function is shown, but the bias generation circuit 23a is a circuit having a function of standby or stopping the oscillation circuit 1.

  Compared with the bias generation circuit 23, PMOS transistors MP31 and MP32 are added to the bias generation circuit 23a. By setting the gate signal PDX of the PMOS transistor MP31 to “L” and the gate signal PD of the PMOS transistor MP32 to “H”, it is possible to control the current not to flow through the reference resistor RE1. When the gate signal PDX becomes “L”, the PMOS transistor MP31 is turned ON. On the other hand, since the PMOS transistor MP32 is turned off, the gate potential of the PMOS transistor MP4 becomes the power supply voltage VCC, and the PMOS transistor MP4 is turned off. As a result, no current flows through the reference resistor RE1. At this time, it is desirable to stop the operational amplifier AMP1 and the reference voltage generation circuit 24 as necessary.

  When the gate signal PDX becomes “H” and the gate signal PD becomes “L”, the PMOS transistor MP31 is turned off and the PMOS transistor MP32 is turned on. As a result, the gate of the PMOS transistor MP4 is connected to the drain of the PMOS transistor MP4, and thus operates in the same manner as the bias generation circuit 23.

As described above, according to the oscillation circuit 1 of the present embodiment, the integrated circuit 2 generates the reference current based on the reference resistor RE1 and the reference voltage VREF provided outside.
By providing the reference resistor RE1 outside the integrated circuit 2, it is possible to avoid the disadvantages of the conventional circuit in which the temperature dependency of the resistor manufactured by the integrated circuit process built in the chip has a complicated dependency. The problem that the fluctuation of the absolute value of the resistor manufactured by the LSI process is large and the fluctuation of the absolute value is large, the problem that the temperature-dependent variation among samples can be avoided.

  By providing the reference resistor RE1 outside the integrated circuit 2, the variation in the absolute value of the reference resistor RE1 is improved. However, the temperature dependency of the reference resistor RE1 at the time of manufacturing the oscillator circuit 1 or at the time of designing the oscillator circuit 1 is improved. I can't know sex. For this reason, the temperature dependence of the reference voltage VREF is set by the setting register 25 after the component selection of the reference resistor RE1 is completed or after the component mounting of the reference resistor RE1 is completed. As a result, the value of the reference resistor RE1 for each oscillation circuit 1 can be adjusted, and the temperature dependence of the reference voltage VREF can be adjusted. Therefore, since it becomes possible to generate a reference current that is more stable with respect to temperature than in the conventional circuit, the temperature dependence of the oscillation frequency of the integrated circuit 2 that determines the oscillation frequency based on this reference current is further increased. Can be small.

  In order to reduce the temperature dependence of the reference current, it is preferable that the temperature of the reference resistor RE1 and the temperature of the circuit that generates the reference voltage VREF are substantially equal, and as close as possible to the chip on which the oscillation circuit 1 is mounted. In this embodiment, since the SIP is mounted with the reference resistor RE1 in the same package as the chip on which the integrated circuit 2 is mounted, the reference is not limited by the manufacturing process of the chip. It is possible to improve the accuracy of the resistance value of the resistor RE1 and the variation in temperature dependence, and to match the temperatures.

  In this embodiment, as an example, the reference current generation circuit is configured by the operational amplifier AMP1 and the NMOS transistor MN4. However, the circuit configuration of this part is not particularly limited, and various modifications are possible. .

Next, an oscillation circuit according to a second embodiment will be described.
Hereinafter, the oscillation circuit of the second embodiment will be described focusing on the differences from the first embodiment described above, and description of similar matters will be omitted.

  The oscillation circuit of the second embodiment is different from the oscillation circuit 1 of the first embodiment in the configurations of the reference voltage generation circuit and the constant voltage circuit. Specifically, the oscillation circuit according to the second embodiment generates a bandgap voltage (a constant voltage independent of temperature) using a reference voltage generation circuit. The constant voltage circuit according to the second embodiment creates the constant voltage VREG using this band gap voltage.

FIG. 7 is a diagram illustrating a reference voltage generation circuit according to the second embodiment.
The reference voltage generation circuit 24a is a circuit that adds an element to the reference voltage generation circuit 24 to simultaneously generate a bandgap circuit output. Specifically, compared to the reference voltage generation circuit 24, PMOS transistors MP33 and MP34 and a resistor RI4 are added to the reference voltage generation circuit 24a.

  As described in the first embodiment, the PMOS transistors MP14 to MP17 whose gate potential is the output AMPO2 of the operational amplifier AMP2 of the reference voltage generation circuit 24 have a current (PTAT current) that increases in proportion to the absolute temperature. Flows. On the other hand, a current (CTAT current) that decreases in proportion to the absolute temperature flows through the PMOS transistors MP23 to MP26 whose gate potential is the output AMPO3 of the operational amplifier AMP3.

  The PMOS transistor MP33 and the PMOS transistor MP34 cause the PTAT current and the CTAT current to flow into the resistor RI4, add the currents, and convert them into voltages, thereby generating the band gap voltage VBGR. By appropriately selecting the ratio of the PTAT current and the CTAT current, the component that increases in proportion to the absolute temperature cancels out the component that decreases in proportion to the absolute temperature, and a constant current that does not depend on temperature can be obtained. Since this is converted into a voltage by the resistor RI4, a band gap voltage VBGR independent of temperature can be obtained as an output potential.

Next, a constant voltage circuit according to a second embodiment will be described.
FIG. 8 is a circuit diagram showing a constant voltage circuit according to the second embodiment.
The constant voltage circuit 21a is a circuit that generates a constant voltage VREG from the band gap voltage VBGR obtained from the reference voltage generation circuit 24a, and includes an operational amplifier AMP4, a PMOS transistor MP35, and resistors RF1 and RF2.

  Since the potential of the band gap voltage VBGR and the potential of the node DIVO1 are equalized by the feedback control of the operational amplifier AMP4, the constant voltage circuit 21a stabilizes the circuit. Therefore, the constant voltage VREG is designed by designing the ratio of the resistors RF1 and RF2. Can be set to a desired value.

According to the oscillation circuit of the second embodiment, the same effect as that of the oscillation circuit 1 of the first embodiment can be obtained.
According to the oscillation circuit of the second embodiment, the circuit configuration in which a few circuit elements are added to the reference voltage generation circuit 24 generates the circuit for generating the reference voltage VREF and the band gap voltage VBGR. A reference voltage generation circuit 24a integrated with the circuit is obtained. Thereby, since the number of circuit elements can be reduced, it is possible to reduce the area occupied by the circuit necessary for configuring the integrated circuit.

  In the reference voltage generation circuit 24a, the current is added only by the PMOS transistor MP33 and the PMOS transistor MP34. However, as in the circuit portion that generates the reference voltage VREF, the band is obtained by adjusting the addition ratio by register setting. Correction when the gap voltage deviates from the design value is also possible, and it is useful to provide a register for correcting the band gap voltage separately from the setting register 25.

Next, the concept of the reference voltage generation circuit and the band gap circuit of the oscillation circuit of the present invention will be described.
FIG. 9 is a block diagram showing the concept of the reference voltage generation circuit and the band gap circuit of the oscillation circuit of the present invention. In the oscillation circuit 1b of FIG. 9, the same reference numerals are given to the same parts as those of the oscillation circuit 1, and the description thereof is omitted.

  The reference voltage generation circuit 24b includes a PTAT voltage generation circuit 241 that generates a voltage VPTAT that increases in proportion to the absolute temperature, a CTAT voltage generation circuit 242 that generates a voltage VCTAT that decreases in proportion to the absolute temperature, and a desired ratio. And an addition ratio setting circuit 243 for adding VPTAT and voltage VCTAT. The integrated circuit 2b includes an addition ratio setting circuit 27 that is provided outside the reference voltage generation circuit 24b and has the same function as the addition ratio setting circuit 243.

The addition ratio setting circuit 243 generates the reference voltage VREF by multiplying the voltage VPTAT and the voltage VCTAT by a coefficient and adding them.
The addition ratio setting circuit 27 generates a band gap voltage VBGR by multiplying the voltage VPTAT and the voltage VCTAT by a coefficient and adding them.

Each coefficient of the addition ratio setting circuit 243 and the addition ratio setting circuit 27 is controlled by a control signal CTC1 controlled by a value set in the setting register 25.
Based on the band gap voltage VBGR, the constant voltage circuit 21b generates a constant voltage VREG. The reference voltage VREF is supplied to the operational amplifier AMP1, generates a reference current, and is supplied to the circuit through the bias generation circuit 23.

  In this way, the circuit elements can be reduced by sharing the PTAT voltage generation circuit 241 and the CTAT voltage generation circuit 242 in the band gap circuit and the VREF generation circuit. If the circuit embodies the concept as shown in FIG. 9, the effect of reducing the number of elements can be obtained, and the circuit configuration at the transistor level is not limited to the reference voltage generation circuit 24a shown in FIG.

Next, an oscillation circuit according to a third embodiment will be described.
FIG. 10 is a circuit diagram illustrating an oscillation circuit according to the third embodiment.
Hereinafter, the oscillation circuit 1c according to the third embodiment will be described focusing on the differences from the first embodiment described above, and description of similar matters will be omitted.

The oscillation circuit 1c is different from the oscillation circuit 1 of the first embodiment in the configuration of the feedback circuit that generates the reference current.
The oscillation circuit 1c includes a PMOS transistor MP36 and a PMOS transistor MP37 instead of the NMOS transistor MN4, and an operational amplifier AMP5 instead of the operational amplifier AMP1. Further, a bias generation circuit 23 c is provided instead of the bias generation circuit 23.

The operational amplifier AMP5 is different from the operational amplifier AMP1 in that a reference voltage VREF is applied to its inverting input terminal.
The oscillation circuit 1c performs feedback control by the operational amplifier AMP5 so that the potential of the node NVR of the reference resistor RE1 matches the reference voltage VREF. When the potential of the node NVR becomes higher than the reference voltage VREF, the potential of the output node PG36 of the operational amplifier AMP5 becomes higher. Since the potential of the output node PG36 becomes higher, the current of the PMOS transistor MP36 decreases and the potential of the node NVR becomes lower. Conversely, when the potential of the node NVR becomes lower than the potential of the reference voltage VREF, the potential of the output node PG36 of the operational amplifier AMP5 becomes lower. When the potential of the output node PG36 decreases, the current of the PMOS transistor MP36 increases and the potential of the node NVR increases. As a result, the potential of the node NVR and the potential of the reference voltage VREF are substantially equal.

  By supplying the current flowing through the PMOS transistor MP36 to the bias generation circuit 23c by, for example, the PMOS transistor MP37 constituting the current mirror, the bias potential of the integrated circuit 2c can be generated based on the reference current.

FIG. 11 is a circuit diagram showing a configuration of a bias generation circuit according to the third embodiment.
By the feedback control of the operational amplifier AMP5, a reference current determined by the reference voltage VREF and the reference resistor RE1 flows through the PMOS transistor MP36. At this time, since the gate potential of the output node PG36 necessary for flowing the reference current to the PMOS transistor MP36 is determined, this reference current is adjusted by the mirror ratio by the current mirror circuit, and converted to the bias potential of the NMOS transistor NM5. Thus, the bias potentials PB1 and NB1 can be generated.

  Since the gate potential of the PMOS transistor MP36 (potential of the output node PG36) is supplied to the gates of the PMOS transistors MP5, MP7, and MP9, the control signal CMR1, CMR2, and CMR3 are controlled to flow to the NMOS transistor MN5. The current can be adjusted, whereby the absolute value of the oscillation frequency of the oscillation circuit 1c can be adjusted.

According to the oscillation circuit 1c of the third embodiment, the same effect as that of the oscillation circuit 1 of the first embodiment can be obtained.
The oscillation circuit of the present invention has been described based on the illustrated embodiment. However, the present invention is not limited to this, and the configuration of each part is replaced with an arbitrary configuration having the same function. can do. Moreover, other arbitrary structures and processes may be added to the present invention.

  Further, the present invention may be a combination of any two or more configurations (features) of the above-described embodiments.

1 is a circuit diagram illustrating an oscillation circuit according to a first embodiment. FIG. It is a figure which shows the relationship between the temperature dependence of a reference resistance, and the temperature dependence setting of a reference voltage. It is a figure which shows the relationship between the temperature dependence of a reference resistance, and the temperature dependence setting of a reference voltage. It is a circuit diagram which shows the structure of a bias generation circuit. It is a circuit diagram which shows the structure of a reference voltage generation circuit. FIG. 5 is a diagram showing a modification of the bias generation circuit shown in FIG. 4. It is a figure which shows the reference voltage generation circuit of 2nd Embodiment. It is a circuit diagram which shows the constant voltage circuit of 2nd Embodiment. It is a block diagram which shows the concept of the reference voltage generation circuit and band gap circuit of the oscillation circuit of this invention. It is a circuit diagram which shows the oscillation circuit of 3rd Embodiment. It is a circuit diagram which shows the structure of the bias generation circuit of 3rd Embodiment. It is a figure which shows the structure of the conventional CR oscillation circuit. It is a figure which shows the waveform of each part at the time of operation | movement of the circuit shown in FIG. It is a figure which shows the other structure of the conventional CR oscillation circuit.

Explanation of symbols

1, 1b, 1c Oscillation circuit 2, 2b, 2c Integrated circuit 21, 21a, 21b Constant voltage circuit 22 Constant current source 23, 23a, 23c Bias generation circuit 24, 24a, 24b Reference voltage generation circuit 25 Setting register 27, 243 Addition Ratio setting circuit 241 PTAT voltage generation circuit 242 CTAT voltage generation circuit AMP1 to AMP5 Operational amplifier C1, C2 Capacitance INV1 to INV3 Inverter MN1 to NM4 NMOS transistor MP1 to MP3 PMOS transistor N1 to N4 Node PAD1 Pad RE1 Reference resistance

Claims (3)

In the oscillation circuit mounted on the microcontroller,
A reference resistor for generating a reference current;
An operational amplifier circuit that is provided separately from the reference resistor and supplies a current to the reference resistor, a reference voltage generation circuit that determines a reference voltage to be applied to the reference resistor, and a constant voltage circuit that generates a constant voltage An integrated circuit that determines an oscillation frequency based on the reference current and the constant voltage;
A register in which a value for controlling the temperature dependency of the reference voltage output from the reference voltage generation circuit is set for each reference resistor so as to have the same temperature dependency as the temperature dependency of the reference resistor ;
I have a,
The oscillation circuit, wherein the reference voltage generation circuit sets a reference voltage using a value set in the register . The operational amplifier circuit performs feedback control so that the potential of one end of the reference resistor matches the potential of the reference voltage output by the reference voltage generation circuit,
According to the value set in the register, the temperature dependency of the reference resistor and the temperature dependency of the reference voltage generation circuit are matched,
Generating a reference current having a value obtained by dividing the reference voltage by a resistance value of the reference resistor;
2. The oscillation circuit according to claim 1, wherein the oscillation frequency is determined by the reference current and a capacitor having a constant signal amplitude. In the oscillation circuit mounted on the microcontroller,
A reference resistor for generating a reference current;
An operational amplifier circuit that is provided separately from the reference resistor and supplies a current to the reference resistor, a reference voltage generation circuit that determines a reference voltage to be applied to the reference resistor, and a constant voltage circuit that generates a constant voltage An integrated circuit that determines an oscillation frequency based on the reference current and the constant voltage;
A register for setting the temperature dependence of the reference voltage output from the reference voltage generation circuit so as to have the same temperature dependence as the temperature dependence of the reference resistance;
A PTAT voltage generation circuit for generating a voltage that increases in proportion to the absolute temperature;
A CTAT voltage generating circuit for generating a voltage which decreases in proportion to the absolute temperature, and possess,
The constant voltage circuit adds the output of the PTAT voltage generation circuit and the output of the CTAT voltage generation circuit at a rate such that the temperature dependency is zero, and the reference voltage generation circuit is connected to the PTAT voltage generation circuit. The output and the output of the CTAT voltage generation circuit are added at a rate such that the temperature dependence becomes 0, and the rate of addition of the output of the PTAT voltage generation circuit and the output of the CTAT voltage generation circuit is determined by the register. originating Fukairo you, characterized in that.

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