JP4982750B2 - Random number generator and method of creating random number generator - Google Patents

Description

  The present invention relates to a random number generator, and more particularly to a random number generator capable of generating a true random number based on a ring oscillator and a method for creating the random number generator.

  In simulation fields such as the Monte Carlo method, key generation, key exchange, and circuit masking in the cryptography and security fields, large numbers of random numbers and random numbers with good randomness are often required.

  Random numbers are roughly classified into true random numbers and pseudo-random numbers. True random numbers are random numbers that cannot be predicted and are not reproducible. Normally, random numbers are generated based on essentially random physical phenomena such as thermal noise and fission, and post-processing is performed after discretization and encoding. For this reason, since an analog circuit is required, an external circuit is often added. Since a special circuit is required outside, there are problems in terms of mounting density, low power consumption, and tamper resistance. Therefore, an attempt has been made to generate a true random number using only an FPGA (Field Programmable Gate Array) regardless of an external circuit.

  For example, in an example in which a random number is generated using an analog PLL (Phase locked Loop), the random number can be configured only by a specific FPGA equipped with the analog PLL.

  In addition, in the example of generating a random number by adding an external circuit consisting of a resistor and a capacitor to the outside of the FPGA, the random number can be generated regardless of the manufacturer of the FPGA and its type, but the generation of the random number is an external circuit. Therefore, if the additional circuit is removed, the generation of random numbers stops, and the generated random numbers can be sampled from the outside, so there is a problem in terms of security.

  On the other hand, a method of generating a true random number using an FPGA which is a programmable digital circuit and requiring no external circuit has been proposed (see, for example, Non-Patent Documents 1 and 2). Since a closed circuit can be configured inside the FPGA, it is useful in terms of tamper resistance, cost reduction, and a circuit as an IP (Intellectual Property) core. In Non-Patent Document 1, a random number generator using only a digital circuit and based on jitter caused by a plurality of ring oscillators is studied from a theoretical standpoint. In Non-Patent Document 1, CPLD (Complex Programmable Logic Device) and FPGA are also examined, but actual evaluation is not performed. Further, in Non-Patent Document 2, evaluation is performed by performing mounting limited to a specific condition.

On the other hand, an oscillation unit that oscillates by feeding back some of the cascaded logic gate outputs to the input side via a feedback resistor is supplied to the logic gate via a predetermined resistor. A random number generating integrated circuit characterized in that the predetermined resistor is laminated on the signal line through an insulating layer has already been disclosed (see, for example, Patent Document 1).
Japanese Patent No. 3650826 By B. Suner, W. Martin, and DRStinson, “A true random number generator with provable security and built-in attack resistance (A Provably Secure True Random Number Generator with Built-in Tolerance to Active Attacks) ”, March 29, 2006, http://www.cacr.math.uwaterloo.ca/~dstinson/papers/rng-IEEE.pdf “FPGA vendor agnostic True Random Number Generator” by D. Schellekens, B. Preneel, and I. Verbauwhede, “FPGA vendor agnostic True Random Number Generator” Proc. 16th International Conference on Field Programmable Logic and Applications (FPL 2006), August 28-30, Session M3.A Cryptographic Applications, http://www.cosic.esat.kuleuven.be/publications/article-790.pdf

The present invention is a delay circuit that actively uses wiring resources. The present invention aims to provide a true random number generator using a ring oscillator that also uses jitter of wiring resources and a method of creating the random number generator.

The present invention also relates to a delay circuit that actively uses wiring resources in a programmable integrated circuit. The present invention aims to provide a true random number generator using a ring oscillator that also uses jitter of wiring resources and a method of creating the random number generator.

In order to achieve the above object, a random number generator according to claim 1 of the present invention comprises at least one or more wiring resources in any or all of the logic elements of a ring oscillator composed of a plurality of logic elements. A ring oscillator provided with a delay circuit; and a sampling circuit connected to an output of the ring oscillator and extracting a jitter output at a predetermined sampling frequency , wherein the logic element is provided in a programmable integrated circuit In the integrated circuit, the wiring resource is composed of a local interconnect arranged in the vicinity of the logic element, a column interconnect extending in the column direction, and / or a row interconnect extending in the row direction. It is characterized by.

The random number generator according to claim 2 of the present invention is provided with a delay circuit composed of at least one or more wiring resources in any or all of the logic elements of a ring oscillator composed of a plurality of logic elements. A plurality of ring oscillators, connected to outputs of the plurality of ring oscillators, connected to an exclusive OR circuit for generating an exclusive OR output of the plurality of ring oscillators, and connected to an output of the exclusive OR circuit; A sampling circuit for extracting a jitter output at a predetermined sampling frequency , wherein the logic element is composed of a logic element provided in a programmable integrated circuit, and the wiring resource is in the vicinity of the logic element in the integrated circuit. A local interconnect, a column interconnect extending in the column direction, and / or Characterized in that consists of row interconnect extending in the row direction.

The random number generator according to claim 3 of the present invention is the random number generator according to claim 1 or 2, further comprising a post-processing circuit connected to the output of the sampling circuit and for processing the jitter output. It is characterized by providing.

According to a fourth aspect of the present invention, there is provided a method for creating a random number generator, comprising: a plurality of logic elements; a wiring resource for electrically connecting the logic elements; In a method for producing a random number generator in which a random number generator is provided in a programmable integrated circuit including at least an element, a ring oscillator forming step for forming at least one ring oscillator using the plurality of logic elements, and the ring oscillator A jitter generation step of providing a fixed-length wiring resource including at least one or more switching elements between one logic element and another logic element, and an output generated by the ring oscillator formation step and the jitter generation step Predetermined signal The method of creating a random number generator and a sampling extracting step of sampling extracted with ring frequency.

  According to the random number generator and the method of creating the random number generator of the present invention, a true random number can be generated.

Next, embodiments of the present invention will be described with reference to the drawings. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic and different from the actual ones. Moreover, it is a matter of course that portions having different dimensional relationships and ratios are included between the drawings.

Further, the embodiment described below exemplifies an apparatus and a method for embodying the technical idea of the present invention. The technical idea of the present invention is the arrangement of each component as described below. It is not something specific. The technical idea of the present invention can be variously modified within the scope of the claims.

[First embodiment]
The random number generator according to the first embodiment of the present invention is provided with a delay circuit composed of at least one wiring resource in any or all of the logic elements of a ring oscillator composed of a plurality of logic elements. A ring oscillator, and a sampling circuit connected to the output of the ring oscillator for extracting a jitter output at a predetermined sampling frequency.

A ring oscillator is a circuit that connects and oscillates a plurality of gates in a ring shape. Normally, odd-numbered NOT gates Q ₁ , Q ₂ ,..., Q _{2n + 1} (where n is an integer of 1 or more) are configured as shown in FIG. An oscillator based on a ring oscillator is strongly affected by temperature and external conditions, and is unstable and has a large jitter compared to a crystal oscillator.

In the random number generator according to the first embodiment of the present invention, as shown in FIG. 1 (b), an odd number of stages NOT gate Q _1, Q _2, ..., in addition to Q _{2n + 1,} the jitter As a generation source, a delay circuit D _n based on wiring resources is positively introduced and used for random number generation.

  The true random number generation circuit using the ring oscillator according to the first embodiment of the present invention performs post-processing for adjusting the bias of the noise source 14 and the noise source, adjusting the bit rate, and the like, as shown in FIG. Part 16.

  The noise source unit 14 may bundle the outputs of a plurality of ring oscillators with exclusive OR in order to increase the rate of jitter per unit time. Therefore, in the configuration example shown in FIG. A sum ring oscillator 10 is provided. Further, in order to generate a random number at a constant time interval, a sampling circuit 12 for sampling the output of the exclusive OR ring oscillator 10 at a constant frequency is provided. Instead of a plurality of ring oscillators, a single ring oscillator may be used as shown in FIG.

FIG. 2 shows an oscillation of a ring oscillator (type A: comparative example) in a case where a true random number generating circuit using a ring oscillator does not actively introduce a delay circuit D _n due to wiring resources as shown in FIG. FIG. 1 schematically shows a comparison between the waveform and the oscillation waveform of the ring oscillator (type B: the present invention) when the delay circuit D _n is actively introduced as shown in FIG. 1B.

In FIG. 2, a sampling waveform is also shown. In the true random number generation circuit using the ring oscillator according to the first embodiment of the present invention, the jitter interval is increased as j ₁ > j ₀ by positively introducing the delay circuit D _n using the wiring resources. At the same time, the oscillation period increases as T ₁ > T _0, and the ratio of the jitter interval to the oscillation period also increases as j ₁ / T ₁ > j ₀ / T ₀ .

  FIG. 3 shows an exclusive OR circuit that outputs the outputs of three ring oscillators in the noise source unit 14 in order to increase the rate of jitter per unit time in the random number generator according to the first embodiment of the present invention. 18 schematically shows an example of a waveform that is bundled at 18 to increase the ratio of jitter in all signals. Outputs of individual ring oscillators shown in FIGS. 3 (a) to 3 (c) are bundled by an exclusive OR circuit 18 and an output waveform having an increased jitter interval and jitter ratio is obtained as shown in FIG. 3 (d). Can be obtained.

  4 to 5 show various modifications of the configuration of the ring oscillator in the random number generation circuit according to the first embodiment of the present invention.

FIG. 4A shows a ring oscillator including three stages of NOT gates Q ₁ , Q ₂ , Q ₃ and a delay circuit D ₁ . FIG. 4B shows a ring oscillator comprising three stages of NOT gates Q ₁ , Q ₂ , Q ₃ and delay circuits D ₁ , D ₂ . FIG. 4C also shows a ring oscillator comprising three stages of NOT gates Q ₁ , Q ₂ , Q ₃ and delay circuits D ₁ , D ₂ , and shows an example in which the arrangement of the delay circuits D ₁ , D ₂ is changed. .

5A shows a plurality of odd-stage NOT gates Q _n−1 , Q _n , Q _{n + 1} ,... And delay circuits corresponding to the respective NOT gates D _n−1. , D _n , D _{n + 1} ,... 5B shows the NOT gates... Q _n−1 , Q _n , Q _{n + 1} ,... Of FIG. 5A from the p-channel transistor Q _A and the n-channel transistor Q _B. An example constituted by a CMOS inverter is shown. Each CMOS inverter is connected between the power supply voltage V _DD and the ground potential, and delay circuits... D _n−1 , D _n , D _{n + 1} ,. ing.

  Here, the wiring resources include not only wiring in the integrated circuit but also a plurality of logic elements (logic elements), switch circuits, and the like that are interposed between the buffer circuit and the route selection between the NOT gates.

In addition, NOT gates Q ₁ , Q ₂ ,..., Q _{2n + 1} are not only inverters but also in logic arrays, gate arrays, programmable gate arrays, or FPGAs described in detail in FIGS. A logic element is also included.

  In addition to a simple 1-input 1-output NOT gate, the NOT gate includes a case where a 2-input 1-output NAND gate is connected to be used as one input. An (XOR) gate or the like can also be used.

  Therefore, the wiring resources include not only wiring in these integrated circuits but also route selection between logic elements (logic elements) such as in a logic array, in a gate array, in a programmable gate array, or in an FPGA. In addition, a plurality of buffer circuits, a plurality of logic elements, a switch circuit, and the like interposed in the middle are also included.

  Therefore, the ring oscillator applied to the random number generator according to the embodiment of the present invention is not only a simple inverter chain but also actively intervenes wiring resources, in a logic array, in a gate array, in a programmable gate array, Alternatively, a circuit configuration in which logic elements in the FPGA or the like are connected in a ring shape is also included.

According to the random number generator according to the first embodiment of the present invention, the delay circuit positively using wiring resources And a true random number generator using a ring oscillator that also uses the jitter of the wiring resources can be provided.

[Second Embodiment]
The random number generator according to the second embodiment of the present invention is provided with a delay circuit including at least one wiring resource in any or all of the logic elements of a ring oscillator composed of a plurality of logic elements. Are connected to the outputs of the plurality of ring oscillators and the outputs of the plurality of ring oscillators, and are connected to the outputs of the exclusive OR circuits for generating the exclusive OR outputs of the plurality of ring oscillators and the outputs of the exclusive OR circuits. And a sampling circuit for extracting the jitter output at the sampling frequency.

  FIG. 6 shows a schematic circuit configuration of a random number generator according to a comparative example of the present invention. The noise source section is shown, and the post-processing section is omitted.

In the random number generator according to the comparative example shown in FIG. 6, a plurality of basic circuit configuration examples of the ring oscillator shown in FIG. 1A are arranged, and the outputs of the plurality of ring oscillators are bundled by the exclusive OR circuit 18. Further, the output signal of the exclusive OR circuit 18 is input to a D-type flip-flop circuit (D-FF) 20, and a random number is sampled at a constant frequency to generate a random number at a constant time interval, thereby obtaining a random number output. Here, as shown in FIG. 6, the length of the ring oscillator is defined as l, the number of ring oscillators is defined as k, and the sampling frequency is defined as f _S.

  FIG. 7 shows a schematic circuit configuration of a random number generator according to the second embodiment of the present invention. The noise source section is shown, and the post-processing section is omitted.

The random number generator according to the second embodiment of the present invention shown in FIG. 7 has the same configuration as the ring oscillator applied to the random number generator according to the first embodiment of the present invention shown in FIG. K examples are arranged, and outputs of k ring oscillators are bundled by an exclusive OR circuit 18. Further, the output signal of the exclusive OR circuit 18 is input to a D-type flip-flop circuit (D-FF) 20 and a random number is sampled at a sampling frequency f _S in order to generate a random number at regular time intervals to obtain a random number output. . In FIG _{7, A 1, A 2,} ..., A k, B 1, B 2 ,, B k, and _{C 1, C 2, ...,} 23 for displaying the C _k are each shows a NOT gate. An IC 22 is an interconnect indicating a wiring resource.

FIG. 8 shows a schematic circuit configuration of a random number generator according to a modification of the second embodiment of the present invention. In the example shown in FIG. 8, k configuration examples similar to the ring oscillator applied to the random number generator according to the first embodiment of the present invention shown in FIG. 5A are arranged, and the k ring oscillators are arranged. The output is bundled by the exclusive OR circuit 18. Further, the output signal of the exclusive OR circuit 18 is input to a D-type flip-flop circuit (D-FF) 20 and a random number is sampled at a sampling frequency f _S in order to generate a random number at regular time intervals to obtain a random number output. . In FIG. _{8, N 11, N 21,} ..., N k1, N 12, N 22, ..., N k2, ... and N _1n, N _2n, ..., to display the N _kn 23 shows both NOT gate . An IC 22 is an interconnect, and the wiring resource is the same as in FIG.

According to the random number generator according to the second embodiment of the present invention, the delay circuit positively using wiring resources Can be provided, and a ring oscillator that also uses wiring resource jitter can be configured in parallel to provide a true random number generator with an increased amount of jitter.

[Third embodiment]
(FPGA)
The random number generator according to the third embodiment of the present invention shows an example using only FPGA. In order to generate a true random number using only the FPGA, a ring oscillator is used as shown in the random number generator according to the first embodiment. In addition, a large number of ring oscillators are required to obtain the required randomness. In order to suppress an increase in circuit cost, the random number generator according to the third embodiment of the present invention uses a ring generator. A delay circuit using a wiring resource (interconnect) that generates jitter as a basis for random numbers is actively introduced into a part of the oscillator and used for generating a true random number.

  FPGA resources are composed of logic element resources including lookup tables and registers, and wiring resources. For example, as shown in FIG. 9, the basic unit of the FPGA is a logic array block (LAB) 25 in which 10 logic elements (LE) 24, which are the smallest circuit units, and a local interconnect arranged around the LAB 25. 26, a column interconnect (CL) 27 disposed around the local interconnect 26 and LAB 25 and extending in the column direction, and a row interconnect (RL) 28 disposed around the local interconnect 26 and LAB 25 and extending in the row direction. With.

  Programmable wiring in the FPGA can be realized by the local interconnect 26, the column interconnect (CL) 27, and the row interconnect (RL) 28. At the intersection of the column interconnect (CL) 27 and the row interconnect (RL) 28, a transistor switch is arranged, and jitter may exist there.

  The random number generator according to the third embodiment of the present invention uses a logic element (LE) 24, which is the smallest circuit unit of the FPGA, as a NOT gate, and a local interconnect 26 and a column interconnect between the NOT gates of the ring oscillator. A wiring resource (interconnect) composed of (CL) 27 and row interconnect (RL) 28 is inserted. With this configuration, the jitter of the oscillation waveform can be increased.

  For example, when wiring resources (interconnects) are not actively introduced, the LE 24 in the LAB 25 is configured as individual NOT gates, and each of them connected in a ring shape is parallelized, so that the comparison shown in FIG. A random number generator similar to the random number generator according to the example can be configured.

On the other hand, when actively introducing wiring resources (interconnects), for example, as shown in FIG. 10, the LEs 24 in separate LABs 25 indicated by INV1, INV2, and INV3 are configured as individual NOT gates. As shown by the dotted line and the solid line between them, the wiring resources (interconnects) connected in a ring shape are arranged in parallel, so that the random number generator according to the second embodiment of the present invention shown in FIG. Random number generators can be configured on the FPGA. That is, as shown in FIG. 7, a configuration example in which ring oscillator length l = 3 and ring oscillators with interconnects (ICs) 22 inserted in two places is parallelized can be realized using FPGA. As shown in FIG. 11, the FPGA includes a plurality of LABs 25 arranged in a matrix and a plurality of column interconnects extending in the column direction..., CL _i-4 , CL _i-3 , CL _i-2 , CL _{i- 1} , CL _i , CL _{i + 1} , CL _{i + 2} ,... And a plurality of row interconnects extending in the row direction, RL _i−1 , RL _i , RL _{i + 1} ,. Therefore, the wiring resources (interconnects) between the NOT gates can be arbitrarily selected by the route selection of the column interconnect and row interconnect on the FPGA. In FIG. 11, the local interconnect 26 is omitted.

  The number k of ring oscillators is, for example, k = 110 to 210 when the delay circuit due to the wiring resource (interconnect) is not actively introduced, whereas the delay circuit due to the wiring resource (interconnect) is positive. For example, when it is introduced in FIG.

  The random number generator according to the third embodiment of the present invention that effectively uses the wiring resource (interconnect) is compared with the random number generator according to the comparative example.

The random number generator according to the comparative example constitutes a ring oscillator as shown in FIG. 6, wherein the length of each ring oscillator is 1 = 3 and the number of ring oscillators is k = 20. The exclusive OR of the outputs of the 20 ring oscillators is sampled at the sampling frequency f _S = 50 MHz, and the output of the random number generator is obtained.

  A specific arrangement configuration example of the random number generator according to the third embodiment of the present invention is shown in FIGS. FIG. 13 shows a detailed arrangement configuration example on the FPGA in order to explain the route selection of FIG. Each of A, B, and C in FIGS. 12 and 13 corresponds to one NOT gate, and an interconnect is inserted between A and B and B and C by separating B by one.

  In the example of FIGS. 12 and 13, an interconnect having a wiring delay of 1.365 ns is inserted between A and B, and an interconnect having a wiring delay of 1.334 ns is inserted between B and C. As shown in FIG. 13, this wiring delay corresponds to the sum of three row interconnect units and three column interconnect units. The wiring delay between C and A is as small as 0.367 ns because it is within the same LAB 25.

(How to create a random number generator)
A method of creating a random number generator according to the third embodiment of the present invention is as follows, for example.

Random number generation in a programmable integrated circuit provided at the intersection of a plurality of LEs 24, wiring resources (interconnects) for electrically connecting the LEs 24, and the wiring resources (interconnects) and switching elements for switching the wirings In the method of creating a random number generator provided with a generator, (a) a ring oscillator forming step for forming at least one ring oscillator using a plurality of LEs 24, (b) one LE 24 constituting the ring oscillator and another LE 24 A jitter generation step of providing a fixed-length wiring resource including at least one or more switching elements in between, and (c) sampling the output signal generated by the ring oscillator formation step and the jitter generation step at a predetermined sampling frequency f _S Sampling extraction to extract And a step.

(Randomness evaluation method)
The random number generator can be evaluated based on the circuit area, the generation speed, and the randomness of the generated random number. The circuit area is determined by the required LE 24 of the FPGA, and the generation speed is determined by the circuit operating frequency. Randomness is evaluated from various statistical tests.

In the evaluation of the random number generator according to the third embodiment of the present invention, NISTSP 800-22 (http://csrc.nist.gov/publications/nistpubs/index.html: A Statistical Test Suite for Random and Pseudo- random number generators for Cryptographics Applications). For the test, the case of the circuit configuration of the comparative example as in FIG.
As in FIG. 7, the circuit configurations according to the embodiment of the present invention were compared at 1000 sumps (1,000,000 bits per sample) for each. The parameters used in the random number test are as shown in FIG. The parameters l = 3, k = 20, and f _S = 50 MHz were the same.

  Normally, a true random number generator uses a post-processing unit 16 as shown in FIG. 1C in order to generate a random number having better randomness, but here, a wiring resource (interconnect) is added. In order to see the difference in randomness due to the above, the random number generation output was directly applied to NISTSP 800-22 without going through the post-processing unit 16 and the statistical properties were examined.

(Randomness evaluation result)
Regarding the circuit area, both the random number generator according to the comparative example and the random number generator according to the third embodiment of the present invention had an LE number of 67. The generation speed was 50 Mbps from the sampling frequency f _S = 50 MHz for both the random number generator according to the comparative example and the random number generator according to the third embodiment of the present invention.

  The evaluation result of randomness is shown in FIG. FIG. 15 shows the significance (p-value) calculated for each test item, and the distribution degree (uniformity) of the value and the test pass rate (ratio) are summarized. In FIG. 15, for each test, ○ means pass and x means fail. With respect to the non-overlapping template test, when the template size is 9, the results obtained for 148 types of templates are represented by the number of accepted and rejected.

  As is clear from FIG. 15, neither the random number generator according to the comparative example nor the random number generator according to the third embodiment of the present invention has passed many tests. As described above, this is because the number k of ring oscillators is 20, and the ratio of generated jitter is small. However, it can be seen that the random number generator according to the third embodiment of the present invention using wiring resources (interconnect) clearly has a higher randomness than the random number generator according to the comparative example.

  In the random number generator according to the third embodiment of the present invention, details of the result of the non-overlapping template test are expressed as shown in FIG. FIG. 16 shows a case where different test results are obtained from 148 types of templates of the same test. As can be seen from FIG. 16, many template tests that did not pass in the random number generator according to the comparative example pass in the random number generator according to the third embodiment of the present invention. .

  In FIG. 16, neither the random number generator according to the comparative example nor the random number generator according to the third embodiment of the present invention passed the discrete Fourier transform (DFT) or Serial 2 test. However, it can be seen that the acceptance ratio (PROPORTION) of the random number generator according to the third embodiment of the present invention is improved.

  Depending on the application, there may be a surplus in the wiring resources (interconnect) on the FPGA. For this reason, the degree of freedom in circuit design can be improved by effectively utilizing the surplus wiring resources (interconnects).

  According to the random number generator according to the third embodiment of the present invention, it is possible to construct a true random number generator using a ring oscillator by actively utilizing wiring resources (interconnects) on the FPGA.

[Other embodiments]
As described above, the present invention has been described according to the first to third embodiments. However, it should not be understood that the description and drawings constituting a part of this disclosure limit the present invention. From this disclosure, various alternative embodiments, examples and operational techniques will be apparent to those skilled in the art.

In particular, in the random number generator according to the third embodiment of the present invention, an example in which FPGA is applied is disclosed, but the present invention is not limited to FPGA. Even if a gate array, a logic array, a programmable logic array, an ASIC, or the like is used, a true random number generator with increased jitter can be configured by actively utilizing wiring resources (interconnects).
The wiring resource (interconnect) includes not only wiring in the integrated circuit but also a plurality of logic elements, switch circuits, and the like that are interposed in the middle by route selection between NOT gates. The NOT gate includes not only a simple inverter but also a logic element in the logic array, the gate array, or the FPGA. Therefore, in the wiring resource (interconnect), not only the wiring in these integrated circuits but also a plurality of intermediately arranged by route selection between logic elements in such logic array, gate array, or FPGA. Also included are logic elements, switch circuits, and the like.

  Therefore, the ring oscillator applied to the random number generator according to the embodiment of the present invention is not only a simple inverter chain, but also actively intervenes wiring resources, and logic in the logic array, gate array, or FPGA. A circuit configuration in which elements are connected in a ring shape is also included.

Therefore, a true random number generator according to the embodiment of the present invention having a desired length l, a predetermined number k, and a predetermined sampling frequency f _S can be configured as a desired ASIC.

  As described above, the present invention naturally includes various embodiments that are not described herein. Therefore, the technical scope of the present invention is defined only by the invention specifying matters according to the scope of claims reasonable from the above description.

[How to use random number generator]
The random number generator according to the embodiment of the present invention can be used for, for example, key generation, key exchange, circuit mask, pachinko probability variation, and the like. By using this random number generator for key generation, etc., it is possible to generate keys with true random numbers, exchange keys, circuit masks, and change the probability of pachinko while effectively using the limited resources of programmable integrated circuits. It can be carried out.

  Although the embodiment of the present invention has been described as a random number generator, it can be used as a mere jitter generator by removing the sampling circuit from the random number generator. In this case, the present jitter generator can be used as a jitter generator for a sample used for inspecting measurement accuracy in a jitter measuring apparatus for measuring jitter.

(A) A basic circuit configuration example of a ring oscillator. (B) The basic circuit structural example of the ring oscillator which comprises the random number generator which concerns on the 1st Embodiment of this invention. (C) The typical block block diagram of the random number generator which concerns on the 1st Embodiment of this invention. In the true random number generating circuit using a ring oscillator, actively in the case of not introducing a delay circuit D _n-wired resources ring oscillator: delay and oscillation waveform diagram of the (Type A Comparative Example), due to aggressive interconnect resources circuits D _n FIG. 2 is an oscillation waveform diagram and a sampling waveform diagram of a ring oscillator (type B: the present invention) in the case of introducing the signal. In the random number generator according to the first embodiment of the present invention, in order to increase the rate of jitter per unit time, in the noise source unit, the outputs of the three ring oscillators are bundled by an exclusive OR circuit. FIG. 3A to FIG. 3C are diagrams schematically showing waveform examples that increase the rate of jitter in a signal, and FIG. 3D is an exclusive waveform diagram of each ring oscillator. OR circuit output waveform diagram. (A) Another configuration example of the ring oscillator constituting the random number generator according to the first embodiment of the present invention. (B) Still another configuration example of the ring oscillator constituting the random number generator according to the first embodiment of the present invention. (C) The structural example of another ring oscillator which comprises the random number generator which concerns on the 1st Embodiment of this invention. (A) The structural example of another ring oscillator which comprises the random number generator which concerns on the 1st Embodiment of this invention. (B) The structural example of another ring oscillator which comprises the random number generator which concerns on the 1st Embodiment of this invention. The structural example of the random number generator which concerns on the comparative example of this invention. The structural example of the random number generator which concerns on the 2nd Embodiment of this invention. The structural example of the random number generator which concerns on the modification of the 2nd Embodiment of this invention. The internal circuit block diagram of FPGA applied to the random number generator which concerns on the 3rd Embodiment of this invention. The example of an internal circuit structure of FPGA applied to the random number generator which concerns on the 3rd Embodiment of this invention. FIG. 10 is a layout configuration diagram of an FPGA LAB applied to a random number generator according to a third embodiment of the present invention. The circuit position figure in FPGA applied to the random number generator which concerns on the 3rd Embodiment of this invention. The detailed circuit position diagram in FPGA applied to the random number generator which concerns on the 3rd Embodiment of this invention. The parameter used in the statistical test of NISTSP 800-22 in the random number generator according to the third embodiment of the present invention. In the random number generator which concerns on the 3rd Embodiment of this invention, the test result by NISTSP800-22. The result of the Non-overlapping Template test in the random number generator concerning the 3rd embodiment of the present invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Exclusive OR ring oscillator 12 ... Sampling circuit 14 ... Noise source part 16 ... Post-processing part 18 ... Exclusive OR circuit (XOR)
20 ... D-type flip-flop (D-FF)
22 ... Interconnect (IC)
23 ... NOT gate 24 ... Logic element (LE)
25 ... Logic array block (LAB)
26 ... local interconnect _{27, ..., CL i-4} , CL i-3, CL i-2, CL i-1, CL i, CL i + 1, CL i + 2, ...... column interconnect 28, ..., RL _{i-1, RL i, RL} i + 1, ...... wax Interconnect _{Q 1, Q 2, ...,} Q n-1, Q n, Q n + 1, ..., Q 2n + 1 ..., A 1, A 2 _{, ..., A k, B 1} , B 2 ,, B k, and _{C 1, C 2, ...,} C k, N 11, N 21, ..., N k1, N 12, N 22, ..., N k2, ... and N _1n , N _2n , ..., N _kn ... NOT gate Q _A ... p-channel MOS transistor Q _B ... n-channel MOS transistors D ₁ , D ₂ , ..., D _n-1 , D _n , D _{n + 1} ... Delay circuits τ ₁ , τ ₂ ,..., Τ _n−1 , τ _n , τ _{n + 1} ... Delay time T ₀ , T ₁ .
j ₀ , j ₁ ... Jitter interval

Claims (4)

A ring oscillator in which a delay circuit composed of at least one wiring resource is provided in any or all of the logic elements of a ring oscillator composed of a plurality of logic elements;
A sampling circuit connected to the output of the ring oscillator and extracting a jitter output at a predetermined sampling frequency ;
The logic element is composed of a logic element provided in a programmable integrated circuit, and the wiring resource is a local interconnect disposed in the vicinity of the logic element in the integrated circuit, a column interconnect extending in a column direction, and A random number generator comprising a row interconnect extending in the row direction . A plurality of ring oscillators in which a delay circuit composed of at least one wiring resource is provided in any or all of the logic elements of the ring oscillator composed of a plurality of logic elements;
An exclusive OR circuit connected to the outputs of the plurality of ring oscillators and generating an exclusive OR output of the plurality of ring oscillators;
A sampling circuit connected to the output of the exclusive OR circuit and extracting a jitter output at a predetermined sampling frequency ;
The logic element is composed of a logic element provided in a programmable integrated circuit, and the wiring resource is a local interconnect disposed in the vicinity of the logic element in the integrated circuit, a column interconnect extending in a column direction, and A random number generator comprising a row interconnect extending in the row direction . The random number generator according to claim 1, further comprising a post-processing circuit connected to an output of the sampling circuit and processing the jitter output. A random number in which a random number generator is provided in a programmable integrated circuit that includes at least a plurality of logic elements, wiring resources that electrically connect the logic elements, and switching elements that perform wiring switching at the intersection of the wiring resources. In the generator creation method,
  A ring oscillator forming step of forming at least one ring oscillator using the plurality of logic elements;
  A jitter generation step of providing a fixed-length wiring resource including at least one or more switching elements between one logic element and another logic element constituting the ring oscillator;
  A sampling extraction step for sampling the output signal generated by the ring oscillator formation step and the jitter generation step at a predetermined sampling frequency;
  A method of creating a random number generator having

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