JP4971866B2 - Camera system - Google Patents

Description

  The present invention relates to a camera control device, and more particularly to a camera control device that is applied to, for example, a surveillance camera system and controls a video camera from the outside.

An example of this type of device is disclosed in Patent Document 1. According to this background art, a power supply device and a television camera are connected by a coaxial cable, and a vertical synchronization signal and a field identification signal are supplied from the power supply device to the television camera via the coaxial cable. A timing control unit provided in the television camera controls vertical synchronization and field synchronization based on a vertical synchronization signal and a field identification signal supplied from the power supply device.
JP-A-7-312700 [H04N 5/073, 5/225, 7/18]

  However, if it is assumed that a control signal is supplied to the TV camera via a coaxial cable in order to control the pan / tilt operation and zoom magnification of the TV camera from the power supply side, this control signal is erroneously given to the timing control unit. This may hinder accurate control of vertical synchronization or field synchronization.

  Therefore, a main object of the present invention is to provide a camera control device capable of stabilizing the synchronization establishment operation.

  The camera control device according to the present invention (14: reference numeral corresponding to the embodiment, hereinafter the same) defines capturing means (T1-T4) for capturing a video signal periodically output from the camera (12) and imaging timing. First supply means (66) for supplying a timing pulse to the camera, second supply means (601-604) for supplying a control pulse for controlling the imaging operation excluding the imaging timing to the camera, and a video signal captured by the capture means and the first Determining means (S43) for determining whether or not synchronization is established with the timing pulse supplied by the one supplying means, and activating the second supplying means when the determination result of the determining means is affirmative The control means (S31, S55) for stopping the second supply means when the determination result of the determination means is negative is provided.

  Video signals periodically output from the camera are captured by the capturing means. The first supply means supplies a timing pulse that defines the imaging timing to the camera, and the second supply means supplies a control pulse that controls the imaging operation excluding the imaging timing to the camera. It is determined by the determining means whether synchronization is established between the video signal captured by the capturing means and the timing pulse supplied by the first supplying means. The control unit starts the second supply unit when the determination result of the determination unit is positive, and stops the second supply unit when the determination result of the determination unit is negative.

  Therefore, the supply of control pulses is stopped in a state where synchronization is not established between the video signal and the timing pulse. When synchronization is established between the video signal and the timing pulse, supply of a control pulse is started. As a result, the control pulse does not interfere with the synchronization establishment operation in the camera, and the synchronization establishment operation is stabilized.

  Preferably, the capturing means captures the video signal through a coaxial cable (C1-C4). The first supply means and the second supply means supply the timing pulse and the control pulse through the coaxial cable, respectively.

  More preferably, the camera includes adjustment means (28p) for adjusting the imaging timing by the PLL method, and the first supply means supplies a timing pulse for the adjustment operation of the adjustment means.

  Preferably, the first creation means (62) creates the first timing pulse based on the video signal periodically output from the reference camera, and the second creation means (64) creates the second timing pulse internally. . The first supply means supplies one of the first timing pulse created by the first creation means and the second timing pulse created by the second creation means to the camera.

  The camera control program according to the present invention includes a capturing means (T1-T4) for capturing a video signal periodically output from the camera (12), and a first supplying means (66) for supplying a timing pulse defining the imaging timing to the camera. And a video signal captured by the capture means in the processor (68) of the camera control device (14) including the second supply means (601-604) for supplying the camera with a control pulse for controlling the imaging operation excluding the imaging timing. A determination step (S43) for determining whether synchronization is established with the timing pulse supplied by the first supply means, and the second supply means is activated when the determination result of the determination means is affirmative On the other hand, this is a camera control program for executing a control step (S31, S55) for stopping the second supply means when the determination result of the determination means is negative.

  The camera control method according to the present invention comprises a capturing means (T1-T4) for capturing a video signal periodically output from the camera (12), and a first supplying means (66) for supplying a timing pulse defining the imaging timing to the camera. , And a camera control method executed by a camera control device (14) provided with a second supply means (601-604) for supplying a control pulse for controlling an imaging operation excluding the imaging timing to the camera. A discriminating step (S43) for discriminating whether or not synchronization is established between the video signal to be outputted and the timing pulse supplied by the first supplying means, and the second supply when the discrimination result of the discriminating means is affirmative A control step (S31, S55) is provided for starting the means and stopping the second supply means when the determination result of the determination means is negative.

  According to the present invention, the supply of the control pulse is stopped when the synchronization is not established between the video signal and the timing pulse. When synchronization is established between the video signal and the timing pulse, supply of a control pulse is started. As a result, the control pulse does not interfere with the synchronization establishment operation in the camera, and the synchronization establishment operation is stabilized.

  The above object, other objects, features and advantages of the present invention will become more apparent from the following detailed description of embodiments with reference to the drawings.

  With reference to FIG. 1, the surveillance camera system 10 of this embodiment includes four surveillance cameras 121 to 124 that photograph different surveillance areas, and a camera driver 14 that drives the surveillance cameras 121 to 124.

  The composite video signal of the channel CH1 created by the surveillance camera 121 is given to the camera driver 14 through the coaxial cable C1, and the composite video signal of the channel CH2 created by the surveillance camera 122 is given to the camera driver 14 through the coaxial cable C2. The composite video signal of channel CH3 created by the surveillance camera 123 is given to the camera driver 14 through the coaxial cable C3, and the composite video signal of channel CH4 created by the surveillance camera 124 is given to the camera driver 14 through the coaxial cable C4. It is done.

  The 4-channel composite video signal thus supplied to the camera driver 14 is subjected to predetermined processing and then supplied to a DVR (Digital Video Recorder) 16 via coaxial cables C5 to C8. The composite video signal of the channel CH1 is supplied to the DVR 16 through the coaxial cable C5, and the composite video signal of the channel CH2 is supplied to the DVR 16 through the coaxial cable C6. The composite video signal of channel CH3 is supplied to DVR 16 via coaxial cable C7, and the composite video signal of channel CH4 is supplied to DVR 16 via coaxial cable C8.

  The camera driver 14 also provides each of the monitoring cameras 121 to 124 with a VP pulse for establishing synchronization between the monitoring cameras 121 to 124 and a control pulse for controlling operations such as pan / tilt and zooming. Here, the VP pulse is generated by the camera driver 14 so as to be common between the channels. On the other hand, the control pulse is generated by the DVR 16 for each channel and is given to the camera driver 14 via the coaxial cables C5, C6, C7, or C8.

  The VP pulse and control pulse for the channel CH1 are supplied to the monitoring camera 121 through the coaxial cable C1, and the VP pulse and control pulse for the channel CH2 are supplied to the monitoring camera 122 through the coaxial cable C2. Further, the VP pulse and the control pulse for the channel CH3 are given to the monitoring camera 123 through the coaxial cable C3, and the VP pulse and the control pulse for the channel CH4 are given to the monitoring camera 124 through the coaxial cable C4. Each of the monitoring cameras 121 to 124 controls the phase and frequency of each of the VD signal (vertical synchronization signal) and the HD signal (horizontal synchronization signal), that is, the shooting timing of each frame by PLL processing based on the VP pulse, The pan / tilt operation and zoom operation are controlled with reference. The operation of the DVR 16 is controlled by the controller 18.

  Each of the monitoring cameras 121 to 124 is configured as shown in FIG. The optical image in the monitoring area is irradiated on the imaging surface of the imaging device 22 through the zoom lens 20. The TG (Timing Generator) 26 gives a timing signal based on the VD signal (vertical synchronization signal) and the HD signal (horizontal synchronization signal) output from the SG (Signal Generator) 28 to the imaging device 22. As a result, the imaging surface is exposed every 1/30 seconds, and charges of a plurality of pixels generated by each exposure, that is, raw video signals are read out in a raster scanning manner. In this way, a video signal representing the object scene is output from the imaging device 22 at a frame rate of 30 fps.

  The camera processing circuit 30 performs processing such as color separation, white balance adjustment, YUV conversion, and NTSC encoding on the video signal output from the imaging device 22, and outputs the composite video signal on which the above-described VD signal, HD signal, and the like are superimposed. create. The created composite video signal is given to the connector CNCT through the pulse sampling circuit 32, and is output toward the camera driver 14 through one of the coaxial cables C1 to C4.

  The pulse sampling circuit 32 extracts the VP pulse and the control pulse given from the camera driver 14 to the connector CNCT through any one of the coaxial cables C1 to C4, and the control pulse erasing circuit 38 and the control pulse decoding circuit 42 extract these extracted pulses. Give to each of.

  The control pulse erasing circuit 38 specifies a control pulse overlapping period based on the VD signal from the SG 28 in order to erase the control pulse from the VP pulse and the control pulse given from the pulse sampling circuit 32, and erases the control pulse during this period. An operation (mask process) is executed. As a result, only the VP pulse is given to the selector 40. The selector 40 selects either the internal VP pulse generated from the VP pulse generating circuit 36 or the external VP pulse supplied from the control pulse erasing circuit 38, and applies the selected VP pulse to the SG 28. A PLL (Phase Lock Loop) circuit 28p provided in the SG 28 executes PLL processing with reference to a given VP pulse. As a result, synchronization is established between each of the VD signal and the HD signal generated by the SG 28 and the VP pulse.

  The control pulse decoding circuit 42 decodes the control pulse given from the pulse sampling circuit 32 and gives the decoded control signal to the CPU 44. The CPU 44 controls the pan head 46 and / or the driver 24 so as to execute the pan / tilt operation and the zoom operation according to the given control signal. The orientation of the imaging surface is defined by the pan head 46 and the position of the zoom lens 20 is defined by the driver 24.

  The camera driver 14 is configured as shown in FIG. The coaxial cables C1 to C4 are connected to the connectors T1 to T4, respectively, and the coaxial cables C5 to C8 are connected to the connectors T5 to T8, respectively.

  The composite video signal of the channel CH1 is given to the pulse erasing circuit 561 via the adder 521. The pulse erasure circuit 561 erases the VP pulse and the control pulse superimposed on the composite video signal, and the video output circuit 581 performs a predetermined output process on the composite video signal from the pulse erasure circuit 561. The processed video signal is applied to the connector T5.

  The composite video signal of the channel CH2 is subjected to the same processing as described above by the adder 522, the pulse erasing circuit 562 and the video output circuit 582, and the composite video signal of the channel CH3 is the adder 523, the pulse erasing circuit 563 and the video output circuit 583. The composite video signal of channel CH3 is subjected to the same processing as described above by the adder 524, the pulse erasing circuit 564, and the video output circuit 584.

    The synchronization separation circuit 501 separates the VD signal from the composite video signal of the channel CH1, and gives the separated VD signal to the control pulse extraction circuit 601. The control pulse extraction circuit 601 specifies a control pulse superposition period based on a given VD signal, and performs an extraction operation during this period. The control pulse given from the DVR 16 to the connector T5 is extracted by the control pulse extraction circuit 601 and given to the adder 521 via the adder 541. The control pulse applied from the DVR 16 to the connector T6 is extracted by the control pulse extraction circuit 602 during a period based on the VD signal separated from the composite video signal of the channel CH2 by the synchronization separation circuit 502. The extracted control pulse is supplied to the adder 522 via the adder 542.

  The control pulse applied from the DVR 16 to the connector T7 is extracted by the control pulse extraction circuit 603 during the period based on the VD signal separated from the composite video signal of the channel CH3 by the synchronization separation circuit 503. The extracted control pulse is given to the adder 523 via the adder 543. The control pulse applied from the DVR 16 to the connector T8 is extracted by the control pulse extraction circuit 604 during a period based on the VD signal separated from the composite video signal of the channel CH4 by the synchronization separation circuit 504. The extracted control pulse is supplied to the adder 524 via the adder 544.

  The control pulse extraction operation (output operation) by each of the control pulse extraction circuits 601 to 604 is turned on / off by the CPU 68. This on / off operation is executed with reference to the VD pulse output from each of the sync separation circuits 501 to 504. The control pulse is extracted (output) when the extraction operation is in the on state, and is not extracted (non-output) when the extraction operation is in the off state.

  When synchronization is established with five or more cameras, a composite video signal of a system to which other cameras are connected is supplied to the synchronization separation circuit 70 from a BNC connector (not shown). The motivation separation circuit 70 separates the VD signal from the captured composite video signal, and provides the separated VD signal to the VP pulse generation circuit 62 and the CPU 68. The VP pulse generation circuit 62 generates an external VP pulse that is synchronized with the applied VD signal, and supplies the generated external VP pulse to the selector 66. On the other hand, the VP pulse generation circuit 64 independently creates an internal VP pulse and gives the created internal VP pulse to the selector 66.

  The CPU 68 instructs the selector 66 to select the internal VP pulse when the VD signal is not output from the sync separation circuit 70, while instructing the selector 66 to select the external VP pulse when the VD signal is output from the sync separation circuit 70. . The selector 66 selects an internal VP pulse or an external VP pulse in accordance with an instruction, and applies the selected VP pulse to each of the adders 541 to 544. Adders 541 to 544 provide VP pulses from selector 66 to adders 521 to 524, respectively. As a result, the VP pulse and the control pulse are superimposed on the composite video signal.

  The SG 28 shown in FIG. 2 generates a VD signal every 16.68 milliseconds in a steady state (see FIG. 4A). The VP pulse creation circuit 62 shown in FIG. 3 creates an external VP pulse every 16.68 milliseconds based on such a VD signal (see FIG. 4B). The external VP pulse is output from the VP pulse generation circuit 62 at a timing immediately before the VD signal falls. The VP pulse generation circuit 64 also generates an internal VP pulse every 16.68 milliseconds.

  When a camera operation such as pan / tilt or zoom is performed on the controller 18, the DVR 16 generates a control pulse corresponding to the camera operation. The generated control pulse is superimposed on the coaxial cable C5, C6, C7 or C8 at the timing immediately after the VD signal rises (see FIG. 4C).

  FIG. 5A shows a signal waveform in a state where the synchronization is established between the composite video signal output from each of the monitoring cameras 121 to 124 and the VP pulse output from the camera driver 14 (steady state). As can be seen from FIG. 5A, the VP pulse and the control pulse are superimposed on the composite video signal with the VD signal interposed therebetween. While the pulse extraction circuit 32 shown in FIG. 2 extracts both the superimposed VP pulse and the control pulse, the PLL circuit 28 requires only the VP pulse. Therefore, in this embodiment, the control pulse erasing circuit 38 is provided in the preceding stage of the selector 40, and the mask process is executed in the period after the VD signal rises, that is, in the control pulse superposition period.

  However, during the synchronization establishment operation based on the VP pulse given from the camera driver 14 (transient state), there is no guarantee that the VP pulse is superimposed immediately before the falling edge of the VD signal, for example, as shown in FIG. As described above, the VP pulse is superimposed in the period in which the control pulse is to be superimposed. Then, the synchronization establishment operation may become unstable due to the extraction operation of each of the control pulse extraction circuits 601 to 604 shown in FIG. 3 and / or the erase operation of the control pulse erasure circuit 38 shown in FIG. . Therefore, in this embodiment, the extraction operation of the control pulse extraction circuits 601 to 604 and the erase operation of the control pulse erasure circuit 38 are turned off in the transient state. As a result, the synchronization establishment operation with reference to the external VP pulse is stabilized.

  CPU44 provided in each of the monitoring cameras 121-124 performs the process according to the flowchart shown in FIG. A control program corresponding to this flowchart is stored in a flash memory (not shown).

  First, initialization processing is executed in step S1. Specifically, the control pulse erase circuit 38 is commanded to turn off the control pulse erase operation, and the variable CNT_A is set to “0”. From the control pulse erasing circuit 38, the pulse extracted by the pulse extraction circuit 32 is output as it is.

  In step S3, it is determined based on the output from the control pulse erasing circuit 38 whether or not an external VP pulse has been detected. If “YES” here, the process proceeds to a step S 5 to request the selector 40 to select the output of the control pulse extraction circuit 38, that is, the external VP pulse. On the other hand, if NO, the process proceeds to step S7, and the selector 40 is requested to select the output of the VP pulse generation circuit 36, that is, the internal VP pulse. The PLL circuit 28p executes PLL processing with reference to the VP pulse selected by the selector 40. The VD signal and the HD signal are synchronized with the VP pulse from the selector 40.

  In step S9, the variable CNT_B is set to “0”, and in step S11, the cycle of the VD signal given from SG28 is measured. In step S13, it is determined whether or not the measured cycle is within the range of 16.68 ± 0.6 milliseconds. If “NO” here, it is considered that synchronization is not established between the VP pulse, the VD signal, and the HD signal, and the process returns to step S1.

  If “YES” in the step S13, the variable CNT_B is incremented in a step S15, and it is determined whether or not the variable CNT_B exceeds “3” in a step S17. If the variable CNT_B is “3” or less, it is considered that the synchronization establishment operation is not yet stable, and the process returns to step S11 for reconfirmation. If the variable CNT_B exceeds “3”, it is considered that the synchronization establishment operation is stable, and the process proceeds to step S19.

  In step S19, the variable CNT_A is incremented. In step S21, it is determined whether or not the variable CNT_A indicates “1”. If “NO” here, the process directly returns to the step S3, whereas if “YES”, the process returns to the step S3 through the steps S23 to S25. In step S23, a standby process of 8 seconds is executed, and in step S25, the control pulse erase circuit 38 is commanded to turn on the control pulse erase operation. As a result of the determination process in step S21, the processes in steps S23 to S25 are performed only once immediately after the synchronization establishment operation is stabilized.

  The CPU 68 provided in the camera driver 14 executes the channel CHN task (N: channel number) shown in FIGS. 8 to 9 for each channel. Since the number of channels assumed in this embodiment is four, the channel CH1 task to CH4 task are activated simultaneously. A control program corresponding to this flowchart is also stored in a flash memory (not shown).

  First, initialization processing is executed in step S31. Specifically, the control pulse extraction circuit 60N is commanded to turn off the control pulse extraction operation, and the variable CNT_AN is set to “0”. When the control pulse extraction operation is turned off, the control pulse superimposing operation on the composite video signal is also turned off.

  In step S33, it is determined whether or not a VD signal is output from the output of the synchronization separation circuit 70 (whether or not an external video signal is detected). If “YES” here, the process proceeds to a step S 35 to request the selector 66 to select the output of the VP pulse generation circuit 62, that is, the external VP pulse. On the other hand, if NO, the process proceeds to step S37 to request the selector 66 to select the output of the VP pulse generation circuit 64, that is, the internal VP pulse. A VP pulse selected by the selector 66 is superimposed on the composite video signal.

  In step S39, the variable CNT_B is set to “0”, and in step S41, the cycle of the VD signal given from the synchronization separation circuit 50N is measured. In step S43, it is determined whether or not the measured cycle falls within the range of 16.68 ± 0.4 milliseconds (0.4 milliseconds <0.6 milliseconds in step S13). If “NO” here, it is considered that synchronization is not established between the VP pulse selected by the selector 66 and the VD signal separated by the synchronization separation circuit 50N, and the process returns to step S31.

  If “YES” in the step S43, the variable CNT_BN is incremented in a step S45, and it is determined whether or not the variable CNT_BN exceeds “3” in a step S47. If the variable CNT_BN is “3” or less, it is considered that the synchronization establishment operation is not yet stable, and the process returns to step S41 for reconfirmation. If the variable CNT_BN exceeds “3”, it is considered that the synchronization establishment operation is stable, and the process proceeds to step S49.

  In step S49, the variable CNT_AN is incremented. In step S51, it is determined whether or not the variable CNT_AN indicates “1”. If “NO” here, the process directly returns to the step S33, whereas if “YES”, the process returns to the step S3 through the steps S53 to S55. In step S53, a standby process of 10 seconds (10 seconds> 8 seconds in step S23) is executed, and in step S55, the control pulse extraction circuit 60N is commanded to turn on the control pulse extraction operation. As a result of the determination process in step S51, the processes in steps S53 to S55 are executed only once immediately after the synchronization establishment operation is stabilized.

  As can be understood from the above description, the composite video signals periodically output from the monitoring cameras 121 to 124 are captured by the connectors T1 to T4. The captured composite video signal is subjected to output processing by the video output circuits 581 to 584. The selector 66 supplies VP pulses that define the imaging timing to the monitoring cameras 121 to 124, and the control pulse extraction circuits 601 to 604 supply control pulses that control the imaging operation excluding the imaging timing to the monitoring cameras 121 to 124. The CPU 68 determines whether synchronization is established between the composite video signal captured by the connectors T1 to T4 and the VP pulse supplied by the selector 66 (S43). The CPU 68 activates the control pulse extraction circuits 601 to 604 when the determination result is affirmative, and stops the control pulse extraction circuits 601 to 604 when the determination result of the determination means is negative (S31, S55).

  Therefore, the supply of the control pulse is stopped in a state where synchronization is not established between the composite video signal and the VP pulse. When synchronization is established between the composite video signal and the VP pulse, supply of the control pulse is started. Thereby, the control pulse does not disturb the synchronization establishing operation in the monitoring cameras 121 to 124, and the synchronization establishing operation is stabilized.

  In this embodiment, it is assumed that the four monitoring cameras 121 to 124 are controlled. However, the number of monitoring cameras is not limited to four, and may be one.

It is a block diagram which shows the structure of one Example of this invention. It is a block diagram which shows an example of a structure of the surveillance camera applied to the FIG. 1 Example. It is a block diagram which shows an example of a structure of the camera driver applied to the FIG. 1 Example. (A) is a waveform diagram showing an example of a VD signal, (B) is a waveform diagram showing an example of a VP pulse, and (C) is a waveform diagram showing an example of a control pulse. (A) is a waveform diagram showing an example of a composite video signal before external synchronization is established, and (B) is a waveform diagram showing an example of a composite video signal after external synchronization is established. It is a flowchart which shows a part of operation | movement of CPU applied to the FIG. 2 Example. FIG. 4 is a flowchart showing one portion of behavior of a CPU applied to the embodiment in FIG. 3; FIG. 11 is a flowchart showing another portion of behavior of the CPU applied to the embodiment in FIG. 3; FIG. 10 is a flowchart showing still another portion of behavior of the CPU applied to the embodiment in FIG. 3;

Explanation of symbols

10 ... surveillance camera system 12 ... surveillance camera 14 ... camera driver 16 ... DVR
DESCRIPTION OF SYMBOLS 22 ... Imaging device 28p ... PLL circuit 601-604 ... Control pulse extraction circuit 68 ... CPU

Claims (4)

A camera system comprising a camera and a camera control device for controlling the camera,
The camera control device includes:
First capture means for capturing an image signal is periodically outputted from the camera,
First supply means for supplying a timing pulse defining imaging timing to the camera;
Second supply means for supplying a control pulse for controlling an imaging operation excluding the imaging timing to the camera;
First determination means for determining whether synchronization is established between the video signal captured by the capture means and the timing pulse supplied by the first supply means, and the determination result of the first determination means is while starting the second supply means when it is positive, with a supply control means for stopping said second feeding means when the determination result of said first determining means is negative,
The camera
Second capturing means for capturing the timing pulse and the control pulse;
Invalidating means for executing an invalid operation for invalidating the pulse captured by the second capturing means for a predetermined period;
Imaging control means for controlling the imaging timing based on the timing pulse;
Operation control means for controlling an imaging operation excluding the imaging timing based on the control pulse;
Second determination means for determining whether synchronization is established between the video signal and the timing pulse; and
A camera system comprising: an invalidity control unit that activates the invalidation unit when the determination result of the second determination unit is affirmative, and stops the invalidation unit when the determination result of the second determination unit is negative . The first capturing means captures the video signal through a coaxial cable,
The camera system according to claim 1, wherein the first supply unit and the second supply unit supply the timing pulse and the control pulse through the coaxial cable, respectively. The camera includes adjustment means for adjusting the imaging timing by a PLL method,
The camera system according to claim 1, wherein the first supply unit supplies the timing pulse for the adjustment operation of the adjustment unit. A first creating means for creating a first timing pulse based on a video signal periodically output from the reference camera; and a second creating means for internally creating a second timing pulse;
The first supply unit supplies one of a first timing pulse generated by the first generation unit and a second timing pulse generated by the second generation unit to the camera. The camera system according to any one of the above.

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