JP4968516B2 - Device having a signal identification circuit - Google Patents

Description

  The present invention relates to an apparatus having a circuit for receiving a transmission signal modulated by quadrature amplitude modulation (QAM).

  In wireless communication systems, attention has been focused on MIMO technology that improves communication efficiency by using a plurality of transmission / reception antennas. A technique that can achieve the theoretically best demodulation quality in a MIMO communication receiver is MLD (Maximum Likelihood Detection). However, since MLD has a large calculation amount, various calculation amount reduction methods have been proposed.

  Patent Document 1 proposes a method of reducing the amount of calculation by approximating the “Euclidean distance between two points in an n-dimensional space” necessary for MLD processing by approximation.

  Non-Patent Document 1 discloses a technique (QRM-MLD) for reducing the amount of computation by making it possible to perform MLD processing in stages by QR decomposition of a channel matrix and narrowing down survival candidates at each stage of MLD processing. Has proposed.

On the other hand, in Patent Document 2, focusing on one transmission signal in the QRM-MLD method, the number of symbol candidates gradually decreases from the first stage to the fourth stage in the four-stage QRM-MLD. It has been pointed out that the accuracy of estimation is deteriorated by excessively narrowing down candidates narrowed down in the first stage. For this reason, it is described that the order of a plurality of received signals is rearranged and the determination is performed by the QRM-MLD method.
JP-A-2005-217506 JP 2006-121348 A K. J. et al. Kim and J.M. Yue, “Joint channel estimation and data detection algorithms for MIMO-OFDM systems,” in Proc. Thirty-Sixth Assymar Conference in Signals, Systems and Computers, pp. 1857-1861, Nov. 2002.

  Despite efforts such as Patent Document 1 and Non-Patent Document 1, the computational load of MLD processing in a high-speed communication mode such as 4 × 4 MIMO and 16QAM modulation is still enormous, which is an obstacle to practical application of LSI. Furthermore, it has been proposed to increase the calculation load again in order to suppress the degradation of transmission signal identification or determination accuracy by reducing the calculation load. In the development of an LSI for a MIMO communication receiver, How to reduce the calculation load is an important issue.

  One method for realizing processing that requires a large amount of computation with a small amount of hardware resources is to use a device whose circuit can be reconfigured. By dynamically reconfiguring the circuit, enormous operations can be executed in a time-sharing manner, and the hardware resources required for the operations can be reduced. However, in the communication field where real-time performance is strongly required, it is impossible to process all processes in a time-sharing manner, and a circuit for a communication receiver is mounted on a reconfigurable device with limited computing resources. It is important to reduce the amount of computation in parallel.

  On the other hand, if the evaluation based on the Euclidean distance is changed to an evaluation using an approximate evaluation function, in many cases, the amount of calculation is reduced and the identification accuracy of the transmission signal is deteriorated. Therefore, it is required to reduce the amount of calculation without degrading the accuracy of the Euclidean distance calculation.

One embodiment of the present invention is an apparatus including a signal identification circuit for identifying a transmission signal transmitted by QAM modulation. The signal identification circuit uses a reception signal that has received a transmission signal as a reception result, a plurality of transmission constellations that can be transmitted or a plurality of replicas respectively corresponding to a plurality of transmission constellations as a plurality of transmission signal component candidates, and a reception result and A distance calculation circuit that calculates the Euclidean distance between the plurality of transmission signal component candidates or the square thereof as an evaluation value is included. The distance calculation circuit further commonly executes at least a part of the calculation common to the transmission signal component candidates corresponding to the transmission constellation common to the real part (real part) among the plurality of transmission signal component candidates. A first arithmetic circuit and a plurality of transmission signal component candidates that perform at least a part of the operations common to the transmission signal component candidates corresponding to the transmission constellation that has a common imaginary part (imaginary part). 2 arithmetic circuits. The reception signal (reception signal vector (rotated reception signal vector)) obtained by performing signal conversion by multiplying the reception signal (vertical vector y) by the conjugate transpose matrix Q ^H of the unitary matrix Q is multiplied by the reception signal. z).

  The distance calculation circuit further includes a third calculation circuit that commonly executes at least a part of the calculation common to the transmission candidates corresponding to the transmission constellation having a common distance from the origin among the plurality of transmission signal component candidates. It is desirable to include.

  One form of the signal identification circuit is a circuit for separating a plurality of reception signals received by a plurality of reception antennas into a plurality of transmission signals transmitted from the plurality of transmission antennas by the QRM-MLD method. A plurality of signals (signal candidates) that can be transmitted from a plurality of transmission antennas each include a plurality of transmission signal components.

  The signal identification circuit acquires the evaluation value related to a first-stage transmission signal component candidate that is a part of the plurality of transmission signal component candidates, and includes a plurality of transmission signal components in the first-stage transmission signal component candidates that survive. A maximum likelihood determination circuit that performs multi-stage maximum likelihood determination, including adding an evaluation value by adding other second-stage transmission signal component candidates of the candidate. The maximum likelihood determination circuit includes a distance calculation circuit at each stage for calculating an evaluation value at each stage, and the distance calculation circuit at each stage targets a transmission signal component candidate added at each stage. 1 arithmetic circuit and 2nd arithmetic circuit are included.

  In this apparatus, the Euclidean distance calculation at each stage of QRM-MLD of 16QAM or more is comprehensively transformed, so that the amount of calculation can be greatly reduced without degrading the demodulation quality at all as compared with QRM-MLD. Therefore, it is possible to improve the manufacturing cost and power consumption of the LSI for mounting the signal identification circuit.

  The R matrix in the QRM-MLD scheme is an upper triangular matrix, and the diagonal component is composed only of the real part. The transmission signal component candidate added at each stage of the maximum likelihood determination circuit that performs multi-stage maximum likelihood determination corresponds to the diagonal component of the R matrix, the diagonal component of the R matrix and the added transmission signal component candidate, Is multiplied.

  One form of the first arithmetic circuit calculates the square of the difference between the product of the common real part of the diagonal component of the R matrix and the corresponding transmission signal component candidate and the real part of the other component required for the distance calculation One form of the second arithmetic circuit is a difference between the product of the common imaginary part of the diagonal component of the R matrix and the corresponding transmission signal component candidate and the imaginary part of the other component. Including a circuit for calculating the square of.

  That is, the first arithmetic circuit, except for the first stage, calculates the product of the real part of the received signal at each stage and the common part of the diagonal component at each stage of the R matrix and the corresponding transmission signal component candidate. And a circuit for calculating the square of the value obtained by subtracting the real part of the product of the transmission signal candidate selected in the previous stage and the non-diagonal component. Except for the first stage, the real part of the other components corresponds to the value obtained by subtracting the real part of the product of the transmission signal candidate and the off-diagonal component selected in the previous stage from the real part of the received signal at each stage. . In the first stage, the real part of the other component corresponds to the real part of the received signal.

  Further, the second arithmetic circuit, except for the first stage, calculates the product of the imaginary part of the received signal at each stage and the common imaginary part of the diagonal component at each stage of the R matrix and the corresponding transmission signal component candidate. And a circuit for calculating the square of a value obtained by subtracting the imaginary part of the product of the transmission signal candidate selected in the previous stage and the non-diagonal component. Except for the first stage, the imaginary part of the other components corresponds to the value obtained by subtracting the imaginary part of the product of the transmission signal candidate selected in the previous stage and the off-diagonal component from the imaginary part of the received signal at each stage. . In the first stage, the imaginary part of the other component corresponds to the imaginary part of the received signal.

  The distance calculation circuit at each stage further performs at least a part of the calculation common to the transmission signal component candidates corresponding to the transmission constellation having the same distance from the origin among the transmission signal component candidates added at each stage. It is desirable to include a third arithmetic circuit that executes in common.

  One form of the third arithmetic circuit is a circuit for calculating a transmission signal component candidate corresponding to a diagonal component of the R matrix by replacing a common distance from the origin with a constant, and an origin of other components required for the distance calculation. And a circuit for calculating the distance from the. One form of the first arithmetic circuit includes a circuit that multiplies the diagonal component and the real part of the other component, and the second arithmetic circuit includes the diagonal component and the imaginary part of the other component. And a circuit that multiplies.

  In other words, the third arithmetic circuit calculates a transmission signal component candidate corresponding to the diagonal component of the R matrix by replacing the common distance from the origin with a constant, and the real part of the received signal at each stage. A circuit that calculates the square of the value obtained by subtracting the real part of the product of the transmission signal candidate selected in the previous stage and the non-diagonal component, and the transmission signal candidate selected in the previous stage from the imaginary part of the reception signal in each stage And a circuit that calculates a square of a difference between values obtained by subtracting the imaginary part of the product of the non-diagonal component. The first arithmetic circuit includes a diagonal component and other components, that is, a difference between a real part of a product of a transmission signal candidate and a non-diagonal component selected in a previous stage from a real part of a received signal in each stage, And a circuit that multiplies. The second arithmetic circuit calculates the difference between the diagonal component and other components, that is, the imaginary part of the product of the transmission signal candidate selected in the previous stage and the non-diagonal component from the imaginary part of the received signal at each stage. , And a circuit for multiplying.

  By adding the third arithmetic circuit, the square calculation is unnecessary in the first arithmetic circuit and the second arithmetic circuit, and the square calculation can be reduced. On the other hand, the first arithmetic circuit and the second arithmetic circuit increase multiplication calculations. Therefore, it is preferable that the multiplication element is mounted on a device prepared in advance. An example of such a device is a reconfigurable device that can reconfigure a circuit by changing the connections of multiple elements, including multiplication elements.

  In the reconfigurable device, a circuit for executing a wide variety of applications can be simultaneously or time-divisionally mounted. Therefore, it is suitable for a device further having an application for outputting information including data obtained by the transmission signal identified by the signal identification circuit.

  Hereinafter, assuming that a 16QAM modulated signal is received and separated by 2048-point OFDM modulation and QRM-MLD of 4 × 4 MIMO and 1200 subcarriers, 16 candidates can be survived in all stages. The structure of embodiment is shown.

  FIG. 1 shows an example of a receiving system. This reception system 9 is a system for comparison with the reception system 1 of the embodiment shown in FIG. 2, and a distance calculation unit for a replica generation unit for generating transmission signal component candidates to calculate a square Euclidean distance. And shown in an independent state. The receiving system 9 includes four receiving antennas 2 and four A / D units 3 that digitize analog signals obtained by the respective antennas 2. The received signal is OFDM (Orthogonal Frequency Division Multiplexed) and has 1200 subcarriers. The reception system 9 includes four FFT units 4 for performing Fourier transform on the digital signal output from each A / D unit 3 and dividing the digital signal into 1200 subcarriers, and 16QAM modulation is performed for each subcarrier. The received signal is received by 4 × 4 MIMO and separated by the QRM-MLD method. The reception system 9 further includes a signal identification circuit 19 for identifying the signal of each subcarrier. The signal identification circuit 19 includes a QRM section 10 that performs QR decomposition and an MLD section 20 that estimates a transmission signal from a reception signal by the MLD method. The MLD section 20 estimates the transmission signal for each of the 1-1200 subcarriers. The signal obtained in this way is decoded by the decoder 6 to be converted into data, and is passed to the application 7 to be transmitted in an appropriate form such as an image, sound, character data, etc. via an appropriate medium such as a display, a speaker, or a printer. Is output.

  The QRM section 10 includes a channel estimation unit 11, a ranking unit 12, a sorting unit 13, a QR decomposition unit 14, and a signal exchange unit 15. The channel estimation unit 11 obtains a channel impulse response value or a channel estimation value based on a reception signal including a known pilot signal on both transmission and reception sides. Further, a channel matrix H having a channel estimation value as a matrix element is obtained.

  The ranking unit 12 ranks the plurality of received signals received in order of power. The sorting unit 13 rearranges the received signals in the order of the magnitude of power, or notifies the downstream unit of the order of arrangement.

The QR decomposition unit 14 determines the matrices Q and R so that the channel matrix H obtained by the channel estimation unit 11 is represented by the product of the unitary matrix Q and the upper triangular matrix R (H = QR). R is output. Signal converting unit 15, by multiplying the vertical vector y (y = (y0, y1 , y2, y3) T) conjugate transposed matrix ^{Q H} of the unitary matrix Q to the plurality of received signals SC0m~SC3m the component, Signal conversion is performed, and a received signal vector (rotated received signal vector) z (z = (z0, z1, z2, z3) ^T ) is output.

The MLD section 20 is a maximum likelihood determination circuit for identifying (determining and estimating) a transmission signal from the reception signal vector z by a maximum likelihood determination method (MLD method). In the MLD section 20, the square of the Euclidean distance between the received signal vector z and a plurality of transmission signal candidate replicas (replica symbols) is calculated as an evaluation value, and a transmission signal candidate having a small Euclidean distance is output as a transmission signal. To do. A received signal of 16QAM modulated 4 × 4 MIMO scheme has 65536 (16 × 16 × 16 × 16) transmission signal candidate vector candidates x (x = (x0, x1, x2, x3) ^T ) (transmission constellation). . The MLD section 20 calculates the Euclidean distance between the reception signal vector z and the transmission signal replica in the order of the transmission signal component candidates x3, x2, x1, and x0 of the transmission signal candidate vector x, and transmits the transmission signal component candidates in a survival manner. The transmission signal is identified by a method of narrowing down. That is, the MLD section 20 is a maximum likelihood determination circuit that performs maximum likelihood determination in multiple stages.

  Therefore, the MLD section 20 includes a first-stage distance calculation circuit 21 that calculates the Euclidean distance by paying attention to the component z3 of the reception signal vector z and the transmission signal component candidate x3, and the component z2 of the reception signal vector z. Focusing on the second stage distance calculation circuit 22 for calculating the Euclidean distance by paying attention to the transmission signal component candidates x3 and x2, the component z1 of the reception signal vector z, and the transmission signal component candidates x3, x2 and x1. The fourth stage of calculating the Euclidean distance by paying attention to the third stage distance calculation circuit 23 for calculating the Euclidean distance, the component z0 of the received signal vector z, and the transmission signal component candidates x3, x2, x1 and x0. A distance calculation circuit 24.

  Further, the MLD section 20 includes a likelihood output unit 25 that calculates the likelihood or likelihood of the last-stage surviving transmission signal candidates. The likelihood is expressed by a log likelihood ratio (LRR). The output of the likelihood output unit 25 indicates the result of separation or identification of the received signal, and the output is output to a decoder, for example, the turbo decoder 6.

  The first-stage distance calculation circuit 21 includes a replica generation unit 21a that generates a replica symbol for the transmission signal component candidate x3, and a distance calculation unit 21b that calculates a square Euclidean distance between the replica symbol and the reception signal component z3. I have. The replica generation unit 21a generates 16 replica symbols from the component r33 of the matrix R and the 16 transmission signal component candidates x3. In the MLD section 20, the first-stage distance calculation circuit 21 survives all transmission signal component candidates and provides them to the second-stage distance calculation circuit 22.

  The distance calculation circuit 22 in the second stage focuses on the received signal component z2. Since the components r22 and r23 of the matrix R are known, the number of transmission signal component candidates x3 is 16, and the number of transmission signal component candidates x2 is 16, the replica generation unit 22a at this stage generates replica symbols of 256 types of signal candidates. . The distance calculation unit 22b at this stage calculates the square Euclidean distance between these 256 replica symbols and the received signal component z2. Further, the distance calculation circuit 22 includes a selection circuit 22e, and selects 16 types of combinations of transmission signal component candidates at this stage in ascending order of the square Euclidean distance, and survives to the next stage.

  The third-stage distance calculation circuit 23 and the fourth-stage distance calculation circuit 24 have the same configuration. The third-stage distance calculation circuit 23 focuses on the received signal component z1. The components r11, r12, r13 of the matrix R are known, and the combinations of the transmission signal component candidates x2 and x3 are narrowed down to 16 in the previous stage. Further, the number of transmission signal component candidates x1 is 16. Therefore, the replica generation unit 23a at this stage generates 256 kinds of replica symbols of signal candidates, and the distance calculation unit 23b receives the 256 replica symbols and the received signal. The square Euclidean distance with the component z1 is calculated. The selection circuit 23e selects 16 combinations of transmission signal component candidates from the transmission signal component candidate combinations at this stage in ascending order of the square Euclidean distance, and survives them in the next stage.

  The fourth-stage distance calculation circuit 24 focuses on the received signal component z0. The components r00, r01, r02, r03 of the matrix R are known, and the combinations of the transmission signal component candidates x1, x2, and x3 are narrowed down to 16 in the previous stage. Further, there are 16 transmission signal component candidates x0. Therefore, the replica generation unit 24a at this stage generates 256 kinds of replica symbols of the signal candidates, and the distance calculation unit 24b receives these 256 replica symbols and the received signal. The square Euclidean distance with the component z0 is calculated. At this stage, four signal component candidates included in the signal candidates are prepared, and the selection circuit 24e selects and outputs 16 transmission signal candidates from the transmission signal candidates in ascending order of the square Euclidean distance.

  FIG. 2 shows a schematic configuration of a receiving system 1 according to one embodiment of the present invention. The receiving system 1 has almost the same configuration as the receiving system 9 of the comparative example. However, in the first-stage distance calculation circuit 21, the replica generation unit 21a and the distance calculation unit 21b are replaced with a composite type distance calculation unit 21x that integrates these functions. The same applies to the distance calculation circuits 22, 23, and 24 at other stages, and the replica generation unit and the distance calculation unit are replaced with composite type distance calculation units 22x, 23x, and 24x, respectively. In the composite type distance calculators 21x to 24x, a replica is generated using the fact that the real part and the imaginary part of the transmission constellation point of 16QAM modulation are known, and in particular, the diagonal component of the R matrix The generation of a replica related to is replaced with a constant operation, and is taken into a square Euclidean distance calculation circuit.

  FIG. 3 shows a transmission constellation point for 16QAM modulation. It is known that the I coordinate (imaginary part (imaginary part)) and Q coordinate (real part (real part)) take four types of values of ± 1 and ± 3. These transmission constellation points correspond to transmission signals for one antenna. The transmission signals for four antennas are four combinations of transmission constellation points, and can have a possibility of 65536 (= 16 to the fourth power). When the transmission constellation points are expressed as complex numbers, the transmission signals for four antennas are expressed as four-element complex vectors (vertical vectors).

  FIG. 4 shows the input / output specifications of the MLD section 20 (MLD process) in QRM-MLD. The input signals are a rotated received signal vector z (z = (z0, z1, z2, z3) [vertical vector]) and an upper triangular matrix R (R = (r00, r01,..., R33)). The output signal is the 16 most probable transmission signal vector candidates x (x = (x0, x1, x2, x3) [vertical vector]) and the log likelihood of each candidate. The log likelihood is the square Euclidean norm (square Euclidean distance) of the residual vector (z−R × x).

  FIG. 5 shows input / output specifications of the distance calculation circuit 21 which is the first stage. The input signal is a received signal component z3 and an R matrix component r33. The output signals are 16 types of transmission signal component x3 (transmission constellation point of transmission antenna 3) and partial log likelihood (square Euclidean distance corresponding to each candidate) L3 corresponding to each candidate. The partial log likelihood L3 is the log likelihood of only the transmission antenna No. 3, and is the square of the complex absolute value of the equation (z3-r33 × x3). As shown in FIG. 5, this equation can be interpreted as the calculation of the distance between the multiplication result of the diagonal component r33 of the R matrix and the transmission signal component x3 and the other component w3. There are 16 candidates for the transmission signal component x3 of the 16QAM modulation system as shown in FIG. In the composite type distance calculation unit 21x, the transmission signal component x3 is converted into a constant and is taken into the distance calculation circuit.

  FIG. 6 shows input / output specifications of the distance calculation circuit 22 which is the second stage. The input signals are the output signal of the first stage, the received signal component z2, and the R matrix components r22 and r23. The output signals are 16 sets of transmission signal component {x2, x3} pairs and partial log likelihood L2 corresponding to each candidate (log likelihood of only the second and third transmission antennas). As shown in FIG. 6, the expression for calculating the partial log likelihood L2 includes a portion that can be transformed into the calculation of the distance between the diagonal component r22 and the transmission signal component x2 of the R matrix and the other component w2. Yes. There are 16 candidates for the transmission signal component x2 of the 16QAM modulation system as shown in FIG. In the composite distance calculation unit 22x, the transmission signal component x2 is converted into a constant and is taken into the distance calculation circuit. There are 256 (16 × 16) types of candidates for the transmission signal component {x2, x3}, and the selection circuit 23e selects and outputs only 16 types having a small partial log likelihood.

  FIG. 7 shows the input / output specifications of the distance calculation circuit 23 as the third stage. The input signals are the output signal of the second stage, the received signal component z1, and the R matrix components r11 to r13. The output signals are 16 combinations of three combinations of transmission signal components {x1, x2, x3} and partial log likelihood L1 corresponding to each candidate (log likelihood of only transmission antennas 1 to 3). . As shown in FIG. 7, the expression for obtaining the partial log likelihood L1 includes a part that can be transformed into the calculation of the distance between the diagonal component r11 and the transmission signal component x1 of the R matrix and the other component w1. Yes. There are 16 candidates for the transmission signal component x1 of the 16QAM modulation system as shown in FIG. In the composite distance calculation unit 23x, the transmission signal component x1 is converted into a constant and is taken into the distance calculation circuit.

  There are theoretically 4096 (16 × 16 × 16) types of transmission signal component {x1, x2, x3}, but 16 types of signal component candidates {x2, x3} are already out of 256 types in the second stage. It is narrowed down to. Therefore, there are 256 (16 × 16) combinations of signal component candidates {x1, x2, x3} processed by the third stage. The third stage selects and outputs only 16 types having a small partial log likelihood L1 from among 256 types of transmission signal candidates by the selection circuit 23e.

  FIG. 8 shows the input / output specifications of the distance calculation circuit 24 as the fourth stage. The input signals are the output signal of the third stage, the received signal component z0, and the R matrix components r00 to r03. The output signals are 16 sets of candidates for the transmission signal vector x and log likelihood L0 corresponding to each candidate. As shown in FIG. 8, the equation for calculating the partial log likelihood L0 includes a portion that can be transformed into the calculation of the distance between the diagonal component r00 and the transmission signal component x0 of the R matrix and the other component w0. Yes. There are 16 candidates for the transmission signal component x0 of the 16QAM modulation system as shown in FIG. In the composite distance calculation unit 24x, the transmission signal component x0 is converted into a constant and is taken into the distance calculation circuit.

  Theoretically there are 65536 (16 × 16 × 16 × 16) types of transmission signal vectors x, but the transmission signal candidates {x1, x2, x3} have already been narrowed down to 16 out of 4096 types in the third stage. The transmission signal vector x candidates processed by the fourth stage are 256 (16 × 16) types. The fourth stage selects and outputs only 16 types having a low log likelihood from the 256 types of transmission signal vector x candidates by the selection circuit 24e.

  FIG. 9 is an internal configuration of the replica generation unit 21a and the distance calculation unit 21b of the first stage distance calculation circuit 21 of the reception system 9 of the comparative example. The signal z3re is the real part of the received signal component z3, the signal z3im is the imaginary part of the received signal component z3, and the signal r33re is the real part of the R matrix component r33. Due to the nature of QR decomposition, the imaginary part of the diagonal component of the R matrix is 0, so the imaginary part r33im of the component r33 does not exist. In the figure, box (-) is a subtracter, box (+) is an adder, and box (^ 2) is a squarer. The same applies to the other drawings. In the other drawings, the box (x) is a multiplier. A box (±) is a simultaneous adder / subtracter (an arithmetic unit that calculates both the sum and difference simultaneously).

  In FIG. 9, in the distance calculation circuit 21a, in order to calculate 16 types of partial log likelihoods according to the definition formula, 32 subtracters, 32 squarers, and 16 adders are used. For this reason, the number of arithmetic units is large and it is not suitable for practical use of LSI. Furthermore, it is necessary to use some adders and sign inverters in the left large frame.

  FIG. 10 shows an example of a composite distance calculation circuit 21x. This distance calculation circuit 21xa is a first calculation circuit that commonly executes a calculation common to transmission signal component candidates corresponding to transmission constellation points having a common real part x3re among the sixteen transmission signal component candidates x3. 31 and a second arithmetic circuit 32 that commonly executes a calculation common to transmission signal component candidates corresponding to transmission constellation points having a common imaginary part x3im among the sixteen transmission signal component candidates x3, And an individual calculation circuit 33 that calculates the calculation results of the first calculation circuit 31 and the second calculation circuit 32 for each transmission signal component candidate.

  In the figure, “× 2” written along the wiring means that the value of the wiring is doubled. The same applies to other drawings, where “× 8” represents 8 times and “× 16” represents 16 times. These power-of-two calculations can be realized simply by shifting the bit allocation of the signal wiring, and do not require a logic gate, and therefore are not regarded as an arithmetic unit.

  More specifically, the first arithmetic circuit 31 includes the real component x3re of the diagonal component r33 of the R matrix and the corresponding transmission signal component candidate x3, that is, -3, -1, 1 and 3, This is a circuit that calculates the square of the difference between the other component required for the distance calculation, that is, the real part w3re (ie, z3re) of the component w3 (ie, z3). The other component w3 at this stage is the component z3 of the received signal z.

  Further, the second arithmetic circuit 32 requires the imaginary part x3im of the diagonal component r33 of the R matrix and the corresponding transmission signal component candidate x3, that is, -3, -1, 1 and 3, and the distance calculation. This is a circuit for calculating the square of the difference between the other component, that is, the component w3 (ie, z3) and the imaginary part w3im (ie, z3im).

  Then, the individual arithmetic circuit 33 adds the square of the difference between the real part and the square of the difference between the imaginary part of each transmission signal component candidate x3 to add a partial log likelihood for each transmission signal component candidate x3. L3 is calculated. For this reason, in the distance calculation circuit 21xa shown in FIG. 10, four simultaneous adders / subtractors, 17 adders, and eight squarers are used and compared with the circuit shown in FIG. Cost can be greatly reduced.

  In order to compare the distance calculation circuit 21xa shown in FIG. 10 with the distance calculation circuit 21 shown in FIG. 9, it is easy to understand if each circuit is modified as shown in FIG. FIG. 11A is the same circuit as the distance calculation unit 21b of FIG. 9, and changes the appearance of the arithmetic unit arrangement. Two subtracters, two squarers, and one adder are combined into a SED (Square Euclidean Distance) calculation module 34, and 16 modules are arranged corresponding to 16QAM constellation points. In FIG. 11B, circuits 31b to 33b corresponding to the arithmetic circuits 31 to 33 in the distance arithmetic circuit 21xa of FIG. 10 are arranged so as to be easily compared with FIG. The arithmetic circuits 31b and 32b in FIG. 11B are slightly different from the arithmetic circuits 31 and 32 in FIG. 10, but “subtract negative values” and “add positive values” are the same. FIG. 11B shows substantially the same arithmetic circuit as FIG. 11 (a) and 11 (b) are compared, it can be seen that FIG. 11 (b) is an equivalent circuit in which common operations of the real part imaginary part of FIG. 11 (a) are summarized for each row and column. Recognize. Therefore, if FIG. 11 (a) and FIG. 11 (b) are interposed, while FIG. 10 is a circuit equivalent to FIG. 9, the amount of arithmetic units can be greatly reduced, the implementation in the terminal is facilitated, and the consumption It turns out that electric power can also be reduced.

  FIG. 12 shows another example of the composite distance calculation circuit 21x. This distance calculation circuit 21xb performs a part of the calculation common to the transmission signal component candidates corresponding to the transmission constellation points having the same real part x3re among the 16 transmission signal component candidates x3. Among the sixteen transmission signal component candidates x3, the second common circuit executes a part of the calculation common to the transmission signal component candidates corresponding to the transmission constellation points having the common imaginary part x3im. And an arithmetic circuit 52. Further, the distance calculation circuit 21x performs a common operation common to the transmission signal component candidates corresponding to the transmission constellation points having the same distance from the origin among the 16 transmission signal component candidates x3. An arithmetic circuit 53 is included.

  More specifically, the third arithmetic circuit 53 sets a common distance from the origin for the transmission signal component candidate x3 corresponding to the diagonal component r33 of the R matrix (as will be described later, 2, 10, 18). ), And a circuit 53b for calculating the distance from the origin of the other component w3 required for the distance calculation distance. Furthermore, the third arithmetic circuit 53 includes a circuit 53c that adds the outputs of the circuits 53a and 53b.

  The first arithmetic circuit 51 includes a circuit that multiplies the diagonal component r33re and the real part w3re (z3re) of the other component, and the second arithmetic circuit 52 includes the imaginary part of the diagonal component r33re and the other component. A circuit for multiplying by w3im (z3im) is included.

  Further, the distance calculation circuit 21xb multiplies the output of the first calculation circuit 51 and the output of the second calculation circuit 52 by a constant by the coordinates of the transmission signal component candidate x3, and the output of this circuit 55. And a circuit 56 for calculating the partial log likelihood L3 corresponding to each transmission signal component candidate x3 by adjusting the output of the third circuit 53.

  In FIG. 13, in order to explain the distance calculation circuit 21xb, the defining equation of the partial log likelihood L3 is equivalently transformed, and only the related terms of the transmission signal component x3 are extracted as PartA, PartB, and PartC. FIG. 14 shows a list of the values of the Part A, Part B, and Part C terms in FIG. 14 for each of the 16 types of transmission signal component candidates x3. The component candidate x3 itself can take 16 types of values, but the Part A term takes only 3 types of values of 18, 10, and 2. The Part B term and the Part C term take only four kinds of values of ± 2, ± 6. This indicates that the defining formula of the partial log likelihood L3 includes symmetry around the origin (Part A term) and row and column symmetry (Part B term and Part C term).

  FIG. 15 shows that 16 types of 16QAM modulation transmission constellation points can be divided into three groups symmetrical about the origin. Therefore, the 16 types of 16QAM modulation transmission constellation points have symmetry around the origin in addition to the symmetry of the imaginary part and the real part in the rows and columns shown in FIGS. If the distance is the third axis (R axis), three-dimensional display can be performed as shown in FIG.

  When the diagonal components r33re of the R matrix are arranged from (H0, V0) to (H3, V3) in correspondence with the constellation points, the points (H1, V1), (H1, V2), (H2, V1) And (H2, V2) take the same value “2” for the Part A term. For this reason, as shown in FIG. 16B, starting from the same arithmetic unit R1, the wiring may be extended toward the arithmetic units arranged at the respective constellation points. Similarly, points (H0, V1), (H0, V2), (H1, V3), (H2, V3), (H3, V2), (H3, V1), (H2, V0) and (H1, V0) ) Takes the same value “10” for the PartA term. Points (H0, V0), (H0, V3), (H3, V3) and (H3, V0) take the same value “18” for the Part A term.

  Therefore, as shown in FIG. 16 (c), at each constellation point, the partial log likelihood corresponding to each constellation point is obtained by adding the data coming from these H wiring, V wiring, and R wiring. L3 can be calculated.

  FIG. 17 is an R arithmetic circuit that outputs R1 to R3, and shows a third arithmetic circuit unit 53 that commonly executes arithmetic operations common to transmission signal component candidates corresponding to transmission constellations having a common distance from the origin. It is an example. FIG. 18 is a V operation circuit that outputs V0 to V3, and a first operation circuit 51 that commonly executes some of the operations common to the transmission signal component candidates corresponding to the transmission constellation points that share the real part. It is an example. Further, FIG. 19 is an H operation circuit that outputs H0 to H3, and is a second operation that commonly executes a part of operations common to transmission signal component candidates corresponding to transmission constellation points having common imaginary parts. 2 is an example of a circuit 52; The calculator (Neg) indicates that the sign is inverted.

  In the circuits of the levels shown in FIGS. 16 to 19, the R arithmetic circuit has two squarers, the six adders, the H arithmetic circuit and the V arithmetic circuit have two multipliers, four adders, and the entire constellation. Only 32 adders are required at a point. Therefore, compared with the circuit shown in FIG. 9, the amount of arithmetic units can be greatly reduced. For this reason, mounting in a terminal becomes easy and power consumption can be reduced.

  FIG. 20 is a circuit in which the third arithmetic circuit 53 shown in FIG. 17 is further optimized, and corresponds to the third arithmetic circuit 53 shown in FIG. In this circuit, the calculation around the Part A term is performed by a small number of arithmetic units. Therefore, the calculation around the Part A term corresponding to the 16 types of signal component candidates x3 can be performed at once using four adders and two squarers.

  FIG. 21 is a circuit in which the first arithmetic circuit 51 and the second arithmetic circuit 52 shown in FIGS. 18 and 19 are further optimized. The first arithmetic circuit 51 and the second arithmetic circuit shown in FIG. Circuits 52 and 55 are included. This circuit configuration is a circuit configuration in which operations around the Part B term and the Part C term are collectively performed by a small number of arithmetic units. Eight kinds of values are collectively calculated using three simultaneous adders / subtractors, two adders, and two multipliers. When the values (8 types) calculated by the circuit shown in FIG. 21 and the values (8 types) obtained by inverting these values are combined, 16 types of values corresponding to 16 types of transmission signal component candidates x3 are obtained.

  Note that the square value of the diagonal component r33re of the R matrix is not obtained by putting the component r33re in a squarer, but a value obtained in the middle of the QR decomposition process can be used, and without using a squarer. Can be processed. As a result, in the distance calculation circuit 12xb shown in FIG. 12, 16 types of partial log likelihoods L3 are collectively obtained using only two multipliers, two squarers, six adders, and 11 simultaneous adders / subtractors. Can be calculated. Compared with the circuit shown in FIG. 9, the number of arithmetic units can be greatly reduced. Furthermore, in the distance calculation circuit 12xb shown in FIG. 12, the same applies to the distance calculation circuit 12xa, but only mathematical equivalence deformation is performed and approximate calculation is not performed. Therefore, the quality of the partial log likelihood L3 obtained by these arithmetic circuits 12xa and 12xb is equivalent to that obtained from the arithmetic circuit shown in FIG.

  Thus, focusing on the first-stage distance calculation circuit 21 shown in FIG. 12, one embodiment of the present invention is an apparatus having a signal identification circuit for identifying a transmission signal transmitted by QAM modulation. The signal identification circuit is a circuit for separating a plurality of reception signals received by a plurality of reception antennas into a plurality of transmission signals transmitted from the plurality of transmission antennas, using a QRM-MLD method. The plurality of signals that can be transmitted from each include a plurality of transmission signal components, and the signal identification circuit acquires evaluation values relating to some first-stage transmission signal component candidates of the plurality of transmission signal component candidates; Multi-stage maximum likelihood determination, including adding an evaluation value by adding other second-stage transmission signal component candidates to the surviving first-stage transmission signal component candidates. Including the maximum likelihood decision circuit to perform. The maximum likelihood determination circuit includes a distance calculation circuit at each stage for calculating an evaluation value at each stage. The distance calculation circuit 21 in the first stage includes a circuit 53. The circuit 53 calculates a square of the real part (z3re) of the received signal and a square of the imaginary part (z3im) of the received signal. And a circuit that outputs a value obtained by multiplying the square of the real part of the diagonal component of interest in the first stage of the R matrix (r33re ^ 2) by the distance that can be taken from the origin, And a circuit for summing outputs of these circuits. Further, the distance calculation circuit 21 in the first stage includes a circuit 51 that multiplies the real part (r33re) of the diagonal component of interest in the first stage of the R matrix and the real part (z3re) of the received signal. , A circuit 52 that multiplies the real part (r33re) of the diagonal component of interest in the first stage of the R matrix and the imaginary part (z3im) of the received signal. Further, the distance calculation circuit 21 includes a circuit 55 that calculates the sum of H (imaginary part) and V (real part) in transmission candidates by shifting the outputs of the circuit 51 and the circuit 52 by the addition / subtraction bit. Further, the distance calculation circuit 21 includes a circuit 53 that adds the outputs of the circuit 53 and the circuit 55.

  FIG. 22 shows the internal configuration of the second stage distance calculation circuit 22. The distance calculation circuit 22 of the second stage has the 16 candidate transmission blocks 22w and the minimum 16 types of transmissions out of the partial log likelihood L2 of the combinations of the 256 types of transmission signal candidates x2 and x3 output from them. And a selection unit (leading candidate narrowing block) 22e for selecting signal candidates.

  The input of the candidate counting block 22w is 16 kinds of component candidates x3 output from the first stage distance calculation circuit 21, the corresponding partial log likelihood L3, and the unique input signal of the second stage distance calculation circuit 22. A received signal component z2 and R matrix components r22 and r23. Each candidate counting block 22w adds 16 types of component candidates x2 (constellation points in FIG. 3) to the given component candidate x3 to generate 16 types of component candidate pairs {x2, x3}. 16 types of partial log likelihood L2 corresponding to the pair candidates are calculated and output.

  The block configuration of the second-stage distance calculation circuit 22 shown in FIG. 22 is common to both the receiving system 9 of the comparative example shown in FIG. 1 and the receiving system 1 of the embodiment shown in FIG. In the receiving system 9 of the comparative example shown in FIG. 1, each candidate counting block 22w includes a replica generation unit 22a and a distance calculation unit 22b. In the receiving system 1 of the embodiment shown in FIG. 2, each candidate counting block 22w includes a composite type distance calculation unit 22x. In any case, the outputs of the candidate counting blocks 22w are the same, and the potential candidate narrowing block 22e may have a common internal configuration.

  FIG. 23 shows the internal configuration of the counting block 22w of the receiving system 9 of the comparative example. Here, the partial log likelihood L2 is obtained according to the definition formula for a combination of one type of component candidate x3 and 16 types of component candidates x2. The counting block 22w includes a replica generation unit 22a that generates replicas of 16 types of component candidates x2. The counting block 22w further includes a distance calculation unit 22b that calculates a partial log likelihood L2, and the distance calculation unit 22b and a calculation circuit 22b1 that performs calculation related to the component candidate x2 and a common part other than the component candidate x2 (others) Component) w2 (w2re and w2im) and an arithmetic circuit 22b2. The arithmetic circuit 22b1 for the component candidate x2 has the same configuration as the distance arithmetic unit 21b of the first stage distance arithmetic circuit 21 shown in FIG.

  FIG. 24 is an internal configuration of the counting block 22w of the receiving system 1 of the embodiment. The counting block 22w includes the composite distance calculation unit 22xb described with reference to FIG. The distance calculation unit 22xb includes a calculation circuit 22xb1 that performs a calculation related to the component candidate x2, and a calculation circuit 22xb2 that calculates a common part (other components) w2 other than the component candidate x2. The real part w2re of the other component w2 at this stage is a value obtained by subtracting the real part v2re of the product of the transmission signal candidate x3 selected in the previous stage and the off-diagonal component r23 from the real part z2re of the received signal. The imaginary part w2im of the other component w2 is a value obtained by subtracting the imaginary part v2im of the product of the transmission signal candidate x3 selected in the previous stage and the off-diagonal component r23 from the imaginary part z2im of the received signal. The same applies to the third and subsequent stages.

  The configuration of the arithmetic circuit 22xb2 is the same as that of the arithmetic circuit 22b2 shown in FIG. The configuration of the arithmetic circuit 22xb1 is the same as that of the distance arithmetic unit 21xb shown in FIG. 12, and includes a third arithmetic circuit 53, a first arithmetic circuit 51, a second arithmetic circuit 52, and the like. Therefore, detailed description of these circuits is omitted.

  In the circuit shown in FIG. 23, 32 subtracters, 32 squarers, and 32 adders are necessary to configure the arithmetic circuit 22b1. On the other hand, in the circuit shown in FIG. 24, two multipliers, two squarers, seven adders, and 11 simultaneous adders / subtracters are required to construct the arithmetic circuit 22xb1. Further, the second stage distance calculation circuit 22 includes 16 counting blocks 22w in order to perform parallel calculation of combinations of 256 types of component candidates. Therefore, the difference between the above computing units is very large, and greatly contributes to reduction in mounting area and power consumption.

  It should be understood by those skilled in the art that a circuit having the same configuration as the distance calculation unit 21xa shown in FIG. 10 can be applied instead of the calculation circuit 22xb1 shown in FIG.

  FIG. 25 shows the internal configuration of the third stage distance calculation circuit 23. The distance calculation circuit 23 in the third stage includes 16 candidate counting blocks 23w and the minimum 16 types of partial log likelihoods L1 of combinations of 256 types of transmission signal candidates x1, x2, and x3 output therefrom. And a selection unit (potential candidate narrowing block) 23e for selecting transmission signal candidates.

  The input of the candidate counting block 23w is a combination of 16 types of component candidates x2 and x3 output from the second stage distance calculation circuit 22, the corresponding partial log likelihood L2, and the third stage distance calculation circuit 23. A received signal component z1 which is a specific input signal, and R matrix components r11, r12 and r13. Each candidate counting block 23w adds 16 types of component candidates x1 (constellation points in FIG. 3) to the given combination of component candidates to generate 16 types of component candidate pairs {x1, x2, x3}. , 16 types of partial log likelihood L1 corresponding to 16 types of pair candidates are calculated and output.

  The configuration of the third stage distance calculation circuit 23 shown in FIG. 25 is the same as that of the second stage distance calculation circuit 22 described with reference to FIGS. FIG. 26 shows the internal configuration of the counting block 23w of the receiving system 9 of the comparative example. Here, the partial log likelihood L1 is determined according to the definition formula for a combination of one type of component candidate x2 and x3 and a combination of 16 types of component candidate x1. The counting block 23w includes a replica generation unit 23a that generates replicas of 16 types of component candidates x1. The counting block 23w further includes a distance calculation unit 23b that calculates a partial log likelihood L1, and the distance calculation unit 23b and a calculation circuit 23b1 that performs calculation related to the component candidate x1 and a common part other than the component candidate x1 (others) Component) w1 (w1re and w1im) to obtain an arithmetic circuit 23b2. The arithmetic circuit 23b1 for the component candidate x1 has the same configuration as the distance arithmetic unit 21b of the first stage distance arithmetic circuit 21 shown in FIG.

  FIG. 27 is an internal configuration of the counting block 23w of the receiving system 1 of the embodiment. The counting block 23w includes the composite distance calculation unit 23xb described with reference to FIG. The distance calculation unit 23xb includes an operation circuit 21xb1 that performs an operation related to the component candidate x1, and an operation circuit 23xb2 that calculates a common part (other components) w2 other than the component candidate x2. The configuration of the arithmetic circuit 23xb2 is the same as that of the arithmetic circuit 23b2 shown in FIG. The configuration of the arithmetic circuit 23xb1 is the same as that of the distance arithmetic unit 21xb shown in FIG. 12, and includes a third arithmetic circuit 53, a first arithmetic circuit 51, a second arithmetic circuit 52, and the like. The configurations and operations of these circuits are as described with reference to the circuits of the first stage and the second stage described above. Therefore, detailed description of these circuits is omitted. Those skilled in the art can understand that a circuit having the same configuration as the distance calculation unit 21xa shown in FIG. 10 can be applied instead of the calculation circuit 23xb1 shown in FIG. The configuration of the fourth stage distance calculation circuit 24 is also similar to the third stage distance calculation circuit 23, and a detailed description thereof will be omitted.

  In the MLD section 20, one portion (unit or circuit) to which the configuration of the distance calculation unit according to the present embodiment shown in FIG. 10 or FIG. There are 16 4-stage distance calculation circuits 22 to 24, respectively. Therefore, by applying the circuit of this embodiment, the number of arithmetic units can be greatly reduced. For this reason, the area which mounts the receiving system 1 can be reduced, and also power consumption can be reduced. Further, as shown in FIG. 12, the distance calculation unit (distance calculation unit, distance calculation circuit) 21xb and the distance calculation unit using the same configuration as this require a multiplier. Therefore, it is preferable that the reception system 1 is mounted on hardware in which a multiplier is prepared in advance, for example, an LSI. An example of such hardware is a reconfigurable device developed by the applicant.

  FIG. 28A shows an example of a reconfigurable device. This device 1 is a semiconductor integrated circuit device called DAPDNA developed by the present applicant. The device 100 includes a RISC core module 102 called DAP and a dynamic reconfigurable data flow accelerator 103 called DNA. In addition to the DAP 102 and the DNA 103, the device 100 includes a direct input / output interface 104 for the DNA 103, a PCI interface 105, an SDRAM interface 106, a DMA controller 107, other peripheral devices 108, and a high-speed connection for connecting them. Switching bus 109. The DAP 102 includes a debug interface 102a, a RISC core 102b, an instruction cache 102c, and a data cache 102d. The DNA 103 is used to reconfigure the PE matrix 110 by changing the function and / or connection of the PE matrix 110 in which the 376 PEs (PEs, processing elements) are arranged two-dimensionally and the PEs included in the PE matrix 110. A configuration memory 119 in which configuration data 118 is stored.

  The configuration memory 119 has a plurality of banks. For example, as shown in FIG. 28B, in the PE matrix 110, the first function (data flow, circuit design) 117a is configured by the configuration data 118 stored in the foreground bank. In addition, the second function 117b and the third function 117c are configured by configuration data stored in different background banks. By switching the bank of the memory 119, the second function 117b or the third function 117c is reconfigured in the PE matrix 110 instead of the first function 117a. The reconstruction of the PE matrix 110 is performed dynamically in one cycle, for example.

  A reconfigurable device (dynamic reconfigurable device) 100 has a plurality of functions (subfunctions) in which the receiving system 1 is time-divided including the functions of the decoder 6 and the application 7 as shown in FIG. So that the PE matrix 110 can be reconfigured in a time-sharing manner. With such use, an application that requires a large amount of hardware resources can be executed using the device 100 with a small amount of hardware resources.

  Also, as shown in FIG. 28 (d), the PE matrix 110 can be reconfigured to implement a plurality of functions in order to execute a receiving system or a plurality of types of applications having different receiving methods. Through such use, many applications can be executed using the common hardware (device) 100. Since this device 100 can be implemented by switching many functions at a data flow level (data path level, hardware level) instead of a program level (instruction level), the function of the receiving system 1 is comparable to that of dedicated hardware. Processing can be done at speed.

  FIG. 29 shows a specific arrangement example of PEs included in the PE matrix 110. Among PEs shown in FIG. 29, PEs beginning with “EX” include an arithmetic operation called an EXE element, a logical operation, and a 2-input comparison function. Furthermore, “EXC” has a CMPSB instruction, “EXF” has an FF1 instruction, “EXM” has a multiplication instruction, “EXR” has a BREV instruction, and “EXS” Each type includes a calculation function unique to the BSWAP instruction.

  PEs beginning with “DL” are delay elements, and can each set a delay of 1-8 clocks. “DLE” is for data delay within a segment, “DLV” is for data transmission / reception between vertical segments, “DLH” is for data transmission / reception between horizontal segments, and “DLX” is It is an element for data transmission / reception between vertical and horizontal segments.

  The PE matrix 110 further includes “RAM”, an internal DNA memory, “LDB”, an internal DNA buffer for data input, “STB”, an internal DNA buffer for data output, and address generation for the internal DNA buffer. “C16E” element, “C32E” address generation element for external memory space, “LDX” data input element from DNA direct I / O, and data output element to DNA direct I / O “STX” is arranged.

  FIG. 30 illustrates a schematic configuration of an EXE element (“EXM”) including an ALU 111a, a MUL (16 × 16) 111b, an FF 111c, and the like as an example of a PE. This EXM is configured to execute an arithmetic operation, a logical operation, a two-input comparison function, or a multiplication instruction or a compound instruction based on the configuration data 118 stored in the configuration memory 119 of the DNA 103. it can. In addition, since a plurality of FFs 111c are built in, it is possible to control the latency from data input to output to the element PE.

  The PE matrix 110 includes a plurality of PEs and a routing matrix (wiring group) 120 for connecting them. The connection of PEs by the routing matrix 120 can be controlled by the configuration data 118. Therefore, the PE matrix 110 has different circuits (data paths) by changing the function of each of the plurality of PEs and / or changing the connection of at least a part of the routing matrix 120 according to the configuration data 118. , Data flow) can be reconfigured. For this reason, the PE matrix 110 can be mounted with a circuit for configuring the reception system 1 described above. When the resource becomes insufficient, the functions are mounted in a time division manner. If there is a surplus of resources, it is possible to implement other functions and share resources.

  The configuration relating to the distance calculation of the present invention is effective for a signal identification circuit for identifying a transmission signal transmitted by QAM modulation, and can be applied to 64 QAM in the same manner as 16 QAM. Further, the number of arithmetic units can be reduced more than the circuit for identifying the transmission signal of 16QAM, and a great effect can be obtained. The 64QAM case will be described below.

  FIG. 31 shows a transmission constellation point for 64QAM modulation, and corresponds to FIG. It is known that the I coordinate (imaginary part) and the Q coordinate (real part) take eight values of ± 1, ± 3, ± 5, and ± 7. Therefore, by paying attention to the symmetry of the coordinates of these constellation points and / or the symmetry around the origin, it is possible to reduce the number of calculators necessary for the circuit that calculates the log likelihood as described above.

  In particular, when the partial log likelihood is calculated according to the definition formula for 64QAM modulation as in the distance calculation circuit shown in FIG. 9, only the first stage distance calculation circuit is compared with the circuit shown in FIG. 4 times as many arithmetic units are required. In 16QAM modulation, 16 sets of Euclidean distance calculations may be performed in the first stage distance calculation, whereas in 64QAM modulation, 64 sets of Euclidean distance calculations must be performed in the first stage distance calculation. In the distance calculation circuits in the second to fourth stages, it is necessary to perform Euclidean distance calculation several times to several tens of times depending on the number of combinations of transmission signal candidates that can survive.

  In FIG. 32, for all constellation points of 64QAM modulation, the partial log likelihood definition equation is equivalently transformed as shown in FIG. 13, the related terms of the transmission signal component x3 are extracted, and these Part A terms and Part B terms are extracted. And a part table showing what values the PartC term is. There are 64 types of constellation points, but the Part A term takes only nine types of values 98, 74, 58, 50, 34, 26, 18, 10, and 2, and the Part B and Part C terms are ± 14, ± 10. , ± 6, ± 2 only 8 values.

  FIG. 33 is an example of a circuit structure that performs operations around the Part A term in the case of 64QAM modulation, and is a circuit corresponding to the third operation circuit 53 shown in FIG. 20 for 16QAM modulation. In the third arithmetic circuit 53 of 64QAM modulation, nine types of operations around the Part A term can be performed with six adders, two simultaneous adders / subtractors, and two squarers.

  FIG. 34 shows an example of a circuit structure that performs operations around the Part B term and the Part C term in the case of 64QAM modulation. The 16 QAM modulation includes the first arithmetic circuit 51 and the second arithmetic circuit 52 shown in FIG. , And a circuit 55 that performs constant multiplication and adjustment according to the coordinates of the signal component candidate x3. Even in the case of 64QAM modulation, 32 types of values can be obtained with 15 simultaneous adders / subtractors, 1 adder, 1 subtractor, and 2 multipliers.

  FIG. 35 is a circuit configuration of the distance calculation circuit 21 of the first stage of the MLD section 20 in the case of 64QAM modulation, and is a diagram corresponding to FIG. 12 for 16QAM modulation. With a small number of calculators, 64QAM partial log likelihood L3 can be calculated. In particular, the number of multipliers and squares may be the same in the MLD section for 16QAM modulation and the MLD section 20 for 64QAM modulation.

  As described above, several examples of the embodiment of the present invention have been described for the cases of 4Q4 MIMO 16QAM and 64QAM. The circuit structures shown above are only some examples of embodiments of the present invention, and the present invention is not limited to these circuit structures.

The figure which shows schematic structure of the receiving system of a comparative example. The figure which shows schematic structure of the receiving system of embodiment. A list of transmission constellation points at the time of 16QAM modulation. This is an input / output specification of MLD processing in 4 × 4 MIMO QRM-MLD, and indicates input / output of an MLD section. Input / output specification of the distance calculation circuit of the first stage of the MLD section. Input / output specification of the distance calculation circuit of the second stage of the MLD section. Input / output specifications of the third stage distance calculation circuit in the MLD section. Input / output specification of the distance calculation circuit in the fourth stage of the MLD section. The schematic structure of the 1st stage of the receiving system of a comparative example. 1 is a schematic configuration example of a distance calculation circuit of a reception system according to an embodiment. 11A and 11B are views for explaining the configuration of the first stage shown in FIG. The schematic structure of the other example of the distance calculating circuit of the receiving system of embodiment. It is a figure for demonstrating the distance calculating circuit shown in FIG. 12, and is a figure which shows a mode that the calculation formula of logarithmic likelihood is equivalently deformed. 14 is a list of values that can be taken by the Part A to C terms in the formula shown in FIG. 13. The figure which shows the symmetry around the origin of the transmission constellation point at the time of 16QAM modulation. FIG. 16A is a diagram for explaining the distance calculation circuit shown in FIG. 12, and FIG. 16A is a diagram showing the symmetry (commonality) of coordinates and the symmetry (commonality) around the origin; FIG. 16B is a diagram showing the commonality around the origin, and FIG. 16C is a diagram showing combinations of computing units at the constellation points. The figure which shows an example of the circuit calculated paying attention to the commonality around the origin. The figure which shows an example of the circuit calculated paying attention to the commonality of a real part. The figure which shows an example of the circuit calculated paying attention to the commonality of an imaginary part. FIG. 15 is a diagram illustrating an example of a circuit that performs calculations around the Part A term in FIG. 14, that is, pays attention to the commonality around the origin. FIG. 15 is a diagram showing an example of a circuit that performs calculations around Part B and C terms in FIG. 14, that is, calculations by paying attention to the commonality between the real part and the imaginary part. The figure which shows the structure of the distance calculation circuit of the 2nd stage of an MLD section. The figure which shows an example of the internal structure of the candidate count block of the 2nd stage of a comparative example. The figure which shows an example of the internal structure of the candidate count block of the 2nd stage of embodiment. The figure which shows the structure of the distance arithmetic circuit of the 3rd stage of an MLD section. The figure which shows an example of an internal structure of the candidate count block of the 3rd stage of a comparative example. The figure which shows an example of the internal structure of the candidate count block of the 3rd stage of embodiment. FIG. 28 (a) shows a schematic configuration of an example of a reconfigurable device, FIG. 28 (b) shows a schematic of the PE matrix, and FIGS. 28 (c) and 28 (d) show the PE matrix. The state of dynamic reconfiguration is shown. The figure which shows the type of PEs arrange | positioned at PE matrix. The figure which shows an example of PE containing a multiplier. A list of transmission constellation points at the time of 64QAM modulation. FIG. 14 is a list of values that can be taken by the Part A to C terms in FIG. 13 during 64 QAM modulation. The figure which shows an example of the circuit which pays attention to the calculation of the periphery of PartA term at the time of 64QAM modulation, ie, paying attention to the commonality around the origin. The figure which shows an example of the circuit which computes paying attention to the calculation of the periphery of PartB and C term at the time of 64QAM modulation, ie, the commonality of a real part and an imaginary part. An example of the internal structure of the distance calculation circuit of the 1st stage of the MLD section at the time of 64QAM modulation.

Explanation of symbols

1, 9 Reception system 19 Signal identification circuit, 20 MLD section (maximum likelihood determination circuit)
21 First stage distance calculation circuit 22 Second stage distance calculation circuit 23 Third stage distance calculation circuit 24 Fourth stage distance calculation circuit 31, 51 First calculation circuit 32, 52 Second calculation circuit 53 3 arithmetic circuit

Claims (9)

An apparatus having a signal identification circuit for identifying a transmission signal transmitted by QAM modulation,
The signal identification circuit receives the transmission signal as a reception result, and sets a plurality of transmission constellations that can be transmitted or a plurality of replicas corresponding to the plurality of transmission constellations as a plurality of transmission signal component candidates, A distance calculation circuit for calculating an Euclidean distance between the reception result and the plurality of transmission signal component candidates or a square thereof as an evaluation value;
This distance arithmetic circuit is a first arithmetic circuit that commonly executes at least a part of operations common to transmission signal component candidates corresponding to transmission constellations having a common real part among the plurality of transmission signal component candidates. When,
And a second arithmetic circuit that commonly executes at least a part of operations common to transmission signal component candidates corresponding to transmission constellations having a common imaginary part among the plurality of transmission signal component candidates.   2. The distance calculation circuit according to claim 1, further comprising: at least a part of a calculation common to transmission signal component candidates corresponding to a transmission constellation corresponding to a transmission constellation having a common distance from an origin among the plurality of transmission signal component candidates. An apparatus including a third arithmetic circuit that executes in common. 2. The circuit according to claim 1, wherein the signal identification circuit is a circuit for separating a plurality of reception signals received by a plurality of reception antennas into a plurality of transmission signals transmitted from the plurality of transmission antennas by a QRM-MLD method. Yes,
The plurality of signals that can be transmitted from the plurality of transmission antennas each include a plurality of transmission signal components,
The signal identification circuit is
Obtaining the evaluation value relating to a part of the first-stage transmission signal component candidates of the plurality of transmission signal component candidates, and substituting the plurality of transmission signal component candidates into the first-stage transmission signal component candidates remaining. Including a maximum likelihood determination circuit for performing multi-stage maximum likelihood determination, including adding the other second-stage transmission signal component candidates to obtain the evaluation value,
The maximum likelihood determination circuit includes a distance calculation circuit in each stage for calculating an evaluation value in each stage, and the distance calculation circuit in each stage targets transmission signal component candidates added in each stage. An apparatus comprising a first arithmetic circuit and the second arithmetic circuit.   4. The distance calculation circuit according to claim 3, wherein the distance calculation circuit at each stage is further common to transmission signal component candidates corresponding to transmission constellations having a common distance from the origin among the transmission signal component candidates added at each stage. An apparatus including a third arithmetic circuit that commonly executes at least a part of the operations to be performed. In claim 3,
The first arithmetic circuit calculates a square of a difference between a product of a common real part of a diagonal component of an R matrix and a corresponding transmission signal component candidate and a real part of another component required for distance calculation. Including
The second arithmetic circuit includes a circuit that calculates a square of a difference between a product of a common imaginary part of the diagonal component of the R matrix and a corresponding transmission signal component candidate and an imaginary part of the other component. ,apparatus. In claim 4,
The third arithmetic circuit is configured to calculate a transmission signal component candidate corresponding to a diagonal component of the R matrix by replacing a common distance from the origin with a constant, and another component required for the distance calculation from the origin. A circuit for calculating the distance,
The first arithmetic circuit includes a circuit that multiplies the diagonal component and the real part of the other component,
The second arithmetic circuit includes a circuit that multiplies the diagonal component by an imaginary part of the other component. The device of claim 1, comprising a reconfigurable device capable of reconfiguring a circuit,
The distance computing circuit is implemented in the reconfigurable device.   8. The apparatus according to claim 7, wherein the reconfigurable device is capable of reconfiguring a circuit by changing a connection of a plurality of elements including a multiplication element.   2. The apparatus according to claim 1, further comprising an application for outputting information including data obtained by the transmission signal identified by the signal identification circuit.

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