JP4967735B2 - Connection monitoring device, and network device and network test device using the same. - Google Patents

Description

  The present invention relates to a connection monitoring apparatus that performs reachability monitoring between monitoring points in a network, and a network device and a network test apparatus using the same, and more particularly, even when the time indicated by timeout information differs in received frames. The present invention relates to a connection monitoring apparatus that can reliably detect the cancellation of connection disconnection, and a network device and a network test apparatus using the connection monitoring apparatus.

  In a network such as a LAN, WAN, and the Internet, various network devices such as switches and routers are connected and communicate with each other using a predetermined protocol (for example, TCP / IP).

In the network interface layer (data link layer: layer 2), communication is performed using, for example, an IEEE 802.3 frame, an Ethernet (registered trademark) frame, or the like.

  A network test apparatus is used to test, evaluate, verify, etc. the network itself and network equipment. For example, when network evaluation or the like is performed, a network test apparatus is connected to the network, a frame flowing on the connection line is acquired, and various statistical information is obtained from the acquired frame to perform a test or the like.

  When testing network devices, etc., test data is generated according to a predetermined protocol to give various measurement traffic loads to the network devices to measure and acquire response frames to the load, The frame is exchanged and a test or the like is performed from the acquired frame (see Non-Patent Document 1).

In recent years, standardization has also been performed in networks, and various regulations are also provided in layer 2 technologies such as Ethernet (registered trademark) . And in the maintenance management of a wide area network, for example, Y. of ITU-T (International Telecommunication Union Telecommunication Standardization Sector). Various functions for fault management, fault management, and performance management are specified in 1731 (standardized in 2006) and IEEEag (the Institute of Electrical and Electronics Engineers) 802.1ag (to be standardized in 2007). Yes.

Such IEEE802.1ag is called “ Ethernet (registered trademark) OAM (Operation, Administration, Maintenance)”, and means “operation, management, maintenance” in a communication business network.

In order to satisfy the standardization requirements, there is a trend to install functions defined in Ethernet (registered trademark) OAM in layer 2 switches and network test equipment.

As one of the functions defined in the Ethernet (registered trademark) OAM, a CC (Continuity Check: reachability monitoring between monitoring points) function is defined for fault management. For example, a CCM (Continuity Check Messages) frame (connection monitoring frame) is periodically transmitted from a predetermined layer 2 switch to a destination layer 2 switch (a relay switch may be included between monitoring points). And monitoring whether the monitoring points are connected. Of course, the CCM frame is also defined in the standard.

  Note that a large number of network devices are connected to the network, and each network device transmits a CCM frame. Accordingly, the receiving side device uses the information in the CCM frame (such as MEG Level (Maintenance Entity Group Level), MEP ID (MEG End Point Identifier), MEG ID (Maintenance Entity Group Identifier), etc.) for the CCM frame addressed to itself. Or whether it is a CCM frame for the device itself, based on whether it exceeds a predetermined level. Hereinafter, receiving a CCM frame refers to a CCM frame that satisfies these conditions.

  Information related to the CCM frame transmission interval and timeout (PERIOD value (period value: 3 bits)) is inserted into the CCM frame periodically transmitted for monitoring, and the transmission side adds this PERIOD value to the PERIOD value. A CCM frame is transmitted at a transmission interval based on the transmission interval.

  On the receiving side, after receiving the CCM frame, a PERIOD value is extracted from the received frame, and a new CCM frame is received until a time (timeout time) 3.5 times the transmission interval indicated by the PERIOD value elapses. If none is received, it is required to determine that a LOC (Loss of Continuity) detection has occurred because a failure has occurred.

  Then, after detecting the LOC, if a new CCM frame is received and two or more CCM frames are received within the timeout period indicated by the PERIOD value extracted from the received CCM frame, the LOC is detected as the failure has been resolved. It is required to be determined to be released.

FIG. 5 shows an example of the PERIOD information table.
FIG. 6 is a diagram showing a configuration of a conventional connection monitoring apparatus in which the CC function is implemented.
In FIG. 6, a CCM receiving circuit 10 receives a frame from the network, extracts a CCM frame from the input frame, and outputs a CCM reception signal indicating that the CCM frame has been received and a PERIOD value of the CCM frame. .

  The LOC detection circuit 20 receives the CCM reception signal and the PERIOD value from the CCM reception circuit 10 and outputs a LOC detection signal Ld.

  The LOC release circuit 30 includes a counter unit 31 (the counter unit 31 includes an up counter 32, a down counter 33, and a signal output unit 34), and an AND circuit 35. The CCM reception circuit 10 receives a CCM reception signal and a PERIOD value. The LOC release signal Ok is output.

  The count unit 31 receives a CCM reception signal, a PERIOD value, and a signal from the AND circuit 35, and outputs a LOC release signal Ok and a count end signal end.

  The up counter 32 receives the CCM reception signal and the start signal St from the AND circuit 35.

  The down counter 33 receives the period value and the start signal St from the AND circuit 35.

  The signal output unit 34 receives the count value of the up counter 32 and the count value of the down counter 33, and outputs a LOC release signal Ok when the count value of the up counter 32 becomes “2” or more, and the count value of the down counter 33 When “0” is “0”, a low-level signal “end” is output to the AND circuit 35.

  In the S-R (Set-Reset) flip-flop circuit 40, the LOC detection signal Ld from the LOC detection circuit 20 is input to the S terminal, and the LOC release signal Ok from the LOC release circuit 30 is input to the R terminal. Based on the level of Ok, a signal indicating the presence / absence of LOC detection is output.

The operation of such an apparatus will be described.
The CCM receiving circuit 10 receives a frame from the network, extracts a CCM frame from the received frames, and extracts a PERIOD value from the CCM frame. Then, the CCM reception signal and the PERIOD value are output to the LOC detection circuit 20 and the LOC release circuit 30.

  The LOC detection circuit 20 obtains a timeout time from the PERIOD value with reference to a table (table shown in FIG. 5) stored in a memory (not shown), and receives a new time from the reception circuit 10 before the timeout time elapses. When the CCM reception signal is not input, an active signal (L → H → L pulse signal) detection signal Ld is output to the SR flip-flop 40. As a result, the SR flip-flop 40 outputs a high level signal indicating LOC detection.

  On the other hand, the up counter 32 of the LOC release circuit 30 resets the count value to “0” by the start signal St from the AND circuit 35, and after the start signal St from the AND circuit 35, a newly input CCM reception is received. Count the number of signals and output the count value.

  Further, the down counter 33 refers to a table stored in a memory (not shown), obtains a timeout time from the PERIOD value, sets a count value corresponding to the timeout time, and uses a start signal St from the AND circuit 35. Start decrementing the count value (decrease the count value to "-1"). Then, the down counter 33 outputs the count value to the signal output unit 34, and when the count value from the down counter 33 is not “0”, the signal output unit 34 outputs the low-level signal End to the AND circuit 35. .

  Then, when the count value from the up counter 32 exceeds “2”, the signal output unit 34 receives the LOC release signal Ok of the active signal to the flip-flop 40 on the assumption that two or more CCM reception signals are received within the timeout time. Output. As a result, the S-R flip-flop 40 outputs a low-level signal indicating LOC detection cancellation.

  Further, when the count value of the down counter 33 becomes “0”, the signal output unit 34 outputs a high level signal “end” indicating that the count of the down counter 33 is completed to the AND circuit 35. In FIG. 6, the CCM receiving circuit 10, the detection circuit 20, the counters 32 and 33, and the signal output unit 34 include clock signals for synchronizing the circuits (the clock frequency is compared with the pulse width of the pulse signal of each circuit. Is fast enough).

Nobuyuki Hiraoka and three others, “IP Network Testing Machine AE5511 Traffic Tester Pro”, Yokogawa Technical Report, Vol. 49, no. 4 (2005), p33-36

  As shown in FIG. 5, there are a plurality of PERIOD values in the CCM frame, and the PERIOD value may differ depending on the CCM frame.

  However, the signal output unit 34 cannot newly set the count value of the down counter 33 until the count value of the down counter 33 becomes “0”. As a result, the CCM reception signal input during the down-count cannot be used as a base point for setting the count value of the counter 33.

This will be specifically described with reference to FIG. FIG. 7 is a timing chart showing the operation of the LOC release circuit 30. Illustration of the clock signal is omitted.

  Here, it is assumed that the PERIOD values of the CCM reception signals S (2) to S (5) are sufficiently larger than the PERIOD value of the CCM reception signal S (1).

  Since the down count value is “0” in the initial state, the signal end from the signal output unit 34 is at a high level. Then, the AND circuit 35 outputs a start signal St in response to the CCM reception signal S (1). As a result, the up counter 32 sets the count value to “0”, the down counter 33 starts down counting, and the signal output unit 34 sets the signal end to the low level.

  When the CCM reception signal S (2) is input, the up counter 32 increments the count value from “0” to “1”, but the down counter 33 is down regardless of the CCM reception signal S (2). Continue counting.

  Further, the signal output unit 34 sets the signal end to the high level when the down-counting is finished (count value “0”). Then, the count value of the up counter 32 is cleared and the count value of the down counter 33 is set by the next reception signal S (3), and the down count is started. Further, the CCM reception signals S (4) and S (5) are sequentially input, the reception signal S (5) has an up count value “2”, and the output signal 34 outputs the LOC release signal Ok.

  As shown in FIG. 7, if the CCM reception signal S (2) is used as a base point for down-counting, the reception signal S (4) can output the LOC release signal Ok, but during the down-counting, a new reception signal S ( 2) cannot be used as a base point for down-counting, and as a result, there is a problem that the LOC release signal Ok cannot be output at an optimal timing.

  Therefore, an object of the present invention is to realize a connection monitoring apparatus that can reliably detect the disconnection cancellation even when the time indicated by the timeout information differs in the received frames, and a network device and a network test apparatus using the connection monitoring apparatus. There is.

The invention described in claim 1
In a connection monitoring device that performs reachability monitoring between monitoring points in a network,
A reception circuit that extracts a frame for connection monitoring from the frames from the network, and outputs a frame reception signal and timeout information included in the detected frame each time it is extracted;
A detection circuit that outputs a connection disconnection detection signal when the next frame reception signal is not input from the reception circuit within the time indicated by the timeout information from the reception circuit;
After detection by this detection circuit, when n new frame reception signals are input from the reception circuit within the time indicated by the timeout information from the reception circuit, a signal indicating that the disconnection has been resolved is output. (N + 1) release circuits to perform,
And an activation circuit that sequentially activates the release circuits one by one for each frame reception signal from the reception circuit.
The invention according to claim 2 is the invention according to claim 1,
The release circuit includes a down counter that counts a time-out time based on the frame reception signal and a signal from the activation circuit.
The invention according to claim 3 is the invention according to claim 1 or 2,
The receiving circuit is an IEEE 802.1ag standard or an ITU-T Y.264 standard. A CCM frame defined by the 1731 standard is extracted, and a period value in the CCM frame is output as timeout information.
The invention according to claim 4
In a network device connected to the network and transmitting a frame according to the address of the frame,
The connection monitoring device according to any one of claims 1 to 3 is provided, and an alarm is output by a connection disconnection detection signal from the connection monitoring device.
The invention according to claim 5
In a network test apparatus that is connected to the network or network device and tests the network or network device,
The connection monitoring device according to any one of claims 1 to 3 is provided, and an alarm is output by a connection disconnection detection signal from the connection monitoring device.

  When the release circuit receives “n” received signals within a predetermined time from the received signal as the base point, it outputs a signal indicating that the disconnection has been resolved. Since the release circuit is provided in parallel with “n + 1”, and the activation circuit activates the release circuit in order for each reception signal, all of the reception signals can be used as a base point. Thereby, even when the time indicated by the timeout information differs in the received frames, it is possible to reliably detect the cancellation of the connection disconnection.

Embodiments of the present invention will be described below with reference to the drawings.
FIG. 1 is a block diagram showing an embodiment of the present invention. Here, the same components as those in FIG. In FIG. 1, LOC release circuits 50 (1) to 50 (3) are provided in parallel instead of the LOC release circuit 30.

  The OR circuit 60 performs an OR operation on the signals Ok (1) to Ok (3) output from the LOC release circuits 50 (1) to 50 (3) and uses the operation result as the lock release signal Ok. Output to. That is, when any one of the LOC release circuits 50 (1) to 50 (3) outputs the signals Ok (1) to Ok (3), the output signal of the SR flip-flop 40 is reset (low level). .

  The activation circuit 70 receives a CCM reception signal (corresponding to a frame reception signal in the claims) from the CCM reception circuit 10, and every time a signal is input, any one of the LOC release circuits 50 (1) to 50 (3). The crab activation signals Op (1) to Op (3) are output.

The operation of such an apparatus will be described.
First, a reset signal is output from a reset unit (not shown) to the LOC detection circuit 20, the SR flip-flop 40, the LOC release circuits 50 (1) to 50 (3), and the activation circuit 70, and each circuit is initialized. . That is, the signal Ld of the LOC detection circuit 20, the output signal of the flip-flop circuit 40, the output signals Ok (1) to Ok (3) of the LOC release circuits 50 (1) to 50 (3), NG (1) to NG ( Set all of 3) to low level. In addition, the output destination of the start signal of the start circuit 70 is set to the LOC release circuit 50 (1).

First, the operation of LOC detection will be described, and then the operation of canceling this LOC detection will be described.
The CCM receiving circuit 10 receives a frame from the network, extracts a CCM frame from the received frames, and extracts a PERIOD value from the CCM frame. Then, both the CCM reception signal and the PERIOD value are output to the LOC detection circuit 20 and the LOC release circuits 50 (1) to 50 (3), and the CCM reception signal is output to the activation circuit 70.

  The LOC detection circuit 20 obtains a timeout time from the PERIOD value with reference to a table (table shown in FIG. 5) stored in a memory (not shown), and receives a new time from the reception circuit 10 before the timeout time elapses. When the CCM reception signal is not input, an active signal (L → H → L pulse signal) detection signal Ld is output to the SR flip-flop 40. As a result, the SR flip-flop 40 outputs a high level signal indicating LOC detection.

Next, an operation for canceling the LOC detection will be described.
When a CCM frame is received after the LOC detection state, the CCM reception circuit 10 outputs a CCM reception signal and a PERIOD value. Then, the activation circuit 70 outputs activation signals Op (1) to Op (3) for activating the release circuits 50 (1) to 50 (3). This signal is sequentially output to any one of the release circuits 50 (1) to 50 (3) every time a CCM reception signal is input.

  For example, for the first (first frame) CCM reception signal, the activation signal Op (1) is output to the LOC cancellation circuit 50 (1), and for the second frame CCM reception signal, the LOC cancellation circuit 50 (1). The activation signal Op (2) is output to 2), and the activation signal Op (3) is output to the LOC release circuit 50 (3) for the CCM reception signal of the third frame. In the fourth frame, the signal returns to the LOC release circuit 50 (1) and outputs the signal OP (1). Similarly, the signals in the order of the circuits 50 (2), 50 (3), 50 (1). OP (2), Op (3), and OP (1) are output.

  Each of the LOC release circuits 50 (1) to 50 (3) detects the LOC release using the activation signal Op (1) as a trigger. Specifically, two new CCM reception signals are input within the timeout period based on the PERIOD value, with the CCM reception signal input together with the activation signals OP (1) to OP (3) as the base point of the timeout period. In this case, signals Ok (1) to Ok (3) indicating LOC release are output to the OR circuit 60. Then, the OR circuit 60 outputs the calculation result to the SR flip-flop 40 as the LOC release signal Ok, and thereby the SR flip-flop 40 outputs a low level signal indicating that the LOC has been released.

  Accordingly, the LOC release circuit 50 (1) starts detecting the LOC release based on the jth frame (j is a natural number) after the LOC is detected, and the LOC release circuit 50 (2) is the (j + 1) th frame after the LOC is detected. LOC release detection is started from the base point, and the LOC release circuit 50 (3) starts detecting LOC release from the (j + 2) th frame after the LOC detection.

  Thus, when the LOC release is not detected and the (j + 3) th frame is input to the release circuit 50 (1), the release circuit 50 (1) is always in the LOC release non-detection (timeout) state. Therefore, the release circuit Ok (1) is always output if it is not in the time-out state), so that the release circuit 50 (1) performs LOC release detection again with the (j + 3) th frame as a base point.

  FIG. 2 is a diagram showing an example of the configuration of the LOC release circuits 50 (1) to 50 (3) of the apparatus shown in FIG. 3 and 4 are timing charts for explaining the operation of the circuits 50 (1) to 50 (3) shown in FIG.

  In FIG. 2, an AND circuit 51 receives a CCM reception signal and activation signals Op (1) to Op (3) (the activation signal is abbreviated as Op and also abbreviated in FIG. 2), and the calculation result is an active signal. Output as a start signal St.

  The down counter 52 receives the PERIOD value and the start signal St, and outputs a signal end when the count value becomes “0”.

  In the SR flip-flop 53, the start signal St is input to the S terminal, and the signal end is input to the R terminal.

  In the flip-flop 54, a high level signal is input to the input terminal, a CCM reception signal is input to the enable terminal, and a start signal St is input to the reset terminal.

  The knot circuit 55 inverts the activation signal Op.

  The AND circuit 56 receives the output signal in of the SR flip-flop 53, the output signal cc of the flip-flop 54, the CCM reception signal, and the output signal of the knot circuit 55, and outputs the calculation result to the OR circuit 60.

  The operation of such an apparatus will be described. First, the operation for detecting LOC release will be described (see FIG. 3). Further, an example in which the activation circuit 70 outputs the activation signal OP (1) to the release circuit 50 (1) will be described.

  Since the high-level operation signal Op (1) is input to the AND circuit 51 from the starting circuit 70, the CCM reception signal S (1) is input by inputting the CCM reception signal S (1) in this state. The start signal St is input to the down counter 52 so as to be a base point. Then, the down counter 52 obtains a count value (timeout time) from the PERIOD value, and starts down counting. The down counter 52 obtains a timeout time with reference to the table shown in FIG. 5 stored in a memory (not shown), and sets a count value corresponding to the timeout time.

  Further, the SR flip-flop 53 is set by the start signal, and a high level signal in is output.

  Further, the flip-flop 54 is reset by the start signal, and a low level signal cc is output from the output terminal.

  Note that after the activation circuit 70 inputs the CCM reception signal S (1) (after the CCM reception signal S (1) changes from high level to low level), the activation signal Op (1) to the release circuit 50 (1). Is set to the low level, and the activation signal Op (2) (not shown) to the release circuit 50 (2) is set to the high level.

  When the second frame CCM reception signal S (2) is input during the down-counting, the flip-flop 54 is enabled and outputs a high-level signal cc. That is, at the time of the reception signal S (1) of the first frame, the output signal of the flip-flop 54 is reset by the start signal St and is at the low level.

  Further, when the CCM reception signal S (3) of the third frame is input during the down-counting, all the signals to the AND circuit 56 become high level, and the AND circuit 56 detects the LOC release signal Ok (1) of the active signal. Is output.

  That is, the SR flip-flop 53 outputs a high level signal “in” in response to the start signal St. The flip-flop 54 outputs a high-level signal cc indicating that the first CCM reception signal has already been detected with respect to the base CCM reception signal S (1). The knot circuit 55 outputs a high level signal (inversion signal of the activation signal Op (1)) indicating that the CCM reception signal being input is not the base point. A CCM reception signal S (3) indicating that the CCM frame has been received is input to the AND circuit 56 in a state where the above three conditions are met, and the AND circuit 56 performs a logical product to perform the LOC release signal Ok. (1) is output. Note that the down counter 52 interrupts the counting by the release signal Ok (1).

Next, the operation when the LOC is not released will be described (see FIG. 4).
The output of the start signal St, the count start of the down counter 52, and the output of the SR flip-flop 53 are set (high level) by the start signal Op and the CCM reception signal S (1) as the base point, as in FIG. is there.

  Similarly to FIG. 3, the output of the flip-flop 54 becomes high level by the CCM reception signal S (2) of the second frame.

  However, if the count value of the down counter 52 becomes “0” before the CCM reception signal S (3) of the third frame is input to the release circuit 50 (1) (all bits of the output from the counter are low). Level) and the count end signal end, the SR flip-flop 53 is reset (the signal is low level), and a signal NG indicating that the lock cannot be detected is output. After the signal NG (= signal end) is output, the current state is maintained until the activation signal Op is input again.

  As described above, when the cancellation circuits 50 (1) to 50 (3) receive “two” CCM reception signals within the timeout period from the CCM reception signal as the base point, the LOC detection cancellation signal is output. Then, "3" release circuits are provided in parallel, and the activation circuit 70 activates the release circuits 50 (1) to 50 (3) in order for each CCM reception signal, so that all of the CCM reception signals are used as a base point. be able to. Thereby, even when the period value is different in the CCM frame, it is possible to reliably detect the LOC detection cancellation.

  Here, in FIGS. 1 and 2, illustration of a clock that outputs a clock signal is omitted. In addition, the CCM receiving circuit 10, the detection circuit 20, the release circuits 50 (1) to 50 (3), and the activation circuit 70 include clock signals for synchronizing the circuits (the clock frequency is the pulse width of the pulse signal of each circuit). Is sufficiently fast compared to). The clock signal is also input to the down counter 52 and the flip-flop 54 of the release circuits 50 (1) to 50 (3).

The present invention is not limited to this, and may be as shown below.
(1) Instead of the LOC release circuits 50 (1) to (3), three LOC release circuits 30 shown in FIG. 6 may be used side by side. In this case, activation signals Op (1) to Op (3) from the activation circuit 70 may be used for the AND circuit 35 instead of the signal end.

(2) The condition for canceling the LOC detection in accordance with the IEEE 802.1ag standard is that it is canceled if two CCM reception signals are received within the timeout period, but the number of reception may be any number. If n CCM reception signals are received within the time-out period, the release circuit 50 may be provided in parallel when it is canceled. The output of the high level signal output from the flip-flop circuit 54 may be delayed according to the number of signals received. For example, when three signals are received within the time-out period, the flip-flop 54 may output a high-level signal when receiving the second CCM reception signal.

(3) Although an Ethernet (registered trademark) frame has been described as an example of a frame, it may be a frame of any standard.

(4) The connection monitoring apparatus shown in FIGS. 1 and 2 may be used by being incorporated in a network device or a network test apparatus.

  For example, it may be used in a network device represented by a layer 2 switch connected to a network and transferring / transmitting received frames according to the address of this frame. And it is good to output an alarm by the LOC detection signal from the connection monitoring apparatus shown in FIG. 1, and to erase the alarm by the LOC release signal.

  Further, it may be used in a network test apparatus that is connected to a network or network equipment (layer 2 switch) and tests the network or network equipment. And it is good to output an alarm by the LOC detection signal from the connection monitoring apparatus shown in FIG. 1, and to erase the alarm by the LOC release signal. In addition, a record of whether or not an alarm is detected may be stored in the memory, and the network or network device may be analyzed based on this record. Further, when time-out signals NG (1) to NG (3) from the LOC release circuits 50 (1) to 50 (3), the PERIOD values at this time are recorded in the memory, and the LOC release analysis is performed. Good.

It is the block diagram which showed one Example of this invention. FIG. 2 is a diagram illustrating a detailed configuration example of a part of the apparatus illustrated in FIG. 1. It is a timing chart explaining an example of operation | movement of the apparatus shown in FIG. 6 is a timing chart for explaining an example of another operation of the apparatus shown in FIG. It is the figure which showed the relationship of a PERIOD (period) value, a transmission interval, and timeout time. It is the figure which showed the structure of the conventional connection monitoring apparatus. It is a timing chart explaining an example of operation | movement of the apparatus shown in FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 CCM receiving circuit 20 LOC detection circuit 40 SR flip-flop 50 (1) -50 (3) LOC cancellation | release circuit 52 Down counter 70 Starting circuit

Claims (5)

In a connection monitoring device that performs reachability monitoring between monitoring points in a network,
A reception circuit that extracts a frame for connection monitoring from the frames from the network, and outputs a frame reception signal and timeout information included in the detected frame each time it is extracted;
A detection circuit that outputs a connection disconnection detection signal when the next frame reception signal is not input from the reception circuit within the time indicated by the timeout information from the reception circuit;
After detection by this detection circuit, when n new frame reception signals are input from the reception circuit within the time indicated by the timeout information from the reception circuit, a signal indicating that the disconnection has been resolved is output. (N + 1) release circuits to perform,
A connection monitoring apparatus, comprising: an activation circuit that sequentially activates the release circuit one by one for each frame reception signal from the reception circuit. The connection monitoring apparatus according to claim 1, wherein the release circuit includes a down counter that counts a time-out time based on the frame reception signal and a signal from the activation circuit. The receiving circuit is an IEEE 802.1ag standard or an ITU-T Y.264 standard. 3. The connection monitoring apparatus according to claim 1, wherein a CCM frame defined by the 1731 standard is extracted and a period value in the CCM frame is output as timeout information. In a network device connected to the network and transmitting a frame according to the address of the frame,
A network device comprising the connection monitoring device according to claim 1, wherein an alarm is output by a connection disconnection detection signal from the connection monitoring device. In a network test apparatus that is connected to the network or network device and tests the network or network device,
A network test apparatus comprising the connection monitoring apparatus according to claim 1, wherein an alarm is output by a connection disconnection detection signal from the connection monitoring apparatus.

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