JP4950806B2 - Defect inspection apparatus, defect inspection method, semiconductor device manufacturing system, and semiconductor device manufacturing method - Google Patents

Description

  The present invention relates to a defect inspection apparatus, a defect inspection method, a semiconductor device manufacturing system, and a semiconductor device manufacturing method.

  In the manufacturing process of a semiconductor device, a large number of elements in which patterns are formed on a semiconductor wafer are formed. The completed device is inspected for electrical characteristics and defective products are removed from the assembly process. In the semiconductor device manufacturing process, the yield is very important, and the inspection result of the electrical characteristics is fed back to the manufacturing process and used for management of each process. However, the manufacturing process of the semiconductor device is formed by a number of processes, and it takes a very long time from the start of manufacturing until the inspection of electrical characteristics is performed. Therefore, even if it is found out that the manufacturing process is defective by the inspection of the electrical characteristics, a large number of wafers are already in the process at that time, and the result of the inspection cannot be fully utilized for improving the yield.

  Therefore, defect inspection is performed in which a pattern formed in an intermediate process (for example, each layer) is inspected to detect a defect (foreign matter, pattern defect, etc.). If defect inspection is performed in a plurality of processes among all processes, the occurrence of defects can be detected quickly, and the inspection results can be reflected in process management quickly.

  The defect inspection is performed by applying inspection light to the wafer, condensing the reflected light with a lens, creating an image with an image sensor, and comparing it with a reference image. The inspection light has different reflection intensity depending on the pattern on the wafer, the light level is the same, and when the inspection is performed with the same threshold value of the received light intensity that is regarded as a defect, the defect is easy to detect (high sensitivity area) and difficult to detect. A region (low sensitivity region) is generated. Therefore, for example, in a memory product having a simple cell portion shape and a small number of cells, defect inspection is performed by setting different sensitivities for the cell portion and the peripheral circuit portion manually while looking at the wafer.

  However, when the pattern is random as in a logic product, high sensitivity regions and low sensitivity regions are scattered and there are a large number of them, and it is extremely difficult to manually set the sensitivity. For this reason, in the logic product, the entire wafer has to be inspected with the same sensitivity, and if the pseudo defects are reduced to a certain ratio, the defects in the low sensitivity region cannot be detected.

  In order to solve such a problem, the inspection region is divided into partial inspection regions, and the wiring density (= wiring area / partial inspection region area) is calculated for each partial inspection region, and based on the calculated wiring density A defect inspection apparatus that assigns a sensitivity rank to each partial inspection region and sets inspection parameters has been proposed (see, for example, Patent Document 1).

However, the sensitivity rank based only on the wiring density does not match the actual defect detection sensitivity. In addition, there are a huge number of partial inspection areas with sensitivity ranks. If these are sent to the inspection apparatus as they are, there is a risk that the inspection apparatus may not operate normally or the setting of the inspection area may fail. .
Japanese Patent Laid-Open No. 2002-323458

  An object of this invention is to provide the defect inspection apparatus which can perform a defect inspection by setting an appropriate sensitivity rank for every appropriate inspection area.

  A defect inspection apparatus according to an aspect of the present invention includes an inspection area dividing unit that divides an area for performing defect inspection of a wafer on which a circuit pattern is formed into a plurality of divided inspection areas, and the division based on the design data of the circuit pattern. A coverage / edge density calculation unit for calculating a wiring coverage and a wiring edge density for each inspection region; and a sensitivity evaluation value for each of the divided inspection regions based on the wiring coverage and the wiring edge density, and the sensitivity A sensitivity rank setting unit that sets a sensitivity rank based on an evaluation value, an inspection execution region setting unit that sets an inspection execution region by simplifying the shape of the divided inspection region in which the same sensitivity rank is set, and the inspection A defect inspection unit that sets inspection parameters based on the sensitivity rank of the execution area and performs defect inspection of the inspection execution area.

  A defect inspection apparatus according to an aspect of the present invention is based on an inspection area dividing unit that divides an area for defect inspection of a wafer on which a circuit pattern is formed into a plurality of divided inspection areas, and design data of the circuit pattern. An edge density calculation unit that calculates a wiring edge density for each of the divided inspection regions; a sensitivity rank setting unit that sets a sensitivity rank based on the wiring edge density; and the divided inspection regions in which the same sensitivity rank is set. An inspection execution region setting unit that simplifies the shape and sets an inspection execution region, and a defect inspection unit that sets inspection parameters based on a sensitivity rank of the inspection execution region and performs defect inspection of the inspection execution region Is.

  According to one embodiment of the present invention, a defect inspection method forms a circuit pattern using a defect inspection apparatus having an inspection region dividing unit, a coverage / edge density calculating unit, a sensitivity rank setting unit, an inspection execution region setting unit, and a defect inspection unit. A method for inspecting a defect of a wafer, wherein the inspection area dividing unit divides an area in which the wafer defect is inspected into a plurality of divided inspection areas, and the coverage / edge density calculating unit calculates the circuit pattern. A wiring coverage and wiring edge density for each of the divided inspection areas are calculated based on design data, and a sensitivity evaluation value for each of the divided inspection areas is calculated based on the wiring coverage and the wiring edge density by the sensitivity rank setting unit. The divided inspection region that is calculated, sets a sensitivity rank based on the sensitivity evaluation value, and is set with the same sensitivity rank by the inspection execution region setting unit Shape simplifies, sets the inspection execution region, to set the test parameters based on sensitivity ranks of the inspection-executing region by the defect inspection unit, it is intended to include performing the defect inspection of the inspection-executing region.

  A method of manufacturing a semiconductor device according to an aspect of the present invention includes an inspection region dividing unit, a coverage / edge density calculating unit, a sensitivity rank setting unit, an inspection execution region setting unit, a defect inspection unit, a pattern forming apparatus, and an apparatus parameter correction unit. A method of manufacturing a semiconductor device using a semiconductor manufacturing system comprising: a step of forming a circuit pattern on a wafer by the pattern forming device based on an apparatus parameter; and a region for performing defect inspection of the wafer by the inspection region dividing unit. A step of dividing into a plurality of divided inspection regions, a step of calculating a wiring coverage and a wiring edge density for each of the divided inspection regions based on design data of the circuit pattern by the coverage / edge density calculation unit, and the sensitivity Based on the wiring coverage and the wiring edge density by the rank setting unit, the sensitivity evaluation value for each of the divided inspection areas is determined. A step of setting a sensitivity rank based on the sensitivity evaluation value, a step of simplifying the shape of the divided inspection region in which the same sensitivity rank is set by the inspection execution region setting unit, and setting an inspection execution region And an inspection parameter is set based on a sensitivity rank of the inspection execution region by the defect inspection unit, and a defect inspection of the inspection execution region is performed, and the apparatus parameter correction unit performs the defect inspection based on the result of the defect inspection. Correcting the apparatus parameters, and the pattern forming apparatus forms a circuit pattern on the wafer based on the corrected apparatus parameters.

  According to the present invention, defect inspection can be performed by setting an appropriate sensitivity rank for each appropriate inspection region.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  (First Embodiment) FIG. 1 shows a schematic configuration of a defect inspection apparatus according to a first embodiment of the present invention. Design data (mask data) is output from the design unit 1. The inspection area dividing unit 2 divides the inspection area of the inspection target chip. The coverage / edge density calculation unit 3 calculates the coverage and edge density in each divided inspection region. Based on the calculated coverage and edge density, the sensitivity rank setting unit 4 calculates a sensitivity evaluation value for each divided inspection region, and sets the sensitivity rank based on the sensitivity evaluation value. The inspection execution area setting unit 5 groups the divided inspection areas set with the same sensitivity rank, performs graphic processing so that the grouped divided inspection areas have a rectangular shape, and sets the inspection execution area. This is because the inspection area is set to a rectangle when the defect inspection unit 6 performs the inspection. In the defect inspection unit 6, inspection parameters (light level, light reception intensity threshold, etc.) are set for each sensitivity rank.

  A defect inspection is performed, the detected defect is classified for each cause by the defect classification unit 7, and an inspection parameter is set so that the pseudo defect rate is a predetermined value or less. After the setting of the inspection parameter is completed, the sensitivity evaluation value representative value (representative evaluation value) in the inspection execution region and the set inspection parameter are registered in the sensitivity library 8. The representative evaluation value is, for example, a median value or an average value of sensitivity evaluation values in the inspection execution region. In the defect inspection after the next time, the inspection parameter setting can be automated by searching the sensitivity library 8 using the representative evaluation value and acquiring the inspection parameter. The detected defects are stored in the defect data storage unit 9 and displayed on the display unit 10 in a wafer map or chart format.

  Next, the operation of each unit will be described.

  The inspection area dividing unit 2 divides an area where the inspection target chip is inspected into a plurality of areas. For example, as shown in FIG. The size of the lattice can be set arbitrarily. In the following description, it is assumed that the inspection area is divided into a grid.

  The coverage / edge density calculation unit 3 calculates the coverage and edge density of each lattice using design data (mask data). The coverage is the wiring occupation ratio (= wiring area / grid area) in the grid. For example, the coverage is 1 when there is wiring in the entire surface of the lattice, and the coverage is 0 when there is no wiring in the lattice. An example of the coverage calculation is shown in FIG. FIG. 3A shows an inspection area divided into a lattice shape. FIG. 3B is an enlarged view of a part of the inspection region, and wiring patterns as shown in FIG. 3B are formed in the lattices g1 to g6. The coverage of each of the lattices g1 to g6 is shown in FIG. Since no wiring pattern is formed on the lattice g2, the coverage is zero.

  An example of edge density calculation in the lattices g1 to g6 is shown in FIGS. The edge density is the density of the edge of the wiring (between the wiring and the base). A method for calculating the edge density will be described. First, the size of the wiring pattern (FIG. 4A) in the region for calculating the edge density is reduced by d [μm] in the vertical and horizontal directions (FIG. 4B). d is set to a sufficiently small value with respect to the wiring width. Then, an area (FIG. 4C) obtained by subtracting the reduced pattern area from the pattern area before the size reduction becomes the edge portion of the pattern. The wiring edge portions in the lattices g1 to g6 are as shown in FIG. FIG. 5B shows the edge density (= edge portion area / lattice area) of each lattice at this time. The example which calculated | required the coverage and edge density about each of the grating | lattices g1-g6 is shown in FIG.

  7 and 8 show another example of edge density calculation. As shown in FIG. 7, a wiring pattern with a coverage of 0.33 is formed on square grids g71 and g72 each having a side of 10 [μm]. Although the coverage is the same, a more complicated wiring pattern is formed in the lattice g72. The patterns formed in the lattices g71 and g72 are reduced by 0.2 (= d) [μm] in the vertical and horizontal directions, respectively, and the pattern after reduction is subtracted from the pattern before reduction, as shown in FIG. The edge part is obtained as follows. The edge density of the lattice g71 is 0.0474, and the edge density of the lattice g72 is 0.1012. Thus, the edge density can represent the complexity of the wiring pattern in each lattice. Since the reflection intensity of inspection light in defect inspection is influenced not only by the coverage but also by line and space density, the edge density is calculated and used for sensitivity rank setting in this embodiment.

The sensitivity rank setting unit 4 calculates a sensitivity evaluation value (pattern density) from the coverage and edge density in each lattice, and sets the sensitivity rank based on the sensitivity evaluation value. The sensitivity evaluation value ev is obtained by the following formula.
Sensitivity evaluation value ev (i) = (max (coverage) −coverage (i)) × (max (edge density) −edge density (i))
Here, max (coverage) is the maximum coverage in all lattices, and max (edge density) is the maximum edge density in all lattices. I is a lattice number. The example which calculated | required the sensitivity evaluation value about the grating | lattices g1-g6 is shown in FIG. Among all the lattices including the lattices g1 to g6, the maximum coverage is 0.9 and the maximum edge density is 0.22.

  Based on the sensitivity evaluation value calculated in this way, a sensitivity rank is determined for each lattice. Here, it is divided into two ranks of low sensitivity and high sensitivity. The median value (median) or average value of the sensitivity evaluation values is set as a boundary value, a lattice having sensitivity evaluation values equal to or higher than the boundary value is set as a low sensitivity rank, and a lattice less than the boundary value is set as a high sensitivity rank. An example of setting the sensitivity rank is shown in FIG. The boundary value is 0.05, the low sensitivity rank is rank A, and the high sensitivity rank is rank B.

  The inspection execution area setting unit 5 groups lattices having the same sensitivity rank, divides the grouped polygons into rectangles (rectangles), and sets the inspection execution area. This is because the defect inspection apparatus performs defect inspection by setting the inspection area to a rectangle.

  The process of dividing the grouped polygon into rectangles includes a step of simplifying by reducing the number of vertices of the grouped polygon and a step of dividing the simplified polygon into rectangles.

  First, steps for simplifying by reducing the number of vertexes of a grouped polygon will be described with reference to FIGS. FIG. 11A shows an inspection region divided into a lattice, and FIG. 11B shows an enlarged view of a part thereof. A sensitivity rank is set for each lattice, and processing is performed from the low sensitivity rank (rank A) region.

  First, as shown in FIG. 11C, a rectangle is generated for each grid in which the target rank (rank A) is set. As shown in FIG. 11 (d), the rectangle to be generated is made smaller by s / 2 above, below, left and right of the lattice frame. That is, the rectangle to be generated is smaller than the lattice frame by s in both the vertical and horizontal directions. s is an arbitrary value smaller than one side of the lattice frame.

  Next, the generated rectangles are each increased by a length s in the horizontal direction. As a result, the respective rectangles are connected in the horizontal direction to form a strip shape as shown in FIG.

  Next, the length t is reduced in the lateral direction. As shown in FIG. 12B, strips whose horizontal length is t or less are lost by this process. The greater the value of t, the smaller the number of polygon vertices.

  Next, t is increased in the horizontal direction as shown in FIG. The strips that disappeared in the previous process remain disappeared.

  Next, an AND (logical product) process of this pattern (FIG. 12C) and the first rectangular pattern (FIG. 11C) is performed to obtain a rectangular pattern as shown in FIG.

  Next, each rectangle is enlarged by a length s in the vertical direction. As a result, the respective rectangles are connected in the vertical direction to form a strip shape as shown in FIG.

  Next, the length r is reduced in the vertical direction. As shown in FIG. 12 (f), strips whose vertical length is r or less are lost by this processing. As the value of r increases, the number of polygon vertices decreases. Here, s, r, and t are preferably s <r <t.

  Next, as shown in FIG. 12G, the length r is increased in the vertical direction to obtain a strip pattern A. The strips that disappeared in the previous process remain disappeared.

  Subsequently, the above process is performed by switching the order of the vertical process and the horizontal process.

  First, each rectangle shown in FIG. 11C is lengthened s in the vertical direction. Accordingly, as shown in FIG. 13A, the respective rectangles are connected in the vertical direction to form a strip shape.

  Next, the length t is reduced in the vertical direction. As shown in FIG. 13B, strips whose vertical length is t or less are lost by this process.

  Next, t is increased in the vertical direction as shown in FIG. The strips that disappeared in the previous process remain disappeared.

  Next, an AND (logical product) process of this pattern (FIG. 13C) and the first rectangular pattern (FIG. 11C) is performed to obtain a rectangular pattern as shown in FIG.

  Next, each rectangle is increased in length s in the horizontal direction. As a result, the respective rectangles are connected in the horizontal direction to form a strip shape as shown in FIG.

  Next, the length r is reduced in the lateral direction. As shown in FIG. 13 (f), strips having a horizontal length of r or less disappear by this process.

  Next, as shown in FIG. 13G, the strip pattern B is obtained by increasing r in the horizontal direction. The strips that disappeared in the previous process remain disappeared.

  OR (logical sum) processing of the strip pattern A and strip pattern B obtained by the above processing is performed. In the strip pattern A alone, the length in the horizontal direction is t or less but the long region in the vertical direction disappears. In the strip pattern B alone, the length in the vertical direction is t or less but the long region in the horizontal direction disappears. Resulting in. Therefore, OR processing of two strip patterns is performed to obtain a composite pattern as shown in FIG. 14 so that a region that is short in either the vertical direction or the horizontal direction and long in the other direction is not lost. .

  When the obtained composite pattern is increased by length s / 2 in the vertical and horizontal directions in a lattice unit, a polygon with a reduced number of vertices as shown in FIG. 15 is obtained.

  By the simplification steps as described above, the area of rank A shown in FIG. 11B becomes a simplified polygon area with a reduced number of vertices as shown in FIG.

  Subsequently, in the step of dividing the simplified polygon into rectangles, the polygon obtained in the simplification step is divided into rectangles (quadrangles) as shown in FIG. Although the polygon is divided in the vertical direction here, it may be divided in the horizontal direction as shown in FIG. A rectangle with a small area may be excluded from the rank A inspection region as a rectangle obtained in the rectangle dividing step as in the region D of FIG. The area that is not the target is the rank B inspection area.

  As shown in FIG. 18, the lattice of rank A that has been excluded from the rank A inspection area by the simplification step is assigned to the high sensitivity rank (rank B). The rank B region is a high-sensitivity region in which defects are easily found, and if a defect inspection for a low-sensitivity region in which defects are difficult to find is performed on this region, pseudo defects are likely to occur. In this embodiment, the reason why the low-sensitivity (rank A) region is simplified is to prevent the occurrence of pseudo defects.

  The area excluding the rank A inspection area obtained by the above processing becomes the rank B inspection area. For example, when the rank A inspection area as shown in FIG. 19A is obtained, the rank B inspection area is as shown in FIG. 19B.

  The inspection area information for each sensitivity rank set by the inspection execution area setting section 5 is sent to the defect inspection section 6. Defect inspection is performed using the actual wafer, the defect classification unit 7 classifies the defect, and measures the pseudo defect rate. Defect inspection includes image creation by an image sensor (not shown) and comparison between the created image and a reference image. The reference image is an image of a wafer (chip) that has been inspected last time and an image of a wafer (chip) that has been inspected last time. The defect is detected by comparing with these two reference images.

  Setting of inspection parameters such as a light level and a threshold value of received light intensity, defect inspection, and defect classification are repeated until the pseudo defect rate becomes a predetermined value or less. In this way, appropriate inspection parameters are set for each sensitivity rank. Further, the coordinate system of the mask data is sent together with the inspection area information for each sensitivity rank, and is converted into the coordinate system of the defect inspection unit 6.

  The set inspection parameter and the representative value of the sensitivity evaluation value in the inspection area are stored in the sensitivity library 8. In the next defect inspection or later, the inspection parameter setting can be automated by searching the sensitivity library 8 using the representative value of the sensitivity evaluation value, and the time required for the inspection parameter setting can be shortened.

  Defects detected by the defect inspection are stored in the defect data storage unit 9. Moreover, it is displayed on the display unit 10 in the form of a wafer map or chart, and the user can confirm whether or not a defect has occurred.

  As described above, an appropriate sensitivity rank can be set in the inspection area by the defect inspection apparatus according to the first embodiment of the present invention. Further, the shape and number of inspection areas can be kept within the allowable range of the defect inspection apparatus.

  (Second Embodiment) FIG. 20 shows a schematic configuration of a semiconductor manufacturing system according to a second embodiment of the present invention. The defect inspection apparatus 104 uses the defect inspection apparatus according to the first embodiment. The wafer that has completed the previous steps (wafer cleaning, thin film formation, MOS transistor creation, etc.) is transferred to the wiring pattern forming apparatus 102 by the wafer transfer control apparatus 101. In the wiring pattern forming apparatus 102, a wiring metal film is first formed by sputtering or CVD (chemical vapor deposition). Then, a resist (positive type in which the light irradiation region becomes soluble) is applied, and the wiring pattern is transferred and burned through a metal photomask by exposure processing. Then, the resist portion irradiated with light is dissolved with a developing solution to form a resist mask. The wiring metal film is etched using this resist mask, and the resist is removed to form a wiring pattern.

  Device parameter information (for example, exposure amount, focus value, developer temperature, etc.) of the pattern forming device 102 when forming a wiring pattern is monitored by a sensor (not shown) attached to the device, and the device parameter database 105 is used. Sent to.

  The patterned wafer is transferred to the defect inspection apparatus 104 by the wafer transfer control apparatus 101. In the defect inspection apparatus 104, mask data is input from the metal photomask design unit 103, and based on the mask data, inspection area division, coverage rate and edge density calculation, sensitivity rank setting for each divided area, inspection execution area And perform defect inspection.

  Inspection result information is input from the defect inspection apparatus 104 to the apparatus parameter control unit 106. In addition, apparatus parameters at the time of pattern formation of a wafer subjected to defect inspection are input from the apparatus parameter database 105. The apparatus parameter / defect database 107 stores correlation information between the generated defect and the apparatus parameter. When a defect is detected by defect inspection, the apparatus parameter control unit 106 searches the apparatus parameter / defect database 107 for the detected defect, and obtains the apparatus parameter to be controlled and its correction amount from the correlation information and the apparatus parameter. Then, the apparatus parameter correction information is output to the wiring pattern forming apparatus 102. In the wiring pattern forming apparatus 102, the apparatus parameters are corrected based on the apparatus parameter correction information.

  Since the defect inspection apparatus 104 sets an optimum sensitivity rank based on the coverage and the edge density, it is possible to accurately detect defects. In addition, the time required for defect inspection can be shortened by simplifying the shape of the inspection execution area and dividing it into rectangles.

  In addition, by accurately detecting defects correlated with device parameters and correcting device parameters at an early stage, it is possible to suppress the occurrence of the same defects in wafers to be processed from the next time onwards. Yield can be increased. When the semiconductor device to be manufactured has a multi-layer structure, the defect inspection can be quickly detected by performing the defect inspection every time the wiring pattern of each layer is formed, and can be reflected in the device parameters quickly.

  Based on the inspection result of the defect inspection apparatus 104, not only apparatus parameter correction but also apparatus cleaning, manufacturing process change, apparatus modification, apparatus change, and the like may be performed. The change in the manufacturing process is, for example, adding a cleaning process to the circuit pattern formation including a plurality of processes. As a result, it is possible to eliminate a defect factor that cannot be eliminated by correcting the apparatus parameters.

  As described above, the semiconductor manufacturing system according to the second embodiment of the present invention performs defect inspection by setting an appropriate sensitivity rank for each appropriate inspection region, suppresses the occurrence of defects based on the inspection result, and yield. Can be high.

  The sensitivity rank set by the sensitivity rank setting unit 4 is not limited to two ranks of low sensitivity and high sensitivity, and may be three ranks or more. When the rank is three, the inspection execution area setting unit 5 performs the simplification process and the rectangular division process in order from the area with the lowest sensitivity to obtain the area with the lowest sensitivity and the area with the second lowest sensitivity from the entire surface of the chip. The excluded area is set as the inspection execution area having the highest sensitivity. However, since the inspection parameters are set for each rank in the defect inspection unit 6, it is necessary to consider that the time required for creating a recipe for the defect inspection apparatus becomes longer. Further, the coverage / edge density calculation unit 3 may obtain the peripheral length of the wiring pattern in each divided inspection region instead of the density of the edge portion of the wiring. The circumference of the wiring pattern can also represent the density of the line and space.

  In the above embodiment, the sensitivity rank setting unit 4 calculates the sensitivity evaluation value using the coverage and the edge density, and sets the sensitivity rank of each grid. However, the sensitivity rank is set using only the edge density. May be. When the sensitivity rank is set to two ranks of low sensitivity and high sensitivity, a lattice having an edge density equal to or higher than the boundary value is set to the low sensitivity rank (rank A), and a lattice having less than the boundary value is set to the high sensitivity rank (rank B). As the boundary value, the median (median) or average value of the edge density can be used.

  The inspection execution area may be set by the inspection execution area setting unit 5 as follows. Assume that a sensitivity rank is set for each of the divided inspection areas divided in a lattice shape as shown in FIG.

  First, the number of low-sensitivity ranks (rank A) in each row is checked. If the number is less than m (here, 2), the division inspection area of rank A in that row is set to rank B. As shown in FIG. 21B, the lattices g11, g12, and g13 are set to rank B. Next, the number of ranks A in each column is checked. If n (here, 1) or less, the division inspection area of rank A in that column is set to rank B. As shown in FIG. 21C, the lattices g14, g15, and g16 are set to rank B. Thereby, the simplified inspection area SA1 is obtained.

  Subsequently, the number of ranks A in each column of the divided inspection area shown in FIG. 22A (same as FIG. 21A) is checked. If m (= 2) or less, rank A of the column is checked. Are set to rank B. As shown in FIG. 22B, the lattices g21, g22, and g23 are set to rank B. Next, the number of ranks A in each row is examined. If n (= 1) or less, the division inspection area of rank A in that row is set to rank B. As shown in FIG. 22C, the lattice g24 is set to rank B. Thereby, the simplified inspection area SA2 is obtained.

  Rank A is set in the divided inspection area where rank A is set in at least one of the simplified inspection areas SA1 and SA2, and rank B is set in the divided inspection area where rank B is set in either case. By doing so, the shape of the rank A inspection region can be simplified as shown in FIG. As shown in FIG. 24, the inspection execution area can be set by dividing the rank A inspection area into rectangles (rectangle 1 and rectangle 2).

  The m and n can be arbitrarily set according to the number of lattices. As the number of m and n increases, the shape of the rank A inspection region is simplified. In addition, by setting the number of m and n to n <m, it is possible to prevent the rank A inspection area having a small number in one of the row direction and the column direction and a large number in the other direction from being set to rank B. I can do it.

  (Third Embodiment) FIG. 25 shows a schematic configuration of a defect inspection apparatus according to a third embodiment of the present invention. The defect inspection apparatus according to the present embodiment includes a calculation unit 310, a storage unit 320, a defect inspection unit 330, and a display unit 340.

  The calculation unit 310 includes a block hierarchy extraction unit 311, a pattern density calculation unit 312, a variation specification determination unit 313, a low variation region extraction unit 314, and a pattern density grouping unit 315.

  The storage unit 320 includes a pattern data storage unit 321, a pattern density storage unit 322, an inspection area storage unit 323, and a defect storage unit 324.

  The pattern data storage unit 321 stores pattern data such as GDS. The pattern data holds the arrangement position and size of the block (IP), and each block is composed of a plurality of smaller blocks.

  The pattern data has a hierarchical structure, and an example is shown in FIG. Tier 1 is a top (TOP) cell 401. It can be seen from the hierarchy 2 that the top cell 401 is composed of the logic 402 and the memory 403. Further, it can be seen from the hierarchy 3 that the logic 402 is composed of an IO 404 and an MPU 405, and the memory 403 is composed of cell arrays 406 and 407 and a peripheral circuit (Peri) 408 which is a peripheral circuit. Here, up to layer 3 is shown, but these blocks are configured by smaller blocks.

  The block hierarchy extraction unit 311 extracts hierarchy information as shown in FIG. 26 from the pattern data stored in the pattern storage unit 321.

  The pattern density calculation unit 312 calculates the pattern density average value and the variation of the pattern density for each block of each layer. Here, the pattern density is any one of coverage, edge density, or sensitivity evaluation value. Since the method of obtaining the coverage, edge density, and sensitivity evaluation value is the same as in the first embodiment, description thereof is omitted.

  The pattern density calculation unit 312 divides each block into a plurality of regions (divided inspection regions), and calculates the pattern density for each divided inspection region. Then, an average value and variation of the pattern density are obtained. The variation is, for example, standard deviation.

  The pattern density calculation unit 312 divides each block into, for example, a lattice-shaped divided inspection region. Considering the stage accuracy of the apparatus, the grid size is preferably 10 μm or more on a side. Further, when the lattice size is increased, a coarse / dense pattern is mixed in one lattice, and therefore, one side of 50 μm or less is preferable.

  FIG. 27 shows an example of obtaining the average value and variation of the pattern density for each block shown in FIG. Edge density is used as the pattern density. The shallower the hierarchy, the more patterns are included, so the variation in pattern density becomes larger, and the variation in pattern density becomes smaller as the hierarchy becomes deeper.

  The pattern density calculation unit 312 stores the calculated pattern density average value and pattern density variation of each block in the pattern density storage unit 322.

  This defect inspection apparatus classifies each block into three groups: a group having a small pattern density variation and a large average value, a group having a small pattern density variation and a small average value, and a group having a large pattern density variation. Then, inspection parameters (sensitivity) are set for each group, and defect inspection is performed. Since an appropriate inspection parameter (sensitivity) is set for blocks belonging to a group having a small variation in pattern density, the defect detection rate is improved.

  Here, a variation boundary value (threshold value) between a group having a large variation in pattern density and a small group is referred to as a variation specification. The variation spec is determined by the variation spec determining unit 313.

  FIG. 28 shows the relationship between the variation specification and the number of blocks belonging to a group with small variation in pattern density (pattern density variation is less than variation specification).

  The smaller the variation spec, the smaller the number of blocks whose pattern density variation is less than the variation spec. As the variation specification increases, the number of blocks whose pattern density variation is less than the variation specification increases.

  Further, when the variation spec is increased to some extent, shallow blocks having a large variation including many patterns belong to a group having a small variation in pattern density, so that the number of blocks whose pattern density variation is less than the variation spec decreases.

  The graph as shown in FIG. 28 is obtained by changing the variation specification by a predetermined step from the initial value and counting the number of blocks belonging to the group having a small variation in pattern density at that time.

  The number of blocks (number of areas) for which inspection parameters (sensitivity) can be set by the defect inspection apparatus is determined in advance, and cannot be a variation specification in a range larger than the maximum set number of blocks (x1 to x2 in the figure). Accordingly, the variation spec is set to a value of x1 or less or x2 or more. The maximum number of set blocks varies depending on the apparatus, and is usually about several hundred to 1,000.

  Next, FIG. 29 shows the relationship between the variation specification and the total area of blocks belonging to a group with small variation in pattern density (pattern density variation is less than variation specification).

  As the variation specs increase, the total area also increases.

  When the variation spec is x1 or less, since the pattern density variation is small, the defect detection rate can be increased, but the target area is reduced. On the other hand, when the variation specification is x2 or more, the target area can be increased, but the defect detection rate decreases because the pattern density variation is large. Whether the variation specification is set to x1 or less or x2 or more is determined based on the requirement of defect inspection to be performed.

  In this way, the variation spec determining unit 313 determines the variation spec. The determined variation specification is stored in the pattern density storage unit 322.

  The low variation area extraction unit 314 uses the determined variation specification to extract blocks belonging to a group having a small pattern density variation (pattern density variation less than the variation specification).

  For example, when the average value and variation of the pattern density as shown in FIG. 27 are obtained and the variation specification (standard deviation σ) is 0.02, the MPU 405 and the cell arrays 406 and 407 are extracted.

  The pattern density grouping unit 315 groups the extracted regions (blocks) into two groups, a group having a high pattern density average value and a group having a low pattern density average value. The boundary value (threshold value) of the pattern density average value is determined in advance according to the pattern density parameter (coverage rate, edge density, or sensitivity evaluation value) to be used.

  In the example shown in FIG. 27, when the boundary value of the pattern density (edge density) average value is 0.1, the cell arrays 406 and 407 are grouped in a group having a high pattern density average value, and the MPU 405 is grouped in a group having a low pattern density average value. Divided. In addition, the IO 404 and the peripheral circuit (Peri) 408 that are not extracted by the low variation area extraction unit 314 are a group having a large variation in pattern density.

  In this way, as shown in FIG. 30, there are three groups in which the inspection area has a small pattern density variation and a large average value, a group having a small pattern density variation and a small average value, and a group having a large pattern density variation. It is classified into one group.

  The grouped examination area information is stored in the examination area storage unit 323.

  The defect inspection unit 330 sets inspection parameters (sensitivity) for each group based on the inspection area information. An example of the inspection parameter (sensitivity) setting is shown in FIG. Sensitivity A to C is set for each group. Then, defect inspection is performed to detect defects. The detection result is stored in the defect storage unit 324. The coordinates and image of the detected defect are displayed on the display unit 340.

The defect inspection method according to the present embodiment will be described with reference to the flowchart shown in FIG.
(Step S3201) A block hierarchy is extracted from pattern data (GDS or the like).
(Step S3202) Each block is divided into grids, and a pattern density (coverage rate or edge density or sensitivity evaluation value) is calculated for each grid.
(Step S3203) The average value and variation (for example, standard deviation) of the pattern density of each block are calculated.
(Step S3204) The initial value of the variation specification is set.
(Step S3205) The number of blocks whose pattern density variation is less than the variation spec is counted.
(Step S3206) If it is the final variation specification, the process proceeds to step S3208. If it is not the final variation specification, the process proceeds to step S3207.
(Step S3207) The variation specification is changed by a predetermined step.
(Step S3208) A variation specification is determined based on the number of blocks whose pattern density variation is less than the variation specification and the maximum number of set blocks.
(Step S3209) A block whose pattern density variation is less than the variation spec determined in step S3108 is extracted.
(Step S3210) The blocks extracted in step S3209 are classified into a plurality of groups based on the pattern density average value.
(Step S3211) Inspection parameters (sensitivity) are set for each of the group classified in Step S3210 and the group composed of blocks not extracted in Step S3209.
(Step S3212) A defect inspection is performed based on the set inspection parameter (sensitivity).

  By extracting areas (blocks) with little variation in pattern density in this way, and further performing grouping based on the pattern density average value and setting the sensitivity for each group, variation in the reflection intensity of inspection light can be suppressed. And the defect detection rate can be improved.

  In addition, by using the edge density or sensitivity evaluation value instead of the coverage as the pattern density, it is possible to extract a region that more accurately reflects the reflection intensity of the inspection light, and to further improve the defect detection rate.

  The defect inspection apparatus according to this embodiment can be used for the defect inspection apparatus 104 of the semiconductor manufacturing system according to the second embodiment shown in FIG.

  The technical scope of the present invention is defined by the terms of the claims, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

It is a schematic block diagram of the defect inspection apparatus by the 1st Embodiment of this invention. It is a figure showing an example of inspection field division in the defect inspection device. It is a figure which shows an example of the coverage calculation in the same defect inspection apparatus. It is a figure which shows an example of edge density calculation in the same defect inspection apparatus. It is a figure which shows an example of edge density calculation in the same defect inspection apparatus. It is a figure which shows an example of edge density calculation in the same defect inspection apparatus. It is a figure which shows another example of edge density calculation in the same defect inspection apparatus. It is a figure which shows another example of edge density calculation in the same defect inspection apparatus. It is a figure which shows an example of the sensitivity evaluation value calculation in the same defect inspection apparatus. It is a figure which shows an example of the sensitivity rank setting in the same defect inspection apparatus. It is a figure which shows an example of the simplification process in the same defect inspection apparatus. It is a figure which shows an example of the simplification process in the same defect inspection apparatus. It is a figure which shows an example of the simplification process in the same defect inspection apparatus. It is a figure which shows an example of the simplification process in the same defect inspection apparatus. It is a figure which shows an example of the simplification process in the same defect inspection apparatus. It is a figure which shows an example of the rectangular division process in the same defect inspection apparatus. It is a figure which shows another example of the rectangular division process in the same defect inspection apparatus. It is a figure which shows an example of the sensitivity rank reset in the same defect inspection apparatus. It is a figure which shows an example of the defect inspection execution area | region in the same defect inspection apparatus. It is a schematic block diagram of the semiconductor manufacturing system by the 2nd Embodiment of this invention. It is a figure which shows another example of the simplification process in a defect inspection apparatus. It is a figure which shows another example of the simplification process in a defect inspection apparatus. It is a figure which shows another example of the simplification process in a defect inspection apparatus. It is a figure which shows another example of the simplification process in a defect inspection apparatus. It is a schematic block diagram of the defect inspection apparatus by the 3rd Embodiment of this invention. It is a figure which shows an example of the hierarchical structure of pattern data. It is a figure which shows an example of the average value and dispersion | variation in the edge density of each block. It is a graph which shows the relationship between variation specification and the number of blocks whose pattern density dispersion | variation is less than variation specification. It is a graph which shows the relationship between variation specification and the total area of the block whose pattern density dispersion | variation is less than variation specification. It is a figure which shows an example of grouping of a block. It is a figure which shows an example of the sensitivity setting to the grouped circuit block. It is a flowchart of the defect inspection method by the same embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Design part 2 Inspection area division part 3 Coverage rate / edge density calculation part 4 Sensitivity rank setting part 5 Inspection execution area setting part 6 Defect inspection part 7 Defect classification part 8 Sensitivity library 9 Defect data storage part 10 Display part

Claims (4)

An inspection area dividing unit that divides an area for defect inspection of a wafer on which a circuit pattern is formed into a plurality of divided inspection areas;
A pattern density calculation unit that calculates a pattern density for each of the divided inspection regions based on design data of the circuit pattern;
An inspection execution region / sensitivity rank setting unit for setting a sensitivity rank based on the pattern density in a plurality of inspection execution regions each having a plurality of the divided inspection regions;
A defect inspection unit that sets inspection parameters based on the sensitivity rank of the inspection execution region and performs defect inspection of the inspection execution region;
Equipped with a,
The pattern density calculation unit calculates a wiring edge density as the pattern density, or a sensitivity evaluation value based on a wiring edge density and a wiring coverage,
The inspection execution region / sensitivity rank setting unit sets a sensitivity rank for each of the divided inspection regions based on the pattern density, and groups the plurality of divided inspection regions adjacent to each other and having the same sensitivity rank set. A defect inspection apparatus characterized by simplifying grouped shapes and setting the inspection execution area . Dividing the wafer defect inspection area on which the circuit pattern is formed into multiple division inspection areas,
Calculate the pattern density for each of the division inspection regions based on the design data of the circuit pattern,
A sensitivity rank based on the pattern density is set in a plurality of inspection execution regions each having a plurality of the divided inspection regions,
A defect inspection method for setting an inspection parameter based on a sensitivity rank of the inspection execution area and performing a defect inspection of the inspection execution area ,
Calculate the sensitivity evaluation value based on the wiring edge density, or the wiring edge density and the wiring coverage as the pattern density,
A sensitivity rank for each of the divided inspection areas is set based on the pattern density, a plurality of the divided inspection areas that are adjacent to each other and set with the same sensitivity rank are grouped, and a grouped shape is simplified to perform the inspection. A defect inspection method characterized by setting an execution area . A pattern forming apparatus for forming a circuit pattern on a wafer based on apparatus parameters;
An inspection area dividing unit that divides an area for defect inspection of the wafer on which the circuit pattern is formed into a plurality of divided inspection areas, a pattern that calculates a pattern density for each of the divided inspection areas based on design data of the circuit pattern A density calculation unit, an inspection execution region / sensitivity rank setting unit for setting a sensitivity rank based on the pattern density in a plurality of inspection execution regions each having a plurality of the divided inspection regions, and an inspection based on the sensitivity rank of the inspection execution region A defect inspection apparatus having a defect inspection unit for setting a parameter, performing a defect inspection of the inspection execution region, and outputting an inspection result;
A device parameter control unit that generates correction information of the device parameter based on the inspection result and outputs the correction information to the pattern forming device;
Equipped with a,
The pattern density calculation unit calculates a wiring edge density as the pattern density, or a sensitivity evaluation value based on a wiring edge density and a wiring coverage,
The inspection execution region / sensitivity rank setting unit sets a sensitivity rank for each of the divided inspection regions based on the pattern density, and groups the plurality of divided inspection regions adjacent to each other and having the same sensitivity rank set. A system for manufacturing a semiconductor device, wherein the inspection execution area is set by simplifying a grouped shape . A circuit pattern is formed on the wafer based on the device parameters,
Dividing an area for defect inspection of the wafer on which the circuit pattern is formed into a plurality of divided inspection areas;
Calculate the pattern density for each of the division inspection regions based on the design data of the circuit pattern,
A sensitivity rank based on the pattern density is set in a plurality of inspection execution regions each having a plurality of the divided inspection regions,
Set inspection parameters based on the sensitivity rank of the inspection execution area, perform defect inspection of the inspection execution area,
Correcting the device parameters based on the results of the defect inspection;
A method of manufacturing a semiconductor device that forms a circuit pattern on a wafer based on the corrected device parameters ,
The pattern density calculation unit calculates a wiring edge density as the pattern density, or a sensitivity evaluation value based on a wiring edge density and a wiring coverage,
The inspection execution region / sensitivity rank setting unit sets a sensitivity rank for each of the divided inspection regions based on the pattern density, and groups the plurality of divided inspection regions adjacent to each other and having the same sensitivity rank set. A method of manufacturing a semiconductor device, wherein the inspection execution area is set by simplifying a grouped shape .

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