JP4945226B2 - Trimming circuit - Google Patents

Description

  The present invention relates to a trimming circuit that generates and outputs a trimming signal for causing a trimming target circuit to be trimmed (adjusted) in a large scale integrated circuit (hereinafter referred to as “LSI”) or the like. It is.

  Conventionally, as a technique related to a trimming circuit, for example, there are those described in the following documents.

JP-A-5-63090 JP 2006-277808 A

  In the conventional trimming circuits described in these Patent Documents 1 and 2, either one of trimming data input from the outside or trimming data generated by cutting a fuse in the fuse circuit is selected by a selector. It is selected and supplied to a circuit to be trimmed that is a trimming target.

  As another conventional trimming circuit, in a system LSI or the like equipped with an analog circuit, a fuse circuit, a flash memory, or a one time programmable read only memory (One Products that support variations in individual device (device) characteristics, such as those equipped with Time Programmable read only memory (hereinafter referred to as “OTP”) and those that change setting values with a metal mask, are also known. Yes.

  However, the conventional trimming circuit has the following problems (a) and (b).

  (A) In the conventional trimming circuits described in Patent Documents 1 and 2, a circuit for generating a selection signal or the like for selecting the selector is required, but this circuit is complicated and the number of circuit elements increases. As a result, the circuit scale increases and it is difficult to reduce the circuit scale of the trimming circuit.

  (B) In other conventional trimming circuits using fuse circuits, OTPs, metal masks, etc., excluding flash memory, set values that have been determined once are taken as countermeasures against characteristic variations due to those fuse circuits, OTPs, metal masks, etc. There is a drawback that it cannot be changed. Because of these drawbacks, the setting value cannot be changed in the evaluation when the circuit to be trimmed is trimmed, so a large number of samples are required. For example, the setting value is changed after shipment from the semiconductor manufacturer to the user. It is impossible to deal with problems and improve characteristics.

  As a countermeasure against this, for example, a method of making the setting value variable by providing a central processing unit (hereinafter referred to as “CPU”) or a register that can be set using another method for the setting value can be considered. However, in the setting by the register, the value must be set every time when starting up, and disadvantages such as software creation on the user side and increase in starting time occur. Moreover, if the number of registers is large, it may not be possible to cope with it.

Accordingly, the present invention is conventional the problems (a), in order to resolve the (b), and restriction data setting circuit as limiting data setting means such as a fuse circuit, a variable, variable data setting means as many times Both of these registers can be mounted together, and both of these means can be switched to provide flexibility in trimming evaluation and after shipment from a semiconductor manufacturer. Furthermore, the circuit configuration is simplified and the circuit scale is reduced. An object of the present invention is to provide a trimming circuit that can be miniaturized.

The trimming circuit of the present invention has a limit data setting circuit , a read circuit, and a register .

The limit data setting circuit is configured to generate an execution trimming signal to be supplied to the trimming circuit based on the set limit data when limit data with a limited number of changes is set. The read circuit is a circuit for reading the execution trimming signal generated by the limit data setting circuit based on a read signal. Further, the register generates a trimming signal for evaluation to be supplied to the circuit to be trimmed based on a function for holding the execution trimming signal read by the reading circuit and variable data to be set. A holding function, and selects either the held evaluation trimming signal or the execution trimming signal and supplies the selected trimming signal to the trimming circuit.

According to the present invention, the read circuit for reading the output signal of the limit data setting circuit and the register for holding the read output signal are provided, and in the register, variable data other than the limit data setting circuit can be set. Is provided. Therefore, before setting the limit data in the limit data setting circuit, the evaluation trimming signal can be generated by setting the variable data in the register. Furthermore, after setting the limit data in the limit data setting circuit, whether or not the read operation is performed by the read circuit, or the limit data setting circuit is enabled or disabled after the read operation is performed. Is possible. This improves trimming evaluation and ease of use after shipment from a semiconductor manufacturer, and facilitates handling when a problem occurs.
In addition, since switching between the evaluation trimming signal and the execution trimming signal to be applied to the circuit to be trimmed is performed by the readout circuit, the circuit configuration for the switching can be simplified and the circuit scale can be reduced.

Trimming circuit, and mixed and restriction data setting circuit as limiting data setting means such as a fuse circuit, both the register as a variable, variable data setting means many times, can be switched by the selection means of these two means I have to.

(Configuration of Example 1)
FIG. 1 is a schematic configuration diagram of a trimming circuit showing a first embodiment of the present invention.
This trimming circuit is, for example, a circuit provided in various circuits and systems such as an LSI for adjusting an analog circuit, etc., and a limit data setting means (for example, a limit data setting circuit such as a fuse circuit or OTP) 10; A variable data setting unit (for example, a register) 20 is provided, and an output side of the variable data setting unit (for example, a register) 20 is connected to a trimming target circuit 40 to be trimmed via a selection unit (for example, a logic circuit) 30.

  The limit data setting circuit 10 executes n bits to be supplied to the trimming circuit 40 based on the limit data D10 when the limit data D10 whose number of changes is limited (for example, can be changed only once) is set. This is a circuit for generating and outputting the trimming signal S10 for output. For example, the limit data setting circuit 10 has a function of outputting all “0” as the n-bit execution trimming signal S10 without writing the limit data D10. The register 20 is, for example, a register having an n-bit initial value of “0”. When variable data D20 that is write data from the CPU or the like is set, the register 20 is supplied to the trimming circuit 40 based on the variable data D20. This circuit generates and outputs an evaluation trimming signal S20 to be supplied. A logic circuit 30 is connected to the output side of the control data setting circuit 10 and the register 20.

When the evaluation trimming signal S20 is output from the register 20 , the logic circuit 30 selects the evaluation trimming signal S20 and applies it to the trimmed circuit 40, and the evaluation trimming signal S20 is not output from the register 20. In some cases, it is a circuit that selects the execution trimming signal S10 and applies it to the circuit to be trimmed 40, and is composed of, for example, n two-input OR gates (hereinafter referred to as "OR gates") 31-1 to 31-n. Has been.

FIG. 2 is a configuration diagram showing an outline of OTP when the limit data setting circuit 10 in FIG. 1 is configured by, for example, OTP.

  The OTP is a kind of programmable read only memory (hereinafter referred to as “PROM”), and has a structure in which, for example, an erasure window in an irreducible PROM (hereinafter referred to as “EPROM”) is omitted. Data can be written to the memory cell only once.

  This OTP has a memory cell matrix 11 for data storage. The memory cell matrix 11 has a plurality of word lines WL and a plurality of bit lines BL orthogonal to the word lines WL, and memory cells (not shown) connected to the intersections are arranged in a matrix. A row address decoder 12 for selecting this is connected to the plurality of word lines WL. Further, a column address decoder 14 for bit line selection is connected to the plurality of bit lines BL via an input / output circuit 13.

  When the limit data D10 is written, the limit data D10 is input to the input / output circuit 13 and written to the memory cell selected by the row address decoder 12 and the column address decode 14. When the execution trimming signal S10 is output, the limit data D10 is read from the memory cell selected by the row address decoder 12 and the column address decode 14, and this is output by the input / output circuit 13 to the execution trimming signal S10. Is converted to output.

FIG. 3 is a configuration diagram showing an outline of one fuse circuit when the limit data setting circuit 10 in FIG. 1 is configured by, for example, n fuse circuits.

  One fuse circuit has a load resistor 15, an output terminal 16, and a laser fuse 17, which are connected in series between the power supply voltage VDD node and the ground. When n-bit limit data D10 is set in n fuse circuits, the laser fuse 17 at a location corresponding to the limit data D10 is cut. When the laser fuse 17 is cut, the potential of the output terminal 16 becomes the “H” level (= “1”) on the power supply voltage VDD side. When the laser fuse 17 is not cut, the potential of the output terminal 16 becomes the “L” level (= “0”) on the ground side. As a result, an n-bit execution trimming signal S10 is output from the output terminals 16 of the n fuse circuits.

(Operation of Example 1)
First, in the stage of evaluating the trimming operation of the trimming circuit 40, the limit data setting circuit 10 is not used (the output is set to all “0” in an invalid state), and variable data of various trimming codes is obtained from the CPU or the like. D20 is set in the register 20. Then, an evaluation trimming signal S20 corresponding to the trimming code is output from the register 20, and is selected by the logic circuit 30 and supplied to the trimming circuit 40. The trimming circuit 40 performs a trimming operation. The output signal of the trimming circuit 40 is monitored (measured) by a tester or the like, and when the desired output signal is output, the trimming signal S20 having the optimum trimming code is found (can be searched), and the trimming operation using the register 20 is performed. Is completed.

  After the optimum value of the trimming code is determined, the limit data D10 of the pattern corresponding to this is set (written) in the limit data setting circuit 10. At this time, the variable data D20 is not set in the register 20, but the output of the register 20 is set to all "0" by a reset signal or the like at the start of the system provided with the trimming circuit of the first embodiment. Then, the execution trimming signal S10 output from the limit data setting circuit 10 becomes valid, and is selected by the logic circuit 30 and applied to the trimming circuit 40. In other words, after the trimming using the register 20 is completed, the trimming signal S10 to the trimming circuit 40 is fixed by performing the trimming using the limit data setting circuit 10, and the trimming circuit 40 is optimal. Trimming operation is performed.

(Effect of Example 1)
According to the first embodiment, in a trimming circuit provided in various circuits such as an LSI or a system, when setting a signal inside the circuit, the output value is limited to “0” once before the set value is changed. The limit data setting circuit 10 that can change the setting of the data D10, the register 20 that can change the setting of the variable data D20 any number of times, and the output of the limit data setting circuit 10 are enabled or the output of the register 20 is enabled In order to select whether or not, the logic circuit 30 that takes the logical sum of the two is provided, and the following effects are obtained.

  In the evaluation stage for the circuit 40 to be trimmed, the variable data D20 is set in the register 20 for evaluation, so that the set value can be changed any number of times. After the optimum value is determined, the restriction data D10 corresponding to the optimum value is set in the restriction data setting circuit 10. Thereby, for example, every time the system is started, the register 20 is initialized by the reset signal and the output becomes all “0”, and the output of the register 20 is invalidated. The trimming signal S10 to be performed is selected by the logic circuit 30 and supplied to the circuit to be trimmed 40 for trimming. Therefore, it is possible to save the trouble of resetting the optimum value in the register 20 every time the system is started. In addition, since no other circuit for selectively operating the logic circuit 30 is required, the circuit configuration can be simplified and the circuit scale can be reduced.

(Configuration of Example 2)
FIG. 4 is a schematic configuration diagram of a trimming circuit showing a second embodiment of the present invention. Elements common to those in FIG. 1 showing the first embodiment are denoted by common reference numerals.

In the trimming circuit according to the second embodiment, instead of the limit data setting circuit 10 according to the first embodiment, a limit data setting circuit that can change the setting of the limit data D10A only once when the output value is “1” before the set value is changed. In addition, in place of the logic circuit 30 of the first embodiment, a logic circuit 30A including n 2-input AND gates (hereinafter referred to as “ AND gates”) 31A-1 to 31A-n is provided. It has been. Other configurations are the same as those of the first embodiment.

(Operation of Example 2)
Since the output value of the limit data setting circuit 10A is “1” at the stage of evaluation of the trimming circuit 40, the output of the register 20 is not used by the logic circuit 30A without using the output of the limit data setting circuit 10A. Is selected. Then, variable data D20 as write data from the CPU or the like is set in the register 20, and the evaluation trimming signal S20 output from the register 20 is selected by the logic circuit 30A and supplied to the trimming circuit 40 for trimming operation. Is done. As a result, the optimum setting value for the trimming circuit 40 can be searched while the restriction data setting circuit 10A that can be changed only once is invalid.

  After the optimum value is determined, the restriction data D10A corresponding to the optimum value is written and set in the restriction data setting circuit 10A. Then, the variable data D20 is not set in the register 20, for example, by initializing the register 20 with a reset signal at system startup. As a result, the execution trimming data S10A output from the limit data setting circuit 10A is selected by the logic circuit 30A, so that the limit data setting circuit 10A becomes valid, and the execution trimming signal S10A causes the trimming circuit 40 Trimming operation is performed.

(Effect of Example 2)
According to the second embodiment, as in the first embodiment, in the evaluation stage, the variable data D20 is set in the register 20 for evaluation. Therefore, the set value can be changed any number of times, and after the optimum value is determined, By setting the limit data D10A in the limit data setting circuit 10A, it is possible to save the trouble of resetting the optimum value every time the system is started. In addition, since no other circuit for selectively operating the logic circuit 30A is required, the circuit configuration can be simplified and the circuit scale can be reduced.

(Configuration of Example 3)
FIG. 5 is a schematic configuration diagram of a trimming circuit showing a third embodiment of the present invention. Elements common to those in FIG. 1 showing the first embodiment are denoted by common reference numerals.

  In the trimming circuit of the third embodiment, an output control means (for example, an output control circuit) 50 is added between the output side of the limited data setting circuit 10 of the first embodiment and the input side of the logic circuit 30.

  The output control circuit 50 is a circuit that controls (for example, invalidates) the output of the execution trimming signal S10 from the limit data setting circuit 10 to the logic circuit 30 based on the control signal (for example, invalidation signal) S50. It is composed of n two-input AND gates 51-1 to 51-n. Each of the AND gates 51-1 to 51-n has one input terminal connected to the output terminal of the limit data setting circuit 10, the other input terminal to which the invalidation signal S50 is input, and the output terminal connected to each OR terminal. The gates 31-1 to 31-n are connected to the input terminals. Other configurations are the same as those of the first embodiment.

(Operation of Example 3)
The output control circuit 50 has a function of invalidating the output signal of the restriction data setting circuit 10 that can change the setting of the restriction data S10 only once by the invalidation signal S50 and validating only the set value of the register 20. ing. Therefore, after the setting value is fixed to “1” by the restriction data setting circuit 10, the restriction data setting circuit 10 is invalidated and the register 20 that can be changed any number of times is invalidated. This is made possible by enabling the signal S50 and writing the variable data D20, which is write data from the CPU or the like, into the register 20.

(Effect of Example 3)
According to the third embodiment, since the output control circuit 50 is provided, even after the limit data setting circuit 10 is set, the limit data setting circuit 10 can be disabled and the register 20 can be enabled. it can. As a result, the set value can be changed without exchanging the device, and it becomes possible to cope with a failure.

(Configuration of Example 4)
FIG. 6 is a schematic configuration diagram of a trimming circuit showing a fourth embodiment of the present invention. Elements common to those in FIG. 4 showing the second embodiment are denoted by common reference numerals.

  In the trimming circuit of the fourth embodiment, output control means (for example, an output control circuit) 50A is added between the output side of the limited data setting circuit 10A of the second embodiment and the input side of the logic circuit 30A.

  The output control circuit 50A is a circuit that controls (for example, invalidates) the output of the execution trimming signal S10A from the limit data setting circuit 10A to the logic circuit 30A based on the control signal (for example, invalidation signal) S50A. It is composed of n two-input OR gates 51A-1 to 51A-n. Each of the OR gates 51A-1 to 51A-n has one input terminal connected to the output terminal of the limited data setting circuit 10A, the other input terminal to which the invalidation signal S50A is input, and the output terminal connected to each AND. The gates 31A-1 to 31A-n are connected to the input terminals. Other configurations are the same as those of the second embodiment.

(Operation of Example 4)
The output control circuit 50A has a function of invalidating the output signal of the limit data setting circuit 10A that can change the setting of the limit data S10A only once by the invalidation signal S50A and enabling only the set value of the register 20. ing. Therefore, after the setting value is fixed to “0” by the restriction data setting circuit 10A, the restriction data setting circuit 10A is invalidated, and the register 20 that can be changed over and over is invalidated. This is made possible by enabling the signal S50A and writing the variable data D20, which is write data from the CPU or the like, into the register 20.

(Effect of Example 4)
According to the fourth embodiment, there are the same effects as the third embodiment.

(Configuration of Example 5)
FIG. 7 is a schematic configuration diagram of a trimming circuit showing a fifth embodiment of the present invention. Elements common to those in FIG. 1 showing the first embodiment are denoted by common reference numerals.

  In the trimming circuit according to the fifth embodiment, a read circuit 60 and variable data setting means (for example, a register) 20A are provided instead of the register 20 and the logic circuit 30 according to the first embodiment. A register 20A is connected to the output side of the limit data setting circuit 10 similar to that of the first embodiment via a read circuit 60, and a circuit to be trimmed 40 is connected to the output side of the register 20A.

  The readout circuit 60 is a circuit that reads out the execution trimming signal S10 generated by the restriction data setting circuit 10 based on the readout signal S60 and supplies it to the register 20A. The register 20A has a function of holding the execution trimming signal S10 read by the reading circuit 60 and variable data D20A that is write data from the CPU or the like, and supplies the trimming signal for evaluation to the trimming circuit 40. This circuit has a function of generating and holding S20A, and selects one of the held evaluation trimming signal S10 or execution trimming signal S20A and supplies it to the trimmed circuit 40.

(Operation of Example 5)
Before the limit data D10 is set in the limit data setting circuit 10 that can be changed only once, the variable data D20A is written and set from the CPU or the like to the register 20A. Thus, the evaluation trimming signal S20A is output from the register 20A, the trimming operation for the circuit to be trimmed 40 is evaluated, and the optimum value of the evaluation trimming signal S20A is determined.

  When the optimum value is determined, the restriction data D10 that can be changed only once corresponding to the optimum value is set in the restriction data setting circuit 10. Thereafter, when the system is started, the read signal S60 is input to the read circuit 60, and the read trimming signal S10 is read from the limited data setting circuit 10 by the read circuit 60 and written to the register 20A. The execution trimming signal S10 written in the register 20A is supplied to the trimming circuit 40, and the trimming circuit 40 performs a trimming operation.

  When the limit data D10 is set in the limit data setting circuit 10 and the setting value is incorrect and is corrected, or when the trimming circuit is operated with data different from the limit data D10 set in the limit data setting circuit 10. The desired variable data D20A is written from the CPU or the like to the register 20A without performing the read operation by the read circuit 60 or after the read operation, and the trimming circuit 40 is controlled by a control signal based on the written data D20A. To work.

(Effect of Example 5)
According to the fifth embodiment, the read circuit 60 that reads the output signal of the limit data setting circuit 10 and the register 20A that holds the read output signal are included. The register 20A includes other than the limit data setting circuit 10. A function for setting data from the CPU or the like is provided. Therefore, before setting the limit data D10 in the limit data setting circuit 10, the evaluation trimming signal S20A can be generated by setting the variable data D20A in the register 20A as in the first and second embodiments. Further, after setting the limit data D10 in the limit data setting circuit 10, the read circuit 60 performs or does not perform the read operation, or enables or disables the limit data setting circuit 10 after performing the read operation. It becomes possible to make it. This improves trimming evaluation and ease of use after shipment from a semiconductor manufacturer, and facilitates handling when a problem occurs.

  In addition, since switching between the evaluation trimming signal S20A and the execution trimming signal S10 to be applied to the trimming circuit 40 is performed by the readout circuit 60, the circuit configuration for the switching can be simplified and the circuit scale can be reduced. Become.

(Configuration of Example 6)
FIG. 8 is a schematic configuration diagram of a trimming circuit showing Embodiment 6 of the present invention.
This trimming circuit has a limit data setting means (for example, limit data setting circuit) 10B, and its output side is connected to the trimming circuit 40 via an output control means (for example, output control circuit) 70. .

The limit data setting circuit 10B has an n-bit limit data setting unit 18 for setting the n-bit limit data D10B in which the number of changes is limited (for example, once), and the number of changes is limited (for example, once). and a n-bit limit data setting unit 19 for setting the n bits of restriction data D10B1 was, the restriction data D10B is set, based on this limited data D10B, for execution to be supplied to the trimming circuit 40 This circuit generates and outputs a trimming signal S10B. Each limit data setting unit 18 and each limit data setting unit 19 have a function of outputting “0” without writing, and outputting “1” when writing is performed. For example, the OTP in FIG. Or the fuse circuit of FIG.

The output control circuit 70 includes n inverters 71-1 to 71-n for inverting the n-bit restriction data D10B1 set in the n-bit restriction data setting unit 19, and n two-input AND gates 72-1. To 72-n. The n 2-input AND gates 72-1 to 72-n include the n-bit restriction data D10B set in the n-bit restriction data setting unit 18 and the output data of the n inverters 71-1 to 71-n. And controls the output of the execution trimming signal S10B.

(Operation of Example 6)
In FIG. 8, for example, after “1” is set in one bit of a circle in the n-bit limit data setting unit 18, AND is set by setting “1” in the limit data setting unit 19 of the adjacent bit. The execution trimming signal S10B output from the gate 72-n can be invalidated ("0"). This makes it possible to invalidate the limit data D10B set only once in the limit data setting unit 18 that can change the setting only once.

(Effect of Example 6)
According to the sixth embodiment, since the output control circuit 70 is provided, even after the limit data D10B is set in the limit data setting unit 18, the limit data setting unit 18 can be invalidated only once. . This makes it possible to change the set value without replacing the device, improving the ease of use after evaluation and shipping from the semiconductor manufacturer, and facilitating handling when a failure occurs.

(Configuration of Example 7)
FIG. 9 is a schematic configuration diagram of a trimming circuit showing a seventh embodiment of the present invention. Elements common to those in FIG. 8 showing the sixth embodiment are denoted by common reference numerals.

  The trimming circuit according to the seventh embodiment includes the same limit data setting means (for example, limit data setting circuit) 10B as that of the sixth embodiment. The output side of the trimming circuit is different from that of the sixth embodiment (for example, output control). Circuit) 70A and connected to the trimming circuit 40 similar to that of the first embodiment.

  The output control circuit 70A includes n inverters 71-1 to 71-n for inverting the n-bit control data D10B1 set in the n-bit control data setting unit 19, and n two-input OR gates 72A-1. To 72A-n. The n two-input OR gates 72A-1 to 72A-n include the n-bit limit data D10B set in the n-bit limit data setting unit 18 and the output data of the n inverters 71-1 to 71-n. Is a circuit that controls the output of the execution trimming signal S10B.

(Operation of Example 7)
In FIG. 9, for example, after setting “0” to one bit of a circle in the n-bit limit data setting unit 18, by setting “0” to the control data setting unit 19 of this adjacent bit, OR The execution trimming signal S10B output from the gates 72A-n can be invalidated (“1”). This makes it possible to invalidate the limit data D10B set only once in the limit data setting unit 18 that can change the setting only once.

(Effect of Example 7)
According to the seventh embodiment, since the output control circuit 70A is provided, there are substantially the same effects as in the sixth embodiment.

(Configuration of Example 8)
FIG. 10 is a schematic configuration diagram of a trimming circuit showing an eighth embodiment of the present invention. Elements common to those in FIGS. 1 and 8 showing the first and sixth embodiments are denoted by common reference numerals. ing.

  The trimming circuit according to the eighth embodiment is configured by combining the limited data setting circuit 10B and the output control circuit 70 according to the sixth embodiment and the register 20 and the logic circuit 30 according to the first embodiment.

(Operation of Example 8)
Before the limit data D10B is set in the limit data setting circuit 10B, the variable data D20 is set in the register 20 from the CPU or the like to perform debugging, evaluation, and the like. After setting the limit data D10B (for example, “1” in the circled bit in FIG. 10) in the limit data setting unit 18, if it is desired to invalidate the limit data D10B, a logical product with the limit data setting unit 18 is obtained. The set value can be invalidated (“0”) by setting “1” in the control data setting unit 19 of the adjacent bit taken. Thereafter, when it is desired to set the value again, normal operation can be realized by setting the variable data D20 in the register 20 from the CPU or the like.

(Effect of Example 8)
According to the eighth embodiment, the set value can be invalidated before or after the limit data D10B is set in the limit data setting circuit 10B. It is possible to realize a countermeasure against erroneous writing of the limited data setting circuit that sets the data D20.

(Configuration of Example 9)
FIG. 11 is a schematic configuration diagram of a trimming circuit showing a ninth embodiment of the present invention. Elements common to those in FIGS. 4 and 9 showing the second and seventh embodiments are denoted by common reference numerals. ing.

  The trimming circuit according to the ninth embodiment is configured by combining the limited data setting circuit 10B and the output control circuit 70A according to the seventh embodiment and the register 20 and the logic circuit 30A according to the second embodiment.

(Operation of Example 9)
Before the limit data D10B is set in the limit data setting circuit 10B, the variable data D20 is set in the register 20 from the CPU or the like to perform debugging, evaluation, and the like. If the restriction data D10B is set in the restriction data setting section 18 (for example, “0” in the circled bit in FIG. 11) and then the restriction data D10B is to be invalidated, a logical sum with the restriction data setting section 18 is obtained. The set value can be invalidated (“0”) by setting “0” in the control data setting unit 19 of the adjacent bit taken. Thereafter, when it is desired to set the value again, normal operation can be realized by setting the variable data D20 in the register 20 from the CPU or the like.

(Effect of Example 9)
According to the ninth embodiment, there are almost the same effects as the eighth embodiment.

(Configuration of Example 10)
FIG. 12 is a schematic configuration diagram of a trimming circuit showing Embodiment 10 of the present invention.
The trimming circuit according to the tenth embodiment includes m number of limit data setting circuits 10-1 to 10-m similar to the limit data setting circuit 10 shown in FIG. 1 according to the first embodiment. A circuit to be trimmed 40 similar to that of the first embodiment is connected via a selector 80 for switching. Furthermore, another restriction data setting means (for example, a restriction data setting circuit) 81 for controlling the switching of the selector 80 is connected to the selector 80. The limit data setting circuit 81 is an n-bit circuit that can change the held data once and holds the addresses AD1 to ADm of the other limit data setting circuits 10-1 to 10-m.

(Operation of Example 10)
After setting the limit data D10 in the limit data setting circuit that can be set only once (for example, the limit data setting circuit 10-1 at the address AD1), if you want to modify the value, the limit data that can be set once for the select signal An address value (for example, AD2) is set in the setting circuit 81. Then, since the setting value of the limit data setting circuit 10-2 that can be set only once for a completely different address AD2 is selected by the switching control signal output from the limit data setting unit 81, it can be set again. It becomes.

(Effect of Example 10)
According to the tenth embodiment, even after the limit data D10 is set in the limit data setting circuit (for example, 10-1), another limit data setting circuit (for example, 10-2) is set by the selector 80. You can select and change the set value. This improves usability.

(Configuration of Example 11)
FIG. 13 is a schematic configuration diagram of a trimming circuit showing an eleventh embodiment of the present invention. Elements common to those in FIGS. 7 and 12 showing the fifth and tenth embodiments are denoted by common reference numerals. ing.

  The trimming circuit according to the eleventh embodiment includes the limited data setting circuits 10-1 to 10-n, 81 and the selector 80 according to the tenth embodiment, and the read circuit 60, the register 20A, and the trimmed circuit 40 according to the fifth embodiment. , Are combined.

(Operation of Example 11)
Before setting the limit data D10 in the limit data setting circuit (for example, 10-1), the variable data D20A is set in the register 20A from the CPU or the like, and debugging, evaluation, and the like are performed. After setting the control data D10 in the limit data setting circuit 10-1, if it is desired to modify the set value, an address value (for example, AD2) is set in the limit data setting circuit 81 for the select signal. Then, since the set value of the limit data setting circuit 10-2 of the completely different address AD2 is selected by the switching control signal output from the limit data setting unit 81, it becomes possible to set again.

(Effect of Example 11)
According to the eleventh embodiment, before setting the limit data D10 in the limit data setting unit (for example, 10-1), the trimming signal to be supplied to the trimming circuit 40 is set by setting the variable data D20A in the register 20A. S20A can be generated. Even after the limit data D10 is set in the limit data setting circuit (for example, 10-1), the selector 80 selects another limit data setting circuit (for example, 10-2) and changes the set value. can do. This improves usability.

(Modification)
This invention is not limited to Examples 1-11, A various utilization form and deformation | transformation are possible. For example, the following forms (1) and (2) are used as the usage form and the modification examples.

  (1) The number of data settings in the limit data setting circuits 10, 10-1 to 10-n,... Is not limited to one, but the OTP in FIG. 2 and the fuse circuit in FIG. It is possible to change several times by devising.

  (2) The limit data setting circuits 10-1 to 10-n and 81 and the selector 80 shown in FIG. 12 can be used in combination with the trimming circuits shown in FIG. 1 and FIGS.

1 is a schematic configuration diagram of a trimming circuit showing Embodiment 1 of the present invention. FIG. It is a block diagram which shows the outline of OTP at the time of comprising the control data setting circuit 10 in FIG. 1 by OTP, for example. It is a block diagram which shows the outline of one fuse circuit at the time of comprising the control data setting circuit 10 in FIG. 1 by n fuse circuits, for example. It is a schematic block diagram of the trimming circuit which shows Example 2 of this invention. It is a schematic block diagram of the trimming circuit which shows Example 3 of this invention. It is a schematic block diagram of the trimming circuit which shows Example 4 of this invention. It is a schematic block diagram of the trimming circuit which shows Example 5 of this invention. It is a schematic block diagram of the trimming circuit which shows Example 6 of this invention. It is a schematic block diagram of the trimming circuit which shows Example 7 of this invention. It is a schematic block diagram of the trimming circuit which shows Example 8 of this invention. It is a schematic block diagram of the trimming circuit which shows Example 9 of this invention. It is a schematic block diagram of the trimming circuit which shows Example 10 of this invention. It is a schematic block diagram of the trimming circuit which shows Example 11 of this invention.

Explanation of symbols

10, 10-1 to 10-m, 10A, 10B, 81 Restricted data setting circuit 20, 20A Register 30, 30A Logic circuit 40 Circuit to be trimmed 50, 50A, 70, 70A Output control circuit 60 Read circuit 70 Selector

Claims (2)

A limit data setting circuit that generates an execution trimming signal to be supplied to the trimming circuit based on the set limit data when the limit data with a limited number of changes is set;
A readout circuit for reading out the execution trimming signal generated by the restriction data setting circuit based on a readout signal;
A function of holding the execution trimming signal read by the reading circuit; and a function of generating and holding an evaluation trimming signal to be supplied to the trimming circuit based on the set variable data. A register that selects one of the held trimming signal for evaluation or the trimming signal for execution and supplies it to the circuit to be trimmed,
A trimming circuit comprising: The limit data setting circuit is composed of a fuse circuit capable of changing the limit data only once, a one-time programmable read-only memory, or a one-time programmable circuit or element. The trimming circuit according to claim 1.

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