JP4934953B2 - Current output type drive circuit and electronic device - Google Patents

Description

  The present invention relates to a current output type driving circuit and an electronic device that output a driving current to each of a plurality of loads such as LEDs (Light Emitting Diodes).

  In recent years, mobile phones have become increasingly sophisticated, and mobile phones equipped with electronic parts such as cameras and a large number of LEDs have become widespread. In addition to being used for the backlight of the liquid crystal display and the operation key, the LED is used to flash according to the incoming melody or to flash according to the progress of the game. On the other hand, low power consumption is required for mobile phones.

  In order to realize this requirement, for example, a current output type driving circuit that controls a power supply voltage supplied to a plurality of LEDs is disclosed (see Patent Document 1). In this current output type drive circuit, the power supply voltage is controlled to the minimum while ensuring the margin necessary for light emission of the LED having the maximum forward voltage, thereby efficiently driving the LED and reducing the power loss. .

In a conventional mobile phone, a plurality of LEDs having different emission colors are turned on / off or blinked using this current output type driving circuit. As the blinking pattern, various blinking patterns such as a blinking pattern in which the brightness changes gently like a firefly as well as a simple ON / OFF repeating pattern are used. These blinking patterns are stored in the ROM as a program, for example.
JP 2004-6533 A

  However, in the conventional mobile phone, the storage capacity of the ROM is limited according to the demand for small size and low power consumption, and thus the storage area of the flashing pattern is also limited, so that more types of flashing patterns can be realized. There was a problem that I couldn't.

  The present invention has been made in view of such circumstances, and an object of the present invention is to provide a current output type driving circuit and an electronic apparatus capable of realizing various types of blinking patterns by a relatively small program. is there.

In order to achieve the above object, a current output type driving circuit according to the present invention includes a first register to which first bit information is input and held, and a plurality of registers to which second bit information is input and held. a second register, for a plurality of loads connected to a common power supply voltage, load and provided each of the second set of registers corresponds, with respect to the corresponding said load, said corresponding second a plurality of current output circuit to output the driving current register of corresponding to a second bit information held, and a reference current generating circuit for changeably generating a reference current in response to the first bit information provided, each of the plurality of current output circuit, one end of which is grounded, the other end, a reference resistor that occur a reference voltage based on the reference current input from the reference current generation circuit, each bit Multiple of different values And the presence or absence of current generation when the reference voltage is applied to each bit resistor is controlled according to the second bit information, and the sum of the generated currents is used as the drive current for the corresponding load. And a current generation circuit for outputting.
The electronic device according to the present invention includes a plurality of light emitting elements that are connected to a power supply voltage by a common power source and emit light in a plurality of colors, and a current output type drive that outputs and controls each driving current of the plurality of light emitting elements. The current output type driving circuit includes a first register that receives and holds first bit information, and a plurality of second bits that receive and hold second bit information. and registers the the plurality of light emitting elements, respectively emitting element and a second set of registers are provided corresponding, for the corresponding light emitting element, a second of said corresponding second register holds comprising of a plurality of current output circuit to output the driving current corresponding to bit information, and a reference current generating circuit for changeably generating a reference current in response to the first bit of information, the plurality of current outputs Each of the circuits is one End of which is grounded, it comprises at the other end, a reference resistor that occur a reference voltage based on the reference current input from the reference current generating circuit, a plurality of bit resistance of different value for each bit, each bit resistance A current generation circuit that controls the presence or absence of current generation when the reference voltage is applied to the output according to the second bit information, and outputs a sum of the generated currents as a drive current of the corresponding light emitting element; Have.

According to the current output type driving circuit and the electronic apparatus of the present invention, since the reference current can be controlled by the main variable current source based on the reference current setting data, the main output current can be changed by changing the reference current setting data. The drive currents of the plurality of current output circuits controlled by the control circuit can be changed.
Therefore, since a plurality of loads, for example, a plurality of light emitting elements can be driven by a combination of the reference current setting data and the drive current setting data, compared to driving a plurality of loads by the drive current setting data program alone, Many types of drive patterns can be realized with a small number of programs.

A plurality of loads connected to a common power supply voltage are driven by respective current output circuits. The current output circuit outputs a drive current based on the drive current setting data of each load. This drive current is controlled by an operational amplifier. Operational amplifier inputs the output voltage of the reference current and the current output circuit amplifies and outputs an error voltage of these. The reference voltage is obtained by a reference resistance circuit to which a reference current generated by the reference current generation circuit is input. The reference current generation circuit includes a variable current source that controls the reference current based on reference current setting data.

Hereinafter, a current output type driving circuit and an electronic apparatus according to the present invention will be described with reference to the drawings.
FIG. 1 is a diagram illustrating a configuration of a current output type driving circuit according to the first embodiment.
As shown in FIG. 1, the current output type driving circuit of the first embodiment is a driving circuit that is provided in, for example, a cellular phone and drives n (n is an integer of 2 or more) LEDs 1-1 to 1-n. is there. Among the n LEDs 1-1 to 1-n, p (p is an integer of 1 or more smaller than n) LEDs 1-1 to 1-p are backlight LEDs for a liquid crystal display (not shown). n−p) LEDs 1− (p + 1) to 1−n are LEDs for notification of incoming calls. The n LEDs 1-1 to 1-n are connected to a common power supply voltage VLED.

  The current output type drive circuit according to the first embodiment includes n current output type DACs (Digital to Analog Converters) 2-1 to 2-n, n error amplifier circuits 3-1 to 3-n, and n pieces. Level shifters 4-1 to 4-n, n synchronization registers 6-1 to 6-n, n logic circuits 7-1 to 7-n, and n control registers 8-1 to 8- n, sampling clock generation circuit 9, data input circuit 10, reference voltage generation circuit 11, reference current generation circuit 12, logic circuit 13, control register 14, minimum voltage detection circuit 15, and reference voltage buffer 16, a power supply voltage control circuit 17, a power supply voltage generation circuit 18, a control circuit 19, a capacitor CBGR, and a resistor REXT.

For example, current output type DAC 2-1, error amplifier circuit 3-1, current source CIS-1 , level shifter 4-1, flag register 5-1, synchronization register 6-1, logic circuit 7-1 and control register 8-1 Are provided corresponding to the LED 1-1. Any one of the LEDs 1-1 to 1-n is represented as LED1-i (i is an integer from 1 to n).

When the enable signal SEN is activated, the data input circuit 10 sequentially outputs serial data SDATA for driving n LEDs 1-1 to 1-n from a host device (not shown) in synchronization with the clock signal SCK. Input, convert to parallel data and output. The serial data SDATA collectively includes commands for turning on / off each of n LEDs 1-1 to 1-n, drive current setting data, and drive currents of (np) LEDs 1- (p + 1) to 1-n. And reference current setting data for control.
When the identification codes ID _{m-1 to} ID ₀ are set, the data input circuit 10 converts the serial data SDATA having the set identification code into parallel data. The identification codes ID _{m-1 to} ID ₀ are set when a plurality of current output type drive circuits of the first embodiment are used, and share the signal line of serial data SDATA with other current output type drive circuits. .

The parallel data converted by the data input circuit 10 is input to the control registers 8-1 to 8-n or the control register 14.
The control register 8-i has, for example, a 2-bit register [MD1, MD0] and a 4-bit register [D3, D2, D1, D0]. The registers [MD1, MD0] store lighting / extinguishing commands for the LEDs 1-i. The registers [D3, D2, D1, D0] store drive current setting data for the LED1-i.
The control register 14 includes, for example, 2-bit registers [R1, R0]. The registers [R1, R0] store reference current setting data.

The logic circuit 7-i performs a logical operation of the turn-on / off instruction stored in the registers [MD1, MD0] of the control register 8-i and the drive current setting data stored in the registers [D3, D2, D1, D0]. (Logical product) is performed, and the calculation result is output as drive current setting data of LED1-i.
When the LED1-i turn-off command is stored in the registers [MD1, MD0], the drive current of the LED1-i is “0” regardless of the data stored in the registers [D3, D2, D1, D1]. When the setting data is output and the LED1-i lighting command is stored in the register [MD1, MD0], the data stored in the register [D3, D2, D1, D1] is used as the driving current setting data for the LED1-i. Is output.
The logic circuit 13 performs a logical operation on the reference current setting data stored in the registers [R1, R0] of the control register 14, and outputs the calculation result as reference current setting data [XSL3, XSL4, XSL5] to the reference current generation circuit 12. Output.

The synchronization register 6-i inputs and holds drive current setting data for the LED1-i output by the logic circuit 7-i in synchronization with the sampling clock signal SAMPLCK.
The level shifter 4-i shifts the signal level of the drive current setting data held in the synchronous register 6-i and outputs control signals for switch circuits SWD3 to SWD0 (described later) of the current output type DAC2-i.

FIG. 2 is a diagram showing the configuration of the current output type DAC 2-i and the error amplifier circuit 3-i shown in FIG. FIG. 3 is a diagram showing the configuration of the switch circuit shown in FIG.
As shown in FIGS. 2 and 3, the error amplifying circuit 3-i drives the driving current of the LED 1-i output from the current output type DAC 2-i and the driving current setting data held in the synchronization register 6-i. This circuit amplifies an error from the current, and is configured by an operational amplifier, for example. A constant current source CIS that supplies a constant reference current IREF is connected to the p error amplifier circuits 3-1 to 3 -p among the n error amplifier circuits 3-1 to 3 -n, and (n A variable current source VIS that supplies a variable reference current IREF is connected to the -p) error amplifier circuits 3- (p + 1) to 3-n. The error amplifier circuit (op-amp) 3-i inputs a reference voltage through the positive input terminal INP, inputs the output voltage of the current output type DAC 2-i through the negative input terminal INN, and amplifies these error voltages. Output through the output terminal AMPO.

  The current output type DAC 2-i forms a feedback loop together with the error amplifier circuit 3-i, and performs feedback control for causing the drive current of the LED 1-i to follow the drive current corresponding to the drive current setting data from the level shifter 4-i. . The current output type DAC2-i includes four nMOS transistors MND3 to MND0, four current detection resistors RMON3 to RMON0, a reference resistor circuit Rref, a capacitor C, and four switch circuits SWD3 to SWD0. .

  The nMOS transistors MND3 to MND0, the current detection resistors RMON3 to RMON0, and the switch circuits SWD3 to SWD0 are bits of the drive current setting data held in the 4-bit registers [D3, D2, D1, D0] of the synchronization register 6-i. It is provided corresponding to each of. Any one of the nMOS transistors MND3 to MND0 is represented as a transistor MNDk (k is an integer of 0 to 3).

  The drain of the nMOS transistor MNDk is connected to the cathode of LED1-i. The source of the nMOS transistor MNDk is grounded via the current detection resistor RMONk. The gate of the nMOS transistor MNDk is connected or grounded to the output terminal AMPO of the error amplifier circuit 3-i through the switch circuit SWDk.

The nMOS transistors MND3 to MND0 are weighted so that the respective output currents are 2 ³ : 2 ² : 2: 1. For example, the nMOS transistors MND2 to MND0 are configured by connecting two, four, and eight transistors equivalent to the transistor MND3 in parallel, respectively.
The current detection resistors RMON3 to RMON0 are weighted so that the respective resistance values are 1: 2: 2 ² : 2 ³ . For example, the current detection resistors RMON2 to RMON0 are configured by connecting two, four, and eight transistors equivalent to the current detection resistor RMON3 in parallel, respectively.

  The switch circuit SWDk includes a switch circuit SWDk1, a switch circuit XSWDk2 that performs a switch operation opposite to the switch circuit SWDk1, and a switch circuit SWDk3 that performs the same switch operation as the switch circuit SWDk1. The switch circuit SWDk1 performs a switching operation between the output terminal AMPO of the error amplifier circuit 3-i and the gate of the nMOS transistor MNDk. The switch circuit XSWDk2 performs a switching operation between the gate of the nMOS transistor MNDk and the ground (GND). The switch circuit SWDk3 performs a switching operation between the negative input terminal INN of the error amplifier circuit 3-i and the source of the nMOS transistor MNDk.

  When the bit of the drive current setting data is “1”, the switch circuit SWDk connects the transistor MNDk to the error amplifier circuit 3-i to set the transistor MNDk to the on state, and the bit of the drive setting data is “0”. At this time, the transistor MNDk is grounded, and the transistor MNDk is set to the off state.

  Among the nMOS transistors MND3 to MND0, a current based on the output voltage of the error amplifier circuit 3-i flows through the nMOS transistor MNDk that is turned on by the switch circuit SWDk, and the combined current is output to the LED1-i. . A reference voltage Vref is generated in the reference resistor Rref by the constant current source CIS or the variable current source VIS output from the reference current generating circuit 12. The error amplifier circuit 3-i amplifies an error voltage between the reference voltage Vref and the output voltage based on the combined current of the nMOS transistor MNDk. The amplified error voltage is input to the gate of the nMOS transistor MND.

If the gain of the error amplifying circuit 3-i is sufficiently high, the reference voltage Vref generated in the reference resistor Rref and the output voltage of the transistor MNDk are substantially equal, so that the current detection resistor RMONk has its resistance value and reference voltage. A constant current determined by Vref flows. Therefore, the drive current Iout flowing through the LED 1-i is expressed as the following equation.
IOUT = n × IREF (R _n−1 , R _n−2 ,..., R ₁ , R ₀ ) × (2 ^m−1 D _m−1 +2 ^m−2 D _m−2 +... + 2D1 + D0),
here,
m is the number of weighted nMOS transistors MNDk,
Dk is k bits (drive current setting data) of the control register
n = RREF / RMON0,
RREF is the resistance value of the reference resistor Rref.
RMON0 is the resistance value of the current detection resistor RMON0,
_{IREF (R n-1, R} n-2, ‥‥, R 1, R 0) , the reference current IREF is set based on the reference current setting data.

In addition, the forward voltage of LED1-i changes with the luminescent color. For example, the forward voltage of the red LED is about 2.0V, the forward voltage of the green LED is about 3.0V, the forward voltage of the blue LED is about 3.0V, and the forward voltage of the white LED is about 3.5V. is there. For this reason, the drive voltage VDi (= VLED−VF) of the LED 1 -i varies depending on the emission color.
When the forward voltage of the LED 1-i is small and the driving voltage is large, the drain voltage of the nMOS transistors MND3 to MND0 is large, so that the gate voltage is small. Therefore, the output voltage of the error amplifier circuit 3-i becomes small. On the other hand, when the forward voltage of the LED1-i is large and the driving voltage is small, the drain voltage of the nMOS transistors MND3 to MND0 is small, so that the gate voltage is large. Therefore, the output voltage of the error amplifier circuit 3-i increases.
As described above, the output voltage of the error amplifying circuit 3-i differs depending on the emission color of the LED1-i connected to the current output type DAC2-i.

  Returning to FIG. 1, the sampling clock generation circuit 9 generates a sampling clock signal SAMPLCK. The synchronization registers 6-1 to 6-n hold drive current setting data in synchronization with the sampling clock signal SAMPLCK.

  The control circuit 19 performs overall control of the current output type driving device. For example, the control circuit 19 monitors current setting data output from the logic circuits 7-1 to 7-n, and determines whether or not driving current setting data for lighting at least one LED 1-i is output. To do. When the drive current setting data for lighting the LED is output, the control circuit 19 outputs the reference voltage generation circuit 11, the reference current generation circuit 12, the minimum voltage detection circuit 15, the reference voltage buffer 16, the power supply voltage generation circuit 18, and the power supply voltage. The power supply voltage is supplied to the analog circuit such as the control circuit 17 and the error amplifier circuit 3-i and the sampling clock generation circuit 9 to activate them. On the other hand, when the drive current setting data for lighting the LED is not output, the control circuit 19 deactivates these circuits by stopping the supply of the power supply voltage of these circuits. Thereby, power consumption of these circuits in the standby state can be reduced.

FIG. 4 is a diagram showing a configuration of reference current generating circuit 12 shown in FIG. FIG. 5 is a truth table showing the relationship between the reference current setting data and the reference current IREF.
As shown in FIG. 4, the reference current generation circuit 12 includes an operational amplifier OPAMP3, inverters INV1, INV2, PMOS transistors MP10, MP11, MP12, a capacitor C1, and p constant current sources CIS-i (in FIG. 4). And (n−p) variable current sources VIS-i (only one is shown in FIG. 4).
When the reference current generation circuit 12 is activated by the control circuit 19, each of the reference currents IREF from the p constant current sources CIS is converted into p current output DACs 2-1 to 2-p (n− Each of the reference currents IREF2 from the p) variable current sources VIS is supplied to (n−p) current output DACs 2- (p + 1) to 2-n.

The constant current source CIS-i includes PMOS transistors MP20 and MP21. The variable current source VIS-i includes PMOS transistors MP30, MP31, MP40, MP41, MP50, and MP51.

  The operational amplifier OPAMP3 controls the gate voltage of the PMOS transistor MP10 and applies the same voltage as the capacitor CBGR to the resistor REXT. At this time, the current IREFo = CBGR / REXT flows through the resistor REXT and the PMOS transistor MP10. The PMOS transistors MP11 and MP12 cut off the through current during standby.

  The PMOS transistors MP20, MP30, MP40, and MP50 constitute a current mirror with the PMOS transistor MP10 and pass a current proportional to the transistor size. The transistor sizes of the PMOS transistors MP30, MP40, and MP50 are set based on the reference current setting data [XSL3, XSL4, XSL5] that is the logical operation result of the registers [R1, R0] of the control register 14. For example, the PMOS transistors MP20, MP30, MP40, and MP50 output currents of 400 μA, 200 μA, 100 μA, and 100 μA, respectively. The PMOS transistors MP21, MP31, MP41, and MP51 control (select) the PMOS transistors MP20, MP30, MP40, and MP50, respectively.

The constant power supply current CIS-i outputs a constant reference current IREF based on the reference current setting data XSL2 input to the gate of the PMOS transistor MP21.
The variable current source VIS-i selects the PMOS transistors MP30, MP40, and MP50 based on the reference current setting data XSL3, XSL4, and XSL5 input to the gates of the PMOS transistors MP31, MP41, and MP51, and generates the variable reference current IREF. Output. As shown in FIG. 5, the variable current source VIS-i outputs three types of reference currents IREF of 400 μA, 300 μA, and 200 μA except for the OFF state (0 μA).

Returning to FIG. 1, the reference voltage generation circuit 11 generates the reference voltage Vref and outputs it to the reference voltage buffer 14 when activated by the control circuit 19.
The lowest voltage detection circuit 15 compares the voltages VD1 to VDn at the output terminals of the current output type DACs 2-1 to 2-n connected to the cathodes of the LEDs 1-1 to 1-n to detect the lowest voltage. The lowest voltage detected is the output voltage of LED1-i with the maximum forward voltage.

Reference buffer 14 is a circuit that mimics the voltage shift of the minimum voltage detection circuit 15, an equivalent voltage shift and shift amount of the detection voltage VMIN output from the minimum voltage detecting circuit 15 for the voltage of the detection source output terminal This difference is corrected by applying it to the reference voltage Vref.
The power supply voltage control circuit 17 controls the power supply voltage VLED of the power supply voltage generation circuit 18 so that the detection voltage VMIN_MSK of the minimum voltage detection circuit 15 approaches a predetermined voltage. The power supply voltage generation circuit 18 supplies the power supply voltage VLED to the anodes of the LEDs 1-1 to 1-n according to a control signal from the power supply voltage control circuit 17.

  The power supply voltage control circuit 17 compares the reference voltage Vref_BUF corrected by the reference voltage buffer 16 with the detection voltage VMIN_MSK. When the detection voltage VMIN_MSK is lower than the reference voltage Vref_BUF, the power supply voltage VLED of the power supply voltage generation circuit 18 is increased, and when the detection voltage VMIN_MSK is higher than the reference voltage Vref_BUF, the power supply voltage VLED of the power supply voltage generation circuit 18 Reduce.

  The power supply voltage generation circuit 18 includes, for example, a boosting power supply circuit that boosts the power supply voltage VDD (about 3 V) of the analog circuit to generate the power supply voltage VLED (about 4.5 to 5 V) of the LED. The power supply voltage generation circuit 18 executes the boosting operation when increasing the power supply voltage VLED, and stops the boosting operation when decreasing the power supply voltage VLED. When the boosting operation is stopped, the power supply voltage VLED naturally drops due to the driving current of LED1-i.

Next, the operation of the current output type driving apparatus of Example 1 will be described.
Serial data SDATA from the host device input to the data input circuit 10 is converted into parallel data. The turn-on / off command and drive current setting data included in the parallel data are stored in the registers [MD1, MD0] and the registers [D3, D2, D1, D0] of the control registers 8-1 to 8-n, respectively. The reference current setting data included in the parallel data is stored in the registers [R1, R0] of the control register 14.

  Next, the logical circuits 7-1 to 7-n calculate the logical product of the ON / OFF commands MD1 and MD0 of the control registers 8-1 to 8-n and the current setting data D3, D2, D1, and D0, and turn them on. When the commands MD1 and MD0 are set, the drive current setting data D3, D2, D1, and D0 are output as they are, and when the turn-off commands MD1 and MD0 are set, the current setting data for setting the current to zero. Is output. On the other hand, the logic circuit 13 performs a logical operation based on the reference current setting data R1 and R0, and outputs the reference current setting data XSL3, XSL4, and XSL5.

  When the drive current setting data D3, D2, D1, and D0 output from the logic circuits 7-1 to 7-n are current setting data for lighting at least one LED, the control circuit 18 generates each analog circuit and sampling clock. Circuit 9 is activated.

  Next, 400 μA of reference current IREF is output from the p constant current sources CIS-1 to CIS-p of the reference current generating circuit 12, and (n−p) variable current sources VIS− (p + 1) to VIS−. The reference current IREF of 400 μA, 300 μA, or 200 μA is set and output by n. As a result, the reference current IREF is input to the current output type DACs 2-1 to 2-n.

In synchronization with the sampling clock signal SAMPLCK from the sampling clock generation circuit 9, the drive current setting data of the logic circuit 7-i is transferred to the synchronization register 6-i.
Next, feedback control is performed by the current output type DAC 2-i and the error amplifying circuit 3 so that the drive current of the LED 1-i follows the drive current setting data set in the synchronous register 6-i. Is driven.

  When LED1-i is driven, the lowest voltage detection circuit 15 detects the lowest voltage from the voltages VD1 to VDn at the output terminals of the current output type DACs 2-1 to 2-n. The minimum voltage is the voltage at the output terminal of the current output type DAC 2-i connected to the LED 1-i having the maximum forward voltage. For example, when a plurality of LEDs 1-i having different forward voltages due to different emission colors are used, the voltages VD1 to VDn at the output terminals of the current output DACs 2-1 to 2-n vary in various ways.

  The lowest voltage detected by the lowest voltage detection circuit 15 is compared with the reference voltage Vref_BUF of the reference voltage buffer 16 by the power supply voltage control circuit 17. When the minimum voltage is lower than the reference voltage Vref_BUF, the power supply voltage control circuit 17 controls the power supply voltage generation circuit 18 so that the power supply voltage VLED increases. When the minimum voltage is higher than the reference voltage Vref_BUF, The power supply voltage generation circuit 17 is controlled by the power supply voltage control circuit 17 so that the power supply voltage VLED decreases.

Thus, the power supply voltage VLED is feedback-controlled so that the lowest voltage among the voltages VD1 to VDn approaches the reference voltage Vref_BUF.
For this reason, if the reference voltage Vref_BUF is set to an appropriate value so as to ensure the minimum margin that allows a desired drive current to flow in the LED having the maximum forward voltage, the light emission luminance of the LED can be maintained. The power supply voltage VLED can be set to the minimum within the range.

FIG. 6 is a diagram showing the blinking operation of the light emitting element. FIG. 6A is a diagram showing a blinking operation of the present invention, and FIG. 6B is a diagram showing a conventional blinking operation.
The current output drive circuit of the first embodiment, the drive current setting data _{[D m-1, D m} -2, ‥‥, D 1, D 0] more by changing, for example the RGB (red, green and blue) Various blinking patterns can be realized by changing the brightness of the three-color LED. For example, the brightness of the blinking of the three color RGB LEDs can be dynamically changed to bright, dark, dark, bright, dark, dark,. In addition, the brightness of the three colors RGB can be changed in several steps according to the ambient brightness. Thereby, power consumption can be saved.

In FIG. 6, the vertical axis represents output current (= brightness), and the horizontal axis represents time.
It is assumed that a mountain-shaped blinking pattern in which the brightness is changed stepwise and LED1-i blinks slowly is performed in the normal mode and the power saving mode. The brightness of the power saving mode is half that of the normal mode.
As shown in FIG. 6B, in the conventional current output type drive circuit, in the normal mode, the blinking pattern in which the drive current setting data is increased or decreased in 16 steps is repeated. In the power saving mode, in order to halve the current value, a blinking pattern in which the drive current setting data is increased or decreased in eight steps is repeated. In this case, different flashing pattern programs are used in the normal mode and the power saving mode.

On the other hand, as shown in FIG. 6A, in the current output type drive circuit of the first embodiment, the same flashing pattern (drive current setting data) program is used in the normal mode and the power saving mode. In the power saving mode, when the current value is half that of the normal mode, the reference current setting data is changed. For example, an instruction (change of reference current setting data) for rewriting [R ₁ , R ₀ ] = [H, H] of the control register 14 shown in FIG. 5 to [L, H] is executed, and the variable current source VIS For example, the reference current IREF is changed from 400 μA to 200 μA. In the power saving mode, half the brightness of the normal mode is increased or decreased in 16 steps. As described above, by changing the reference current setting data, it is possible to realize a plurality of types of blinking patterns with different brightnesses by a program of one blinking pattern (drive current setting data).

As described above, according to the first embodiment, a variable reference is generated by the variable current source VIS-i of the reference current generation circuit 12 based on the reference current setting data stored in the control register 14 and logically operated by the logic circuit 13. The current IREF is output, and the output current of the current output type DAC 2-i is controlled by the error amplification circuit 3-i based on the reference voltage Vref generated in the reference resistance circuit Rref of the current output type DAC 2-i to thereby control the LED 1-i. To drive.
Accordingly, the drive current of the LED 1-i can be controlled by changing the reference current setting data. Therefore, by combining the reference current setting data and the drive current setting data, the drive current setting data program alone can be used for the LED 1-i. Compared to the conventional case of controlling the drive current, it is possible to execute various types of flashing pattern programs with fewer programs.

FIG. 7 is a diagram illustrating a configuration of a current output type driving circuit according to the second embodiment.
In the current output type driving circuit of the first embodiment, error amplification circuits 3-1 to 3-n are provided in each of the n current output type DACs 2-1 to 2-n, and p error amplification circuits 3-1 to 3-1 are provided. The constant current sources CIS-1 to CIS-p are respectively connected to 3-p, and the variable current sources VIS- (p + 1) to VIS are respectively connected to the (np) error amplifier circuits 3- (p + 1) to 3-n. -N is provided. These circuits are constituted by a large number of circuit elements and consume a considerable amount of power.

  In contrast, the current output type drive circuit of the second embodiment includes an error amplifier circuit 31 and a constant current source CIS commonly connected to the p current output type DACs 2-1 to 2-p, and (np). An error amplifier circuit 32 and a variable current source VIS commonly connected to the current output type DACs 2- (p + 1) to 2-n are provided to reduce the power consumption of the current output type drive circuit. The p current output type DACs 2-1 to 2-p and the (np) current output type DACs 2- (p + 1) to 2-n are connected to and controlled by the error amplification circuits 31 and 32, respectively, in a time division manner. The The constant current source CIS and the variable current source VIS are provided in the reference current generation circuit 12.

As shown in FIG. 7, the current output type drive circuit of the second embodiment includes n current output type DACs (Digital to Analog Converters) 22-1 to 22-n, error amplifier circuits 31 and 32, and n pieces. Level shifters 42-1 to 42-n, n flag registers 5-1 to 5-n, n synchronization registers 6-1 to 6-n, and n logic circuits 7-1 to 7- n, n control registers 8-1 to 8-n, sampling clock generation circuit 9, data input circuit 10, reference voltage generation circuit 11, reference current generation circuit 12, logic circuit 13, and control A register 14, a minimum voltage detection circuit 15, a reference voltage buffer 16, a power supply voltage control circuit 17, a power supply voltage generation circuit 18, a control circuit 19, a capacitor CBGR, and a resistor REXT are provided.
In addition, the same code | symbol is attached | subjected to the component same as each part of the current output type drive circuit of Example 1 shown by FIG. 1, and the description is abbreviate | omitted.

In order to perform time-sharing control of the plurality of current output type DACs 22-1 to 22-n using error amplifier circuits 31 and 32 connected in common, n flag registers 5-1 to 5-n are provided. .
Based on the sampling clock signal SAMPLCK from the sampling clock generation circuit 9, the flag signals are circulated by p flag registers 5-1 to 5-p and (np) flag registers 5- (p + 1) to 5-n. Shifted. When the flag is set in the flag register 5-i, the drive current setting data of the logic circuit 7-i is transferred to the synchronization register 6-i. At the same time, the control signals of the switch circuits SWIP, SWIN, SWO (FIGS. 8 and 9) for circulating the connection destination of the error amplifier circuit are generated.
Similarly to the first embodiment, the level shifter 42-i shifts the signal level of the drive current setting data held in the synchronization register 6-i and generates control signals for the switch circuits SWD3 to SWD0 of the current output circuit 2-i. In addition, the signal level of the flag register 5-i is shifted to generate control signals for the switch circuits SWIP, SWIN, SWO (FIGS. 8 and 9) of the current output circuit 2-i.

FIG. 8 is a diagram showing the configuration of the current output DAC 22-i and the error amplifier circuits 31 and 32 shown in FIG. FIG. 9 is a diagram showing the configuration of the switch circuit shown in FIG.
8 and 9, the same components as those of the current output DAC 2-i and the error amplifying circuit 3-i of the first embodiment shown in FIGS. Is omitted.
As shown in FIGS. 7 and 8, the current output type DAC 22-i is obtained by adding switch circuits SWIP, SWIN, and SWO to the current output type DAC 2-i of the first embodiment shown in FIGS. .

The switch circuit SWIP performs a switch operation between the positive side input terminal INP of the error amplifier circuit 31 or 32 and the reference resistor Rref. The switch circuit SWIN performs a switch operation between the negative side input terminal INN of the error amplifier circuit 3 and the switch circuits SWD3 to SWD0. The switch circuit SWO performs a switch operation between the output terminal AMPO of the error amplifier circuit 3 and the gates of the nMOS transistors MND3 to MND0.
The switch circuits SWIP, SWIN, and SWO are flag signals that are cyclically shifted by p flag registers 5-1 to 5-p and (n−p) flag registers 5- (p + 1) to 5-n, respectively. When the flag is set in the flag register 5-i, the switch is turned on. When the flag is released, the switch is turned off.

  The error amplifying circuits 31 and 32 are composed of operational amplifiers as in the first embodiment, and input the reference voltage from the switch circuit SWIP of the current output type DAC 22-i through the positive input terminal INN, and output the current through the negative input terminal INP. The output voltage from the switch circuit SWIN of the circuit 22-i is input, and these error voltages are amplified and output through the output terminal AMPO.

  The current output circuit 22-i is selectively connected to the error amplifier circuit 3-i by the switch circuits SWIP, SWIN, and SWO. When the current output circuit 2-i is connected to the error amplifying circuit 31 or 32 by the switch circuits SWIP, SWIN, and SWO, it forms a feedback loop with the error amplifying circuit 31 or 32, and the level shifter 4 Perform feedback control to follow the drive current of the drive current setting data of -i. On the other hand, when disconnected from the error amplifier circuit 31 or 32, the capacitor C holds the drive current before the disconnection. The capacitor C has one end connected to the drains of the nMOS transistors MND3 to MND0 and the other end grounded (VSS). When the switch circuit SWIN is disconnected, the capacitor C holds the output voltage of the nMOS transistors MND3 to MND0. Thereby, the current output circuit 2-i is controlled in a time division manner.

  Note that the reference current generating circuit 12 of the second embodiment includes p constant current sources CIS-i and (np) variable current sources VIS-i shown in FIG. Since the variable current source VIS is used, detailed description thereof is omitted.

Next, the operation of the time division control of the current output circuit 2-i according to the second embodiment will be described.
When the switch circuits SWIP, SWIN, SWO of the current output circuit 2-i are turned on based on the flag signal, the reference current IREF from the reference current generation circuit 12 flows to the reference resistor Rref, and the reference voltage Vref is generated. . Next, the error between the reference voltage IREF generated at the reference resistor Rref and the output voltage of the current output circuit 2-i is amplified by the error amplifier circuit 31 or 32. Next, the amplified error voltage is input to the gate of the nMOS transistor MNDk that is turned on by the switch circuit SWDk. Thus, feedback control is performed by the current output type DAC 2-i and the error amplification circuit 3 so that the drive current of the LED 1-i follows the drive current setting data of the synchronization register 6-i, and the LED 1-i is driven. The

  Next, when the switch circuits SWIP, SWIN, SWO are set to OFF, the output voltage of the current output circuit 2-i is held by the capacitance of the capacitor C and the gate of the nMOS transistor MNDk. As a result, the output current of the nMOS transistor MNDk continues to flow.

As described above, according to the second embodiment, the error amplifier circuit 31 and the constant current source CIS commonly connected to the p current output types DACs 2-1 to 2-p, and the (np) current output types. An error amplifier circuit 32 and a variable current source VIS commonly connected to DACs 2- (p + 1) to 2-n are provided, and p current output type DACs 2-1 to 2-p and (np) currents are provided. The output type DACs 2- (p + 1) to 2-n are connected to the error amplifier circuits 31 and 32 in a time division manner and controlled.
Therefore, power consumption of the current output type driving circuit can be reduced.

FIG. 10 is a diagram illustrating the configuration of the mobile phone according to the third embodiment.
As shown in FIG. 10, the mobile phone of the third embodiment is a mobile phone to which the current output type driving circuit of the first or second embodiment is applied, and includes a CPU 101, a color LCD (Liquid Crystal Display) 102, a monochrome LCD 103, an input unit. 104, an incoming call notification unit 105, a sound source IC 106, and an LED drive circuit 107. In this example, the LED drive circuit 107 corresponds to the current output type drive circuit of the second embodiment for convenience of explanation.

  The mobile phone according to the third embodiment is a so-called foldable mobile phone, and includes a base unit (not shown) and a rotating unit (not shown) that is opened and closed by a hinge mechanism provided at one end of the base unit. An input unit 104 is provided on the inner surface side of the base unit. Further, a color LCD 102 is provided on the inner surface side of the rotating part, and a monochrome LCD 103 is provided on the outer surface side of the rotating part.

The CPU 101 turns on / off the power of the mobile phone based on the input information input from the input unit 104 and controls each unit.
The color LCD 102 constitutes a first screen of the cellular phone, and displays a selection screen for various functions, a destination telephone number for outgoing and incoming calls, an e-mail message, and the like. The color LCD 102 is provided with three W (white) LEDs 1-1 to 1-3 that are driven by an LED driving circuit 107 as an illumination backlight. The reference current IREF from the constant current source CIS of the reference current generation circuit 12 shown in FIG. 7 is supplied to the current output type DACs 2-1 to 2-3 of the WLEDs 1-1 to 1-3.

  The monochrome LCD 103 constitutes the second screen of the cellular phone, and displays the date and time, the remaining battery level, the communication level, and the like. The monochrome LCD 103 is provided with R (red) LEDs 1-4, G (green) LEDs 1-5, and B (blue) LEDs 1-6 for illumination. The reference current IREF from the variable current source VIS of the reference current generating circuit 12 is supplied to the current output DACs 2-4 to 2-6 of the RLED1-4, the GLED1-5, and the BLED1-6.

  The input unit 104 has operation keys (not shown) such as a power key, a call key, and a numeric keypad. The input unit 104 is provided with RLED1-7, GLED1-8, and BLED1-9 for illumination of these operation keys. The reference current IREF from the variable current source VIS is supplied to the current output type DACs 2-7 to 2-9 of the RLED 1-7, the GLED 1-8, and the BLED 1-9.

  The incoming call notification unit 105 includes an RLED 1-10, a GLED 1-11, and a BLED 1-12. The reference current IREF from the variable current source VIS is supplied to the current output DACs 2-10 to 2-12 of the RLED 1-10, the GLED 1-11, and the BLED 1-12. The sound source IC 106 outputs a synchronization signal SYNC to the LED drive circuit 107.

Next, the operation of the mobile phone according to the third embodiment will be described.
When the rotating part of the mobile phone is opened and the power key of the input part 104 is input, the power supply for each part is supplied by a power source (not shown) such as a lithium ion battery. A data program is supplied to the LED drive circuit 107 by the CPU 101. The WLEDs 1-1 to 1-3 are turned on, and the backlight of the color LCD 102 is illuminated.

  When the rotating unit is closed in this state, the driving of the WLEDs 1-1 to 1-3 is stopped, and the program of the driving current setting data for the BLED1-6 is supplied to the LED driving circuit 107 by the CPU 101. The BLED 1-6 is turned on and the monochrome LCD 103 is illuminated in blue.

  When an incoming call is received, the driving of the BLED 1-6 is stopped, and a program including reference current setting data and driving current setting data of the GLED 1-5, RLED 1-10, GLED 1-11 and BLED 1-12 is supplied to the LED driving circuit 107 by the CPU 101. The The black and white LCD 103 blinks green by the GLED 1-5. RLED 1-10, GLED 1-11, and BLED 1-12 blink with dynamic brightness changed according to the incoming melody from sound source IC 106.

In each of the above operations, in the LED drive circuit 107, the output voltage of the LED 1-i having the maximum forward voltage Vf by the power supply voltage control circuit 17 based on the minimum voltage detected by the minimum voltage detection circuit 15 is the reference voltage. The power supply voltage of the power supply voltage generation circuit 18 is controlled so as to be Vref.
As a result, even when a plurality of LEDs having different forward voltages are simultaneously driven, the lowest voltage that always satisfies the driving condition is output. Therefore, the luminous efficiency of the plurality of LEDs can be increased, and these power losses can be suppressed.

  As described above, according to the third embodiment, the light emission efficiency of the plurality of LEDs is increased, the power loss is suppressed, and the brightness of the plurality of LEDs is dynamically adjusted by combining the reference current setting data and the drive current setting data. It can be changed to blinking.

  In the first to third embodiments, examples of driving a plurality of LEDs of a mobile phone have been described. However, the first and second embodiments can be applied to other electronic devices having a plurality of LEDs. For example, it is suitable for a pachinko gaming machine having a large number of LEDs.

1 is a diagram illustrating a configuration of a current output type drive circuit according to Embodiment 1. FIG. It is a figure which shows the structure of current output type DAC2-i and error amplifier circuit 3-i shown by FIG. It is a figure which shows the structure of the switch circuit shown by FIG. FIG. 2 is a diagram showing a configuration of a reference current generation circuit shown in FIG. 1. It is a truth table showing the relation between reference current setting data and reference current IREF. It is a figure which shows blinking operation | movement of a light emitting element. FIG. 6 is a diagram illustrating a configuration of a current output type driving circuit according to a second embodiment. It is a figure which shows the structure of current output type DAC2-i and error amplifier circuit 3-i which are shown by FIG. It is a figure which shows the structure of the switch circuit shown by FIG. 6 is a diagram illustrating a configuration of a mobile phone according to Embodiment 3. FIG.

Explanation of symbols

  1-1 to 1-n LED, 2-1 to 2-n, current output DAC, 3-1 to 3-n, error amplification circuit, 4-1 to 4-n, level shifter, 5 -1 to 5-n: Flag register, 6-1 to 6-n: Synchronization register, 7-1 to 7-n: Logic circuit, 8-1 to 8-n: Control register, 9: Sampling clock generation circuit, 10 ... Data input circuit, 11 ... Reference voltage generation circuit 11 ... Reference current generation circuit, 13 ... Logic circuit, 14 ... Control register, 15 ... Minimum voltage detection circuit, 16 ... Reference voltage buffer, 17... Power supply voltage control circuit, 18... Power supply voltage generation circuit, 19... Control circuit, CIS-1 to CIS-p .. constant current source, VIS- (p + 1) to VIS-n. Variable current source.

Claims (11)

A first register in which first bit information is input and held;
A plurality of second registers in which second bit information is input and held;
For a plurality of loads connected to a common power supply voltage, provided respectively to the set of load and the second register corresponds, with respect to the corresponding said load, the said corresponding second register holds 2 a plurality of current output circuit to output the drive current corresponding to the bit information,
A reference current generating circuit for generating a reference current that can be changed according to the first bit information ;
With
Each of the plurality of current output circuits is
One end of which is grounded, the other end, a reference resistor that occur a reference voltage based on the reference current input from the reference current generation circuit,
Each bit includes a plurality of bit resistors having different values, and the presence or absence of current generation when the reference voltage is applied to each bit resistor is controlled according to the second bit information, and the sum of the generated currents is supported A current generating circuit that outputs the drive current of the load;
A current output type driving circuit. Each of the plurality of current output circuits and a minimum voltage detection circuit for detecting a minimum output voltage from output voltages appearing at a connection node with the corresponding load ,
A power supply voltage control circuit for controlling the power supply voltage based on the lowest output voltage detected by the lowest voltage output circuit;
The current output type drive circuit according to claim 1, comprising: The reference current generation circuit includes:
A constant current source for generating a constant reference current irrespective of the second bit information;
A plurality of variable current sources for generating a reference current according to the second bit information;
The current output type drive circuit according to claim 1 or 2, comprising: Each of the plurality of current output circuits includes a plurality of transistor circuits that switch-control currents flowing through the plurality of bit resistors having a size corresponding to the weight of each bit of the second bit information .
For the plurality of transistor circuits, a transistor circuit that outputs the current is selected from the plurality of transistor circuits based on the second bit information , and a current output according to the selected transistor circuit is selected . The current output type drive circuit according to any one of claims 1 to 3, wherein a selection circuit that generates the drive current by a sum is connected . Each of the plurality of current output circuits is
A plurality of current control transistors each provided in a path of current flowing through each of the bit resistors;
The reference voltage generated at the other end of the reference resistor is compared with the applied voltage value of each bit resistor, and the current connected to each bit resistor so that the applied voltage value is constant at the reference voltage value. The current output type drive circuit according to claim 4, further comprising an error correction amplifier that controls a control node potential of the control transistor . The error correction amplifier is provided in common for a plurality of current output circuits,
The selection circuit comprises:
A main selection circuit for selecting one or at the time of splitting the current output circuit connected to the error correction amplifier Common,
In the current output circuit selected by the main selection circuit, a sub-selection circuit that controls connection and disconnection of the plurality of bit resistors and the input of the error correction amplifier according to the second bit information ;
The current output type driving circuit according to claim 5, comprising: The current output type drive circuit according to any one of claims 1 to 6, wherein the plurality of loads are a plurality of light emitting elements that emit light in a plurality of colors . A plurality of light emitting elements that emit light in a plurality of colors connected to a power supply voltage with a common power source;
A current output type driving circuit that outputs and controls each driving current of the plurality of light emitting elements ;
With
The current output type driving circuit includes:
A first register in which first bit information is input and held;
A plurality of second registers in which second bit information is input and held;
Wherein the plurality of light emitting elements, respectively emitting element and a second set of registers are provided corresponding, for the corresponding light emitting element, the second bit information corresponding second register holds a plurality of current output circuit to output the drive current corresponding,
A reference current generating circuit for generating a reference current that can be changed according to the first bit information ;
With
Each of the plurality of current output circuits is
One end of which is grounded, the other end, a reference resistor that occur a reference voltage based on the reference current input from the reference current generation circuit,
Each bit includes a plurality of bit resistors having different values, and the presence or absence of current generation when the reference voltage is applied to each bit resistor is controlled according to the second bit information, and the sum of the generated currents is supported A current generation circuit that outputs the driving current of the light emitting element;
Electronic equipment having Each of the plurality of current output circuits and a minimum voltage detection circuit for detecting a minimum output voltage from output voltages appearing at a connection node with the corresponding light emitting element;
A power supply voltage control circuit for controlling the power supply voltage based on the lowest output voltage detected by the lowest voltage output circuit;
The electronic device according to claim 1, comprising: The electronic device is a mobile phone
The electronic device according to claim 9 . The electronic device is a pachinko gaming machine
The electronic device according to claim 9 .

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