JP4929914B2 - Preamble detection apparatus for radio base station apparatus - Google Patents

Description

  The present invention relates to a preamble detection apparatus for a radio base station apparatus in radio communication, and more particularly to a preamble detection apparatus for detecting a preamble included in a random access channel in CDMA communication.

  In W-CDMA, which is a third generation mobile phone communication system, a mobile terminal (UE) transmits an uplink random access channel when connected to a radio base station apparatus. The corresponding physical channel is PRACH (Physical Random Access Channel). The random access channel includes one or a plurality of preambles and a message, and the preamble (4096 chip length) is a signal transmitted to perform spreading code synchronization code detection before transmitting the message. In order to detect the spreading code and reception timing of a message following the preamble, it is necessary to detect the preamble.

  FIG. 1 is a diagram illustrating a conventional configuration for detecting a preamble in a radio base station apparatus. When the radio base station apparatus has a plurality of antennas (6 antennas in FIG. 1), the antenna selection unit 10 selects one antenna by time division, and the preamble of the random access channel received by the selected antenna is It is stored in one of the two memories 20A and 20B. The memory selection unit 30 reads the preamble stored from either the memory 20 </ b> A or 20 </ b> B in a time division manner and sends it to the preamble detection unit 40. As will be described later, the memories 20A and 20B have 1 write port and 16 simultaneous read ports (1W-16R). The capacities of the memories 20A and 20B are 4700 × 32 bits. 32 bits is the depth of the memory, and is not limited to 32 bits, but may be 64 bits, for example.

FIG. 2 is a diagram for explaining the processing of the preamble detection unit 40. In FIG. 2, the preamble detection unit 40 needs to search a wide range of 605 chips according to the current required specification due to the distance relationship with the mobile terminal (UE), so that it shifts by 1 chip 604 times (605-1). ) The length of the preamble (4096 chips) is despread and compared with a known pattern to detect the preamble pattern. Pattern of the preamble is defined in 3GPP (3 ^rd Generation Partnership Project) is a standardization project of a third generation mobile communication system.

  For this reason, when a memory with a single read port is used as the memory 20A or 20B, 4096 × 605 = 2478080 readings are required, and the number of clocks required for this is 2478080 × 1 / (5120 / 3840000) = 1.85856 GHz. In an FPGA (Field Programmable Gate Array) currently provided, an operation of about 100 MHz is desirable. Therefore, as shown in FIG. 1, by using 16 ports for simultaneous reading ports of the memories 20A and 20B, a clock of about 122 MHz is used. It can be operated.

  A mobile terminal (UE) transmits a random access channel from a plurality of predetermined time offsets called access slots. Fifteen access slots are provided in two frames, and are arranged at intervals of 5120 chips.

FIG. 3 is a diagram illustrating the relationship between the access slot to be received and the preamble detection process. As shown in FIG. 3, since the head position of the access slot changes for each antenna, there is a period in which the access slots overlap. In order to absorb this, two memories 20A and 20B are provided, and these are alternately switched. Used. For example, when the antenna ANT # 2 access slots ACS # 2 is stored in the memory 20 B, an access slot ACS # 3 antenna ANT # 3 having a section overlapping with it is stored in the memory 20 A, the antenna ANT # 2 after preamble processing for the access slot ACS # 2 is completed, read from the memory 20 A and is preamble detection process. Similarly, if the access slot ACS # 4 antennas ANT # 4 is stored in the memory 20 B, access slot ACS # 5 of the antenna ANT # 1 having a section overlapping with it it is stored in the memory 20 A, the antenna ANT # 4 after preamble detection processing for the access slot ACS # 4 is completed, read from the memory 20 a and is preamble detection process.

Patent Document 1 below discloses a technique for reducing power consumption by providing means for controlling the phase difference between a read clock and a write clock having different speeds to efficiently use a low-speed memory.
JP-A-8-70289

  In recent years, with regard to the preamble detection processing, further performance improvement has been demanded in order to meet demands such as expansion of the detection range and increase in the number of antennas.

  FIG. 4 is a diagram illustrating an example in which the conventional preamble detection process is configured in two parallel configurations. When it is desired to increase the number of preamble detection processes, for example, since the preamble detection process is performed a plurality of times at the same time, a simple parallel configuration as shown in FIG. 4 is assumed.

  However, as shown in FIG. 3, since access slots may overlap, it is necessary to provide two memories 20A and 20B. However, since the memories 20A and 20B have 16 simultaneous read ports, one read port memory The mounting area is remarkably large, and further expansion is difficult in terms of heat and mounting area, and the number of preamble detection processes cannot be increased with a simple parallel configuration.

  Specifically, the 16-read port memory requires a mounting area and current consumption that is 10 times or more that of the 1-read port memory, and also requires a plurality of preamble detectors 40. In a simple parallel configuration, There arise problems that the mounting area exceeds the size of the mounted device and the current consumption exceeds the heat capacity.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a preamble detection apparatus that can increase the number of preamble detection processes without causing problems of mounting area and heat, and a radio base station apparatus that accommodates the preamble detection apparatus.

The first configuration of the preamble detector of the present invention for achieving the above object, in a preamble detector for detecting a preamble included in the random access channel transmitted from the mobile terminal, the random access channel of the plurality of antennas A selection unit that sequentially selects antennas to be received for each time interval of the access slot, and causes the selected antenna to receive the random access channel over the length period of the random access channel from the start timing of the access slot of the selected antenna, and the selection Random access channels received by the antenna selected by the unit are written, a first memory having a capacity of up to two random access channels and one read port, and a maximum of 2 stored in the first memory Two random Is written one of the random access channel selected from Seth channel, a second memory having a single random access channels of capacity and a plurality of read ports, a random access channel that is written in the second memory the A preamble detection unit that reads from a plurality of read ports and detects a preamble included in the random access channel is provided.

According to a second configuration of the preamble detection apparatus of the present invention, in the first configuration, the first memory has a capacity for two random access channels, each having a capacity for one random access channel. A first random access channel that is divided into a first area and a second area and received by the first antenna among the plurality of antennas selected by the selection unit is written to the first area, A memory control unit that writes a second random access channel received by a second antenna among the plurality of antennas selected subsequent to the first antenna to the second area is provided. .

According to a third configuration of the preamble detection apparatus of the present invention, in the first configuration, the random access channel received by the antenna selected by the selection unit is divided into a plurality of block data, and sequentially in block data units. When writing to the first memory and block data corresponding to one random access channel is written, control is performed so that the random access channel is read from the first memory and transferred to the second memory. A memory control unit is provided, and the capacity of the first memory is smaller than the capacity of two random access channels.

A fourth configuration of the preamble detector of the present invention, in the third configuration, the memory control unit, before Symbol writes the block data in the free area of the first memory, the block data and it writes It is characterized by storing the corresponding areas.

According to a fifth configuration of the preamble detection apparatus of the present invention, in the third configuration, the memory control unit immediately before block data corresponding to one random access channel is written to the first memory. If the preamble detection process of the preamble detection unit for the random access channel is not completed, transfer to the second memory is waited until the process is completed.

  According to a sixth configuration of the preamble detection apparatus of the present invention, in the first configuration, the number of random access channels selected by the selection unit per access slot is n (n is an integer of 2 or more) times, When the number of simultaneous detections in the preamble detector is increased by n times, the capacity of the first memory is approximately n times, and the number of read ports of the second memory is approximately n times.

  According to a seventh configuration of the preamble detection apparatus of the present invention, in the first configuration, the selection unit, the second memory, and the preamble detection unit are integrally configured as a predetermined device, and the first memory Is externally attached to the device.

  A radio base station apparatus according to the present invention includes the preamble detection apparatus having any one of the first to seventh configurations.

  According to the present invention, the memory (second memory) having a plurality of read ports is integrated into one, and the access slot overlap is absorbed by the memory (first memory) having one read port. As a result, the current consumption (heat generation) of the preamble detection device can be reduced, the mounting area can be reduced, and the cost can be reduced, and the performance of the preamble detection device can be improved (the number of detected preambles).

  Embodiments of the present invention will be described below with reference to the drawings. However, such an embodiment does not limit the technical scope of the present invention.

  In the embodiment of the present invention, the memory having a plurality of read ports having a large mounting area and a large amount of heat generation is reduced to one, and instead, even when there is one read port and access slots overlap. A memory having a capacity capable of storing a required number of random access channels is provided.

  FIG. 5 is a diagram illustrating a first configuration of preamble detection processing of the radio base station apparatus according to the embodiment of the present invention. The first configuration has only one 16 read port memory 20 having a memory capacity of 4700 × 32 bits as compared with the configuration of FIG. 1, and further has a memory capacity of 4700 × 32 bits just before the 16 read port memory 20. One read port memory 50 having a double capacity of 4700 × 2 × 32 bits is provided. Since one read port memory 50 has a capacity for two access slots, as shown in FIG. 3, two random access channels can be stored simultaneously even when the access slots overlap. The one read port memory 50 is divided into two planes, and the memory control unit 31 selects a random access channel stored in one of the planes by plane switching, and performs read control of the selected random access channel. .

  By providing the 1-read port memory 50 having a capacity twice that of the 16-read port memory 20, even if the 16-read port memory 20 is reduced to one, the overlap of access slots can be absorbed.

  In the first configuration, the total memory capacity is 1.5 times that of the conventional configuration shown in FIG. 1, but the size and current consumption of the 16 read port memory 20 are 10 times that of the 1 read port memory 50. Since the number of 16-read port memories 20 is reduced to one, the configuration of the preamble detection process can be greatly reduced and the current consumption can be reduced.

  FIG. 6 is a diagram illustrating a second configuration of the preamble detection process of the radio base station apparatus according to the embodiment of the present invention. In the second configuration, the capacity of the 1 read port memory 50 is smaller than the capacity 4700 × 2 × 32 bits which is twice the memory capacity 4700 × 32 bits of the 16 read port memory 20 as compared with the first configuration ( For example, it is characterized by 6000 × 32 bits).

  As shown in FIG. 3, since the access slots overlap only in part, the random access channels stored in the one read port memory 50 are sequentially read, so that the capacity of the one read port memory 50 is reduced to the 16 read port memory. The capacity can be smaller than the capacity 4700 × 2 × 32 bits which is twice the 20 memory capacity 4700 × 32 bits.

  However, in this case, the one read port memory 50 is not simply divided into two planes as in the first configuration, but optimization control of the memory area is required in order to effectively use a small memory capacity. Memory area optimization control by the memory optimization controller 32 will be described later.

  In the second configuration, as in the first configuration, the total memory capacity is about 1.5 times that of the conventional configuration shown in FIG. Since the current is more than 10 times that of the 1-read port memory 50, reducing the 16-read port memory 20 to one results in a significantly reduced preamble detection processing configuration and reduced current consumption. .

  FIG. 7 is a diagram illustrating a third configuration of the preamble detection process of the radio base station apparatus according to the embodiment of the present invention. The third configuration is a configuration example when the second configuration is processed in parallel. When the second configuration is a two parallel processing configuration, as shown in the figure, the capacity of one read port memory 50 is double that of the second configuration (for example, 12000 × 32 bits), and a random access channel for four antennas. Can be stored. Further, a 32 read port memory 21 having a read port (32 ports) twice as many as the 16 read port memory 20 is provided, and the preamble detection unit 40 performs two preamble detection processes simultaneously in parallel by time division multiplexing processing. To process. In the preamble detection unit 40, in order to double the number of preamble detection processes, the clock is doubled or the processing circuit is doubled.

  Therefore, when it is desired to increase the number of preamble detection processes by parallel processing, the capacity of one read port is increased and only the 16 read port memory 20 is replaced with 32 read port memory 21 (in the case of three parallel processing, 48 read ports are used). The number of preamble detection processes can be increased by an architecture substantially similar to that of the memory) and the second configuration. As a result, the degree of freedom in design increases and the development cost for increasing the number of preamble detection processes can be reduced.

  Further, even if the capacity of the 1-port read memory 50 is doubled, the size does not change and is sufficiently smaller than the 16-port read memory 20. Further, the mounting area of the 32-port read memory 21 is larger than that of the 16-port read memory 20, but the mounting area can be reduced to half or less in the 2-parallel processing configuration as compared with the configuration in FIG.

  FIG. 8 is a diagram illustrating a fourth configuration of the preamble detection process of the radio base station apparatus according to the embodiment of the present invention. The fourth configuration is a configuration in which the one read port memory 50 is externally attached in the third configuration, and the one read port memory 50 is connected via the memory interface 60 on the mounting device. The 1-read port memory 50 is suitable for external attachment because the number of connection ports is small. Since the external memory interface 60 is smaller than the one read port memory 50, the mounting device can be reduced in size, and a cheaper mounting device can be selected.

  Of course, in the first configuration and the second configuration, the one read port memory 50 can be externally attached.

  FIG. 9 is a diagram for explaining memory optimization control using the third configuration shown in FIG. 6 as an example. The components 321 to 328 shown in FIG. 9 are processes of the memory optimization control unit 32. In the memory optimization control, the single read port memory 50 is not simply divided into two planes, but the random access channel data is divided into fine block data and stored in the memory area in units of block data. Even when the access slots overlap, the memory area is efficiently used by controlling the address so that new block data is sequentially stored in the memory area where the block data is read from the 1-read port memory 50. This makes it possible to reduce the actual memory capacity and contribute to cost reduction.

  The 512-word head detection unit 321 of the memory optimization control unit 32 divides the random access channel transmitted from the antenna selection unit 10 by time division multiplexing into 512-word units, and detects the head position. The area allocation request unit 322 requests the area management unit 323 to allocate a memory area for storing 512 units of block data detected at the head in accordance with the timing of the head detection.

  The area management unit 323 manages the memory area of the one read port memory 50, and notifies the use area storage unit 324 of the area number of the available free memory area in response to the area allocation request. The memory area is divided in advance into 512-word block data, and each is given an area number. When the area management unit 323 notifies the area number storage unit 324 of the area number of the free memory area, the area management unit 323 sets a use flag for the area number. As a result, the memory area having the area number is recognized as being in use. As will be described later, when a read end notification is received from the read control unit 327, the use flag of the area number corresponding to the read end notification is cleared. As a result, the memory area having the area number is recognized as an empty memory area.

  The area number storage unit 324 stores the area number notified from the area management unit 323 and notifies the read control unit 327 of this. In the case of 2-parallel processing, random access channels for each process are alternately input from a plurality of access slots in a time-sharing manner, so the read control unit 327 manages the area number for each process.

  When the address control unit 325 obtains the area number from the area number storage unit 324, the address control unit 325 determines an address corresponding to the area number and stores the corresponding 512-word block data.

  Since one random access channel is composed of 4700 words, the storage end detection control unit 326 counts 4700 words for each process, and sends a storage end notification to the read control unit 327 every time 4700 words are counted.

  When the read control unit 327 sequentially acquires the area number for each process from the area number storage unit 324 and receives a storage end notification from the storage end detection unit control unit 326, storage of one random access channel is stored. Recognizing the end, the random access channel is transferred from the 1 read port memory 50 to the 32 read port memory 20. At this time, when the BUSY signal (during the detection process) is received from the preamble detector 40, the read controller 327 suspends the transfer of the random access channel and temporarily stores the transfer control signal in the read keeper 328. At the same time as the BUSY signal stops (end of the detection process), the transfer control signal is read from the read hold unit 328 and sent to the memories 50 and 20. When the read control unit 327 reads block data for one random access channel from the one read port memory 20, the read control unit 327 transmits a read end notification to the area management unit 323 together with the read area number.

  In this way, data of one random access channel is divided into a plurality of block data, and sequentially stored in the memory area of one read port memory 20, so that the block data for one random access channel is stored and read sequentially. With this control, the memory area of one read port memory 20 can be used efficiently, and one preamble detection process can be handled with a memory having a capacity smaller than the memory capacity of two random access channels. It becomes possible.

  FIG. 10 is a diagram illustrating an example of a usage state of a memory area. FIG. 10 illustrates the case of three parallel processing, and receives access slots from each antenna (six) at the timing shown in the figure. Since each access slot has a random access channel of 4700 (4096 + 604) chips (see FIG. 2), when divided in units of 512 words, one random access channel is divided into 10 memory areas and stored.

  The use situation of the memory area when the random access channel is sequentially received from the initial state where the memory area of the 1-read port memory 50 is not used at all will be described. When block data in units of 512 words is stored in one memory area, the memory usage is incremented by one.

  At timing a, the first block data (512 words) of the random access channel of antenna # 1 in the access slot of #n is stored in the memory 50. The memory usage is 1. At the next timing b, the first block data of the random access channel of antenna # 2 in the access slot of #n is stored in the memory 50. The memory usage is incremented by 1 and becomes 2.

  At timing c, the second block data of the random access channel of antenna # 1 is stored in the memory 50, and the first block data of the random access channel of antenna # 3 is stored in the memory. Accordingly, 2 is added to the memory usage amount to be 4.

  Thus, the random access channels of antennas # 1 to # 3 are sequentially stored, and at timing d, the last (tenth) block data of antenna # 1 (the last block data is less than 512 words) and the antenna The ninth block data of # 3 is stored, and the first block data of the random access channel of antenna # 5 in the access slot of # n + 1 is stored in the memory 50. Accordingly, the memory usage amount is added by 3 to 27 to 30.

  At the next timing e, all the random access channels of the antenna # 1 are read out, and the preamble detection process for the random access channel of the antenna # 1 is started, so the memory usage is subtracted by 10. On the other hand, at this timing e, the three block data of antennas # 2, # 4, and # 6 are stored, so the memory usage is subtracted 7 (3-10) to 23.

  In this way, when the usage amount of the one read port memory 50 increases or decreases, the maximum usage amount of the memory is 33 at the timing f. That is, the minimum required memory capacity is 512 × 33 = 16896 words, and 4700 × 3, which is necessary when preparing two memory areas for storing 4700 words each in 3 parallel processing as shown in FIG. Compared with x2 = 28200 words, the overlap of access slots can be absorbed with about 60% capacity.

  At timing g, all random access channels of antenna # 2 are read, and preamble detection processing for the random access channel of antenna # 2 is started, so the memory usage is decremented by 10. On the other hand, since the block data of the antenna # 5 is stored at this timing g, the memory usage is subtracted by 9 (1-10) to 24. Thereafter, the memory usage changes in the same manner.

(Appendix 1)
In a preamble detection apparatus for detecting a preamble included in a random access channel transmitted from a mobile terminal,
The antenna that receives the random access channel among a plurality of antennas is selected in order at every time interval of the access slot, and the random access channel is selected from the start timing of the access slot of the selected antenna over the length period of the random access channel. A selection unit for receiving
A random access channel received by the antenna selected by the selection unit is written, a first memory having a capacity of up to two random access channels and one read port;
One random access channel selected from a maximum of two random access channels stored in the first memory is written, a second memory having a capacity for one random access channel and a plurality of read ports;
A preamble detection apparatus comprising: a preamble detection unit that reads a random access channel written in the second memory from the plurality of read ports and detects a preamble included in the random access channel.

(Appendix 2)
In Appendix 1,
The first memory has a capacity for two random access channels and is divided into a first area and a second area each having a capacity for one random access channel;
Write a first random access channel received at a first antenna of the plurality of antennas selected by the selection unit to the first area, the plurality is selected following the first antenna A preamble detection apparatus comprising: a memory control unit that writes a second random access channel received by a second antenna among the second antennas into the second area.

(Appendix 3)
In Appendix 1,
The random access channel received by the antenna selected by the selection unit is divided into a plurality of block data, and sequentially written to the first memory in block data units. Block data corresponding to one random access channel is When written, the memory controller for controlling the random access channel to read from the first memory and transfer to the second memory,
The preamble detection device characterized in that the capacity of the first memory is smaller than the capacity of two random access channels.

(Appendix 4)
In Appendix 3,
The memory control unit, before Symbol writes the block data in the free area of the first memory, the block data and the preamble detection unit, wherein it is possible to store in association with written areas.

(Appendix 5)
In Appendix 3,
The memory control unit, when block data corresponding to one random access channel is written to the first memory, when the preamble detection processing of the preamble detection unit for the previous random access channel is not completed The preamble detection apparatus waits for transfer to the second memory until the processing is completed.

(Appendix 6)
In Appendix 1,
When the number of random access channels selected by the selection unit per access slot is n (n is an integer of 2 or more) and the number of simultaneous detections in the preamble detection unit is n times, A preamble detection apparatus characterized in that the capacity is about n times and the number of read ports of the second memory is about n times.

(Appendix 7)
In Appendix 1,
The preamble detection apparatus, wherein the selection unit, the second memory, and the preamble detection unit are integrally configured as a predetermined device, and the first memory is externally attached to the device.

(Appendix 8)
A radio base station apparatus that accommodates the preamble detection apparatus according to any one of appendices 1 to 7.

It is a figure which shows the conventional structure which detects the preamble in a wireless base station apparatus. It is a figure explaining the process of the preamble detection part. It is a figure which shows the relationship between the access slot to receive and preamble detection processing. It is a figure which shows the example at the time of setting the conventional preamble detection process to 2 parallel structure. It is a figure which shows the 1st structure of the preamble detection process of the wireless base station apparatus in embodiment of this invention. It is a figure which shows the 2nd structure of the preamble detection process of the wireless base station apparatus in embodiment of this invention. It is a figure which shows the 3rd structure of the preamble detection process of the wireless base station apparatus in embodiment of this invention. It is a figure which shows the 4th structure of the preamble detection process of the wireless base station apparatus in embodiment of this invention. FIG. 7 is a diagram illustrating memory optimization control using the third configuration illustrated in FIG. 6 as an example. It is a figure which shows the example of the usage condition of a memory area.

Explanation of symbols

  10: Antenna selection unit, 20 (20A, 20B): 16 read port memory, 21: 32 read port memory, 30: Memory selection unit, 31: Memory control unit, 32: Memory optimization control unit, 40: Preamble detection unit 50: 1 read port memory, 60: interface

Claims (4)

In a preamble detection apparatus for detecting a preamble included in a random access channel transmitted from a mobile terminal,
The antenna that receives the random access channel among a plurality of antennas is selected in order at every time interval of the access slot, and the random access channel is selected from the start timing of the access slot of the selected antenna over the length period of the random access channel. A selection unit for receiving
A random access channel received by the antenna selected by the selection unit is written, a first memory having a capacity of up to two random access channels and one read port;
One random access channel selected from a maximum of two random access channels stored in the first memory is written, a second memory having a capacity for one random access channel and a plurality of read ports;
A preamble detection apparatus comprising: a preamble detection unit that reads a random access channel written in the second memory from the plurality of read ports and detects a preamble included in the random access channel. In claim 1,
The first memory has a capacity for two random access channels and is divided into a first area and a second area each having a capacity for one random access channel;
Write a first random access channel received at a first antenna of the plurality of antennas selected by the selection unit to the first area, the plurality is selected following the first antenna A preamble detection apparatus comprising: a memory control unit that writes a second random access channel received by a second antenna among the second antennas into the second area. In claim 1,
The random access channel received by the antenna selected by the selection unit is divided into a plurality of block data, and sequentially written to the first memory in block data units. Block data corresponding to one random access channel is When written, the memory controller for controlling the random access channel to read from the first memory and transfer to the second memory,
The preamble detection device characterized in that the capacity of the first memory is smaller than the capacity of two random access channels. In claim 1,
The preamble detection apparatus, wherein the selection unit, the second memory, and the preamble detection unit are integrally configured as a predetermined device, and the first memory is externally attached to the device.

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