JP4927946B2 - Method and apparatus for supporting half-duplex terminals in asynchronous mode - Google Patents

Description

  The present disclosure relates generally to wireless communication, and more particularly to techniques for signal acquisition and transmission in a wireless communication system.

  Wireless communication systems are widely deployed to provide various communication services, for example, voice, video, packet data, broadcast and message services can be provided by such wireless communication systems. These systems can be multiple access systems that can support communication for multiple terminals by sharing available system resources. Examples of such multiple access systems include code division multiple access (CDMA) systems, time division multiple access (TDMA) systems, frequency division multiple access (FDMA) systems, and orthogonal frequency division multiple access (OFDMA) systems.

  Wireless communication systems often use frequency division duplex (FDD) for data transmission between a base station and a wireless terminal on the forward and reverse links, where the wireless terminal is forward link (FL) Separate channels are used for the forward and reverse links to allow simultaneous data reception on the reverse link and data transmission on the reverse link (RL). The forward link (or “downlink”) means communication from a base station to one or more terminals, and the reverse link (or “uplink”) is from a terminal to one or more base stations. Means communication.

  A terminal designed to operate in an FDD system can receive and transmit simultaneously using a duplexer that assigns FL and RL communications to different frequency bands to allow simultaneous FL and RL communications. In order to support terminals that cannot receive and transmit at the same time, FDD systems allow base stations and terminals that communicate in half-duplex interlace to alternate between FL transmission and RL transmission. Half-duplex communication can be additionally provided by dividing the frames on the forward and reverse links into half-duplex interlaces. Half-duplex interlace typically groups forward and reverse links into superframes, and all interlaces are assigned an equal number of frames in each superframe and a given frame position within a superframe is relative to a given interlace. It is generated by dividing the frame in each superframe between half-duplex interlaces to always correspond to a particular communication link (ie, forward link or reverse link).

  A terminal in a wireless communication system does not need to know which base station is transmitting in the vicinity thereof. Further, in a system in which a base station operates asynchronously, a terminal does not need to know timing information necessary for communication with a specific base station. Thus, in order to detect for transmission from base stations in the system and to synchronize to the timing and frequency of each detected base station of interest, the terminal may perform signal acquisition on the forward link. it can. The base station can transmit acquisition pilots or other signals to assist in signal acquisition and to allow the terminal to detect the base station. However, in an FDD system that utilizes half-duplex communication in which the base station operates asynchronously, some or all of the acquisition pilots transmitted by the base station are terminals that operate on a single half-duplex interlace. The RL may be transmitted exclusively during RL transmission. As a result, a terminal operating on a single half-duplex interlace may not be able to find asynchronous base stations in the system, resulting in reduced system efficiency.

  The following presents a simplified summary of the disclosed embodiments in order to provide a basic understanding of such embodiments. This summary is not an extensive overview of all intended embodiments, and is not intended to identify key or critical elements or to delineate the scope of such embodiments. Its sole purpose is to present some concepts of the disclosed embodiments in a simplified form as an exception to the detailed description that is presented later.

  The described embodiments alleviate the aforementioned problems by providing support for signal acquisition in FDD systems that utilize half-duplex communications and base stations operating asynchronously. More specifically, interlaced forward and reverse link superframes are such that a given frame position in one superframe alternates between forward and reverse link communications for a particular half-duplex interlace. It is a structure to do. In one example described herein, this groups an odd number of frames into each forward link and reverse link superframe and frames in the forward link and reverse link superframes as the first. This is accomplished by assigning alternating half-duplex and second half-duplex interlaces. By changing the communication link used by a half-duplex interlace at a given frame position, a terminal operating on a single half-duplex interlace operates asynchronously regardless of the time at which the acquisition signal is transmitted. An acquisition signal from the base station can be detected.

  According to one aspect, a method for providing half-duplex communication in the presence of an asynchronous sector in a wireless communication system is described herein. The method comprises splitting transmission timelines on the forward and reverse links into superframes having a fixed odd number of frames. Further, the method can include assigning each frame in the superframe on the forward link and reverse link to one of the first half-duplex interlace and the second half-duplex interlace. The method can also include associating the terminal with one or more half-duplex interlaces. Further, the method can include communicating with the terminal using a frame assigned to one or more half-duplex interlaces associated with the terminal.

  Another aspect can include a memory that stores data related to the first half-duplex interlace and the second half-duplex interlace, wherein the first half-duplex interlace and the second half-duplex interlace are , Having a frame allocated between each superframe on the forward link and reverse link having a predetermined odd number of frames, wherein the frame on the forward link and reverse link is a first half-duplex interlace and Staggered between second half-duplex interlaces.

The wireless communications apparatus can also include a processor configured to associate the access terminal with a half-duplex interlace and communicate with the access terminal using an associated half-duplex interlaced frame.

  Yet another aspect relates to an apparatus that facilitates half-duplex communication in a wireless communication system that operates asynchronously. The apparatus includes means for splitting frames for the forward and reverse links provided by a set of superframes between a first half duplex interlace and a second half duplex interlace. And a given frame position in one sp-ar frame alternates between forward and reverse link communications for a given half-duplex interlace. The apparatus can further include means for determining one or more half-duplex interlaces for communication with the wireless terminal.

  Yet another aspect relates to a computer-readable medium that can comprise code for causing a computer to divide a transmission timeline for the forward and reverse links into superframes having a certain odd number of frames. Further, the computer readable medium can include code for causing a computer to assign a frame in each superframe to one of a plurality of half-duplex interlaces, wherein the frames are staggered between half-duplex interlaces. .

  According to another aspect, an integrated circuit is described herein that can execute computer-executable instructions for supporting half-duplex communication in a wireless communication system in the presence of an asynchronous access point. These instructions may comprise k for dividing the transmission timeline for the forward link into superframe preambles and each superframe having a fixed odd number of frames. Further, the instructions may include dividing the transmission timeline for the reverse link into superframes having a certain odd number of frames. Further, the instructions may include assigning each frame in the superframe on the forward link and reverse link to one of the first half-duplex interlace and the second half-duplex interlace.

  According to yet another aspect, a method of half-duplex communication with an asynchronously operating sector in a wireless communication system is described herein. The method includes a first half-duplex interlace and a second half-duplex interlace for communication with a first sector on each superframe for forward and reverse links having a constant odd number of frames. The first half-duplex interlace and the second half-duplex interlace are assigned to non-overlapping frames in each superframe. Further, the method can comprise communicating with the first sector in one or more associated half-duplex interlaced frames. Further, the method can include attempting to detect a second sector on the forward link in one or more associated half-duplex interlaced frames.

  Another aspect is the first access point on each superframe for the forward and reverse links having a non-overlapping frame in each superframe assigned to a predetermined odd number of frames and half-duplex interlaces. A memory storing data relating to a half-duplex interlace for communication with the. The wireless communications apparatus communicates with a first access point using a frame assigned to a half-duplex interlace and uses a frame assigned to a half-duplex interlace to transmit a second on the forward link. A processor configured to detect one or more acquisition pilots from the success point may further be included.

  Yet another aspect relates to an apparatus that facilitates half-duplex communication in a wireless communication system in the presence of an asynchronous base station. The apparatus can include means for associating with a half-duplex interlace selected from a plurality of half-duplex interlaces for communication with a serving base station, each half-duplex interlace having a predetermined odd number of Includes a frame for the forward and reverse links allocated from each superframe that contains the frame. The apparatus can further include means for communicating with a serving base station using an associated half-duplex interlaced frame. Further, the apparatus can include means for detecting information transmitted from an asynchronous base station using a half-duplex interlaced frame associated with the forward link.

  Yet another aspect relates to a computer-readable medium that can comprise code for causing a computer to establish communication with a first sector in a wireless communication system. Further, the computer-readable medium causes the computer to receive an assignment for the half-duplex interlace for communication with the first sector selected from the first half-duplex interlace and the second half-duplex interlace. The allocated half-duplex interlace includes frames for the forward and reverse links allocated from each superframe including a certain odd number of frames. The computer-readable medium can further include code for causing the computer to communicate with the first sector using the assigned half-duplex interlaced frame. Further, the computer-readable medium further includes a forward link that uses an associated half-duplex interlaced frame, at least in part, by searching for one or more acquisition pilots transmitted by the second sector. Code may be included to cause the computer to attempt to detect the second sector above.

  Another aspect relates to an integrated circuit that executes computer-executable instructions for half-duplex communication in the presence of an asynchronous sector in a wireless communication system. These instructions can include associating with one or more of the first half-duplex interlace and the second half-duplex interlace for communication with the first sector, The double interlace and the second half-duplex interlace are divided into one such that a given frame position in the superframe alternates between forward link communication and reverse link communication for a given half-duplex interlace. Includes frames for the forward and reverse links provided by a set of superframes. Further, the instructions can comprise communicating with the first sector on one or more of the forward and reverse links using one or more associated half-duplex interlaced frames. it can. Further, the instructions can include searching for an acquisition pilot transmitted by a second sector on the forward link using one or more associated half-duplex interlaced frames.

  To the accomplishment of the above and related ends, one or more embodiments comprise the features described in detail below and specifically pointed out in the claims. The following description and the annexed drawings set forth in detail certain illustrative aspects of the illustrated embodiment. However, these aspects only illustrate some of the various ways in which the principles of the various embodiments are used. Further, the disclosed embodiments are intended to include all such aspects and their equivalents.

1 illustrates a wireless multiple-access communication system in accordance with various aspects set forth herein. FIG. 7 is a block diagram of a system that facilitates half-duplex communication in a wireless communication system operating in an asynchronous mode in accordance with various aspects. Fig. 4 illustrates an example FDD half-duplex superframe structure in accordance with various aspects. Fig. 3 illustrates an example superframe structure utilized by an asynchronously operating sector in a wireless communication system. Fig. 3 illustrates an example superframe structure utilized by an asynchronously operating sector in a wireless communication system. 1 illustrates an example superframe structure that facilitates communication with an asynchronously operating sector in a wireless communication system. 1 illustrates an example superframe structure that facilitates communication with an asynchronously operating sector in a wireless communication system. 2 is a flow diagram of a method for half-duplex communication with an access terminal in a wireless communication system. 2 is a flow diagram of a method for half-duplex communication with one or more asynchronously operating sectors in a wireless communication system. FIG. 2 is a block diagram illustrating an example wireless communication system in which one or more embodiments described herein may function. 1 is a block diagram of a system that coordinates half-duplex communication in an asynchronously operating wireless communication system in accordance with various aspects. FIG. 1 is a block diagram of a system that coordinates half-duplex communication in an asynchronously operating wireless communication system in accordance with various aspects. FIG. FIG. 2 is a block diagram of an apparatus that facilitates half-duplex communication with a wireless terminal. FIG. 2 is a block diagram of an apparatus that facilitates half-duplex communication with one or more asynchronous wireless access points.

Detailed description

  Various embodiments are now described with reference to the drawings, wherein like reference numerals are used to refer to like elements throughout. In the following description, for the purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of one or more aspects. However, such embodiments may be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form in order to facilitate describing one or more embodiments.

  As used in this application, the terms “component”, “module”, “system”, etc. refer to computer-related entities, hardware, firmware, a combination of hardware and software, software, or software in execution. Is intended to show. For example, a component may be, but is not limited to being, a process running on a processor, a processor, an object, an executable, a thread of execution, a program, and / or a computer. By way of illustration, both an application running on a computing device and the computing device can be a component. One or more components may exist within a process and / or thread of execution, and one component may be localized to one computer and / or distributed between two or more computers. . In addition, these components can execute from various computer readable media having various data structures stored thereon. Those components may be one or more data packets (eg, one component that interacts with other components in a local system, distributed system, and / or interacts with other systems by signals in a network such as the Internet. May be communicated locally and / or by a process according to a signal having data from

  Moreover, various embodiments are described herein in connection with a wireless terminal and / or a base station. A wireless terminal may refer to a device that provides voice and / or data connectivity to a user. A wireless terminal may be connected to a computing device such as a laptop computer or desktop computer, or it may be a self contained device such as a personal digital assistant (PDA). A wireless terminal may also be referred to as a system, subscriber unit, subscriber station equipment, mobile station, mobile, remote station, access point, remote terminal, access terminal, user terminal, user agent, user equipment or user equipment. it can. Wireless terminals include subscriber stations, wireless devices, mobile phones, PCS phones, cordless phones, session initiation protocol (SIP) phones, wireless local loop (WLL) stations, personal digital assistants (PDAs), wireless connectivity capabilities Or other processing device connected to a wireless modem. A base station (eg, access point) may refer to a device in an access network that communicates with a wireless terminal over an air interface through one or more sectors. The base station may act as a router between the wireless terminal and the access network, even if it includes an Internet Protocol (IP) network, by converting the received air interface frame into an IP packet. The base station also coordinates the management of attributes for the air interface.

  Moreover, various aspects or features described herein may be implemented as a method or product using standard programming and / or engineering techniques. The term “article of manufacture” as used herein is intended to encompass a computer program accessible from any computer-readable device, carrier or medium. For example, computer readable media include magnetic storage devices (eg, hard disks, floppy disks, magnetic strips ...), optical disks (eg, compact discs (CDs) (digital versatile discs (DVDs) ...). ), Smart cards and flash memory devices (eg, cards, sticks, key drives ...), but are not limited thereto.

  Various embodiments will be presented for a system that may include multiple devices, components, modules, and the like. It should be understood and appreciated that the various systems may include additional devices, components, modules, etc. and / or may not include all of the devices, components, modules, etc. discussed with respect to the drawings. It is. A combination of these approaches may also be used.

  Referring now to the drawings, FIG. 1 is an illustration of a wireless multiple-access communication system 100 in accordance with various aspects. In one example, the wireless multiple-access communication system 100 includes multiple base stations 110 and multiple terminals 120. Further, one or more base stations 110 can communicate with one or more terminals 120. By way of non-limiting example, base station 110 may be an access point (Node B) and / or other suitable network entity. Each base station 110 provides communication coverage for a particular geographic area 102. As used herein and generally in the art, the term “cell” can refer to a base station 110 and / or its coverage area 102 depending on the context in which the term is used. To improve system capacity, the coverage area 102 corresponding to the base station 110 may be divided into multiple smaller areas (eg, areas 104a, 104b and 104c). Each of the smaller areas 104a, 104b and 104c may be served by a respective base transceiver subsystem (BTS, not shown). As used herein and generally in the art, the term “sector” can refer to a BTS and / or its coverage area depending on the context in which the term is used. In a cell 102 having multiple sectors 104, BTSs for all sectors 104 of that cell 102 may be located in the base station 110 for the cell 102.

  In other examples, the system 100 can utilize a centralized architecture using a system controller 130 that can couple to one or more base stations 110 and provide coordination and control for the base stations 110. it can. According to other aspects, the system controller 130 may be a single network entity or a collection of network entities. Further, system 100 may utilize a distributed architecture to allow base stations 110 to communicate with each other as needed.

  According to one aspect, terminals 120 may be distributed throughout system 100. Each terminal 120 may be stationary or mobile. By way of non-limiting example, terminal 120 may be an access terminal (AT), a mobile station, user equipment, a subscriber station, and / or other suitable network entity. A terminal may be a wireless device, a mobile phone, a personal digital assistant (PDA), a wireless modem, a handheld device, and so on.

  According to another aspect, system 100 may utilize FDD and utilize simultaneous communication on the forward link (FL) and reverse link (RL) with two separate frequency channels. Further, system 100 may support full-duplex communication for terminal 120 capable of full-duplex communication (“full-duplex terminal”). As used herein and generally in the art, full duplex refers to a mode in which a station (eg, base station 110 or terminal 120) can transmit and receive simultaneously. In one example, a station capable of full-duplex operation may be equipped with a single antenna for both transmission and reception. Thus, the station may have a duplexer that can send a received signal from the data receiving antenna to the receiver and send a conditioned signal from the data transmitting transmitter to the antenna.

  Further, system 100 may also support half-duplex communication for half-duplex (“half-duplex terminal”) for terminals 120 that are not capable of full-duplex operation. As used herein and generally in the art, half duplex refers to a mode in which a station can transmit or receive at a given time but cannot transmit and receive at the same time. In one example, a station capable of only half-duplex operation may be equipped with a single antenna for both transmission and reception. Thus, the station may have a switch that can connect an antenna to the receiver during data reception and can connect a transmitter to the antenna during data transmission.

  In another example, system 100 may include one or more multiple access schemes such as CDMA, TDMA, FDMA, OFDMA, single carrier FDMA (SC-FDMA), and / or other suitable multiple access. A scheme may be used. OFDMA utilizes orthogonal frequency division multiplexing (OFDM), and SC-FDMA utilizes single carrier frequency division multiplexing (SC-FDM). OFDM and SC-FDM can divide the system bandwidth into multiple orthogonal subcarriers (eg, tones, bins ...) that can each be modulated with data. Typically, modulation symbols are sent in the frequency domain with OFDM and in the time domain with SC-FDM. Further, system 100 may utilize a combination of multiple access schemes such as OFDMA and CDMA. Further, system 100 may utilize various framing structures to illustrate how data and signals are transmitted on the forward and reverse links. For clarity, non-limiting examples that may be utilized by system 100 are described in more detail herein.

  FIG. 2 is a block diagram of a system 200 that facilitates half-duplex communication in a wireless communication system operating in an asynchronous mode in accordance with various aspects described herein. In one example, system 200 includes one or more base stations 210 and one or more terminals 220. According to one aspect, base station 210 and terminal 220 may communicate on the forward link (FL) and reverse link (RL) via antenna 216 at base station 210 and antenna 226 at terminal 220. it can. In the system 200, only one antenna 216 is illustrated for each base station 210 and only one antenna 226 is illustrated for each terminal 220, but the base station 210 and / or terminal 220 may be It should be appreciated that there may be multiple antennas 216 and / or 226 for communicating with multiple base stations 210 and / or terminals 220 and other suitable network entities (eg, system controller 130).

  According to one aspect, base station 210 can generate and transmit information necessary to establish communication with terminal 220 to system 200 by utilizing pilot generation component 212. That information can be received and utilized by terminal 220 by using pilot detection component 222 to undergo a signal acquisition process. Illustratively, the information generated by pilot generation component 212 and processed by pilot detection component 222 includes timing and synchronization information for system 200, timing and synchronization information for base station 210 associated with pilot generation component 212, pilot generation component It may relate to the identity of base station 210 associated with 212, overhead information about system 200, and / or other suitable information. In one particular non-limiting example, one or more base stations 210 in system 200 can include multiple antenna groups (not shown), each of which is a group of antennas. Can serve individual coverage areas (eg, sector 104) and can include individual pilot generation components 212 to establish communication with one or more terminals 220.

  In one example, pilot generation component 212 at base station 210 can provide the information necessary to establish communication with terminal 220 in one or more acquired pilots and / or other signals. As a non-limiting example, these signals can include one or more time domain pilots, such as time division multiplexed (TDM) pilots. Upon receiving these signals, pilot detection component 222 at terminal 220 may correlate with the acquired pilot and / or other signals to establish communication with base station 210 that transmitted the signal. The correlation performed by pilot detection component 222 at terminal 220 can be, for example, a direct (eg, real-time) correlation or a delayed correlation.

  According to another aspect, system 200 can utilize FDD communication. However, the one or more terminals 220 may not be designed for operation in a system that utilizes FDD communication. For example, terminal 220 may lack a duplexer or other means to allow terminal 220 to transmit and receive simultaneously, as required by conventional FDD full-duplex communication. In order to allow these terminals 220 to function in the system 200, the base station 210 provides FDD half-duplex communication functionality by dividing the FL and RL transmission timelines into multiple half-duplex interlaces. Interlacing components 214 may be included. Further, one or more terminals 220 may also have an interlacing component 224.

  In one example, the interlacing components 214 and 224 can divide the FL and RL transmission timelines into superframes, each of which is a superframe preamble and / or a predetermined number of It can be further divided into physical layer frames (PHY frames, simply “frames”). Alternatively, the superframe structure for FL and RL transmission timelines can be pre-configured by other network entities (eg, system controller 130). Illustratively, each FL superframe can be configured to include a superframe preamble followed by a predetermined number of frames, and each RL superframe matches a corresponding frame on the forward link. It can be configured to include a predetermined number of frames. The frames can be configured to be adjacent in time, or a guard time can be applied between the frames to prevent interference during transitions between communication links on a half-duplex interlace.

  In another example, interlacing components 214 and 224 can divide the FL and RL transmission timelines between equal half-duplex interlaces. In one illustrative example, interlacing components 214 and / or 224 may assign a first half-duplex interlace and a second half-duplex by allocating frames in an interlaced fashion on the forward and reverse links. The FL and RL transmission timelines can be divided between heavy interlaces. After dividing the FL and RL transmission timelines into half-duplex interlaces, interlacing components 214 and 224 may associate terminal 220 with one or more interlaces. The assignment may be based on, for example, load balancing between interlaces, identification information from terminal 220, and / or other suitable factors. Further, terminal 220 can be further associated with one or more interlaces based on the communication capabilities of terminal 220. For example, a terminal 220 capable of full-duplex operation in system 200 can be associated with all interlaces and can be allowed to communicate with base station 210 on the forward and reverse links in any interlace.

  According to another aspect, pilot generation component 212 at each base station 210 can transmit the signals necessary for signal acquisition by pilot detection component 222 at terminal 220 of the superframe preamble on the forward link. Alternatively, the acquisition signal can be transmitted on one or more frames in the forward link. In one example, system 200 is configured to operate asynchronously so that transmission timelines used by base station 210 and / or antenna groups within base station 210 need not be aligned in time. Can be done. However, such an asynchronous mode of operation for system 200 can conflict with half-duplex communication supported by interlacing components 214 and 224. In particular, since the transmission timeline of base station 210 need not be aligned, if the half-duplex terminal associated with a particular interlace cannot detect the acquired signal, pilot generation component 214 in base station 210 may It may be configured to always transmit an acquisition signal at a time associated with the reverse link of the heavy terminal or at some other time. As a result, it may not be possible to detect when the base station 210 and / or an antenna group within the base station 210 is transmitting an acquisition signal, and therefore communication with the entity cannot be established. If this is not the case, one or more terminals 220 may not be able to detect.

  In order to mitigate the problems presented by the asynchronous mode of operation for system 200, interlacing components 214 and 224 are configured so that a given frame position in each superframe for a given half-duplex interlace is forward link communication and reverse link. FL and RL superframes can be configured to alternate between transmissions. As a specific, non-limiting example, interlacing components 214 and 224 may alternate between forward link communication and reverse link communication with the first frame position in each superframe for a given half-duplex interlace. As such, alternating frames in each FL and RL superframe can be allocated between half-duplex interlaces. In a more specific, non-limiting example, interlacing components 214 and 224 can interleave half-duplex interlaces in a manner that groups an odd number of frames in each FL and RL superframe and alternates frames within that superframe. , The interlace assignment corresponding to a given frame position can be alternated. Such an allocation scheme is one for a given frame position between FL and RL communications for a given half-duplex interlace so that the interlace has an odd number of frames for each communication link in one superframe. Frames can be changed. By changing the communication link used by a half-duplex interlace at a given frame position, a terminal 220 operating on a single half-duplex interlace can be asynchronously transmitted regardless of the time at which the acquisition signal is transmitted. An acquired signal from the operating base station 210 can be detected. For example, if the asynchronous base station 210 transmits information at a time assigned RL transmission to the terminal 220, the interlacing components 214 and / or 224 at the base station 210 and / or the terminal 220 may obtain the acquired information. May be transmitted in subsequent superframes at the time allotted for RL transmission for terminal 220 so that the information can be detected by terminal 220.

  FIG. 3 is a block diagram illustrating an example FDD half-duplex superframe structure 300 in accordance with various aspects described herein. In one example, forward link transmission timeline 310 and reverse link transmission timeline 320 can be divided into respective superframes 315 and 325. Each forward link superframe 315 can be combined with a corresponding reverse link superframe 325 to occupy a preamble followed by a predetermined number of frames in time as indicated by superframe structure 300. In a non-limiting example illustrated by superframe structure 300, forward link superframe 315 can include a preamble followed by 24 forward link frames, and the corresponding reverse link superframe. Frame 325 may include 24 reverse link frames that are preceded by a time interval corresponding to the superframe preamble in forward link superframe 315.

  In another example, two half-duplex interlaces, half-duplex interlace 0, and half-duplex interlace 1 can be defined. Although the term “half-duplex interlace” is used herein, this is only one term that can be used, and any suitable term may be used with respect to the embodiments described herein. It should be recognized that it is good. In one example, half-duplex interlace 0 includes every other forward link frame in each forward link superframe 315 starting with the first forward link frame after the superframe preamble, and Every other reverse link frame in each reverse link superframe 325 starting with a second reverse link frame in the superframe may be included. In another example, half-duplex interlace 1 includes every other forward link frame in each forward link superframe 315 beginning with the second forward link frame after the superframe preamble, and Every other reverse link frame in each reverse link superframe 325 starting with the first reverse link in the superframe may be included. Thus, half-duplex interlace 1 can be complementary to half-duplex interlace 0. More specifically, half-duplex interlace 1 may include forward and reverse link frames in place of the reverse and forward link frames included in half-duplex interlace 0, respectively. Furthermore, both half-duplex interlaces can share a common superframe preamble. Each half-duplex interlace may also include non-overlapping frames in time for the forward and reverse links, which indicates that the forward link frame does not overlap in time with the reverse link frame. means.

  Although the above example describes a superframe structure 300 having two half-duplex interlaces, it should be appreciated that any number of half-duplex interlaces can be defined. In addition, a half-duplex interlace may include the same number of forward and reverse link frames staggered together, or a half-duplex interlace may include a different number of forward and reverse link frames. Also good. In addition, the forward and reverse link frames of each half-duplex interlace in superframe structure 500 are adjacent to each other, but the amount of time to switch between transmission and reception or between reception and transmission is halved. A guard time may be provided between the forward and reverse link frames of each half-duplex interlace to provide to the heavy terminal.

  In one example, as indicated by forward link timeline 310 and reverse link timeline 320, the half-duplex interlace 0 frames for each link are assigned a sequentially increasing index. Similarly, half-duplex interlace 0 forward link frame n follows half-duplex interlace 1 reverse link frame n 'and half-duplex interlace 1 reverse link frame n' is half-duplex. As with interlace 0 reverse link frame n, the half-duplex interlace 1 frame for each link also increases sequentially using prime notation (eg, 1 ', 2' ...). An index can be assigned.

  A terminal (eg, terminal 220) in a wireless communication system that utilizes superframe structure 300 may access the system by one or more of the half-duplex interlaces in various ways. In one example, the terminal can arbitrarily select one of two half-duplex interlaces to access the system. In another example, the terminal can determine the half-duplex interlace to be used for system access and can access the system via the determined half-duplex interlace. Information about which half-duplex interlace to use for system access can be communicated to the terminal in the superframe preamble, known a priori by the terminal or provided in some other way. Additionally and / or alternatively, a base station (eg, base station 210) may determine the capabilities of the terminal and associate the terminal with one or more half-duplex interlaces.

  According to one aspect, data and signals are exchanged between a half-duplex terminal in a half-duplex interlaced frame assigned to the base station and the terminal. In the forward link, the base station sends data and signals (e.g., power control bits and erasure indicators, etc.) to the terminal only in the half-duplex interlaced forward link frame assigned to the terminal. May be. In the reverse link, a terminal may transmit data and signals to the base station only in the half-duplex interlaced reverse link frame assigned to the terminal.

  4A and 4B are illustrations of examples that may be utilized by a sector (eg, base station 210 or an antenna base in one or more base stations 210) in a wireless communication system (eg, base station 200) operating in an asynchronous mode. 2 is a block diagram illustrating a superframe structure 400. FIG. Referring to FIG. 4A, a transmission timeline for an asynchronous sector is illustrated for a series of FL superframes 415 and RL superframes 425. In one example, transmission timelines 410 and 420 correspond to FL and RL transmission timelines for sectors in the system illustrated by superframe structure 400, respectively. As illustrated by FIG. 4A, transmission timelines 410 and 420 may be similar in structure to the respective transmission timelines 310 and 320 illustrated and described with respect to superframe structure 300. As a specific illustration, each FL superframe 415 in the timeline 410 may include a superframe preamble followed by 24 frames, and each RL superframe 425 in the timeline 420 has a corresponding FL It can include 24 frames preceding but preceded by the FL superframe preamble in superframe 415. Further, the frames in imlines 410 and 420 may be split between half-duplex interlaces in an alternating fashion such that FL frames and RL frames are staggered between the interlaces as shown in superframe structure 400. Thus, an equal number of FL and RL frames can be assigned for each interlace in superframes 415 and 425 in superframe structure 400, and a given frame position in a superframe is a given communication link for a given interlace. It can be configured to always correspond to.

  According to one aspect, transmission timeline 430 illustrates a neighboring sector's forward link operating asynchronously from sectors corresponding to timelines 410 and 420. As illustrated by the superframe structure 400, it can be observed that an offset exists between the superframe preamble in the asynchronous sector timeline 430 and the corresponding superframe preamble provided in the FL timeline 410. As can be further observed, before the superframe preamble in the asynchronous sector timeline 430 can be offset so that they coincide with the frames in the other sector timelines 410 and 420.

  Neighboring sectors using FL timeline 430 to establish communications with terminals currently serving by sectors providing timelines 410 and 420 and / or other sectors are pilots 432-434. And / or other information required for signal acquisition may be transmitted during one or more superframe preambles. In one example, pilots 432-434 can be transmitted at certain times in the superframe preamble as illustrated by superframe structure 400. Additionally and / or alternatively, pilots 432-434 can be transmitted at various locations within the superframe preamble or within one or more predetermined FL frames (not shown) in timeline 430. However, due to the offset between sectors caused by the asynchronous mode in which the sector providing the timeline 430 operates, some or all of the information required to establish a connection with the pilots 432-434 and / or the terminal It may be transmitted whenever a frame is allocated for RL communication for interlace on line 420. Thus, a terminal operating on a single half-duplex interlace may not be able to detect a sector whose pilot transmission occurs concurrently with the terminal's RL transmission.

  FIG. 4B illustrates a detailed view of the superframe structure 400. In particular, FIG. 4B illustrates frames in the FL timeline 410 and the RL timeline 420 corresponding to the transmission of the superstructure preamble by neighboring asynchronous sectors on the timeline 430. As can be observed, TDM pilots 432-434 can be transmitted as part of each superframe preamble by an asynchronous sector in timeline 430. In the particular example illustrated by FIG. 4B, TDM pilots 432-434 are transmitted in frames 1 and 13 of interlace 0 and frames 0 ′ and 12 ′ of interlace 1. As further illustrated by FIG. 4B, TDM pilots 432-434 in superframe structure 400 may be received exclusively in interlace 0 FL frames and interlace 1 RL frames. As a result, half-duplex terminals using interlace 0 are given the ability to detect neighboring sectors by using pilots 432-434 in all superframes, while half-duplex terminals using interlace 1 Will not be able to detect neighboring sectors from pilots 432-434 in any superframe.

  5A and 5B are block diagrams illustrating an example superframe structure 500 that facilitates communication with asynchronously operating sectors in a wireless communication system. Referring to FIG. 5A, transmission timelines 510 and 520 for a given sector and a neighboring asynchronous sector FL transmission timeline 530 in a wireless communication system are similar to FIG. 4A in a series of FL superframes 515 and RL supers. Illustrated for frame 525. According to one aspect, neighboring sectors using FL timeline 530 may include pilots 532-534 and / or sectors providing timelines 510 and 520 during one or more superframe assemblies and / or other Other information can be sent to establish communication with the terminal currently served by the sector. As can be observed from the superframe structure 500, the superframe preamble in the timeline 530 and the pilots 532-534 transmitted therein are offset to coincide with the frames in the timeline 510-520 at a given frame position. sell. Thus, in a manner similar to superframe structure 400, pilots 532-534 can communicate at set frame positions in each superframe.

  To alleviate the problems described with respect to superframe structure 400, frames in superframe structure 500 alternate between a predetermined frame position in the superframe and the forward and reverse links for a given interlace. As a specific, non-limiting example, this can be accomplished by configuring superframes in superframe structure 500 such that each superframe includes an odd number of frames. In the particular example illustrated by structure 500, each FL superframe 515 and RL superframe 525 may include 25 frames. The frames within each superframe are then interleaved in a half-duplex interlace manner in a manner similar to superframe structures 300 and 400 to obtain a staggered assignment of frames between the half-duplex interlaces. Can be assigned to. However, in contrast to superframe structures 300 and 400, a given frame position in superframe structure 500 alternates between communication links for a given half-duplex interlace as a result of each superframe containing an odd number of frames. can do.

  FIG. 5B illustrates a detailed view of the superframe structure 500. In particular, FIG. 5B illustrates frames in the FL timeline 510 and the RL timeline 520 corresponding to the transmission of superframe preambles by neighboring asynchronous sectors in the timeline 530. As can be observed, TDM pilots 532-534 can be transmitted as part of each superframe preamble by an asynchronous sector in timeline 530. In the particular example illustrated by FIG. 5B, TDM pilots 532-534 are transmitted in interlace 0 frames 1 and 13 and interlace 1 frames 0 ′ and 13 ′. As can be observed from FIG. 5B, the communication links used by a given interlace at a given frame location within the superframe alternate in the superframe structure 500, so that half-duplex terminals and interlaces utilizing interlace 0 Both half-duplex terminals utilizing 1 are given the ability to detect neighboring sectors transmitting pilots 532-534 in alternating superframes.

  With reference to FIGS. 6-7, illustrated is a method for supporting signal acquisition in a half-duplex communication and asynchronously operating sector-based wireless communication system. For ease of explanation, these methods are illustrated and described as a series of actions, but according to one or more embodiments, some actions may be in a different order and / or here. It should be understood and appreciated that it may occur simultaneously with acts other than those shown and described in FIG. For example, those skilled in the art will understand and appreciate that a method could alternatively be represented as a series of interrelated states or events, such as in a state diagram. Moreover, not all illustrated acts may be required to implement a methodology in accordance with one or more embodiments.

  With reference to FIG. 6, illustrated is a methodology 600 for half-duplex communication with an access terminal (eg, terminal 220) in a wireless communication system (eg, system 200). It should be appreciated that methodology 600 can be performed by, for example, a base station (eg, base station 210), an antenna group within the base station, and / or other suitable network entity. Method 600 begins at blocks 602 and 604, where an FL transmission timeline (eg, FL transmission timeline 310) is a superframe (eg, RL transmission timeline) that includes a superframe preamble and a fixed number of frames, respectively. 320), and the corresponding transmission timeline (eg, RL transmission timeline 320) is divided into superframes (eg, RL superframe 325) each containing a certain number of frames. In one example, the FL superframe and the RL superframe are an odd number that allows greater flexibility for half-duplex communication support between sectors operating asynchronously as described below. Each can be divided at blocks 602 and 604 to include a frame.

  Dividing the FL and RL transmission timelines at blocks 602 and 604, the method 600 can proceed to block 606, where the frame in each FL and RL superframe is a first half-duplex interlace and a second. Assigned to one of the half-duplex interlaces. In one example, frames are alternated at block 606 such that FL and RL frames are staggered between half-duplex interlaces in a manner similar to the interlace assignment illustrated by superframe structures 300, 400, and 500. Assigned in a manner. As illustrated by superframe structure 400, staggered assignments of frames are transmitted to sectors utilizing method 600 by pilots (eg, pilots 432-434) and / or sectors operating asynchronously. Other signals can be transmitted at a predetermined frame position in each FL and RL superframe. Thus, in order for a half-duplex terminal operating in both the first half-duplex interlace and the second half-duplex interlace to be able to detect these pilots, a given frame position in the superframe is both Frames can be allocated at block 606 to alternate between FL and RL communications for interlace. As a specific, non-limiting example, a superframe can be assigned at blocks 602 and 604 to include an odd number of frames. Based on this assignment, a staggered assignment of frames is blocked to change the communication link used by the interlace at a given frame position in a manner similar to the interlace assignment illustrated by the superframe structure 500. Can be done with 606.

  Method 600 then continues to block 608 where the access terminal is associated with a half-duplex interlace. Based on this association, communication using the associated half-duplex interlace can be established to the access terminal at block 610. In one example, communication with an access terminal is established at block 610 by transmitting an acquisition pilot (eg, a pilot generated by pilot generation component 212) and / or other transmissions. Finally, at block 612, communication with the access terminal is performed using a half-duplex interlaced frame associated with the access terminal at block 608. In one example, forward link communication is performed at block 612 using the first frequency channel in the associated half-duplex interlace, and reverse link communication is performed in the second half in the associated half-duplex interlace. This is done at block 612 using the frequency channel.

  FIG. 7 is an illustration of one or more asynchronously operating sectors (eg, base station 210 and / or antenna groups within one or more base stations 210) in a wireless communication system (eg, system 200). 1 illustrates a method 700 for half-duplex communication. It should be appreciated that method 700 can be performed by, for example, a terminal (eg, terminal 220) and / or other suitable network entity. The method 700 begins at block 702, where communication is established to the sector at least partially by detecting acquisition pilots and / or other signals from the sector (e.g., by using the pilot detection component 222). Is done.

  The method 700 continues to block 704, where an entity performing the method 700 is in block 702 on one or more FL superframes (eg, FL superframe 315) and RL superframes (eg, RL superframe 325). An acquisition signal is received and associated with the interlace for communication with the half-duplex sector. In one example, an FL superframe in which communication should occur is a superframe preamble followed by a certain number of frames (eg, by interlacing components 214 and / or 224, or by other suitable network entities). It can be configured to include. In another example, the half-duplex interlace at block 704 causes the FL and RL frames to be staggered between multiple half-duplex interlaces in a manner similar to the interlace assignment illustrated by superframe structures 300, 400, and 500. Can include FL and RL frames that are assigned in an alternating fashion. In addition, allow half-duplex terminals operating on all half-duplex interlaces to detect pilots and / or other signals needed to establish communication with neighboring sectors (eg, at block 708). Thus, a frame can be assigned to a half-duplex interlace such that a predetermined frame position within the superframe alternates between FL and RL communications for a predetermined interlace. In one specific example, this assigns each FL and RL superframe to include an odd number of frames, and then staggers the frames between half-duplex interlaces in a manner similar to superframe structure 500. This can be accomplished by using a staggered assignment.

  Upon completion of the acts described in block 704, method 700 continues to block 706, where at block 702 using half-duplex interlaced FL and RL frames associated with the entity performing method 700 at block 704. Communication is performed with a sector in which communication is established. In one example, forward link communication may be performed at block 706 using a first frequency channel in an associated half-duplex interlaced forward link frame, and reverse link communication may be May be performed at block 706 using a second frequency channel in a half-duplex interlaced reverse link frame.

  Method 700 may end at block 708, where an entity performing method 700 may detect detecting other signals from other sectors in an acquisition pilot and / or associated half-duplex interlaced FL frame. Try. As generally noted above, the sector in which the signal is detected in block 706 can operate asynchronously with the sector in which communication occurs at lock 706, and pilots from the asynchronous sector are assigned to a predetermined number. Received at one or more frame locations within the superframe. By associating with half-duplex interlacing at block 704, which varies between FL and RL communications for a given frame position, the entity performing method 700 is able to start from an asynchronous sector at block 708 regardless of the time at which the signal is received. Can be detected.

  Referring now to FIG. 8, a block diagram illustrating an example wireless communication system 800 in which one or more embodiments can function is provided. According to one aspect, system 800 includes base station 110, half-duplex terminal 120x, and full-duplex terminal 120y. In one example, the base station 110 includes a transmit (TX) data and signal processor 812 that can receive traffic data from the data transmitter 810 and signals from the controller / processor 830 and / or scheduler 834. Controller / processor 830 may provide system information for superframe preambles and / or system information for signals (eg, ACK, PC command, erasure indicator ...) for one or more terminals communicating with base station 110. And scheduler 834 may provide allocation of resources (eg, data channels, frames, and / or subcarriers) on the forward and / or reverse link for the terminals. Further, TX data and signal processor 812 can process (eg, encode, interleave, and / or symbol map) traffic data and signals to provide data symbols and signal symbols, respectively. Base station 110 multiplexes pilot symbols with data and signal symbols, modulates the multiplexed symbols (eg, for OFDMA and / or CDMA), and provides a modulator (Mod) 814 that provides output chips. In addition. In addition, the transmitter (TMTR) 814 can be tuned to output chips (e.g., convert to analog, amplify, filter, and / or upconvert frequency) and forward link signals Can be generated. This forward link signal can then be routed by duplexer 816 and transmitted by antenna 818.

  In another example, half-duplex terminal 120x can include an antenna 852x that receives forward link signals from one or more base stations, including base station 110. Half-duplex terminal 120x also connects a radio frequency (RF) switch that connects antenna 852x to receiver (RCVR) 856x during forward link frames and antenna 852x to transmitter 866x during reverse link frames Can include 854x.

  Additionally and / or alternatively, full-duplex terminal 120y may include an antenna 852y that receives forward link signals from one or more base stations including base station 110. The full-duplex terminal 120y may also include a duplexer 854y that sends the received signal from the antenna 852y to the receiver 856y and further sends the reverse link signal from the transmitter 866y to the antenna 852y.

  Further, each terminal 120x and 120y conditions (eg, filters, amplifies, frequency downconverts, and / or digitizes) the received signal from antenna 852, and provides a receiver 856 that provides samples. Can be included. Terminals 120x and 120y may include a demodulator (Demod) 856 that performs demodulation on the samples (eg, for OFDMA and / or CDMA) and provides symbol estimates. Receive (RX) data and signal processor 858 also processes symbol evaluation (e.g., symbolizes, demaps, deinterleaves, and / or decodes) and receives the decoded data. Terminals 120x and 120y may be included to supply the device and to the controller / processor 870 to provide detected signals (eg, assignment, ACK, PC command, erase indicator ...). According to one aspect, at base station 110, processing by RX data and signal processor 858 and demodulator 856 is complementary to processing by TX data and signal processor 812 and modulator 814, respectively.

  In the reverse link, the TX data and signal processor 864 at each terminal 120x and 120y can process traffic data from the data transmitter 862 and signals from the controller / processor 870 and generate symbols. . The symbols can then be modulated by modulator 866 and adjusted by transmitter 866 to generate a reverse link signal. The reverse link signal can then be routed through the RF switch 854x and transmitted by the antenna 852x at the terminal 120x and / or routed through the duplexer 854y and transmitted by the antenna 852y at the terminal 120x. . At base station 110, reverse link signals from one or more terminals including terminals 120x and / or 120y are received by antenna 818, routed through duplexer 816, conditioned by receiver 820, and demodulator 820. Demodulated and processed by RX data and signal processor 822. In one example, RX data and signal processor 822 can provide decoded data to data receiver 824 and a sensed signal to controller / processor 830.

  According to one aspect, controllers / processors 830, 870x and 870y can direct the operation of various processing units and operations at base station 110 and terminal 120x, respectively. In one example, the controller / processor 830 can perform the methods 900, 1000, 1100, and / or other suitable methods. Additionally and / or alternatively, the controller / processor 870 may perform the methods 900, 1000 and / or other suitable methods. According to another aspect, memories 832, 872x and 872y can store data and program codes for base station 110 and terminals 120x and 120y, respectively. Further, scheduler 834 can schedule terminals that communicate with base station 110 and allocate resources (eg, data channels, frames, and / or subcarriers) to the scheduled terminals.

  FIG. 9 is a block diagram of a system 900 that coordinates half-duplex communication in an asynchronously operating wireless communication system in accordance with various aspects described herein. In one example, system 900 includes a base station or access point 902. As illustrated, the access point 902 receives signals from one or more access terminals 904 via a receive (Rx) antenna 906 and one or more user equipment 904 via a transmit (Tx) antenna 908. Can be sent to.

  Further, the access point 902 can comprise a receiver 910 that receives information from the receive antenna 906. In one example, the receiver 910 can be operatively associated with a demodulator (Demod) 912 that demodulates received information. Demodulated symbols can be analyzed by processor 914. The processor 914 may be coupled to a memory 916 that may store information related to code clusters, access terminal assignments, related lookup tables, unique scrambling sequences, and / or other suitable types of information. Additionally and / or alternatively, the processor 914 can be coupled to an interlacing component 922, which can be coupled to a transmission timeline (e.g., forward link transmission timeline 310 and reverse link transmission timeline 320). Heavy interlace generation and / or assignment of one or more access terminals 904 to one or more half-duplex interlaces can be facilitated. In one example, the access point 902 can use the interlacing component 922 to perform the method 600 and / or other similar and suitable methods with the processor 914 or independently. Access point 902 can also include a modulator 918 that can multiplex a signal for transmission by transmitter 920 via transmit antenna 908 to one or more access terminals 904.

  FIG. 10 is a block diagram of a system 1000 that coordinates half-duplex communication in an asynchronously operating wireless communication system in accordance with various aspects described herein. In one example, system 1000 includes an access terminal 1002. As illustrated, access terminal 1002 can receive signals from one or more access points 1004 and transmit to one or more base stations 1004 via antenna 1008. In one example, the RF switch 1006 controls whether the antenna is operable to receive or transmit data at a given time.

  Further, access terminal 1002 can comprise a receiver 1010 that receives information from antenna 1008. In one example, receiver 1010 can be operatively associated with a demodulator (Demod) 1012 that demodulates received information. Demodulated symbols can be analyzed by processor 1014. The processor 1014 can be coupled to a memory 1016 that can store data and / or program code associated with the access terminal 1002. Additionally and / or alternatively, processor 1014 can be coupled to an interlacing component 1022 that can facilitate assignment of access terminal 1002 to a half-duplex interlace. In one example, the access terminal 1002 can use the interlacing component 1022 to perform the method 700 and / or other similar and suitable methods with or independently of the processor 1014. Access terminal 1002 can also include a modulator 1018 that can multiplex a signal for transmission by a transmitter 1020 through antenna 1008 to one or more access points 1004.

  FIG. 11 illustrates an apparatus 1100 that facilitates half-duplex communication with a wireless terminal (eg, terminal 220 in system 200). It should be appreciated that the block is represented as including a functional block that can be a functional block that represents a function implemented by a processor, software, or combination thereof (eg, firmware). Apparatus 1100 can be implemented in a base station (e.g., base station 210) and / or other suitable network entity, and can transmit a transmission timeline (e.g., superframe structure 500) with one preamble and a predetermined Forward link superframe with an odd number of frames (e.g. forward link superframe 515) and reverse link superframe with a predetermined odd number of frames 1102 (e.g. reverse link superframe 525) Modules for dividing can be included. Further, apparatus 1100 includes a module for assigning forward link frames and reverse link frames to one of a plurality of half-duplex interlaces 1104, and for associating a wireless terminal with half-duplex interlace 1106. A module for establishing communication with the wireless terminal using an acquisition pilot or other signal 1108, and a module for communicating with the wireless terminal using an associated half-duplex interlaced 1110 frame. Can do.

  FIG. 12 illustrates an apparatus 1200 that facilitates half-duplex communication with one or more asynchronous wireless access points (eg, base station 210 in system 200). It should be appreciated that the block is represented as including a functional block that can be a functional block representing a function implemented by a processor, software, or combination thereof (eg, firmware). Apparatus 1200 can be implemented with a terminal (eg, terminal 220) and / or another suitable network entity and can communicate with an access point based on acquisition pilots and / or other signals from access point 1202. Modules for establishing can be included. In addition, apparatus 1200 includes a module for associating with a half-duplex interlace for communication with an access point on forward and reverse link superframes having a constant odd number of frames 1204, and associated half-frames. Module for communicating with access points using duplex interlaced 1206 forward and reverse link frames and acquisition pilot and / or others in associated half duplex interlaced 1208 forward link frames And a module for detecting other signals from other access points.

  It should be appreciated that the embodiments described herein may be implemented by hardware, software, firmware, middleware, microcode, or any combination thereof. If the system and / or method is implemented in software, firmware, middleware or microcode, program code or code segments, they may be stored on a machine-readable medium such as a storage component. A code segment may represent any combination of procedures, functions, subprograms, programs, routines, subroutines, modules, packaged software, classes or instructions, data structures or program statements. A code segment may be coupled to another code segment or a hardware circuit by sending and / or receiving information, data, arguments, parameters, or memory contents. Information, arguments, parameters, data, etc. are passed, forwarded or transmitted using any suitable means including memory sharing, message passing, token passing, network transmission, etc. Also good.

  For software implementation, the techniques described herein may be implemented with modules (eg, procedures, functions, etc.) that perform the functions described herein. The software code may be stored in a memory device and executed by a processor. The memory device may be implemented within the processor or external to the processor, where it may be communicatively coupled to the processor by various means known in the art.

  What has been described above includes examples of one or more embodiments. Of course, it is not possible to describe all possible combinations of components or methods for the purpose of describing the foregoing embodiments, but many other combinations and permutations of various embodiments are possible. One skilled in the art can recognize this. Accordingly, the described embodiments are intended to embrace all such alterations, modifications and variations that fall within the spirit and scope of the appended claims. Further, to the extent that the term “comprising” is used in either the detailed description or in the claims, the term is similar to what is interpreted when the term “comprising” is used as a transition term in the claims. Intended to be comprehensive. Further, the term “or” as used in the detailed description or claims means “non-exclusive or”.

This application claims the benefit of U.S. Provisional Application No. 60 / 843,892 filed on September 11, 2006 and U.S. Application No. 11 / 848,842, filed on August 31, 2007, in its entirety. Is hereby incorporated by reference.
The description corresponding to claim 1-41 filed at the time of filing this application is shown as appendix 1-41.
Appendix 1
A method of providing half-duplex communication in the presence of an asynchronous sector in a wireless communication system including:
Splitting the transmission timeline on the forward and reverse links into superframes with a fixed odd number of frames;
Assigning each frame in the superframe on the forward and reverse links to one of the first half-duplex interlace and the second half-duplex interlace;
Associating the terminal with one or more half-duplex interlaces;
And communicating with the terminal using a frame assigned to the one or more half-duplex interlaces associated with the terminal.
Appendix 2
In the method of Appendix 1, assigning each of the frames is:
Every other frame in each forward link superframe and every other frame in each reverse link superframe was assigned to the first half-duplex interlace and to the first half-duplex interlace Assigning such that the frame is non-overlapping;
And allocating a frame in each forward link superframe and a reverse link superframe that is not allocated to the half-duplex interlace to the second half-duplex interlace.
Appendix 3
In the method of supplementary note 1, dividing the transmission timeline includes dividing the transmission timeline on the forward and reverse links into superframes having 25 frames.
Appendix 4
In the method of appendix 1, communicating with the terminal includes establishing communication with the terminal at least in part by transmitting one or more acquisition pilots to the terminal.
Appendix 5
In the method of method 4, the dividing the transmission timeline includes dividing a transmission timeline on the forward line into a superframe having a superframe preamble and a fixed odd number of frames, And establishing communication with the terminal includes transmitting one or more acquisition pilots on the forward link in a superframe preamble.
Appendix 6
In the method of appendix 1, the wireless communication system is a frequency division duplex (FDD) communication system, the forward link is associated with a first frequency channel, and the reverse link is a second frequency channel. Associated with.
Appendix 7
In the method of Appendix 6, communicating with the terminal includes:
Sending one or more data and signals over the first frequency channel in a forward link frame assigned to the one or more half-duplex interlaces associated with the terminal;
And receiving one or more data and signals over the second frequency channel in a reverse link frame assigned to the one or more half-duplex interlaces associated with the terminal. .
Appendix 8
Wireless communication devices including:
A memory for storing data relating to the first half-duplex interlace and the first half-duplex interlace, the first half-duplex interlace and the second half-duplex interlace having a predetermined odd number of frames; Having a frame allocated between a link and a reverse link, the forward link and the reverse link being staggered between the first half duplex interlace and the second half duplex interlace;
And a processor configured to associate the access terminal with a half-duplex interlace and to communicate with the access terminal using the associated half-duplex interlaced frame.
Appendix 9
In the wireless communication apparatus of appendix 8, the frames in the case superframe on the forward link and the reverse link are in contact with each other.
Appendix 10
In the wireless communication device of appendix 8, between frames in each superframe on the forward link and reverse link to allow the access terminal sufficient time to switch between transmission and transmission or between reception and transmission Is given a guard time.
Appendix 11
In the wireless communication device of appendix 8, each superframe on the forward link and the reverse link has a length of 25 frames.
Appendix 12
The wireless communication device of appendix 8, wherein the processor is further configured to establish communication with the access terminal by communicating an acquisition pilot to the access terminal.
Appendix 13
The wireless communication device according to appendix 8, wherein the memory stores data related to a loading level of the first half-duplex interlace and the second half-duplex interlace, and wherein the processor Further configured to associate the access terminal with a half-duplex interlace based at least in part on the level.
Appendix 14
An apparatus that facilitates half-duplex communication in a wireless communication system that operates asynchronously,
For forward and reverse links provided by a set of superframes such that a given frame position in a superframe alternates between forward and reverse link communications for a given half-duplex interlace Means for dividing the frame between a first half-duplex interlace and a second half-duplex interlace;
Means for determining one or more half-duplex interlaces for communication with a wireless terminal.
Appendix 15
The apparatus of claim 14, wherein the set of superframes includes one or more forward link superframes and one or more reverse link superframes, wherein the one or more forward links The superframe and one or more reverse link superframes include a predetermined odd number of frames.
Appendix 16
In the apparatus of appendix 15, the means for dividing the frame is:
Means for allocating alternating frames in the one or more forward link superframes and non-overlapping frames in the one or more reverse link superframes to the first half-duplex interlace;
And means for allocating the remaining frames in the one or more forward link superframes and the one or more reverse link superframes to the second half-duplex interlace.
Addendum 17
The apparatus of appendix 14, further comprising means for transmitting information to the wireless terminal to establish communication with the wireless terminal via the one or more half-duplex interlaces determined for communication.
Addendum 18
The apparatus of claim 17, further comprising communicating with the wireless terminal in the one or more half-duplex interlaced frames determined for communication.
Addendum 19
A computer readable medium comprising:
Code for causing a computer to divide the transmission timeline for the forward and reverse links into superframes having a fixed odd number of frames;
And code for causing the computer to assign a frame in each superframe to one of the plurality of half-duplex interlaces such that the frames are staggered between the half-duplex interlaces.
Appendix 20
The code for causing the computer to divide the transmission timeline in the computer-readable medium of appendix 19 causes the computer to divide the transmission timeline for the forward link and the reverse link into a superframe having 25 frames. Including kotodo.
Appendix 21
The computer-readable medium of appendix 19, wherein the plurality of half-duplex interlaces includes a first half-duplex interlace and a second half-duplex interlace.
Appendix 22
Code for causing a computer to determine one or more half-duplex interlaces for use from the plurality of half-duplex interlaces;
The computer-readable code of appendix 19, further comprising code for causing a computer to communicate using one or more half-duplex interlaced frames determined for use on the forward link and the reverse link Possible medium.
Appendix 23
The computer readable medium of appendix 22, wherein the code for causing the computer to communicate includes a code for causing the computer to communicate on the forward link using the first frequency channel and a second frequency channel for the computer. Code for communicating on the reverse link.
Appendix 24
An integrated circuit that executes computer-executable instructions for supporting half-duplex communication in a wireless communication system in the presence of an asynchronous access point, the instructions comprising:
Splitting the transmit timeline for the forward link into superframe preambles and each superframe having a fixed odd number of frames;
Splitting the transmission timeline for the reverse link into superframes having a fixed odd number of frames;
And assigning each frame in the forward frame and the superframe on the reverse link to one of a first half-duplex interlace and a second half-duplex interlace.
Appendix 25
In the integrated circuit of appendix 24, the instruction is
Assigning terminals to one or more of the first half-duplex interlace and the second half-duplex interlace;
And communicating with the terminal on the forward link and the reverse link on frames assigned to the one or more associated half-duplex interlaces.
Addendum 26
A method of half-duplex communication with an asynchronously operating sector in a wireless communication system, comprising:
1 of the first half-duplex interlace and the second half-duplex interlace for communication with the first sector on each superframe for the forward and reverse links with a fixed odd number of frames Associated with one or more, the first half-duplex interlace and the second half-duplex interlace are assigned to non-overlapping frames in each superframe;
Communicating with the first sector in the one or more associated half-duplex interlaced frames;
And attempting to detect a second sector on the forward link in the one or more associated half-duplex interlaced frames.
Addendum 27
Appendix 26. The method of appendix 26, wherein one or more of the first half duplex interlace and the second half duplex interlace is associated with each superframe for a forward link and a reverse link having 25 frames. Including associating with one or more of a first half-duplex interlace and a second half-duplex interlace for communication above.
Addendum 28
The method of claim 26, wherein communicating with the first sector includes communicating with the first sector, at least in part, by detecting one or more acquisition pilots from the first sector. Including establishing.
Addendum 29
The method of appendix 26, wherein the wireless communication system is a frequency division duplex (FDD) communication system, the forward link is associated with a first frequency channel, and the reverse link is associated with a second frequency channel. Is done.
Addendum 30
In the method of appendix 29, communicating with the first sector includes:
Receiving one or more of data and signals by the first frequency channel on the forward link in one or more frames of the associated half-duplex interlace;
And transmitting one or more of data and signals over the second frequency channel on the reverse link in one or more frames of the associated half-duplex interlace. Including.
Addendum 31
The method of claim 26, wherein attempting to detect the second sector includes obtaining an pilot from the second sector on the forward link in the one or more associated half-duplex interlaced frames. Including trying to detect.
Addendum 32
For communication with the first access point on each superframe for forward and reverse links with non-overlapping frames in each superframe assigned to a predetermined odd number of frames and half-duplex interlaces A memory for storing data relating to half-duplex interlacing;
A second frame on the forward link configured to communicate with the first access point using a frame assigned to the half-duplex interlace and assigned to the half-duplex interlace; And a processor configured to detect one or more acquisition pilots from the access point.
Addendum 33
The wireless communication device of attachment 32, wherein each superframe for the forward link and the reverse link includes 25 frames.
Addendum 34
The wireless communication apparatus of attachment 33, wherein each superframe for the forward link further includes a superframe preamble.
Addendum 35
The wireless communication apparatus of appendix 34, wherein the processor is at least in part by detecting one or more acquisition pilots transmitted by the first access point on the forward link in a superframe preamble. And is further configured to initialize communication with the first access point.
Addendum 36
An apparatus that facilitates half-duplex communication in a wireless communication system in the presence of an asynchronous base station,
Means for associating with a half-duplex interlace selected from a plurality of half-duplex interlaces for communication with a serving base station, each half-duplex interlace having a respective odd number of frames; Contains frames for the forward and reverse links allocated from the frame;
Means for communicating with a serving base station using the associated half-duplex interlaced frame;
An apparatus comprising means for detecting information transmitted from an asynchronous base station using the associated half-duplex interlaced frame for the forward link.
Addendum 37
In the apparatus of appendix 36, each of the super frames includes 25 frames.
Addendum 38
The apparatus of claim 36, wherein the plurality of half-duplex interlaces includes a first half-duplex interlace and a second half-duplex interlace.
Addendum 39
With code for causing a computer to establish communication with only one sector in a wireless communication system;
Code comprising and causing the computer to receive an assignment for a half-duplex interlace for communication with the first sector selected from a first half-duplex interlace and a second half-duplex interlace Half-duplex interlace includes frames for the forward and reverse links allocated from each superframe with a fixed odd number of frames,
Code for causing a computer to communicate with the first sector using the allocated half-duplex interlaced frame;
And by searching for one or more acquisition pilots transmitted by the second sector, at least in part, using the associated half-duplex interlaced frame, a second on the forward link. A computer readable medium comprising code for causing a computer to attempt to detect a sector.
Appendix 40
An integrated circuit that executes computer-executable instructions for half-duplex communication in the presence of an asynchronous sector in a wireless communication system, wherein the instructions are:
Associated with one or more of the first half-duplex interlace and the second half-duplex interlace for communication with the first sector, the first half-duplex interlace and the first half-duplex Two half-duplex interlaces are provided by a set of superframes divided such that a given frame position in a superframe alternates between forward and reverse link communications for a given half-duplex interlace. Includes frames for the forward and reverse links;
Communicating with the first sector on one or more of the forward link and the reverse link using the one or more associated half-duplex interlaced frames;
And searching for an acquisition pilot transmitted by a second sector on the forward link using the one or more associated half-duplex interlaced frames.
Appendix 41
In the integrated circuit of appendix 40, each superframe in the set of superframes includes an odd number of frames.

Claims (41)

A method for providing half-duplex communication when an asynchronous sector is present in a wireless communication system operating in asynchronous mode, comprising:
Splitting the transmission timeline on the forward and reverse links into superframes having a fixed odd number of frames;
Assigning each frame in the superframe on the forward and reverse links to one of a first half-duplex interlace and a second half-duplex interlace , wherein the first half-duplex interlace and The second half-duplex interlace has frames allocated between a forward link and a reverse link having a predetermined odd number of frames, the forward link and the reverse link being in the first half-duplex. Staggered between the double interlace and the second half-duplex interlace ;
It is associated to the terminal to one or more half-duplex interlaces based on communication capabilities of the terminal;
And communicating with the terminal using a frame assigned to the one or more half-duplex interlaces associated with the terminal;
Including a method . The method of claim 1, wherein assigning each frame is:
Every other frame in each forward link superframe and every other frame in each reverse link superframe was assigned to the first half-duplex interlace and to the first half-duplex interlace Assigning such that the frame is non-overlapping;
And allocating a frame in each forward link superframe and a reverse link superframe that is not allocated to the half-duplex interlace to the second half-duplex interlace.   2. The method of claim 1, wherein dividing the transmission timeline includes dividing the transmission timeline on the forward link and reverse link into superframes having 25 frames.   2. The method of claim 1, wherein communicating with the terminal includes establishing communication with the terminal at least in part by transmitting one or more acquisition pilots to the terminal.   5. The method of claim 4, wherein dividing the transmission timeline includes dividing the transmission timeline on the forward line into a superframe having a superframe preamble and a constant odd number of frames. And establishing communication with the terminal includes transmitting one or more acquisition pilots on the forward link in a superframe preamble.   2. The method of claim 1, wherein the wireless communication system is a frequency division duplex (FDD) communication system, the forward link is associated with a first frequency channel, and the reverse link is a second frequency. Associated with the channel. 7. The method of claim 6, wherein communicating with the terminal is:
Sending one or more data and signals over the first frequency channel in a forward link frame assigned to the one or more half-duplex interlaces associated with the terminal;
And receiving one or more data and signals over the second frequency channel in a reverse link frame assigned to the one or more half-duplex interlaces associated with the terminal. . A memory for storing data relating to the first half-duplex interlace and the first half-duplex interlace, the first half-duplex interlace and the second half-duplex interlace having a predetermined odd number of frames; Having a frame allocated between a link and a reverse link, the forward link and the reverse link being staggered between the first half duplex interlace and the second half duplex interlace;
And a processor configured to associate the access terminal with a half-duplex interlace and communicate with the access terminal using the associated half-duplex interlaced frame ;
A wireless communication device comprising: The wireless communication device according to claim 8, wherein the frames in each superframe on the forward link and reverse link are adjacent to each other. 9. The wireless communication device of claim 8, wherein a frame in each superframe on the forward link and reverse link to allow the access terminal sufficient time to switch between transmission and reception or between reception and transmission. A guard time is given in between.   9. The wireless communication apparatus according to claim 8, wherein each of the superframes on the forward link and the reverse link is 25 frames in length.   9. The wireless communication apparatus of claim 8, wherein the processor is further configured to establish communication with the access terminal by communicating an acquisition pilot to the access terminal.   9. The wireless communications apparatus of claim 8, wherein the memory stores data related to loading levels of the first half-duplex interlace and the second half-duplex interlace, and wherein the processor stores the loading. • further configured to associate the access terminal with a half-duplex interlace based at least in part on the level; An apparatus that facilitates half-duplex communication in a wireless communication system that operates asynchronously,
For forward and reverse links provided by a set of superframes such that a given frame position in a superframe alternates between forward and reverse link communications for a given half-duplex interlace Means for dividing the frame between a first half-duplex interlace and a second half-duplex interlace;
Means for determining one or more half-duplex interlaces for communication with a wireless terminal.   15. The apparatus of claim 14, wherein the set of superframes includes one or more forward link superframes and one or more reverse link superframes, and the one or more forward link superframes. The link superframe and the one or more reverse link superframes include a predetermined odd number of frames. 16. The apparatus of claim 15, wherein the means for dividing the frame is:
Means for allocating alternating frames in the one or more forward link superframes and non-overlapping frames in the one or more reverse link superframes to the first half-duplex interlace;
And means for allocating the remaining frames in the one or more forward link superframes and the one or more reverse link superframes to the second half-duplex interlace.   15. The apparatus of claim 14, further comprising means for transmitting information to the wireless terminal to establish communication with the wireless terminal over the one or more half-duplex interlaces determined for communication.   18. The apparatus of claim 17, further comprising communicating with the wireless terminal in the one or more half-duplex interlaced frames determined for communication. Code for causing a computer to divide the transmission timeline for the forward and reverse links into superframes having a fixed odd number of frames;
And code for causing the computer to assign a frame in each superframe to one of the plurality of half-duplex interlaces such that the frame is staggered between the half-duplex interlaces ;
A computer readable medium comprising:   21. The computer readable medium of claim 19, wherein the code for causing the computer to divide a transmission timeline causes the computer to divide the transmission timeline for the forward link and the reverse link into superframes having 25 frames. Including kotodo for.   20. The computer readable medium of claim 19, wherein the plurality of half duplex interlaces includes a first half duplex interlace and a second half duplex interlace. Code for causing a computer to determine one or more half-duplex interlaces for use from the plurality of half-duplex interlaces;
20. The computer of claim 19, further comprising code for causing a computer to communicate using one or more half-duplex interlaced frames determined for use on the forward link and the reverse link. A readable medium.   23. The computer readable medium of claim 22, wherein the code for causing the computer to communicate includes code for causing the computer to communicate on a forward link using a first frequency channel, and for causing the computer to include a second frequency channel. And a code for communicating on the reverse link. An integrated circuit that executes computer-executable instructions for supporting half-duplex communication when an asynchronous access point is present in a wireless communication system operating in asynchronous mode, the instructions being:
Splitting the transmit timeline for the forward link into superframe preambles and each superframe having a fixed odd number of frames;
Splitting the transmission timeline for the reverse link into superframes having a fixed odd number of frames;
And assigning each frame in the forward frame and the superframe on the reverse link to one of a first half-duplex interlace and a second half-duplex interlace. 25. The integrated circuit of claim 24, wherein the instructions are
Assigning terminals to one or more of the first half-duplex interlace and the second half-duplex interlace;
And communicating with the terminal on the forward link and the reverse link on frames assigned to the one or more associated half-duplex interlaces. A method of half-duplex communication with an asynchronous sector in a wireless communication system operating in asynchronous mode ,
1 of the first half-duplex interlace and the second half-duplex interlace for communication with the first sector on each superframe for the forward and reverse links with a fixed odd number of frames Associated with one or more, the first half-duplex interlace and the second half-duplex interlace are assigned to non-overlapping frames in each superframe;
Communicating with the first sector in the one or more associated half-duplex interlaced frames;
And attempting to detect a second sector on the forward link in the one or more associated half-duplex interlaced frames. 27. The method of claim 26, wherein one or more of the first half duplex interlace and the second half duplex interlace is associated with each of a forward link and a reverse link having 25 frames. Including associating with one or more of the first and second half-duplex interlaces for communication on the superframe.   27. The method of claim 26, wherein communicating with the first sector is at least partially with the first sector by detecting one or more acquisition pilots from the first sector. Including establishing communications.   27. The method of claim 26, wherein the wireless communication system is a frequency division duplex (FDD) communication system, the forward link is associated with a first frequency channel, and the reverse link is a second frequency channel. Related. 30. The method of claim 29, wherein communicating with the first sector is:
Receiving one or more of data and signals by the first frequency channel on the forward link in one or more frames of the associated half-duplex interlace;
And transmitting one or more of data and signals over the second frequency channel on the reverse link in one or more frames of the associated half-duplex interlace. Including.   27. The method of claim 26, wherein attempting to detect the second sector is acquired pilot from the second sector on the forward link in the one or more associated half-duplex interlaced frames. Including trying to detect. For communication with the first access point on each superframe for forward and reverse links with non-overlapping frames in each superframe assigned to a predetermined odd number of frames and half-duplex interlaces A memory for storing data relating to half-duplex interlacing;
A second frame on the forward link configured to communicate with the first access point using a frame assigned to the half-duplex interlace and assigned to the half-duplex interlace; And a processor configured to detect one or more acquisition pilots from the access point.   33. The wireless communication apparatus of claim 32, wherein each superframe for the forward link and the reverse link includes 25 frames.   34. The wireless communication apparatus of claim 33, wherein each superframe for the forward link further includes a superframe preamble.   35. The wireless communications apparatus of claim 34, wherein the processor is at least in part by detecting one or more acquisition pilots transmitted by the first access point on the forward link in a superframe preamble. In particular, it is further configured to initialize communication with the first access point. An apparatus that facilitates half-duplex communication when an asynchronous base station is present in a wireless communication system operating in asynchronous mode ,
Means for associating with a half-duplex interlace selected from a plurality of half-duplex interlaces for communication with a serving base station, each half-duplex interlace having a respective odd number of frames; Contains frames for the forward and reverse links allocated from the frame;
Means for communicating with a serving base station using the associated half-duplex interlaced frame;
An apparatus comprising means for detecting information transmitted from an asynchronous base station using the associated half-duplex interlaced frame for the forward link.   38. The apparatus of claim 36, wherein each superframe comprises 25 frames.   37. The apparatus of claim 36, wherein the plurality of half duplex interlaces includes a first half duplex interlace and a second half duplex interlace. Code for causing a computer to establish communication with a first sector in a wireless communication system operating in an asynchronous mode ;
Code comprising and causing the computer to receive an assignment for a half-duplex interlace for communication with the first sector selected from a first half-duplex interlace and a second half-duplex interlace Half-duplex interlace includes frames for the forward and reverse links allocated from each superframe with a fixed odd number of frames,
Code for causing a computer to communicate with the first sector using the allocated half-duplex interlaced frame;
And by searching for one or more acquisition pilots transmitted by the second sector, at least in part, using the associated half-duplex interlaced frame, a second on the forward link. A computer readable medium comprising code for causing a computer to attempt to detect a sector. An integrated circuit that executes computer-executable instructions for half-duplex communication when an asynchronous sector is present in a wireless communication system operating in asynchronous mode, the instructions being:
Associated with one or more of the first half-duplex interlace and the second half-duplex interlace for communication with the first sector, the first half-duplex interlace and the first half-duplex Two half-duplex interlaces are provided by a set of superframes divided such that a given frame position in a superframe alternates between forward and reverse link communications for a given half-duplex interlace. Includes frames for the forward and reverse links;
Communicating with the first sector on one or more of the forward link and the reverse link using the one or more associated half-duplex interlaced frames;
And searching for an acquisition pilot transmitted by a second sector on the forward link using the one or more associated half-duplex interlaced frames. 41. The integrated circuit of claim 40, wherein each superframe in the set of superframes comprises an odd number of frames.

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