JP4916785B2 - Semiconductor memory device and electronic device equipped with the same - Google Patents

Description

  The present invention relates to a semiconductor memory device and an electronic apparatus including the same. More specifically, the present invention relates to a semiconductor memory device in which memory cells each including a field effect transistor including a memory portion having a function of holding electric charge are arranged, and an electronic apparatus including the semiconductor memory device.

  Conventionally, a virtual ground array structure has been proposed as a memory cell array structure in which nonvolatile memory cells are arranged at high density.

  In the semiconductor memory device having this virtual ground array structure, bit lines electrically connected to the source / drain regions of adjacent memory cells are shared. Therefore, the number of bit lines can be greatly reduced as compared with the case where each memory cell column has an electrically independent bit line. Therefore, when the wiring pitch of the bit lines greatly affects the area of the nonvolatile memory cell array, it is possible to achieve a significant area reduction by adopting the virtual ground array structure.

  However, in the memory cell array constituting the virtual ground array structure, when programming a memory cell, the memory portion of the adjacent memory cell is slightly programmed during the program operation, and the memory state of the memory portion of the adjacent memory cell is changed. There was a problem of change.

  As a method for eliminating the influence on adjacent memory cells during such a program operation, for example, a method disclosed in Japanese Patent Application Laid-Open No. 3-176895 has been proposed.

  Hereinafter, the method of the program described in Patent Document 1 will be described with reference to FIG.

  FIG. 9 shows an EPROM (erasable programmable read only memory) circuit configured with a virtual ground array structure.

  For example, when information is programmed in the memory cell 73m5, 12V is applied to the word line 71w2 connected to the control gate of the memory cell 73m5, 0V is applied to the bit line 72b6 via the transistor 75s3, and the transistor is applied to the bit line 72b5. 7V is applied through 75s2.

  At this time, in order to prevent the programming to the adjacent memory cells 73m6 and 73m4, 0V is applied to the bit lines 72b7, 72b8 and 72b9, and 7V is applied to the bit lines 72b1, 72b2, 72b3 and 72b4, respectively.

  That is, when programming the selected memory cell 73m5, all the bit lines 72b6, 72b7, 72b8, 72b9 on the source side of the selected memory cell 73m5 are grounded, and all the bits on the drain side of the selected memory cell 73m5 are grounded. A program potential is applied to the lines 72b1, 72b2, 72b3, 72b4, 72b5.

Although not shown in the figure, by providing a pass gate between adjacent bit lines and turning on the pass gate provided between the bit lines that need to be equipotential, the potential between the bit lines can be equalized with higher accuracy. It is also possible to prevent misprogramming due to a time lag when applying a potential.
Japanese Patent Laid-Open No. 3-176895

  However, in the method shown in FIG. 9, it is possible to suppress the influence on the adjacent cells to the minimum. However, in the memory cell array configured by the virtual ground array structure, in order to reduce the area of the memory array, the memory array is serially connected. As the number of connected memory cells increases, the number of bit lines that need to be charged / discharged only to eliminate the influence of adjacent cells, regardless of the program operation, is increased. There has been a problem that power consumption due to charging and discharging of the wires increases.

  In addition, when providing pass gates between adjacent bit lines, the control lines for controlling the pass gates must be electrically independent of each other. However, as the number of memory cells connected in series increases, In addition, the number of independent control lines increases, and there is a problem that the circuit area of the pass gate increases in the semiconductor memory device.

  Therefore, an object of the present invention is to reduce the power consumption caused by the charge / discharge of the bit line even when the number of memory cells connected in series is increased, and to suppress the increase in circuit area as compared with the prior art. It is an object of the present invention to provide a semiconductor memory device having a virtual ground array structure that can be used.

In order to solve the above problems, a semiconductor memory device of the present invention provides:
A plurality of memory cells each consisting of a field effect transistor share a word line, and the memory cell has a virtual ground array structure sharing a bit line with an adjacent memory cell; and
A controller for programming in parallel at least two memory cells sharing the word line ;
Multiple control lines;
Multiple pass gates of the same polarity each consisting of a field effect transistor and
With
For each of the control lines, at least two gate electrodes of the pass gates are connected, and the pass gates are respectively connected between adjacent bit lines,
The control unit turns off the pass gate connected between the bit lines on both sides of each of the at least two memory cells to be programmed, while the control unit connects the bit lines on both sides of the memory cells that should not be programmed. The potential of the control line is controlled so that the pass gate is turned on .

  According to the above invention, in the memory cell array configured by the virtual ground array structure, the control unit programs at least two memory cells sharing the word line in parallel. The number of bit lines to be performed can be reduced, and the power consumption due to charging / discharging of the bit lines during the program operation can be greatly reduced.

According to the invention , the control unit controls the potential of the control line to turn off the pass gate connected between the bit lines on both sides of each of the at least two memory cells to be programmed. since turn on the connected the pass gate between the two sides of the bit lines of the memory cells which should not be, the potential between the bit line connected to memory cells not to be programmed equal Tsu coercive high precision, giving a potential It is possible to prevent erroneous programming due to a time lag at the time.

  In addition, since at least two gate electrodes of the same polarity pass gate are connected to each control line, the number of control lines with respect to the total number of pass gates can be reduced, and the area of the semiconductor memory device can be reduced. Can do.

In one embodiment,
In the memory cell array, m (m is an integer, m ≧ 4) stages of memory cells are connected in series,
The control unit programs the kth memory cell and the {n + (k−1)} th memory cell in parallel (where n and k are integers, 1 ≦ k <n <m, and , N + (k−1) ≦ m).

  According to the above embodiment, the k-th (k = 1, 2, 3,..., (N−1)) memory cell and the {n + (k−1)}-th memory cell are always Between them, [{n + (k−1)} − k−1] = (n−2) memory cells, that is, a fixed (n−2) number of memory cells, in parallel, And it can be programmed regularly. Therefore, the program can be systematically arranged and control becomes easy.

  Further, when the on / off state of the pass gate is controlled by controlling the potential of the control line by the control unit, the balance of the number of bit lines to be charged / discharged can be relatively improved.

In one embodiment,
In the memory cell array, m (m is an integer, m ≧ 4) stages of memory cells are connected in series,
The control unit programs the (n−k) th memory cell and the {n + (k−1)} th memory cell in parallel (where n and k are integers, 1 ≦ k <n). <M and n + (k−1) ≦ m).

  According to the embodiment, the (n−k) th memory cell and the {n + (k−1)} th memory cell are programmed in parallel.

  At this time, as k = 1, 2, 3,... (N−1), between the {n + (k−1)} th memory cell and the (n−k) th memory cell. , [{N + (k−1)} − (n−k) −1] = (2k−2) memory cells. Therefore, the programs can be systematically ordered, and control of the programs becomes easy.

In one embodiment,
The memory cell
A gate electrode formed on the semiconductor layer via a gate insulating film;
A channel region disposed under the gate electrode via the gate insulating film,
A diffusion region disposed on both sides of the channel region and having a conductivity type opposite to that of the channel region;
A memory function body which is formed on both sides of the gate electrode and has a function of holding charge or polarization;

  In the above embodiment, the memory cell is similar in structure to a transistor element generally used in a logic circuit as compared with a conventional EPROM or flash memory which is a typical nonvolatile memory. And the logic circuit part have the advantage that the mixed mounting process is simple.

  In addition, the memory cell has an advantage that the gate insulating film can be easily thinned and thus can be easily miniaturized.

In one embodiment,
The memory cell
A semiconductor layer;
A gate electrode;
A composite gate insulating film provided between the semiconductor layer and the gate electrode;
A channel region disposed under the gate electrode via the composite gate insulating film;
A first diffusion region and a second diffusion region disposed on both sides of the channel region and having a conductivity type opposite to that of the channel region;
The composite gate insulating film is
A first insulating film in contact with the gate electrode;
A third insulating film in contact with the channel region;
A second insulating film between the first insulating film and the third insulating film,
The second insulating film is
A first storage region located above the boundary between the first diffusion region and the channel region;
A second storage region located above a boundary between the second diffusion region and the channel region.

  According to the embodiment, since the first storage area and the second storage area of the memory cell are located above the boundary between the channel area and the diffusion area, the first and second storage areas The advantage is that the current difference due to the amount of the stored charge is large and the speed of writing and erasing is fast.

  In addition, since the shape of the second insulating film in which the first and second storage areas are formed is simple, there is little variation in manufacturing the second insulating film and the first and second storage areas. There is little variation in the characteristics of the memory cell due to the variation during the manufacture.

  In addition, since the electronic device of the present invention includes the above-described semiconductor memory device, power consumption due to charging / discharging of the bit line can be reduced.

  In addition, the electronic device of the present invention has the advantage of being small and compact because the circuit area of the semiconductor memory device can be reduced.

  Here, the electronic device refers to a portable information terminal such as a cellular phone, a portable audio device, a portable video device, a DVD, a television, and the like.

  According to the present invention, in a memory cell array having a virtual ground array structure, even if the number of memory cells connected in series is increased, at least two memory cells are programmed in parallel by the control unit. It is possible to reduce power consumption due to the above.

Further, according to this onset bright, so connecting the gate electrodes of a plurality of pass gates to the same control line, compared to the number of pass gates, by reducing the number of control lines, it is possible to reduce the circuit area .

  FIG. 1A shows a cross-sectional view of an embodiment of a memory element which is a memory cell included in a semiconductor memory device of the present invention.

  In the memory element shown in FIG. 1A, a gate electrode 11 is formed on a P-type well region 14 formed on the surface of a semiconductor substrate via a gate insulating film 13. The side surfaces of the gate electrode 11 have memory function bodies 12a and 12b that actually retain charges or polarization by a rewrite operation. N-type diffusion regions 15a and 15b functioning as a source region or a drain region are formed on both sides of the gate electrode 11 and in the P-type well region 14, respectively. The diffusion regions 15a and 15b have an offset structure. That is, the diffusion regions 15a and 15b do not reach the region under the gate electrode 11, and the offset regions under the memory function bodies 12a and 12b constitute a part of the channel region.

  As the holding film having a function of holding charge or polarization in the memory function bodies 12a and 12b, a silicon nitride film, a ferroelectric film, or the like can be used. Although the memory function bodies 12a and 12b are configured not to be shown in order to hold charges or polarization for a longer period, the upper and lower sides of the holding film may be covered with an insulating film typified by a silicon oxide film. For example, when a silicon nitride film is used as a holding film having a function of holding charges, the memory function bodies 12a and 12b may have a three-layer structure of silicon oxide film-silicon nitride film-silicon oxide film.

  Further, as another configuration example of the memory function bodies 12a and 12b, the memory function bodies 12a and 12b may have a structure in which fine particles made of a nanometer-sized conductor or semiconductor are distributed in a dotted pattern in the insulating film.

  The memory function bodies 12a and 12b are not limited to the above-described configuration, and may have other configurations as long as they have a function of holding charge or polarization.

  Hereinafter, a program (write) operation of the memory cell shown in FIG. 1A will be described. Here, the case where the entire memory function bodies 12a and 12b have a function of holding charges will be described. The program (write) refers to injecting electrons into the memory function bodies 12a and 12b when the memory cell is an N-channel type. Hereinafter, description will be made assuming that the memory element is an N-channel type.

  In order to program by injecting electrons into the memory function body 12b, the N type diffusion region 15a is used as a source electrode and the N type diffusion region 15b is used as a drain electrode. For example, 0V is applied to the diffusion region 15a and the P-type well region 14, + 5V is applied to the diffusion region 15b, and + 5V is applied to the gate electrode 11.

  Under such a voltage condition, the inversion layer extends from the diffusion region 15a (source electrode), but a pinch-off point is generated without reaching the diffusion region 15b (drain electrode). The electrons are accelerated by a high electric field from the pinch-off point to the diffusion region 15b (drain electrode) and become so-called hot electrons (high energy conduction electrons). Writing is performed by injecting the hot electrons into the memory function body 12b. Note that no writing is performed in the vicinity of the memory function body 12a because hot electrons are not generated.

  On the other hand, in order to program by injecting electrons into the memory function body 12a, the diffusion region 15b is used as a source electrode and the diffusion region 15a is used as a drain electrode. For example, 0V is applied to the diffusion region 15b and the P-type well region 14, + 5V is applied to the diffusion region 15a, and + 5V is applied to the gate electrode 11.

  Thus, the case of injecting electrons into the memory function body 12b means that the program can be performed by injecting electrons into the memory function body 12a by switching the source / drain regions.

  Next, the erase operation will be described.

  In order to erase the information stored in the memory function body 12a, a positive voltage (for example, + 5V) is applied to the diffusion region 15a and 0V is applied to the P-type well region 14, so that the diffusion region 15a and the P-type well region 14 are applied. And a negative voltage (for example, −5 V) is applied to the gate electrode 11. At this time, in the vicinity of the gate electrode 11 in the PN junction, the potential gradient is particularly steep due to the influence of the gate electrode to which a negative voltage is applied. Therefore, hot holes (high energy holes) are generated on the P-type well region 14 side of the PN junction due to the band-to-band tunnel. This hot hole is drawn toward the gate electrode 11 having a negative potential, and as a result, hole injection is performed in the memory function body 12a. In this way, the memory function body 12a is erased. At this time, 0 V may be applied to the diffusion region 15b.

  When erasing the information stored in the memory function body 12b, the potentials of the diffusion region 15a and the diffusion region 51b may be switched in the above.

  Next, a method for reading the information stored as described above will be described.

  When reading the information stored in the memory function body 12a, the memory cell is operated using the diffusion region 15a as a source electrode and the diffusion region 15b as a drain electrode. For example, 0V is applied to the diffusion region 15a and the P-type well region 14, + 1.8V is applied to the diffusion region 15b, and + 2V is applied to the gate electrode 11. At this time, if electrons are not accumulated in the memory function body 12a, a drain current tends to flow. On the other hand, when electrons are accumulated in the first memory function body 12a, the inversion layer is not easily formed in the vicinity of the memory function body 12a, and therefore, the drain current hardly flows. Therefore, the storage information of the memory function body 12a can be read by detecting the drain current. At this time, the presence or absence of charge accumulation in the memory function body 12b does not greatly affect the drain current because the vicinity of the drain is pinched off.

  On the other hand, when reading the information stored in the memory function body 12b, the memory cell is operated using the diffusion region 15b as a source electrode and the diffusion region 15a as a drain electrode. For example, 0V may be applied to the diffusion region 15b and the P-type well region 14, + 1.8V may be applied to the diffusion region 15a, and + 2V may be applied to the gate electrode 11.

  As described above, when the information stored in the memory function body 12a is read, the information stored in the memory function body 12b can be read by switching the source / drain regions.

  As described above, it is possible to store and read 2 bits per memory cell by switching the source electrode and the drain electrode.

  Since the memory cell shown in FIG. 1A is similar in structure to a transistor element generally used in a logic circuit as compared with a conventional EPROM or flash memory which is a typical nonvolatile memory, the memory cell and the logic cell There is an advantage that the mixed mounting process with the circuit unit is simple.

  In addition, the gate insulating film can be easily reduced in thickness and can be easily miniaturized.

  Note that the symbol shown in FIG. 1B is used as the circuit symbol of the memory cell shown in FIG. 1A.

  FIG. 2A shows another embodiment of a memory cell, that is, a memory element included in the semiconductor memory device of the present invention.

  In the memory element shown in FIG. 2A, a gate electrode 21 is formed on a P-type well region 25 formed on the surface of a semiconductor substrate via a gate insulating film 28. N-type diffusion regions 26 a and 26 b functioning as a source region or a drain region are formed on both sides of the gate electrode 21 and in the P-type well region 25.

  The gate insulating film 28 includes a first insulating film 22, a second insulating film 23, and a third insulating film 24. Further, the second insulating film 23 is a storage region 27a and 27b above the boundary between the P-type well region 25 forming the channel region and the diffusion regions 26a and 26b as a region for further holding charges. have.

  As the second insulating film 23, a silicon nitride film or the like can be used as a film that has a function of holding charges and hardly causes interference between the storage regions 27a and 27b. Note that the second insulating film 23 is not limited to the above structure, and may be formed of a film that has a function of holding charges and hardly causes interference of the storage region.

  The program operation of the memory cell shown in FIG. 2A will be described below.

  In order to program by injecting electrons into the storage region 27b, the N type diffusion region 26a is used as a source electrode, and the N type diffusion region 26b is used as a drain electrode. For example, 0V is applied to the diffusion region 26a and the P-type well region 25, + 4.5V is applied to the diffusion region 26b, and + 9V is applied to the gate electrode 21.

  According to such a voltage condition, hot electrons are generated in the boundary region between the channel region formed in the P-type well region 25 and the diffusion region 26b, and the hot electrons are injected into the storage region 27b. Writing is performed. Note that no writing is performed in the vicinity of the storage area 27a because hot electrons are not generated.

  On the other hand, in order to program by injecting electrons into the storage region 27a, the diffusion region 26b is used as a source electrode and the diffusion region 26a is used as a drain electrode. For example, 0V is applied to the diffusion region 26b and the P-type well region 25, + 4.5V is applied to the diffusion region 26a, and + 9V is applied to the gate electrode 21.

  As described above, in the case of injecting electrons into the storage region 27b, the program can be performed by injecting electrons into the storage region 27a by switching the source / drain regions.

  Next, the erase operation will be described.

  In order to erase the information stored in the storage region 27a, a positive voltage (for example, + 5.5V) is applied to the diffusion region 26a, and 0V is applied to the P-type well region 25, so that the diffusion region 26a and the P-type well region are applied. A reverse bias is applied to the PN junction with 25 and a negative voltage (for example, −8 V) is applied to the gate electrode 21. At this time, in the vicinity of the gate electrode 21 in the PN junction, the potential gradient is particularly steep due to the influence of the gate electrode to which a negative voltage is applied. Therefore, a hot hole is generated on the P-type well region 25 side of the PN junction due to the band-to-band tunnel. This hot hole is drawn in the direction of the gate electrode 21 having a negative potential, and as a result, hole injection is performed in the storage region 27a. In this way, the storage area 27a is erased. At this time, 0 V may be applied to the diffusion region 27b.

  When erasing the information stored in the storage area 27b, the potentials of the diffusion area 26a and the diffusion area 26b may be switched in the above.

  Next, a method for reading the information stored as described above will be described.

  When reading the information stored in the storage area 27a, the memory cell is operated using the diffusion area 26a as a source electrode and the diffusion area 26b as a drain electrode. For example, 0V is applied to the diffusion region 26a and the P-type well region 25, + 2.0V is applied to the diffusion region 26b, and + 3V is applied to the gate electrode 21. At this time, if electrons are not accumulated in the storage area 27a, a drain current tends to flow. On the other hand, when electrons are accumulated in the first storage area 27a, an inversion layer is hardly formed in the vicinity of the storage area 27a, so that a drain current hardly flows. Therefore, the storage information in the storage area 27a can be read by detecting the drain current. At this time, the presence or absence of charge accumulation in the storage region 27b does not significantly affect the drain current because the vicinity of the drain is pinched off.

  When reading the information stored in the storage area 27b, the memory cell is operated by using the diffusion area 26b as a source electrode and the diffusion area 26a as a drain electrode. For example, 0V may be applied to the diffusion region 26b and the P-type well region 25, + 2V to the diffusion region 26a, and + 3V to the gate electrode 21.

  As described above, when the information stored in the storage area 27a is read out, the information stored in the storage area 27b can be read out by switching the source / drain areas.

  As described above, it is possible to store and read 2 bits per memory cell by switching the source electrode and the drain electrode.

  In the memory cell shown in FIG. 2A, that is, the memory element, the storage regions 27a and 27b are formed immediately above the boundary between the channel region formed in the P-type well region 25 and the diffusion regions 26a and 26b. And the current difference due to the large amount of charges stored in 27b is large, and the writing / erasing speed is also fast.

  Further, since the shape of the insulating film 23 in which the memory regions 27a and 27b are formed is simple, there is little variation in element characteristics due to manufacturing variations in the insulating film 23 in which the memory regions 27a and 27b are formed.

  2B is used as the circuit symbol of the memory cell shown in FIG. 2A.

  The voltage applied to each terminal during the program / erase / read operations of the memory element shown in FIGS. 1A and 2A is not limited to the above-described values, and may be higher or lower. .

  Hereinafter, the case where the memory element shown in FIGS. 1A and 1B is used as the memory element included in the semiconductor memory device of the present invention will be described. However, the memory elements shown in FIGS. 2A and 2B may be used as the memory elements regardless of the memory elements shown in FIGS. 1A and 1B. The memory device shown in FIGS. 1A and 1B and the memory device shown in FIGS. 2A and 2B are similar in the method of writing / erasing / reading. The reference number 11 of the gate electrode is 21 and the reference number 15a of the diffusion region is 26a. In addition, the memory element shown in FIGS. 1A and 1B can be easily replaced with the memory element shown in FIGS. 2A and 2B by replacing the reference number 15b of the diffusion region with 26b and optimizing the voltage applied during each operation. It becomes.

  Note that the present invention may use other memory elements regardless of the memory elements shown in FIGS. 1A and 2A. For example, it is also possible to use an EPROM or flash memory that stores information in the floating gate indicated by reference numbers 73m1 to 73m8 in FIG.

(Embodiment 1)
FIG. 3 shows Embodiment 1 of the semiconductor memory device of the present invention.

  As shown in FIG. 3, the memory cells 33m1, 33m2, 33m3,..., 33m8 constituting the virtual ground array structure share the word line 31w2, and the memory cells 33m1, 33m2, 33m3,. Bit lines 32b2, 32b3, 32b4, 32b5, 32b6, 32b7, and 32b8 are shared with adjacent memory cells.

  The memory cells 33m1, 33m2, 33m3,..., 33m8 have memory function bodies 33m1l, 33m2l, 33m3l,..., 33m8l on the left side of the gate electrode, and 33m1r, 33m2r, memory function bodies on the right side of the gate electrode. 33m3r, ..., 33m8r.

  Further, between adjacent bit lines 32b1, 32b2, 32b3, 32b4, 32b5, 32b6, 32b7, 32b8, 32b9, transistors 35p1, 35p2, 35p3 as pass gates for short-circuiting adjacent bit lines as necessary. ..., 35p8 is provided. The transistors 35p1, 35p2, 35p3,..., 35p8 as the pass gates correspond to the memory cells 33m1, 33m2, 33m3,.

  The gates of the transistors 35p1 and 35p5 are connected to the same control line 34s4. The gates of the transistors 35p2 and 35p6 are connected to the same control line 34s3, the gates of the transistors 35p3 and 35p7 are connected to the same control line 34s2, and the gates of the transistors 35p4 and 35p8 are the same. It is connected to the control line 34s1.

  That is, k = 1, 2, 3,... (N−1) corresponds to the gate electrode of the transistor corresponding to the kth memory cell and the {n + (k−1)} th memory cell. The gate electrode of the transistor is connected to the same control line.

  Further, when the control unit 100 programs the kth memory cell and the {n + (k−1)} th memory cell in parallel, the gate electrode of the transistor as the pass gate corresponding to the memory cell is connected. The control line is controlled to a low potential so that both the transistors are turned off and the other transistors are turned on.

  By doing this, when the kth memory cell and the {n + (k−1)} th memory cell are programmed in parallel, always [{n + (k−1)} − between them. k−1] = (n−2) memory cells, that is, a fixed (n−2) number of memory cells are sandwiched, and can be programmed in parallel and regularly. . Therefore, the program can be systematically arranged so that the control becomes easy.

  Further, as described above, the control unit 100 controls the potential of the control line, thereby controlling the on / off state of the transistor as the pass gate to relatively improve the balance of the number of bit lines to be charged / discharged.

  In addition to the potentials of the control lines 34 s 1, 34 s 2, 34 s 3, 34 s 4, the control unit 100 includes the word lines 31 w 1, 31 w 2, 31 w 3 and bit lines 32 b 1, 32 b 2, 32 b 3, 32 b 4, 32 b 5, 32 b 6, 32 b 7, 32 b 8 By controlling the potential of 32b9 as described later, two memory cells can be programmed in parallel.

  The program method will be described in detail below.

  In the first embodiment, two memory cells among the memory cells 33m1, 33m2, 33m3,..., 33m8 that constitute the virtual ground array structure during the program operation by the control unit 100, and the same control line 34s1. , 34 s 2, 34 s 3, 34 s 4, each of the two transistors 35 p 1, 35 p 5; 35 p 2, 35 p 6; 35 p 3, 35 p 7; Program.

  In FIG. 3, memory function bodies 33m1r and 33m5l; memory function bodies 33m1l and 33m5r; memory function bodies 33m2r and 33m6l; memory function bodies 33m2l and 33m6r; memory function bodies 33m3r and 33m7l; memory function bodies 33m3l and 35m7r; And 33m8l; the memory function bodies 33m4l and 33m8r can be programmed in parallel.

  For example, when programming the memory function bodies 33m1l and 33m5r in parallel, the control unit 100 applies 5V to the word line 31w2, 5V to the bit lines 32b1, 32b6 to 32b9, and 0V to the bit lines 32b2 to 32b5.

  Further, at this time, the control unit 100 sets the control line 34s4 to the low level to turn off the transistors 35p1 and 35p5, while setting the control lines 34s3, 34s2, and 34s1 to the high level to set the transistors 35p2, 35p6; 35p3. , 35p7; 35p4, 35p8 are turned on. In this way, by setting the transistors 35p1 and 35p5 sharing the control line 34s4 to the off state and the transistors 32b2 to 32b4 and 32b6 to 32b8 to the on state, erroneous programming due to a time lag when applying the potential is performed. It is preventing.

  When only the memory function body 33m1l is programmed and the memory function body 33m5r remains in the erased state, 5V is applied to the word line 31w2, 5V is applied to the bit line 32b1, and 0V is applied to the bit lines 32b2 to 32b9.

  When only the memory function body 33m5r is programmed and the memory function body 35m1l is left in the erased state, 5V is applied to the word line 31w2, 5V is applied to the bit lines 32b6 to 32b9, and 0V is applied to the bit lines 32b1 to 32b5. .

  FIG. 7 shows a correspondence between memory function bodies for performing programming and program data, and voltages applied to the bit lines 32b1, 32b2, 32b3,..., 32b9 and the control lines 34s1, 34s2, and 34s3.

  In FIG. 7, data “1” indicates an erase state, and data “0” indicates a program state. Therefore, for example, programming the data “10” to the memory function bodies 33m11 to 33m5r means that the memory function body 33m11 maintains the erased state without programming and only the memory function body 33m5r is programmed.

  In addition, regarding the voltage applied to the bit lines 32b1, 32b2, 32b3,..., 32b9, the “H” level is the voltage applied to the drain electrode of the memory cell to be programmed (5 V in this embodiment), and the “L” level is the program. The voltage applied to the source electrode of the memory cell that performs (0 V in the present embodiment), and the applied voltage to the control lines 34s1, 34s2, and 34s3, the “H” level is the voltage that turns on the transistor as the pass gate, The “L” level indicates a voltage that turns off a transistor as a pass gate.

  As described above, when programming the memory cells 33m1, 33m2, 33m3,..., 33m8 in the memory cell array configured by the virtual ground array structure, the memory cell array shares two word lines 31w1, 31w2, or 31w3. Since the memory cells are programmed in parallel, the bit lines 32b1, 32b2, 32b3, 32b4, 32b5, 32b6, 32b7, 32b8, and 32b9 are charged and discharged during the programming operation in the memory cell array configured by the virtual ground array structure. Can be reduced per memory cell, and power consumption due to charging / discharging of the bit line during a program operation can be reduced.

  Each of the two memory cells 33m1, 33m5; 33m2, 33m6; 33m3, 33m7; 33m4, 33m8 includes two transistors 35p1, 35p5; 35p2, 35p6; 35p3, 35p7; 35p4 connected to the respective bit lines. , 35p8, and the gate electrodes of the transistors 35p1, 35p5; 35p2, 35p6; 35p3, 35p7; 35p4, 35p8 as the two pass gates are electrically connected to the same control lines 34s4, 34s3, 34s2, 34s1, respectively. Since they are connected, the area for the control lines 34s4, 34s3, 34s2, and 34s1 of the transistors 35p1, 35p5; 35p2, 35p6; 35p3, 35p7; Can fence, it is possible to provide a small semiconductor memory device in area.

  Note that the control unit 100 may perform reading and erasing control in addition to program control.

  In the above-described example, the number of stages of memory cells connected in series is eight. However, the number is not limited to this, and may be smaller or larger than this.

  FIG. 4 shows an example in which the number of memory cells connected in series is sixteen.

  4, the memory cells 53m1, 53m2, 53m3,..., 53m16 have memory function bodies 53m1l, 53m2l, 53m3l,..., 53m16l located on the left side of the gate, and the right side of the gate. 53m1r, 53m2r, 53m3r,..., 53m16r.

  Between the adjacent bit lines 52b1, 52b2, 52b3,..., 52b17, transistors 55p1, 55p2, 55p3,..., 55p16 are provided as pass gates for short-circuiting the adjacent bit lines as necessary. . The gates of the transistors 55p1 and 55p9 are connected to the same control line 54s8, and the gates of the transistors 55p2 and 55p10 are connected to the same control line 54s7. Similarly, the gates of the two transistors 55p3, 55p11; 55p4, 55p12; 55p5, 55p13; 55p6, 55p14; 55p7, 55p15; 55p8, 55p16 are connected to the same control line 54s6, 54s5, 54s4, 54s3, 54s2, 54s1, respectively. It is connected.

  Also in FIG. 4, for example, when programming in parallel in the memory function bodies 53m1l and 53m9r, although not shown, 5V is applied to the word line 51w2 and 5V is applied to the bit lines 52b1, 52b10 to 52b17 by a control unit similar to FIG. 0V is applied to each of the lines 52b2 to 52b9.

  At this time, the transistors 55p1 and 55p9 sharing the control line 54s8 are turned off, and the transistors 55p2 to 55p9 and 55p11 to 55p16 are turned on, thereby preventing erroneous programming due to a time lag when applying a potential. It becomes possible to do.

  When only the memory function body 53m1l is programmed and the memory function body 53m1r remains in the erased state, 5V is applied to the word line 31w2, 5V is applied to the bit line 32b1, and 0V is applied to the bit lines 32b2 to 32b17.

  Further, when only the memory function body 53m9r is programmed and the memory function body 53m9l is left in the erased state, 5V is applied to the word line 31w2, 5V is applied to the bit lines 32b10 to 32b17, and 0V is applied to the bit lines 32b1 to 32b9. .

(Embodiment 2)
FIG. 5 shows a second embodiment of the semiconductor memory device of the present invention.

  The memory cells 43m1, 43m2, 43m3,..., 43m8 constituting the virtual ground array structure share the word line 41w2, and each of the memory cells 43m1, 43m2, 43m3,. 42b2, 42b3, 42b4,..., 42b8 are shared.

  The memory cells 43m1, 43m2, 43m3,..., 43m8 have a memory function body 43m1l, 43m2l, 43m3l,..., 43m8l located on the left side of the gate electrode and a memory function body 43m1r on the right side of the gate electrode, respectively. 43m2r, 43m3r,..., 43m8r.

  Further, between the adjacent bit lines 42b1, 42b2, 42b3,..., 42b9, transistors 45p1, 45p2, 45p3, 45p3 as pass gates for short-circuiting the bit lines 42b1, 42b2, 42b3,. ..., 45p8 is provided.

  A control unit (not shown) is configured so that (n−k) th memory cell and {n + (k−1)} th memory cell are programmed in parallel, where n and k are integers and 1 ≦ k <n. Control. [{N + (k−1)} − (n−k) −1] = between the {n + (k−1)} th memory cell and the (n−k) th memory cell. The program can be systematically ordered so that (2k-2) memory cells exist, so that control of the program is facilitated.

  The program method is described below.

  In the second embodiment of FIG. 5, the memory function bodies 43m1r and 43m8l; the memory function bodies 43m1l and 43m8r; the memory function bodies 43m2r and 43m7l; the memory function bodies 43m2l and 43m7r; the memory function bodies 43m3r and 43m6l; Memory function bodies 43m4r and 43m5l; the memory function bodies 43m4l and 43m5r can be programmed in parallel.

  For example, when programming in parallel in the memory function bodies 43m1l and 43m8r, 5V is applied to the word line 41w2, 5V is applied to the bit lines 42b1 and 42b9, and 0V is applied to the bit lines 42b2 to 42b8, respectively.

  At this time, by the control of the control unit, the transistors 45p1 and 45p8 sharing the control line 44s4 are turned off, and the transistors 42b2 to 42b7 are turned on, thereby causing an error due to a time lag in applying a potential. Try to prevent the program.

  When only the memory function body 43m1l is programmed and the memory function body 43m8r is left in the erased state, the control unit controls the 5V to the word line 31w2, 5V to the bit line 42b1, and the bit lines 42b2 to 32b9. Apply 0V respectively.

  Further, when only the memory function body 43m8r is programmed and the memory function body 43m1l is left in the erased state, the control unit controls the word line 41w2 to 5V, the bit line 42b9 to 5V, and the bit lines 42b1 to 42b8 to Apply 0V respectively.

  FIG. 8 shows a correspondence between memory function bodies for performing programming and program data, and voltages applied to the bit lines 42b1, 42b2, 42b3,..., 42b9 and the control lines 44s1, 44s2, and 44s3.

  As in FIG. 7, in FIG. 8, data “1” indicates an erased state, and data “0” indicates a programmed state. Therefore, for example, programming the data “10” to the memory function bodies 43m11 to 43m8r means that the memory function body 43m11 maintains the erased state without programming and only programs the memory function body 43m8r.

  As for the voltages applied to the bit lines 42b1, 42b2, 42b3,..., 42b9, the “H” level is the voltage applied to the drain electrode of the memory cell to be programmed (5 V in this embodiment), and the “L” level is the program. The voltage applied to the source electrode of the memory cell that performs (0 V in the present embodiment), and the voltage applied to the control lines 44s1, 44s2, and 44s3 is the voltage that turns on the transistor as the pass gate, The “L” level indicates a voltage that turns off a transistor as a pass gate.

(Embodiment 3)
A mobile phone which is an example of a mobile electronic device in which the semiconductor memory device of Embodiment 1 or 2 described above is incorporated is shown in FIG.

  This cellular phone includes a display unit 61, a ROM (read only memory) 62, a RAM (random access memory) 63, a control circuit 64, an antenna 65, a radio circuit 66, a power circuit 67, an audio circuit 68, a camera module 69, a memory card. 70.

  Among these, the ROM 62 is built in the mobile phone shown in FIG. 6 and is nonvolatile and rewritable. Program data for operating the control circuit and images taken by the camera module 69 are included. Data such as data and audio data to be reproduced by the audio circuit 68 is stored.

  The data may be stored in the memory card 70. Similar to the ROM 62, the memory card 70 has non-volatility and is rewritable. The memory card 70 is further detachable, and plays a role such as backup of the data, data transfer to other devices, and storage of data that cannot be stored in the ROM 62.

  The ROM 62 and the memory card 70 send stored data to the control circuit 64 when requested by the control circuit 64. The data read from the ROM 62 and the memory card 70 is also transferred to the RAM 63 as necessary.

  In recent years, the capacity of control programs and the amount of data to be stored have increased dramatically with the increase in the number of functions of mobile phones. For this reason, the ROM 62 and the memory card 70 are increasingly required to have a large capacity.

  In addition, in order to increase the duration of the battery included in the power supply circuit 67, there is an increasing demand for low power consumption.

  For this reason, a non-volatile memory having a large capacity and low power consumption has been demanded.

  The semiconductor memory device of the first or second embodiment is used for the ROM 62 and the memory card 70. As a result, the ROM 62 and the memory card 70 have lower power consumption than the conventional one, and have a large capacity and a small size.

  In particular, by using the memory element shown in FIG. 1A as a memory cell of a semiconductor memory device, a semiconductor memory device having a simple and inexpensive mixed process of a memory portion and a logic circuit portion can be obtained. A portable electronic device with low power consumption can be obtained at low cost.

It is sectional drawing of the memory cell in the semiconductor memory device of this invention. It is a circuit symbol of the memory cell. It is sectional drawing of the memory cell in the semiconductor memory device of this invention. It is a circuit symbol of the memory cell. 1 is a circuit diagram of an embodiment of a semiconductor memory device of the present invention. 1 is a circuit diagram of an embodiment of a semiconductor memory device of the present invention. 1 is a circuit diagram of an embodiment of a semiconductor memory device of the present invention. It is a schematic block diagram of the portable electronic device incorporating the semiconductor memory device of this invention. It is a figure which shows the correspondence of the memory function body and program data which perform the program in embodiment of FIG. 3, and the applied voltage to a bit line and a control line. FIG. 6 is a diagram illustrating a correspondence relationship between a memory function body and program data for performing programming in the embodiment of FIG. 5 and applied voltages to bit lines and control lines. It is a circuit diagram of a conventional semiconductor memory device.

Explanation of symbols

33m1-33m8, 43m1-43m8, 53m1-53m16 Memory cell 14, 25 P-type well region 13 Gate insulating film 28 Composite gate insulating film 11, 21 Gate electrode 15a, 15b, 26a, 26b Diffusion region 12a, 12b Memory function body 27a 27b Storage area 31w1-31w3, 41w1-41w3, 51w1-51w3 Word line 32b1-32b9, 42b1-42b3, 52b1-52b9 Bit line 100 Control unit

Claims (6)

A plurality of memory cells each consisting of a field effect transistor share a word line, and the memory cell has a virtual ground array structure sharing a bit line with an adjacent memory cell; and
A controller for programming in parallel at least two memory cells sharing the word line ;
Multiple control lines;
Multiple pass gates of the same polarity each consisting of a field effect transistor and
With
For each of the control lines, at least two gate electrodes of the pass gates are connected, and the pass gates are respectively connected between adjacent bit lines,
The control unit turns off the pass gate connected between the bit lines on both sides of each of the at least two memory cells to be programmed, while the control unit connects the bit lines on both sides of the memory cells that should not be programmed. A semiconductor memory device, wherein the potential of the control line is controlled so that a pass gate is turned on . The semiconductor memory device according to claim 1 ,
In the memory cell array, m (m is an integer, m ≧ 4) stages of memory cells are connected in series,
The control unit programs the kth memory cell and the {n + (k−1)} th memory cell in parallel (where n and k are integers, 1 ≦ k <n <m, and , N + (k−1) ≦≦ m)
A semiconductor memory device. The semiconductor memory device according to claim 1 ,
In the memory cell array, m (m is an integer, m ≧ 4) stages of memory cells are connected in series,
The control unit programs the (n−k) th memory cell and the {n + (k−1)} th memory cell in parallel (where n and k are integers, 1 ≦ k <n). <M and n + (k−1) ≦ m)
A semiconductor memory device. The semiconductor memory device according to claim 1 ,
The memory cell
A gate electrode formed on the semiconductor layer via a gate insulating film;
A channel region disposed under the gate electrode via the gate insulating film,
A diffusion region disposed on both sides of the channel region and having a conductivity type opposite to that of the channel region;
A semiconductor memory device comprising: a memory function body formed on both sides of the gate electrode and having a function of holding charge or polarization. The semiconductor memory device according to claim 1 ,
The memory cell
A semiconductor layer;
A gate electrode;
A composite gate insulating film provided between the semiconductor layer and the gate electrode;
A channel region disposed under the gate electrode via the composite gate insulating film;
A first diffusion region and a second diffusion region disposed on both sides of the channel region and having a conductivity type opposite to that of the channel region;
The composite gate insulating film is
A first insulating film in contact with the gate electrode;
A third insulating film in contact with the channel region;
A second insulating film between the first insulating film and the third insulating film,
The second insulating film is
A first storage region located above the boundary between the first diffusion region and the channel region;
A semiconductor memory device comprising: a second storage region located above a boundary between the second diffusion region and the channel region. An electronic apparatus comprising the semiconductor memory device according to claim 1 .

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