JP4914423B2 - Interconnect structure and logic circuit device - Google Patents

Description

  The present invention provides an interconnect structure for interconnecting external wiring and a logic cell group including a plurality of logic cells (for example, a variable grain logic cell (usually abbreviated as VGLC)), A logic circuit device having an interconnection for interconnecting external wiring and the logic cell group, and a logic circuit device in which a cluster structure is formed by clustering and connecting a plurality of logic circuit devices About.

  More specifically, the present invention reduces the logic resource area and power consumption by reducing the wiring resource overhead of a group of logic cells without significantly reducing the flexibility in expressing a logic function with a plurality of logic cells. A method for realizing power and memory savings will be described.

  In recent years, programmable logic circuit devices have attracted attention as devices that can implement logic circuits that meet various user requirements by electrically programming internal circuits. This programmable logic circuit device is known as PLD (Programmable Logic Device), FPGA (Field Programmable Gate Array), DRP (Dynamically Reconfigurable Processor), or DAP / DNA (Digital Application Processor / Distributed Network Architecture). It is also used to construct a large-scale circuit having various functions by itself, beyond the use for trial manufacture of wear.

  And the programmable logic circuit device is generally called a reconfigurable logic device (Reconfigurable Logic Device: usually abbreviated as RLD).

  RLD (Reconfigurable Logic Device) has a feature that the circuit configuration can be rewritten, and has been used in a wide range of industrial equipment, electronic devices and the like by utilizing this feature. RLDs constituting a conventional programmable logic circuit device are roughly classified into two types, that is, a fine-grain method and a coarse-grain method. The fine-grained method has very high flexibility for input in bit units, and can implement random logic efficiently. On the other hand, the coarse-grain method is suitable for executing byte-unit operations at high speed. However, the granularity method of RLD is usually fixed, and there is a disadvantage that applications suitable for implementation are limited. In order to eliminate such an inconvenient situation, VGLC (granularity variable logic cell) has been proposed as a new reconfigurable logic that replaces a programmable logic circuit device such as a conventional FPGA. Since VGLC is implemented with a granularity that matches the application, performance improvement can be expected.

  However, in the VGLC, the number of input lines and output lines of the logic cell group increases due to the flexibility of the logic function expression of the logic cell, resulting in a problem of wiring resource overhead. In particular, recently, the influence of wiring delay has increased due to miniaturization of the manufacturing process, and the influence of this wiring delay cannot be ignored. For this reason, it is required to reduce logic circuit area, power consumption, memory amount and the like by reducing the overhead of the wiring resources of the logic cell group while maintaining the flexibility of the logic function expression of the logic cell.

  Here, the following Patent Documents 1 to 5 related to the conventional programmable logic circuit device as described above are presented as prior art documents.

  Patent Document 1 discloses a tile-type structure of a field programmable gate array having a direct connection or an indirect connection to an adjacent logic element in a logic cell block. However, in this structure, the logic cell block is fixed to the fine granularity method.

  In Patent Document 2, a plurality of LUTs (Look-up Tables) are clustered as one logic cell block, and a programmable logic integrated circuit device having an interconnection block composed of a crossbar and a multiplexer inside the logic cell block. A connection structure is disclosed. This allows input sharing among a plurality of LUTs, and the number of input lines of the logic cell block is reduced to some extent. However, with this structure, the overhead of wiring resources becomes large while maintaining high flexibility in the logic cell.

  Patent Document 3 discloses an FPGA architecture having an antifuse type FPGA using a macro cell. However, in this architecture, since the switches are arranged at all the intersections in the crossbar, the number of switches increases.

  Patent Document 4 discloses reconfigurable logic in which different circuits are configured by changing signal settings in a reconfigurable logic device (RLD). However, in this reconfigurable logic, no countermeasure is taken against the problem related to the interconnection structure for connecting the external wiring and the logic cell group to each other.

  Patent Document 5 discloses a programmable logic element in which programmable logic elements have a hierarchical structure and an interconnection structure in each hierarchy is formed. In this programmable logic element, the switch arrangement of the interconnect structure in each layer is performed by a pseudo-random method.

  Therefore, in any of Patent Documents 1 to 4, problems similar to those of the conventional programmable logic circuit device described above occur. In Patent Document 5, the switch arrangement method is different from that of the present invention.

JP-T 8-509344 JP 2006-246534 A Special table 2004-517543 gazette JP 2007-166579 A JP-A-10-92943

  The present invention has been made in view of the above-described problems, and reduces the overhead to the wiring resources of the logic cell group without significantly reducing the flexibility in expressing the logic function by a plurality of logic cells. An object of the present invention is to provide an interconnection structure and a logic circuit device capable of reducing the area of the logic circuit, power consumption, memory amount, and the like.

In order to solve the above problems, an interconnect structure in accordance with aspects of the present invention has a cross-connection for connecting the input line of the logic cell group including the external wiring and a plurality of logic cells each other the interconnect part is the external wiring and the connection defining means for defining the interconnection relationship between the input line of the logic cell group, the input lines of the interconnect part of the logic cell group output lines A feedback unit for feeding back to the interconnection unit, and the feedback unit is configured to reduce the number of input lines of the interconnect unit without the need to incorporate a feedback signal from the outside, The number of combinations specified by the connection specifying means is determined in consideration of the target logic function in the logic cell while maintaining flexibility regarding function expression. Configured smaller configuration than all of the number of combinations of input and output can be realized.

  Preferably, in the interconnect structure according to an aspect of the present invention, the number of input lines and the number of output lines of the interconnect portion are arbitrarily set.

  Further preferably, in the interconnect structure according to an aspect of the present invention, the logic cell group is configured by a reconfigurable logic cell (for example, a variable-granularity logic cell in which the granularity of operation by the logic cell is variably set). The

  Further preferably, in the interconnect structure according to an aspect of the present invention, it is possible to reduce the number of input lines of the interconnect portion by clamping a specific input line of the interconnect portion to a predetermined level. It is.

  Further preferably, in the interconnection structure according to an aspect of the present invention, the number of combinations defined by the connection defining means is reduced by selecting a specific function from among the logic functions of the plurality of logic cells. It is possible.

  Further preferably, in the interconnection structure according to an aspect of the present invention, the logic functions of the plurality of logic cells are aggregated into specific logic functions belonging to a group of logic functions that take permutations of different input signals. It is possible to reduce the number of combinations defined by the connection defining means.

  Furthermore, preferably, in the interconnect structure according to an aspect of the present invention, the number of configuration memories in the interconnect portion can be reduced by controlling the on / off operation of the plurality of switches by a decoder circuit. Is possible.

  Further preferably, in the interconnect structure according to an aspect of the present invention, a delay circuit is provided in the subsequent stage of the interconnect portion or the logic cell group.

  Still preferably, in an interconnection structure according to an aspect of the present invention, the delay circuit is configured by a fixed delay element or a variable delay element.

On the other hand, the logic circuit device according to the first aspect of the present invention includes a logic cell group including a plurality of logic cells, and an interconnection unit for mutually connecting an external wiring and an input line of the logic cell group. has the door, the interconnect section, said external wiring and the connection defining means for defining the interconnection relationship between the input line of the logic cell group, the interconnecting portion of the logic cell group output lines A feedback unit for feeding back to the input line of the unit, and the feedback unit is configured to reduce the number of input lines of the interconnection unit without the need for receiving a feedback signal from the outside. The number of combinations defined by the connection defining means is determined in consideration of the function of the target logic among the plurality of logic cells while maintaining flexibility regarding function expression. Configured smaller configuration than all of the number of combinations of input and output connection unit is realized.

  Preferably, in the logic circuit device according to the first aspect of the present invention, the number of input lines and the number of output lines of the interconnection section are arbitrarily set.

  Further preferably, in the logic circuit device according to the first aspect of the present invention, the logic cell group includes a reconfigurable logic cell (for example, a granularity variable logic cell in which a granularity of operation by the logic cell is variably set). Consists of.

  Further preferably, in the logic circuit device according to the first aspect of the present invention, the number of input lines of the interconnecting section is reduced by clamping a specific input line of the interconnecting section to a predetermined level. It is possible.

  Further preferably, in the logic circuit device according to the first aspect of the present invention, the number of combinations defined by the connection defining means by selecting a specific function among the logic functions of the plurality of logic cells. Can be reduced.

  Further preferably, in the logic circuit device according to the first aspect of the present invention, the logic functions of the plurality of logic cells are aggregated into specific logic functions belonging to a group of logic functions taking different permutations of input signals. Thus, it is possible to reduce the number of combinations defined by the connection defining means.

  Further preferably, in the logic circuit device according to the first aspect of the present invention, the number of configuration memories in the interconnect portion is reduced by controlling the on / off operation of the plurality of switches by a decoder circuit. Is possible.

  Further preferably, in the logic circuit device according to the first aspect of the present invention, a delay circuit is provided in the subsequent stage of the interconnector or the logic cell group.

  Further preferably, in the logic circuit device according to the first aspect of the present invention, the delay circuit is configured by a fixed delay element or a variable delay element.

On the other hand, the logic circuit device according to the second aspect of the present invention provides a logic cell group including a plurality of logic cells, an interconnect for connecting an external wiring and an input line of the logic cell group to each other. And a plurality of clusters are connected to each other to form a cluster structure. The interconnections in each of the clusters are connected to the external wiring and the input lines of the logic cell group. A connection defining means for defining an interconnection relationship with each other, and a feedback section for feeding back a part of the output line of the logic cell group in each of the clusters to the input line of the interconnect section. cage, by the feedback unit, there is no need to incorporate a feedback signal from the outside, it is configured so that the number of input lines of the interconnect is reduced, in each of the clusters Taking into account the logical function to be in a definitive said logic cell group of the plurality of logic cells, One One maintaining flexibility in function expressions, less than all of the number of combinations of the upper Symbol interconnect input and output configured such configuration is achieved.

  Preferably, in the logic circuit device according to the second aspect of the present invention, the number of input lines and the number of output lines of the interconnection section in each of the clusters are arbitrarily set.

  Further preferably, in the logic circuit device according to the second aspect of the present invention, the logic cell group in each of the clusters has a reconfigurable logic cell (for example, the granularity of operation by the logic cell is variably set). Variable grain logic cell).

  Further preferably, in the logic circuit device according to the second aspect of the present invention, the input of the interconnect unit is clamped to a predetermined level at a specific input line of the interconnect unit in each of the clusters. It is possible to reduce the number of lines.

  Further preferably, in the logic circuit device according to the second aspect of the present invention, by selecting a specific function from among the logic functions of the plurality of logic cells in the logic cell group in each of the clusters. The number of combinations defined by the connection defining means can be reduced.

  Furthermore, preferably, in the logic circuit device according to the second aspect of the present invention, the logic functions of the plurality of logic cells in each of the clusters are specified as belonging to a group of logic functions taking a permutation of different input signals. By combining the logical functions, it is possible to reduce the number of combinations defined by the connection defining means.

  Further preferably, in the logic circuit device according to the second aspect of the present invention, the interconnection unit is controlled by controlling on / off operations of the plurality of switches by a decoder circuit provided in each of the clusters. It is possible to reduce the number of configuration memories.

  Further preferably, in the logic circuit device according to the second aspect of the present invention, a delay circuit is provided in the subsequent stage of the interconnect section or the logic cell group in each of the clusters.

  In summary, according to the present invention, it is possible to reduce the number of input lines from the external wiring while maintaining flexibility in expressing a logic function by a plurality of logic cells. The total number of tracks can be saved.

  Furthermore, in the present invention, the feedback unit for feeding back a part of the signal on the output side of the logic cell group to the input side eliminates the need to incorporate a feedback signal from the outside, thereby reducing the number of input lines from the external wiring. The Furthermore, the signal propagation using the local wiring of the feedback unit increases the signal propagation speed, thereby increasing the speed of the signal passing through the logic cell group.

  Further, according to the present invention, the number of input lines of the interconnection unit is less than the number of output lines of the interconnection unit, or the number of combinations defined by connection defining means such as a plurality of switches is the input / output of the interconnection unit. Since a configuration smaller than the number of all combinations of the above is realized, the logic circuit area, power consumption, memory amount, etc. can be saved while maintaining the flexibility of expressing the logic function with multiple logic cells. Is possible.

  The configuration and operation of the embodiment of the present invention will be described in detail below with reference to the accompanying drawings (FIGS. 1 to 26).

  FIG. 1 is a block diagram showing an embodiment of an interconnection structure according to the present invention. One embodiment of the interconnection structure of FIG. 1 is a reconfigurable switch group (this book) for mutually connecting a logic cell group 2 having a plurality of logic cells, an external wiring ED and an input line of the logic cell group 2. 1 corresponding to the interconnection section of the invention, and a configuration memory 4 for setting the route of the reconfigurable switch group 1. Further, in the embodiment of FIG. 1, a connection block (hereinafter abbreviated as CB) 5-1 that propagates a signal passing through the external wiring ED to the logic cell group 2, and a signal output from the logic cell group 2 to the outside Other CB5-2 which propagates are provided. On the other hand, in the embodiment of FIG. 1, a feedback unit 3 having a feedback line for feeding back a signal output from the logic cell group 2 to the input side of the reconfigurable switch group 1 is provided.

  Here, the reconfigurable switch group 1 functions as a connection defining means for defining an interconnection relationship between the external wiring ED and the input lines of the logic cell group 2. More specifically, the reconfigurable switch group 1 has a plurality of switches arranged at the intersections of the output line of the CB5-1 and the input line of the logic cell group 2. The number of input wirings of the reconfigurable switch group 1 (herein referred to as “input wirings of the reconfigurable switch group 1” so as not to be confused with the input lines of the logic cell group 2) is l, and the output wiring Similarly, in order not to be confused with the output line of the logic cell group 2, the number of "output wiring of the reconfigurable switch group 1" is m, and the combination of l and m is arbitrary. . Normally, the relationship is l <m (for example, l = 10, m = 21). On the other hand, the number of output lines of the logic cell group 2 is n.

  FIG. 2 is a block diagram showing a specific example of the interconnection structure of FIG. Hereinafter, the same components as those described above are denoted by the same reference numerals.

  In the specific example of FIG. 2, a local connection block (hereinafter abbreviated as LCB) 10 is provided as the reconfigurable switch group 1 of FIG. Further, in the specific example of FIG. 2, a variable granularity logic cell (hereinafter abbreviated as VGLC) 20 is provided as the logic cell group 2. On the other hand, in the specific example of FIG. 2, as the feedback unit 3 of FIG. 1, a signal output from the output line of the VGLC 20 (output wiring OUT on the output side of the LCB 10) is fed back to the input wiring IND on the input side of the LCB 10. A local feedback 30 having a feedback line is provided.

  As shown in FIG. 2, the LCB 10 is mounted between the VGLC 20 and the external wiring ED, and has a role of capturing an input signal having a number smaller than the number of input pins (for example, 21) of the VGLC 20 from outside and propagating it to the VGLC 20. . As a result, the number of tracks of wiring is reduced, and the device (logic circuit device) can be downsized. Further, as described above, the local feedback 30 from the output side of the VGLC 20 to the input side of the LCB 10 is provided. As a result, it is not necessary to pass through the external wiring when the signal output from the VGLC 20 is fed back, so that the propagation delay can be improved and the speed of the device can be improved.

  FIG. 3 is a block diagram showing the overall configuration of the specific example of FIG. In FIG. 3A, one tile 7 is illustrated, and in FIG. 3B, a plurality of tiles 7A are illustrated.

  In FIG. 3A, switch blocks (SB) 6-1 to 6-4 for setting a signal propagation path are added in addition to the LCB 10, VGLC 20, and CB 5-1, 5-2 of FIG. ing. A logic circuit device including the components of the switch blocks 6-1 to 6-4 is defined as one tile 7. A logic circuit device having a structure in which a plurality of tiles are arranged in an array is defined as a plurality of tiles 7A.

  FIG. 4 is a block diagram showing the internal configuration of the LCB. As shown in FIG. 4, the LCB 10 includes a switch unit 11 having a plurality of switches and a control unit that controls the plurality of switches in the switch unit 11. However, for the sake of simplicity, only the switch unit 11 will be focused thereafter. On the other hand, in the subsequent drawings, output lines to the outside of the VGLC are omitted.

  Here, four examples of the LCB network structure applied to the present invention will be described with reference to FIGS.

  FIG. 5 is a circuit block diagram showing an example of an LCB mounting structure when a crossbar is used. The LCB 10a shown in FIG. 5 includes a crossbar 11a using a switch 15a such as an nMOS switch element at each contact point between an input wiring IND (for example, 12 inputs) and an output wiring OUD. The input wiring IND of the LCB 10a is an external wiring composed of the global wiring GD, a feedback line of the VGLC 20a, a power supply line VDD, and a ground line GND. Connection to the external wiring is performed using a CB 50a configured with a full cross bar 51a. As a feedback line of the VGLC 20a, a local feedback 30a from the output side of the VGLC 20a to the input side of the LCB 10a is provided. In the LCB 10a, only one input signal is selected for each input pin of the VGLC 20a. Usually, for example, using a decoder circuit that controls four switches, control is performed so that only a specific switch is turned on. This makes it possible to reduce the number of memories of the configuration memory 4 (see FIG. 1), for example, as compared with the case where individual switches are controlled by individual memories (for example, SRAM (Static Random Access Memory)). Become.

  In FIG. 5, the switches 15a are arranged at all the intersections between the input wiring IND from the CB 50a and the input pins to the VGLC 20a. In this case, since an extremely high flexibility is maintained, an arbitrary route can be set. However, on the other hand, a great deal of circuit resources are required.

  FIG. 6 is a circuit block diagram showing an example of an LCB mounting structure when a multiplexer (MUX) is used. The LCB 10b illustrated in FIG. 5 includes a multiplexer 11b having a switching selection unit 11b for selectively connecting an input wiring IND (for example, 12 inputs) and an output wiring OUD. The input wiring IND of the LCB 10b is an external wiring including the global wiring GD and a feedback line such as the local feedback 30a of the VGLC 20b. Connection to the external wiring is performed using a CB 50b constituted by a full cross bar 51b. In the LCB 10b of FIG. 6, the circuit resource amount is smaller than that in the case of using the crossbar.

  FIG. 7 is a circuit block diagram showing an example of the LCB mounting structure when the Clos network is used. The LCB 10c shown in FIG. 7 includes a Clos network 11c for selectively connecting an input wiring IND (for example, 12 inputs) and an output wiring OUD. The Clos network 11c includes an input unit 13-2 and a switching selection unit 13-2. The input wiring IND of the LCB 10c is a feedback line such as an external wiring including the global wiring GD and a local feedback 30c of the VGLC 20c.

  FIG. 8 is a circuit block diagram illustrating an example of an LCB mounting structure when the Benes network is used. The LCB 10d shown in FIG. 8 includes a Benes network 11d for selectively connecting an input wiring IND (for example, 12 inputs) and an output wiring OUD. The Benes network 11d includes an input unit 14-1, a Benes circuit element 14-2, and a switching selection unit 14-3. The input wiring IND of the LCB 10d is a feedback line such as an external wiring including the global wiring GD and a local feedback 30d of the VGLC 20d.

  FIG. 9 is a circuit block diagram for explaining the state of switch control by the decoder circuit. Reducing the total number of memories for switch control leads to a reduction in the amount of data. Therefore, the switches are controlled by a decoder circuit using AND (logical product) gates to reduce the number of memories. FIG. 9 shows an implementation example in which the decoder circuit 8 using the AND gates 82-1 to 82-4 is applied to an LCB using a crossbar.

  Here, the operation using the switch has been described. However, in reality, even if a combinational logic circuit is used, the same function can be realized, and the appended claims are limited to the example using the switch. Of course not. The same applies to the control units using the switches in the other figures.

  FIG. 9 shows a decoder circuit 8 when four switches are controlled using a memory 80 such as a 2-bit SRAM. The decoder circuit 8 includes two inverters 81-1, 81-2, four AND gates 82-1 to 82-4, switches such as four nMOS switch elements 83-1 to 83-4, and the like. Is a simple structure. The memory value is decoded by the decoder circuit 8, and only one specific switch is turned on. The decoder circuit 8 controls the LCB 10e having a plurality of crossbar switches 15e arranged at the intersections of the input wiring IND and the output wiring OUD (the input line of the VGLC 20e).

  The number of switch stages, the number of used memories, and the number of used transistors (Tr) in the network structure when the LCB of FIGS. 5 to 8 is used and when the decoder circuit is applied to the LCB when the crossbar is used. The comparison results are shown in Table 1 below. However, here, it is assumed that a switch group including a plurality of switches for forming the Benes network and the Clos network is configured by a crossbar and a multiplexer (MUX).

  As apparent from Table 1, when the decoder circuit is applied to the LCB using the crossbar, the number of memories is reduced to about one quarter, but the number of transistors used is doubled. Result. Reducing the number of memories leads to a reduction in power consumption during configuration. Hereinafter, the LCB includes a decoder circuit.

  As described above, when a plurality of switches are arranged at all the intersections of the LCB input wiring and output wiring, very high circuit resources are required while maintaining very high flexibility. Therefore, configuring the plurality of switches in the LCB so that the number of switches is smaller than that in the conventional case is useful for reducing the circuit resources of the LCB. Therefore, the configuration to reduce the number of LCB switches and the influence on the flexibility associated therewith will be examined. In order to reduce the number of switches as compared with the conventional case, it is necessary to consider, for example, how many switches are used and where the switches are arranged. Therefore, in this specification, four approaches for reducing the size of the LCB are illustrated in FIGS. It is assumed that a decoder circuit is used for switch control in the LCB.

  FIG. 10 is a circuit diagram showing the configuration of the switches in the LCB for expressing all of the missenious logic (hereinafter abbreviated as Misc.Logic as necessary).

  Misc. Is one of the functions of VGLC. The Logic mode is a mode in which various logics can be realized using the external variable EV depending on the input method and the setting of the configuration memory. However, Misc. Is capable of expressing various logic functions. There are a considerable number of output logic overlaps in the Logic mode. By omitting some of the switches 15 to eliminate this duplication, the flexibility of the LCB 10 can be reduced to some extent, leading to a reduction in the size of the LCB.

  FIG. 10 shows the arrangement of the plurality of switches 15 of the crossbar of the downsized LCB 10. The number of switches in the LCB 10 is reduced to approximately half. Of particular note is the connection of feedback lines. Unlike FIG. 5 described above, many switches are used to connect the feedback lines. This is to make the flexibility of the external signal and the feedback signal equivalent. Here, w [0], c [0], x [0], y [0], z [0],..., AS, and Shift of the output wiring OUD of the LCB 10 are input to the input pins of the VGLC. Represents various signals.

  Preferably, in each of FIGS. 10 to 14, the two uppermost input wirings of the LCB 10 are fixed to the potential of the power supply voltage and the ground potential (0 V). As a result, the logic of a specific input line of the logic cell group can be clamped to “1” or “0”. By providing the input wiring to the potential of the power supply voltage and the ground potential, it is not necessary to supply the logic level “0” or “1” via the global wiring, and the input to the LCB from the global wiring is reduced. Contributes to lower power consumption by reducing circuit size and wiring.

  FIG. 11 is a circuit diagram showing a configuration of a switch in the LCB considering only the arithmetic operation mode and the random logic mode.

  In FIG. 11, Misc. Without considering the Logic mode at all, the focus is only on the arithmetic operation mode using the external variable EV and the random logic (Canonical Form (CF)) mode, and the flexibility of the LCB 10 is reduced to the limit. . That is, the approach of FIG. 11 is to reduce the number of switches 15 in the LCB 10 by constraining the function of VGLC. In the arithmetic operation mode and the random logic mode, the usage method of the input pin is clearly determined. For this reason, it is not necessary to increase the flexibility of the LCB 10. On the other hand, Misc. In Logic, the method of using each input pin varies greatly depending on the logic implemented. For this reason, it is necessary to increase the flexibility of the LCB 10. Therefore, Misc. By prohibiting the use of the Logic mode, the number of switches in the LCB 10 is reduced. One switch is arranged at each VGLC input pin for external input. The number of feedback switches is further increased than in the case of FIG.

  FIG. 12 is a circuit diagram showing a configuration of a switch in the LCB corresponding to a part of Missius Logic (Misc. Logic).

  In FIG. 10 and FIG. 11 described above, Misc. The LCB structure was introduced when all of Logic was considered and when it was not considered at all. Here, the application is pre-mapped to VGLC and used in Misc. Take Logic statistics. Based on this statistical result, frequently used Misc. The structure of the LCB 10 having a plurality of switches 15 is determined so that only Logic can be handled.

  The approach of FIG. 12 is different from the approach of FIG. Allows implementation of some logic in Logic mode. As the logic that enables implementation, the logic frequently used for application implementation is adopted.

  The approach of FIG. 12 is not as functional as VGLC compared to the approach of FIG. 10 described above, but is higher than the approach of FIG. In the LCB 10 of FIG. 12, several switches are added to the LCB of FIG. 11 described above. The number of feedback switches in FIG. 12 is the same as that in FIG.

  FIG. 13 is a circuit diagram showing the configuration of the switch element in the LCB in consideration of the structure of the decoder circuit.

  The structure of the LCB 10 shown in FIG. 13 is obtained by further reducing the size of the LCB 10 while maintaining substantially the same flexibility as the structure of FIG. The key point of the structure of FIG. 10 is the structure of the decoder circuit. As shown in FIG. 9 described above, the decoder circuit controls the switches of the crossbar in units of columns, and the decoder circuit is suitable for the control of the power of 2 power switches. Therefore, in the structure of the LCB 10 in FIG. 13, eight switches are arranged for one row of the crossbar.

A feature of the decoder circuit is that N ² switches can be controlled using N memories. However, if the number of switches controlled for N memories is less than N ² , the memory utilization efficiency is lowered. Therefore, in order to make maximum use of the memory, the number of switches of the LCB 10 is set to N ² . The LCB in the approach of FIG. 13 has a total of 12 signal lines including 10 input lines for the external variable ED, a power supply line (VDD), and a ground line (GND) for each input pin of the VGLC. Thus, eight switches are arranged for each input pin of the VGLC. Of the four approaches, the approach of FIG. 13 uses the most switches 15. Further, by collecting the switches 15 in the central portion, the number of switches used for feedback is reduced.

  The results of the resource comparison of FIGS. 10 to 13 are shown in Table 2 below, and the results of the flexibility comparison are shown in Table 3. In Tables 2 and 3, approaches A, B, C, and D correspond to the approach of FIG. 10, the approach of FIG. 11, the approach of FIG. 12, and the approach of FIG. 13, respectively. Regarding the flexibility, when the LCB (crossbar part, feedback part, and total) related to each approach is mounted, quantification is performed using P representative elements that can be expressed by VGLC. Here, the implementation of the application is evaluated using 12 kinds of medium-scale MCNC benchmark circuits for the LCB structure related to each approach.

  * Note) The feedback variables in the feedback section of Table 2 must have the same flexibility as external variables. The external variable CB ensures flexibility, but the feedback variable must ensure flexibility at the connection portion of the feedback line and the crossbar portion. For this reason, on the contrary, the resource amount of the feedback line increases when the crossbar portion has a small resource amount.

  Here, the P representative source will be described. Misc. The logic that the Logic mode can express is limited. Therefore, the logic in the logic circuit is changed to Misc. It is necessary to determine whether mounting is possible in the Logic mode. Usually, a P (Permutation) representative is used as a Boolean matching method. For example, for a logical function f (x1; x2); g (x1; x2), f (x1; x2) ≠ g (x1; x2), f (x1; x2) = g (x2; x1) To do. In this case, the two logical functions are considered to belong to the same P equivalence class. Then, from the logical functions belonging to the same P equivalence class, one logical function having the smallest output logic is treated as a representative element. This is called a P representative. As a result, it is possible to aggregate a plurality of logical functions into the P representative element, which facilitates Boolean matching.

  As is clear from the comparison results of the circuit resource amounts of the LCBs in Table 2, approach B has the smallest number of switches (SW), the number of memories, and the number of transistors (Tr). However, approach B has the least flexibility due to the small number of switches. When approach A and approach D are compared, approach D has a larger total number of switches, but approach A has a larger number of transistors. This is due to the result of considering the utilization efficiency of the decoder circuit. In Approach D, by increasing the number of switches in the LCB, the number of switches used for feedback is less than half that of the others.

  Next, the flexibility of the LCB is evaluated. In general, the greater the number of switches in the LCB, the higher the flexibility. However, unlike the LUT, the VGLC input pins are not equivalent, and there are input pins that are frequently used and input pins that are not. Therefore, it is necessary to evaluate flexibility based on the frequency of use of each input pin and the number of switches. However, it is difficult to evaluate both directly. Therefore, this time, the flexibility of the LCB is evaluated by the representative element that can be expressed by the VGLC. Table 3 shows Misc. The evaluation result for each function in the Logic mode is shown.

The function notations in Table 3 are as follows.
N Misc-1: N input Misc. Using one basic logic element (usually abbreviated as BLE). Logic
N Misc-2: N input Misc. Using two basic logic elements (BLE). Logic
The values in Table 3 are Misc. The coverage of P representative elements that can be expressed by each approach for all P representative elements that the Logic mode has is shown. Note that approach A is not specified here because it can represent all P representatives. As a result, it was confirmed that the number of P representative elements that can be expressed is smaller in approach D than in approach A, although the number of switches is larger than that in approach A. This shows that not only the number of switches but also where the switches are arranged is very important. Further, approach B and approach C are largely divided into those having a very high relative value (for example, 3 Misc-1) and those having a very low relative value (for example, 5 Misc-2). The reason for this result is due to the number of BLE input pins and the number of input signals. 3Misc-1 implements 3 input logic with 1 BLE (4 pins). Therefore, it is only necessary to consider sharing only one input with the permutation of which signal is input to which pin. On the other hand, 5Misc-2 implements 5-input logic with 2 BLE (number of pins: 9). In this case, it is necessary to consider not only the rearrangement of signals but also sharing of four inputs, and the number of sharing combinations is very large compared to the case of one input. For this reason, not only CB but also the flexibility of LCB becomes very important.

  As shown in Table 3, each LCB has a different P representative element number that can be expressed. In FIGS. 14 to 16 below, an application is mapped to a VGLC in which each LCB is mounted, and the influence of the difference in the number of representative elements that can be expressed is shown based on the mapping result. In order to investigate how much the limitation of the P representative is affected during mounting, mounting evaluation is performed using 12 kinds of medium-scale MCNC benchmark circuits (for example, see FIG. 14).

Here, evaluation objects and evaluation items are as follows.
Evaluation target A) LCB considering all P representatives (Approach A)
B) LCB considering only arithmetic operation mode and random logic mode (approach B)
C) LCB considering approach rate (Approach C)
D) LCB considering the structure of the decoder circuit (Approach D)
Evaluation items and number of BLEs used (when technology mapping)
・ Critical path delay (during technology mapping)
-Number of logical stages (number of critical path stages) (at the time of technology mapping)

  FIG. 14 is a graph for comparing the number of BLEs used for the approach of reducing the number of switches in the four LCBs, a graph for comparing the critical path delay for the approach of reducing the number of switches in the four LCBs, and It is a graph for comparing the number of logical stages with respect to the approach of reducing the number of switches in four LCBs.

  As shown in FIGS. 14 to 16, as a result of implementation evaluation using 12 kinds of medium-scale MCNC benchmark circuits, approach A and approach D have the same results for the number of BLEs used, and approach B is approach A. The average number of BLE used was increased by 14% compared to that of Approach A, and that of Approach C was increased by 11% on average compared to Approach A. Compared to the difference in the number of P representative elements that can be expressed, the implementation results are almost the same. Furthermore, there is almost no difference in the critical path delay for the four approaches. Further, the number of logical stages is almost the same even when the four approaches are compared, and there are many stages of Approach B and Approach C by one or two stages depending on the application. Therefore, it can be seen that the number of P representative elements that can be expressed hardly affects the number of logical stages. This is because of Misc. This is because, among all P representatives that can be expressed in the Logic mode, only some P representatives are used in almost all cases. Since approach P and approach C can represent the same level of P representative elements, there is almost no effect on the mounting results. Thus, it is considered that the flexibility of the LCB may be reduced and the circuit resource amount may be reduced.

  FIG. 17 is a conceptual diagram regarding clustering of a plurality of VGLCs, and FIG. 18 is a block diagram showing an example of a cluster structure having a plurality of VGLCs. Until now, in this specification, the single VGLC 20 was targeted. As shown in the conceptual diagram of FIG. 17, LCBs 10-1 to 10-3 having a cluster structure formed by clustering a plurality of VGLCs 20-1 to 20-3 are mounted.

  More specifically, in the conceptual diagram of FIG. 17, a logic circuit device having a single VGLC 20 including a plurality of logic cells and an LCB 10 for connecting the external wiring and the VGLC 20 to each other is defined as one cluster 21. The cluster structures 210 are formed by connecting the clusters 21-1 to 21-3 to each other. Cluster 21-1 includes VGLC 20 and LCB 10, cluster 21-2 includes VGLC 20-2 and LCB 10-2, and cluster 21-3 includes VGLC 20-3 and LCB 10-3.

  In the example of FIG. 18, a cluster structure 210 is formed by three clusters each having VGLC 20 and LCB 10. Each cluster includes a VGLC 20 including a plurality of logic cells, an LCB 10 for mutually connecting the external wiring ED and the output wiring OUD via a connection block (CB) 5, a VGLC 20 including a plurality of logic cells, The logic circuit device includes a feedback unit 30 for feeding back the output signal of the VGLC 20 to the input wiring IND of the LCB 10. By forming the cluster structure 210, not only the inside of the VGLC 20 but also the adjacent VGLCs can be shared, and the total number of tracks can be reduced. In addition, by providing a wiring for connecting different LCBs, the signal propagation speed is also increased.

  FIG. 19 is a circuit block diagram showing a mounting example of the carry select adder formed as VGLC. It is desired that the cluster structure as shown in FIG. 18 described above can be effectively implemented for both arithmetic operations and logical operations. High flexibility is required to implement logical operations. However, when flexibility is increased, the overhead of wiring resources increases and the advantage of clustering may be impaired. Therefore, the present specification focuses on an arithmetic operation circuit having a regular circuit configuration, particularly a carry select adder. A typical example of the carry select adder is shown in FIG.

  In the carry select adder of FIG. 19, when the carry signal Carry from the lower digit is “0” or “1”, it is necessary to perform two kinds of calculations simultaneously. Therefore, in each cluster 21-1, 21-2, two adders (for example, 3-bit ripple carry adders 22-1 and 23-1, 3-bit ripple carry adders 22-2, 23 function as adder units). -2) is prepared, and a carry signal Carry of “0” or “1” is supplied to each adder. When the operation result of the lower digit is determined, which of the two addition results is adopted is determined as a multiplexer unit (for example, a multiplexer unit 24-1 including four 2: 1 multiplexers (MUX)). , 24-2). As signals input to the multiplexer units 24-1 and 24-2, it is necessary to input not only the output results of the two adders but also the carry signal Carry. Therefore, considering the number of multiplexer units that can be mounted on one VGLC, the adder is 3 bits. In the cluster 21-3 located at the least significant digit, only one 3-bit ripple carry adder 22-3 needs to be prepared. In this way, when two adders and a multiplexer unit are combined into one set, regular connection is possible, so that three VGLCs can be handled as one cluster structure.

  FIG. 20 is a circuit block diagram showing a configuration example of a VGLC configured with basic logic elements (hereinafter abbreviated as BLE) as basic units.

  In FIG. 20, four hybrid cells (HC) 26-1 to 26-4 are cascade-connected, and a pre-logic including EXOR (exclusive OR) gates 25-1 to 25-4 is added to the preceding stage. A VGLC in which an output selector and a 4-bit register (FF (flip flop)) 29 are added to the subsequent stage is illustrated. Here, the circuit element in which the pre-logic is added to the hybrid cell is called “BLE”.

  As shown in FIG. 20, VGLC configured with BLE9 as a basic unit cascades four hybrid cells (HC) 26-1 to 26-4, and includes EXOR gates 25-1 to 25-4, multiplexers. (MUX) 25-6 to 25-8, switch element 25-5, and memories 27-1 and 27-2 for configuration memory bits are added to the preceding stage, and multiplexers (MUX) 28-1 to 28- 3 and an output selector and a 4-bit register 29 are added to the subsequent stage. The VGLC configured as described above has three W, four X, Y, Z, and C each as an input signal, a switching signal AS that switches between addition and subtraction, a control signal Shift ctrl that controls the shift register, and There are four output signals O. Further, the other signals Carry in, Carry out, Shift in, and Shift out are cascade-connected to the adjacent VGLC, and the adder / subtracter and the shift register can be extended by multiple bits. The switching signal AS and the clock pulse CP are input in common to the four BLEs.

  FIG. 21 is a circuit diagram illustrating an example of a function included in the VGLC. As shown in (a), (b), (c), (d), and (e) of FIG. 21, VGLC has arithmetic operation mode, shift register mode, random logic mode, Misc. It has five functions: Logic (Missenious Logic) mode and Wide Range Multiplexer (MUX) mode.

  In the arithmetic operation mode shown in FIG. 21A, four BLEs are used as the full adder 200 to constitute 4-bit addition / subtraction. Also, bit extension is possible by using a carry line between VGLCs. In the shift register mode shown in FIG. 21B, a VGLC output selection unit including four FFs and an output selector is used as the 4-bit shift register 201. In addition, a serial-parallel conversion circuit can be configured by the control signal shift ctrl. In the random logic mode of FIG. 21 (c), VGLC can be used as the Reed-Muller standard form 202. In BLE alone, VGLC can be used as a 2-input standard type (canonical form, hereinafter abbreviated as CF) circuit. By using Shannon expansion, it is possible to express arbitrary logic of three inputs with two BLEs, and it is possible to express arbitrary logic of four inputs with four BLEs. It is also possible to express a combination of 2-input logic and 3-input logic.

  Misc. Of FIG. The Logic mode implements logical operations using the BLE gate structure. Since one BLE is a module 203 with 4 inputs and 2 outputs, it is possible to express logic with 3 and 4 inputs. Unlike the random logic mode, the logic that can be expressed is limited, but the mounting area can be reduced. Using the Shannon expansion as in the random logic mode, the 4-input and 5-input Misc. Logic can be realized. The wide range multiplexer (MUX) mode in FIG. 21E uses BLE as a 2-input 1-output multiplexer 204 and uses three multiplexers (for example, multiplexers 28-1 to 28-3 in FIG. 20). Thus, a wide range multiplexer having a maximum of 8 inputs is configured. Further, by using four BLEs in parallel, it is possible to operate as a multi-bit multiplexer required in the data path circuit.

  FIG. 22 is a circuit diagram illustrating a configuration example of a hybrid cell. Examples of configurations of a full adder, a 2-input Reed-Muller standard type, and a hybrid cell are shown in FIGS. 22 (a), 22 (b), and 22 (c), respectively.

  The full adder shown in FIG. 22A is often used in an arithmetic hardware algorithm, and the 2-input Reed-Muller standard form shown in FIG. 22B uses an arbitrary configuration memory by using four configuration memories. Two-input logic can be implemented. The hybrid cell in FIG. 22 (c) is a logic cell having the characteristics of both a full adder and a 2-input Reed-Muller standard type. As a result, efficient implementation of both arithmetic and logical operations can be expected.

  More specifically, in the VGLC, a full adder which is a basic unit of arithmetic operation as shown in FIG. 22A includes an EXOR gate 206 at the output stage and three AND gates connected to the EXOR gate 206. 205-1, 205-2 and 205-3, and AND gates 207 and 208 for carry. On the other hand, the 2-input Reed-Muller standard form as shown in FIG. 22B has an EXOR gate 213 in the output stage and three AND gates 212-1 and 212-2 connected to the EXOR gate 213. And 212-3, and 4-bit memories 211-1 to 211-4. Comparing the full adder and the 2-input Reed-Muller standard form, the EXOR gate of the output stage and the AND gate connected thereto (the logic circuit 209 in FIG. 22A and the logic circuit 213 in FIG. 22B) It can be seen that they have a common reference). Therefore, by installing a 4-bit memory in (a) of FIG. 22, a hybrid cell capable of expressing a full adder and 2-input Reed-Muller standard form as shown in (c) of FIG. Can do. This hybrid cell includes an EXOR gate 216 at the output stage, three AND gates 215-1, 215-2 and 215-3 connected to the EXOR gate 216, AND gates 217 and 218 for carry, Bit memory 214-1 to 214-4.

  FIG. 23 is a circuit diagram illustrating a relationship between a configuration example of BLE and a function. As described above, a circuit element in which a pre-logic is added to a hybrid cell is called BLE. As shown in FIG. 23A, the BLE is composed of hybrid cells, multiplexers 223 and 224, EXOR gates 221, 225 and 226, AND gates 220-1 to 220-3, and a 5-bit memory 222. It has C, X, Y, and Z as input signals, AS as a switching signal for switching between addition and subtraction, and T and S as output signals. Carry signal Carry is input to multiplexer 223. By adding a variable as each input signal or clamping the level of a specific input signal to “1” or “0”, the addition / subtraction (ADD / SUB) 227, 2-input lead of FIG. -Three types of functions can be performed: Mueller standard form (2RMCF) 228 and multiplexer (MUX) 229.

  Here, attention is focused on addition / subtraction (ADD / SUB) 227 and multiplexer (MUX) 229 in FIG. In the case of addition / subtraction (ADD / SUB) 227, X and Y are used as input signals, and in the case of a multiplexer (MUX), X, Z and C are used. As shown in FIG. 24 described later, assuming that the multiplexer (MUX) is realized when the input to the LCB is 1, m, and n, 1 is connected to X, m is connected to Z, and n is connected to C. To do. On the other hand, in the case of addition / subtraction (ADD / SUB) 227, Y may be connected to either m or n, assuming that X is connected to l.

  FIG. 24 is a schematic diagram showing a pattern of switch arrangement locations. ○ is a portion that needs to be connected, and Δ is a portion that only needs to be connected to either. Since there are six combinations of l, m, and n and X, Z, and C, all patterns are shown in (a) to (f) of FIG. Thus, for example, if the wiring can be made as shown in FIG. 24G, all the patterns shown in FIGS. 24A to 24F can be realized. This indicates that it is not necessary to connect all of the input wiring and the output wiring in the LCB.

Here, the P equivalence class and the P representative element evaluated when the LCB is mounted will be described in more detail. A P equivalence class is defined as a set of logical functions taking permutations of different inputs.
− − −
Example: f (x ₁ , x ₂ , x ₃ ) = x ₁ x ₂ x ₃ v x ₁
− − −
g (x ₃ , x ₂ , x ₁ ) = x ₃ x ₂ x ₁ v x ₃
The above two functions differ only in the sequence of input variables. In this case, these two functions are referred to as “belonging to the same equivalence class”, and a set of functions belonging to the same equivalence class is referred to as a P equivalence class.
On the other hand, among the functions belonging to the same P equivalence class, the P representative element is referred to as a P representative element of the P equivalence class when the output of the function is regarded as a binary number.
For the binary representation of the function, the output values of the following functions are summarized as m ₀ m ₁ ... M ₇ . This bit string is regarded as a binary number and is used as a reference for determining the P representative element.
− − − − −
f (x ₁ , x ₂ , x ₃ ) = m ₀ · x ₁ x ₂ x ₃ vm ₁ · x ₁ x ₂ x ₃ v ... vm ₇ · x ₁ x ₂ x ₃
In the above example, since each binary number representation is (100001111) (10110011) (11010101), the representative element that is the minimum value is (100001111).

  FIG. 25 is a graph showing the usage ratio of each function. Here, the Misc. Used for determining the LCB structure of FIG. We will explain Logic's prior evaluation.

  This Misc. In Logic's prior evaluation, first, technology mapping was performed using 40 MCNC benchmark circuits. From the results of this technology mapping, statistics on the usage rate of each function used (Misc. Logic, CF) were taken. The pie chart in FIG. 25 shows the frequency of use of each function. However, here, only seven types of functions that are frequently used are displayed in a pie chart, and descriptions of functions that are not frequently used are omitted.

From the graph of FIG. 25, the seven types of functions having a high usage rate are as follows.
・ 2CF 10.1% ・ 5Misc-2 2.52%
・ 3Misc-1 38.9% ・ 4CF 2.04%
・ 3CF 18.0% ・ 5Misc-4 10.0%
・ 4Misc-2 15.1%
In the present embodiment, 2CF, 3Misc-1, 3CF and 4CF are considered from the above function.

  FIG. 26 is a block diagram showing another embodiment of an interconnection structure according to the present invention. In another embodiment of FIG. 26, as in the case of FIG. 2 described above, a local connection block (LCB) 10 for mutually connecting the input wiring IND and the output wiring OUD, and a plurality of granularity variable logic cells ( VGLC) 20. On the other hand, a local feedback 30 having a feedback line for feeding back a signal output from the output line of the VGLC 20 to the input wiring IND on the input side of the LCB 10 is provided. The input wiring IND of the LCB 10 is the external wiring ED, the feedback line of the VGLC 20, the power supply line VDD and the ground line GND.

  The logic cell group having a reconfigurable structure as shown in FIG. 26 has many applications to digital filters. This digital filter is configured by applying a delay circuit. Further, the delay amount of the delay circuit 35 is often changed depending on characteristics. In this embodiment, a delay circuit 35 is added to the subsequent stage of the LCB 10 or the subsequent stage of the VGLC 20, and the digital filter is easily configured by adjusting the number of logical stages. The delay circuit 35 may be constituted by a fixed delay element or a variable delay element.

  The present invention can be applied to a programmable logic circuit device having an interconnection structure such as LCB for mutually connecting external wiring and a logic cell group such as VGLC and digital filter including a plurality of logic cells. is there. Furthermore, the present invention can also be applied to a cluster structure formed by clustering a plurality of logic circuit devices and connecting them together.

It is a block diagram which shows one Example of the interconnection structure which concerns on this invention. It is a block diagram which shows the specific example of the interconnection structure of FIG. FIG. 3 is a block diagram illustrating an overall configuration of a specific example of FIG. 2. It is a block diagram which shows the internal structure of LCB. It is a circuit block diagram which shows the example of the mounting structure of LCB at the time of using a crossbar. It is a circuit block diagram which shows the example of the mounting structure of LCB at the time of using a multiplexer. It is a circuit block diagram which shows the example of the mounting structure of LCB at the time of using Clos network. It is a circuit block diagram which shows the example of the mounting structure of LCB at the time of using a Benes network. It is a circuit block diagram for demonstrating the mode of switch control by a decoder circuit. It is a circuit diagram which shows the structure of the switch in LCB for expressing all the missenius logics. It is a circuit diagram which shows the structure of the switch in LCB considering only the arithmetic operation mode and the random logic mode. It is a circuit diagram which shows the structure of the switch in LCB corresponding to a part of Missius logic. It is a circuit diagram which shows the structure of the switch in LCB considering the structure of the decoder circuit. It is a graph for comparing the number of BLEs used for approaches of reducing the number of switches in four LCBs. 6 is a graph for comparing critical path delays for approaches to reducing the number of switches in four LCBs. It is a graph for comparing the number of logical stages with respect to the approach of reducing the number of switches in four LCBs. It is a conceptual diagram regarding clustering of several VGLC. It is a block diagram which shows an example of the cluster structure which has several VGLC. It is a circuit block diagram which shows the example of mounting of a carry select adder. It is a circuit block diagram which shows the structural example of VGLC comprised by making BLE a basic unit. It is a circuit diagram which shows the example of the function which VGLC has. It is a circuit diagram which shows the structural example of a hybrid cell. It is a circuit diagram which shows the relationship between the structural example of BLE and a function. It is a schematic diagram which shows the pattern of a switch arrangement location. It is a graph which shows the usage rate of each function. It is a block diagram which shows the other Example of the interconnection structure which concerns on this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Reconfigurable switch group 2 Logic cell group 3 Feedback part 4 Configuration memory 5 Connection block (CB)
5-1, 5-2 Connection block (CB)
6-1 to 6-4 Switch block 7 Tile 8 Decoder circuit 9 Basic logic element (BLE)
10 Local connection block (LCB)
11 switch unit 12 control unit 15 switch 20 granularity variable logic cell (VGLC)
21 clusters 22-1 to 22-4 3-bit ripple carry adder (RCA)
23-1, 23-2 3-bit ripple carry adder (RCA)
24-1, 24-2 Multiplexer (MUX) units 26-1 to 26-4 Hybrid cells (HC)
29 Output selector and 4-bit register 30 Local feedback 35 Delay circuit

Claims (28)

In interconnect structure having interconnects for connecting the input line of the logic cell group to each other with external wiring and a plurality of logic cells,
The interconnect section includes a connection defining means for defining the interconnection relationship between the input line of the logic cell group and the external wiring,
A feedback unit for feeding back a part of the output line of the logic cell group to the input line of the interconnection unit,
The feedback unit is configured to reduce the number of input lines of the interconnect unit without the need to incorporate a feedback signal from the outside.
The number of combinations defined by the connection defining means is all combinations of the inputs and outputs of the interconnecting part while maintaining flexibility regarding function expression in consideration of the function of the target logic in the plurality of logic cells. interconnect structure wherein the less than the number configuration is configured to be realized. The number of the number and the output line of the input line of the interconnects, the interconnect structure according to claim 1, characterized in that is arbitrarily set. The logic cell interconnection structure according to claim 1, characterized in that the reconfigurable logic cells. 4. The number of input lines of the interconnect portion can be reduced by clamping a specific input line of the interconnect portion to a predetermined level. interconnect structure according to claim. 4. The number of combinations defined by the connection defining means can be reduced by selecting a specific function among logic functions of the plurality of logic cells. An interconnect structure according to any one of the preceding claims . It is possible to reduce the number of combinations defined by the connection defining means by aggregating the logic functions of the plurality of logic cells into specific logic functions belonging to a group of logic functions that take different permutations of input signals. The interconnect structure according to any one of claims 1 to 3, wherein the interconnect structure is provided . 4. The number of configuration memories in the interconnect portion can be reduced by controlling on / off operations of the plurality of switches by a decoder circuit. 5. An interconnect structure according to claim 1 . The interconnect structure according to any one of claims 1 to 7, characterized in that providing a delay circuit in the subsequent stage of the interconnect or the logical cell groups. The delay circuit interconnect structure according to claim 8, characterized in that it is constituted by a fixed delay element. The delay circuit interconnect structure according to claim 8, characterized in that it is constituted by a variable delay element. In a logic circuit device having a logic cell group including a plurality of logic cells, and an interconnection part for mutually connecting an external wiring and an input line of the logic cell group,
The interconnect section includes a connection defining means for defining the interconnection relationship between the input line of the logic cell group and the external wiring,
A feedback unit for feeding back a part of the output line of the logic cell group to the input line of the interconnection unit,
The feedback unit is configured to reduce the number of input lines of the interconnect unit without the need to incorporate a feedback signal from the outside.
The number of combinations defined by the connection defining means is all combinations of the inputs and outputs of the interconnecting part while maintaining flexibility regarding function expression in consideration of the function of the target logic in the plurality of logic cells. A logic circuit device configured to realize a configuration less than a number.   12. The logic circuit device according to claim 11, wherein the number of input lines and the number of output lines of the interconnecting unit are arbitrarily set.   The logic circuit device according to claim 11, wherein the logic cell is a reconfigurable logic cell.   14. The number of input lines of the interconnect portion can be reduced by clamping a specific input line of the interconnect portion to a predetermined level. The logic circuit device according to item.   14. The number of combinations defined by the connection defining means can be reduced by selecting a specific function from among the logic functions of the plurality of logic cells. The logic circuit device according to any one of the above.   It is possible to reduce the number of combinations defined by the connection defining means by aggregating the logic functions of the plurality of logic cells into specific logic functions belonging to a group of logic functions that take different permutations of input signals. The logic circuit device according to claim 11, wherein the logic circuit device is provided.   14. The number of configuration memories in the interconnect portion can be reduced by controlling on / off operations of the plurality of switches by a decoder circuit. The logic circuit device according to one item.   18. The logic circuit device according to claim 11, wherein a delay circuit is provided in a subsequent stage of the interconnection unit or the logic cell group.   The logic circuit device according to claim 18, wherein the delay circuit includes a fixed delay element.   The logic circuit device according to claim 18, wherein the delay circuit includes a variable delay element. A logic circuit device including a logic cell group including a plurality of logic cells, and an interconnection part for mutually connecting an external wiring and an input line of the logic cell group is defined as one cluster, and the plurality of clusters are connected to each other. In a logic circuit device in which a cluster structure is formed by
The interconnection part in each of the clusters includes connection defining means for defining an interconnection relationship between the external wiring and the input line of the logic cell group;
A feedback unit for feeding back a part of an output line of the logic cell group in each of the clusters to an input line of the interconnection unit;
The feedback unit is configured to reduce the number of input lines of the interconnect unit without the need to incorporate a feedback signal from the outside.
The number of combinations defined by the connection defining means is determined while considering the function of the target logic in the plurality of logic cells of the logic cell group in each of the clusters, while maintaining flexibility regarding function expression. A logic circuit device configured to realize a configuration smaller than the total number of combinations of inputs and outputs of the interconnection section.   22. The logic circuit device according to claim 21, wherein the number of input lines and the number of output lines of the interconnection section in each cluster are arbitrarily set.   The logic circuit device according to claim 21, wherein the logic cell in each of the clusters is a reconfigurable logic cell.   The number of input lines of the interconnect can be reduced by clamping a particular input line of the interconnect in each of the clusters to a predetermined level. 24. The logic circuit device according to any one of 1 to 23.   It is possible to reduce the number of combinations defined by the connection defining means by selecting a specific function among the logic functions of the plurality of logic cells of the logic cell group in each cluster. 24. The logic circuit device according to any one of claims 21 to 23, wherein:   By combining the logic functions of the plurality of logic cells in each of the clusters into a specific logic function belonging to a group of logic functions taking different permutations of input signals, the number of combinations defined by the connection defining means is obtained. 24. The logic circuit device according to claim 21, wherein the logic circuit device can be reduced.   By controlling the on / off operation of the plurality of switches by a decoder circuit provided in each of the clusters, it is possible to reduce the number of configuration memories in the interconnect section The logic circuit device according to any one of claims 21 to 23.   28. The logic circuit device according to claim 21, wherein a delay circuit is provided in a subsequent stage of the interconnect section or the logic cell group in each of the clusters.

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